Display panel and display device

Abstract

Embodiments of the present application disclose a display panel and a display device, the display panel comprising: a plurality of arrayed pixel driving circuits, a plurality of first signal lines and a shielding unit; the pixel driving circuits are electrically connected with the first signal lines; a substrate; the pixel driving circuits, the first signal lines and the shielding unit are located on one side of the substrate; in a direction perpendicular to a plane where the substrate is located, at least part of the pixel driving circuits and at least part of the first signal lines overlap with the shielding unit; in the direction perpendicular to the plane where the substrate is located, the first signal lines that overlap with the shielding unit comprise first line segments; at least part of the shielding unit is multiplexed as the first line segments. The display panel and the display device provided by the embodiments of the present application can realize high resolution, and meanwhile can meet the light transmission and display requirements of a high light transmission area in the display panel.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0002] Organic Light Emitting Diode (OLED) display has the advantages of self-illumination, low driving voltage, high luminous efficiency, short response time, and flexible display, and has become the most potential display.

[0003] The OLED element of the OLED display is a current driving type element, and a corresponding pixel driving circuit needs to be set to provide driving current for the OLED element, so that the OLED element can emit light. In addition, a corresponding signal line is also provided in the OLED display device to transmit corresponding signals to the pixel driving circuit to control the pixel driving circuit to drive the OLED element to emit light. In the prior art, in order to solve the threshold voltage drift problem of the driving transistor in the pixel driving circuit caused by process and device aging, a pixel driving circuit with threshold compensation function is usually provided in the display panel.

[0004] However, the current pixel driving circuit with threshold compensation function needs to be provided with a plurality of different signal lines to provide corresponding signals, so that the pixel driving circuit and the signal line electrically connected thereto have a large size, which is not conducive to the high PPI of the display panel; at the same time, it also cannot meet the requirements of high light transmission and display of the high light transmission area. SUMMARY

[0005] In view of the above problems, the embodiments of the present application provide a display panel and a display device to reduce the occupied area of the pixel driving circuit and the signal line electrically connected thereto, which is conducive to the high resolution of the display panel, and can meet the requirements of high light transmission and display of the high light transmission area.

[0006] In a first aspect, the embodiments of the present application provide a display panel, comprising:

[0007] a plurality of arrayed pixel driving circuits, a plurality of first signal lines and a shielding unit; the pixel driving circuit is electrically connected with the first signal line;

[0008] a substrate; the pixel driving circuit, the first signal line and the shielding unit are located on one side of the substrate; at least part of the pixel driving circuit and at least part of the first signal line overlap with the shielding unit in the direction perpendicular to the plane where the substrate is located;

[0009] The first signal line having overlap with the shielding unit in a direction perpendicular to a plane where the substrate substrate is located comprises a first line segment; and at least part of the shielding unit is multiplexed as the first line segment.

[0010] In a second aspect, the embodiment of the present application further provides a display device, comprising the display panel.

[0011] The display panel and the display device provided by the embodiment of the present application can shield the influence of external electric field and / or optical signal on the pixel driving circuit or other components arranged in the display panel by arranging the shielding unit overlapping at least part of the pixel driving circuit and the first signal line, so as to improve the performance of the display panel. Meanwhile, by multiplexing at least part of the shielding unit as the first line segment of the first signal line having overlap with the shielding unit, the first line segment can not only transmit corresponding signals to the pixel driving circuit, but also shield external electric field and / or optical signal, so as to simplify the design of the display panel. In addition, when at least part of the shielding unit is multiplexed as the first line segment, the position originally used for arranging the first line segment can be left empty, so as to reduce the area of the region where the pixel driving circuit and the signal line are located, thereby facilitating increasing the number of pixel driving circuits arranged in the unit area of the display panel and improving the resolution of the display panel. Meanwhile, when the area of the region where the pixel driving circuit and the signal line are located is reduced, the area of the region where no pixel driving circuit and signal line are arranged in the display panel can be increased, thereby facilitating improving the light transmission area of the display panel and meeting the light transmission and display requirements of the high light transmission area. BRIEF DESCRIPTION OF DRAWINGS

[0012] Figure 1 is a structural schematic diagram of a display panel of a related art;

[0013] Figure 2 is a circuit structural schematic diagram of a pixel driving circuit of a related art;

[0014] Figure 3 is a partial top view structural schematic diagram of a display panel of a prior art;

[0015] Figure 4 is a partial top view structural schematic diagram of a display panel provided by an embodiment of the present application;

[0016] Figure 5 is a sectional structural schematic diagram along A-A section of Figure 4

[0017] Figure 6 is a partial top view structural schematic diagram of yet another display panel provided by an embodiment of the present application;

[0018] Figure 7 is a top view structural schematic diagram of a display panel provided by an embodiment of the present application;​

[0019] Figure 8 is a schematic diagram of a film layer structure of a display panel provided by an embodiment of the present application;

[0020] Figure 9 is a schematic diagram of a partial top view structure of a display panel provided by an embodiment of the present application;

[0021] Figure 10 is a schematic diagram of a cross-sectional structure along Figure 9 B-B section in FIG. 1B;

[0022] Figure 11 is a schematic diagram of a film layer structure of a display panel provided by an embodiment of the present application;

[0023] Figure 12 is a schematic diagram of a partial top view structure of a display panel provided by an embodiment of the present application;

[0024] Figure 13 is a schematic diagram of a partial top view structure of a display panel provided by an embodiment of the present application;

[0025] Figure 14 is a schematic diagram of a cross-sectional structure along Figure 13 C-C section in FIG. 1C;

[0026] Figure 15 is a schematic diagram of a film layer structure of a display panel provided by an embodiment of the present application;

[0027] Figure 16 is a schematic diagram of a partial top view structure of a display panel provided by an embodiment of the present application;

[0028] Figure 17 is a schematic diagram of a cross-sectional structure along Figure 16 D-D section in FIG. 1D;

[0029] Figure 18 is a schematic diagram of a partial top view structure of a display panel provided by an embodiment of the present application;

[0030] Figure 19 is a schematic diagram of a cross-sectional structure along Figure 18 E-E section in FIG. 1E;

[0031] Figure 20 is a schematic diagram of a film layer structure of a display panel provided by an embodiment of the present application;

[0032] Figure 21 is a schematic diagram of a partial top view structure of a display panel provided by an embodiment of the present application;

[0033] Figure 22 is a schematic diagram of a cross-sectional structure along Figure 21A cross-sectional structure schematic view of a middle F-F section;

[0034] Figure 23 A partial top view structure schematic view of another display panel provided by the embodiment of the present application;

[0035] Figure 24 A partial top view structure schematic view of another display panel provided by the embodiment of the present application;

[0036] Figure 25 A cross-sectional structure schematic view of a middle J-J section; Figure 24 A cross-sectional structure schematic view of a middle J-J section;

[0037] Figure 26 A partial top view structure schematic view of another display panel provided by the embodiment of the present application;

[0038] Figure 27 A cross-sectional structure schematic view of a middle I-I section; Figure 26 A cross-sectional structure schematic view of a middle I-I section;

[0039] Figure 28 A partial top view structure schematic view of another display panel provided by the embodiment of the present application;

[0040] Figure 29 A partial top view structure schematic view of another display panel provided by the embodiment of the present application;

[0041] Figure 30 A cross-sectional structure schematic view of a middle K-K section; Figure 29 A cross-sectional structure schematic view of a middle K-K section;

[0042] Figure 31 A partial top view structure schematic view of another display panel provided by the embodiment of the present application;

[0043] Figure 32 A cross-sectional structure schematic view of a middle L-L section; Figure 31 A cross-sectional structure schematic view of a middle L-L section;

[0044] Figure 33 A partial top view structure schematic view of another display panel provided by the embodiment of the present application;

[0045] Figure 34 A partial top view structure schematic view of another display panel provided by the embodiment of the present application;

[0046] Figure 35 A structure schematic view of a display panel provided by the embodiment of the present application;

[0047] Figure 36 A partial top view structure schematic view of another display panel provided by the embodiment of the present application;

[0048] Figure 37is a structural schematic diagram of a display device provided by an embodiment of the present application.

[0049] Figure 38 is a cross-sectional structural schematic diagram along Figure 37 M-M section in the display panel. DETAILED DESCRIPTION

[0050] The present application will be further described below in conjunction with the drawings and embodiments. It should be understood that the specific embodiments described herein are intended to be merely illustrative of the present application and not in limitation thereof. It should also be noted that, for the sake of brevity, only the parts of the display device relevant to the present application are shown in the drawings.

[0051] Figure 1 is a structural schematic diagram of a display panel in the related art. As shown in Figure 1 the display area 0110 of the display panel 001 includes a plurality of pixel driving circuits 010 arranged in an array and a plurality of signal lines 021 and 022 crossing horizontally and vertically, the signal lines 021 and 022 defining the positions of the pixel driving circuits 010 and transmitting corresponding signals to the pixel driving circuits 010, so that the pixel driving circuits 010 drive the light emitting elements to emit light (not shown in the figure).

[0052] In the prior art, in order to solve the threshold voltage drift problem of the driving transistor in the pixel driving circuit caused by the process and device aging, a pixel driving circuit with threshold compensation function is usually provided in the display panel, and the common one is a 7T1C pixel driving circuit. Figure 2 is a circuit structural schematic diagram of a pixel driving circuit in the related art, in conjunction with Figure 1 and Figure 2As shown, the pixel driving circuit 010 includes seven transistors and one storage capacitor Cst, and the seven transistors are a driving transistor T, an initialization transistor M4, a data writing transistor M2, a threshold compensation transistor M3, a reset transistor M5, a first light emitting control transistor M1 and a second light emitting control transistor M6. At this time, a plurality of scan signal lines (a first scan signal line Scan1, a second scan signal line Scan2, a third scan signal line Scan3 and a light emitting control signal line Emit) electrically connected to the gates of the transistors in the pixel driving circuit need to be arranged in the display panel 001 to control the on or off of the transistors respectively; at the same time, a plurality of signal lines electrically connected to the sources or drains of the transistors are also arranged in the display panel 001, for example, a data signal line Data for transmitting a data signal, a reset signal line Ref for transmitting an initialization signal and a reset signal and a power signal line PVDD for transmitting a power signal; in this way, in the initialization stage, the first scan signal transmitted by the first scan signal line Scan1 controls the initialization transistor M4 to be turned on, so that the initialization signal transmitted by the initialization signal line Ref is written into the gate of the driving transistor T and the storage capacitor Cst through the turned-on initialization transistor M4, to initialize the gate of the driving transistor T and the storage capacitor Cst, to facilitate the writing of other signals; in the data writing stage, the second scan signal transmitted by the second scan signal line Scan2 controls the data writing transistor M2 and the threshold compensation transistor M3 to be turned on, so that the data signal transmitted by the data signal line Data can be sequentially written into the gate of the driving transistor T and the storage capacitor Cst through the turned-on data writing transistor M2, the driving transistor T and the threshold compensation transistor M3, while the threshold voltage of the driving transistor T is compensated; in the reset stage, the third scan signal transmitted by the third scan signal line Scan3 controls the reset transistor M5 to be turned on, so that the reset signal transmitted by the reset signal line Ref is written into the anode of the light emitting element 020 through the turned-on reset transistor M5, to reset the anode of the light emitting element 020; in the light emitting stage, the light emitting control signal transmitted by the light emitting control signal line Emit can control the first light emitting control transistor M1 and the second light emitting control transistor M6 to be turned on, so that the driving current provided by the driving transistor T can flow into the light emitting element 020 to drive the light emitting element 020 to emit light; since the threshold voltage of the driving transistor T is compensated in the data writing stage, the driving current provided by the driving transistor T to the light emitting element 020 in the light emitting stage will be independent of the threshold of the driving transistor T, thereby ensuring that the light emitting element 020 can accurately and stably emit light, and improving the display effect of the display panel 001.

[0053] However, a plurality of different signal lines need to be arranged in the display panel to provide corresponding signals for the 7T1C pixel driving circuit with threshold compensation function, so that the driving unit formed by the pixel driving circuit and the signal line electrically connected thereto occupies a large area. Figure 3 is a schematic diagram of a partial top view of a display panel in the prior art, as Figure 3 Each driving unit 0100 (including a pixel driving circuit and a signal line electrically connected thereto) has a large size in both the horizontal direction X and the vertical direction Y, which is not conducive to high PPI of the display panel; at the same time, it is also difficult to meet the requirements of light transmission and display of the high light transmission area.

[0054] To solve the above technical problems, the embodiments of the present application provide a display panel, which comprises a plurality of arrayed pixel driving circuits, a plurality of first signal lines and a shielding unit; the pixel driving circuit is electrically connected with the first signal line; a substrate; the pixel driving circuit, the first signal line and the shielding unit are located on one side of the substrate; at least part of the pixel driving circuit and at least part of the signal line overlap with the shielding unit in the direction perpendicular to the plane where the substrate is located; the first signal line which overlaps with the shielding unit in the direction perpendicular to the plane where the substrate is located comprises a first line segment; at least part of the shielding unit is multiplexed as the first line segment.

[0055] By adopting the above technical solution, first, by arranging the shielding unit which overlaps with at least part of the pixel driving circuit and the first signal line, the influence of external electric field and / or optical signal on the pixel driving circuit or other components arranged in the display panel can be shielded, so as to improve the performance of the display panel, which may, for example, be display performance or; second, by multiplexing at least part of the shielding unit as the first line segment of the first signal line which overlaps with the shielding unit, the first line segment can not only transmit corresponding signals to the pixel driving circuit, but also shield external electric field and / or optical signal, so as to simplify the design of the display panel; third, when at least part of the shielding unit is multiplexed as the first line segment, the position originally used for arranging the first line segment can be left empty, so as to reduce the area of the region where the pixel driving circuit and the signal line electrically connected thereto are located, thereby facilitating the increase of the number of pixel driving circuits arranged in a unit area of the display panel and improving the resolution of the display panel; at the same time, when the area of the region where the pixel driving circuit and the signal line are located is reduced, the area of the region where no pixel driving circuit and signal line are arranged can be increased, thereby facilitating the increase of the light transmission area of the display panel and meeting the requirements of light transmission and display of the high light transmission area.

[0056] The above is the core idea of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application. The technical solutions in the embodiments of the present application will be described clearly and completely in combination with the accompanying drawings of the embodiments of the present application.

[0057] Figure 4 is a schematic diagram of a partial top view structure of a display panel provided by an embodiment of the present application, Figure 5 is a schematic diagram of a cross-sectional structure along the A-A section of Figure 4 , in combination with Figure 4 and Figure 5 , the display panel comprises a substrate P1, a plurality of arrayed light emitting elements 40, a plurality of arrayed pixel driving circuits 10 and a plurality of first signal lines 21 located on one side of the substrate P1. The pixel driving circuit 10 is electrically connected to the first signal line 21, and the first signal line 21 can transmit corresponding signals to the pixel driving circuit 10 to control the pixel driving circuit 10 to drive the light emitting element 40 to emit light.

[0058] A shielding unit 30 is further provided on one side of the substrate P1. At least part of the pixel driving circuit 10 and at least part of the first signal line 21 overlap the shielding unit 30 in the direction Z perpendicular to the plane where the substrate P1 is located. Here, the overlap means that, in the plane, the area where at least part of the pixel driving circuit 10 is located and the area where at least part of the first signal line 21 is located both partially overlap the area where the shielding unit 30 is located, and the structures in the overlapping area can be multiplexed with each other. The shielding unit 30 can be used to shield external electric field and / or external light signals. For example, when the shielding unit 30 is used to shield external electric field, the shielding unit 30 can shield the electric field generated from the side of the substrate P1, so as to prevent the electric field from affecting the performance of the pixel driving circuit 10 or some devices in the pixel driving circuit 10, and preventing the electric field from affecting the stability of the signals transmitted by the first signal line 21. When the shielding unit 30 is used to shield external light signals, the shielding unit 30 can prevent external light from affecting the channel of the transistor in the pixel driving circuit 10, so as to prevent the threshold drift of the transistor in the pixel driving circuit 10 and affect the display effect. Alternatively, the shielding unit 30 can be used as a light shielding structure to improve the imaging accuracy of an optical sensor (not shown in the figure). In this way, by providing the shielding unit 30 in the display panel, the display effect of the display panel and / or the imaging accuracy of the light sensing device in the display panel can be improved.

[0059] Correspondingly, the shielding unit 30 can be composed of one or more layers without affecting the design of other structures in the display panel. It can be understood that the first conductive layer for setting the shielding unit can be located between the substrate and the pixel driving circuit, between the functional film layers in the pixel driving circuit, and between the pixel driving circuit and the light emitting element in one or more combinations. In actual applications, it can be designed according to actual needs. For example, as shown in Figure 5 The embodiment only exemplarily illustrates that the first conductive layer P2 for setting the shielding unit 30 is located between the pixel driving circuit 10 and the substrate P1.

[0060] Continuing to combine Figure 4 and Figure 5 As shown in FIGS. 7 and 8, the material of the first conductive layer P2 for setting the shielding unit 30 can be selected from materials with conductive function. At this time, the first signal line 21 that overlaps with the shielding unit 30 in the direction Z perpendicular to the plane of the substrate P1 can include a first line segment 211, and at least part of the shielding unit 30 is multiplexed as the first line segment 211. In this way, by setting the first line segment 211 in the first conductive layer P2, the position originally used to set the first line segment 211 can be vacated in other functional film layers (P3-P9), thereby reducing the area of the region where the pixel driving circuit 10 and the first signal line 21 electrically connected thereto are located, and further facilitating the increase of the number of pixel driving circuits per unit area in the display panel, thereby improving the resolution of the display panel. At the same time, when the area of the region where the pixel driving circuit and the signal line are located is reduced, the area of the region in the display panel where the pixel driving circuit and the signal line are not located can be increased, thereby facilitating the increase of the light transmission area of the display panel, and meeting the light transmission and display requirements of the high light transmission area.

[0061] It can be understood that the functional film layers (P3-P9) described herein do not refer to a single film layer, but a combination of multiple film layers for forming structures such as pixel driving circuits, signal lines, and light emitting elements in the display panel.

[0062] It should be noted that the structure of the currently known pixel driving circuit varies greatly, and the signal line for controlling the operation of the pixel driving circuit can be designed according to actual needs, i.e., the first signal line electrically connected to the pixel driving circuit can be any signal line capable of transmitting signals to the pixel driving circuit, and the embodiments of the present application do not make specific limitations thereon. Meanwhile, for the convenience of description, the embodiments of the present application only exemplarily illustrate the 7T1C pixel driving circuit, and the embodiments of the present application are also applicable to other pixel driving circuits that increase or decrease active devices and / or passive devices based on the 7T1C pixel driving circuit. The active devices include transistors, etc., and the passive devices include capacitors, resistors, inductors, etc.

[0063] The current 7T1C pixel driving circuit usually includes seven transistors and one storage capacitor, and the first signal line electrically connected with the 7T1C pixel driving circuit can be a signal line electrically connected with the source or drain of the transistor in the 7T1C pixel driving circuit, or a signal line electrically connected with the gate of the transistor in the 7T1C pixel driving circuit. The following exemplary describes the influence of the pixel driving circuit and other signal lines when the first signal line is different types of signal lines.

[0064] Optionally, when the first signal line is a signal line electrically connected with the source or drain of the transistor in the pixel driving circuit, continue to combine with reference to Figure 4 and Figure 5 The pixel driving circuit 10 includes at least one first transistor T1; the pixel driving circuit 10 electrically connected with the first segment 211 of the first signal line 21 is a first type of pixel driving circuit 101; the first pole of the first transistor T1 of the first type of pixel driving circuit 101 is electrically connected with the first segment 211 through the first via hole H1.

[0065] In the embodiment of the present application, the first pole and the second pole are one of the source and the drain; that is, when the transistor is a P-type transistor, the first pole is the source and the second pole is the drain, so that the signal transmitted by the first signal line can be input from the source of the first transistor and output from the drain of the first transistor T1; and when the transistor is an N-type transistor, the first pole is the drain and the second pole is the source, so that the signal transmitted by the first signal line can be output from the drain of the first transistor and output from the source of the transistor.

[0066] In this way, by multiplexing at least part of the shielding unit 30 as the first segment 211 electrically connected with the first pole of the first transistor T1 in the first type of pixel driving circuit 101, the position originally used to set the first segment 211 can be vacated to reduce the area of the first type of pixel driving circuit and the area of the signal line electrically connected with the first type of pixel driving circuit, thereby facilitating increasing the number of pixel driving circuits set in a unit area in the display panel and improving the resolution of the display panel; at the same time, when the area of the first type of pixel driving circuit and the area of the signal line electrically connected therewith are reduced, the area of the region in the display panel which is not provided with the pixel driving circuit and the signal line can be increased, thereby facilitating increasing the light transmission area of the display panel and meeting the light transmission and display requirements of the high light transmission area.

[0067] Optionally, continue to combine with reference to Figure 4 and Figure 5The display panel further comprises a plurality of second signal lines 22; the pixel driving circuit 10 further comprises a second transistor T2; the first electrode of the second transistor T2 is electrically connected with the second signal line 22, and the second transistor T2 of at least part of the pixel driving circuits 10 in the same column share the second signal line 22; the distance between the two second signal lines 22 electrically connected with the two first-type pixel driving circuits 101 in the same row and adjacent to each other in the row direction X of the pixel driving circuit is L1, and the line width of the second signal line 22 is L2; wherein 6≤L1 / L2≤8.

[0068] Specifically, in the prior art, the signal lines with the same extension direction are usually arranged in the same layer, while in the technical solution, the first line segment 211 of the first signal line 21 with the same extension direction as the second signal line 22 is arranged in the first conductive P2 for arranging the shielding unit 30, so that compared with the prior art, the area of the region where the signal line arranged in the third metal layer P6 where the second signal line 22 is located is reduced, and the position in the third metal layer P6 where the first line segment 211 is originally arranged is vacated, at this time, the local structure of the first-type pixel driving circuit 10 and the second signal line 22 can be moved, so that the distance between the second signal lines 22 electrically connected with the two first-type pixel driving circuits 101 adjacent to each other is reduced, that is, under the premise that the line width of the second signal line 22 is unchanged, the ratio of the distance between the second signal lines 22 electrically connected with the two first-type pixel driving circuits 101 adjacent to each other to the line width of the second signal line 22 is reduced, and then in the row direction X of the pixel driving circuit 10, the total size of the first-type pixel driving circuit 101 and the second signal line 22 electrically connected therewith can be reduced by 4% to 14%, which is equivalent to that the area of the region where the first-type pixel driving circuit 101 is located can be reduced by 4% to 14%; in this way, compared with the prior art, the area of the region where the first-type pixel driving circuit 10 is located in the display panel is reduced, which can be beneficial to increasing the number of pixel driving circuits 10 arranged in the display panel, that is, increasing the resolution of the display panel; at the same time, when the area of the region where the first-type pixel driving circuit 10 is located is reduced, the area of the region in the display panel where no pixel driving circuit and signal line is arranged can be increased, so as to be beneficial to improving the light transmission area of the display panel, and meeting the light transmission and display requirements of the high light transmission area.

[0069] Optionally, continuing to combine with reference to Figure 4 and Figure 5In general, each light emitting element 40 in the display panel is electrically connected with the pixel driving circuit 10 corresponding thereto, so that each light emitting element 40 can emit light under the driving of the pixel driving circuit 10 corresponding thereto. Correspondingly, the at least one first transistor T1 can include a first light emitting control transistor M1, the pixel driving circuit 10 can further include a second light emitting control transistor M6 and a driving transistor T; the second electrode of the first light emitting control transistor M1 is electrically connected with the first electrode of the driving transistor T; the first electrode of the second light emitting control transistor M6 is electrically connected with the second electrode of the driving transistor T, and the second electrode of the second light emitting control transistor M6 is electrically connected with the anode 41 of the light emitting element 40 through the second via hole H2; at this time, along the first direction Y', the first via hole H11 electrically connected with the first light emitting control transistor M1 and the second via hole H2 overlap; wherein the first direction Y' is parallel to the plane in which the substrate P1 is located and has a first included angle with the column direction Y of the pixel driving circuit 10.

[0070] Exemplarily, since the first line segment 211 of the first signal line 21 is arranged in the first conductive layer P2 for arranging the shielding unit 30, compared with the prior art, the position originally used for arranging the first line segment 211 is vacated, so that the partial structure of the first type pixel driving circuit 101 can be moved in the direction of -X, that is, the first light emitting control transistor M1 and other structures directly electrically connected therewith are moved to the side of the second light emitting control transistor M6, so that the second via hole H2 electrically connected with the second light emitting control transistor M6 and the first via hole H11 electrically connected with the first light emitting control transistor M1 and the first line segment 211 have a relatively close distance L3, so that the first via hole H11 can overlap with the second via hole H2 in the direction Y' having a relatively small offset angle (first included angle) with the column direction Y of the pixel driving circuit 10. Wherein the first included angle can be a relatively small angle, for example, less than or equal to 10 degrees, at this time, the first direction Y' is approximately parallel to the column direction Y of the pixel driving circuit 10.

[0071] When the first signal line 21 is a signal line electrically connected with the first electrode of the first light emitting control transistor M1, the first signal line 21 is a positive power voltage signal line PVDD for transmitting a positive power voltage signal to the first electrode of the first light emitting control transistor M1; correspondingly, the second signal line 22 can be a data signal line Data, and the second transistor T2 electrically connected with the data signal line Data can be a data writing transistor M2.

[0072] It should be noted that, Figure 4 The accompanying drawings are only exemplary drawings of embodiments of the present application, Figure 4The case that the local structure of the first type of pixel driving circuit 101 is moved to reduce the distance between the first via hole H11 and the second via hole H2 is only exemplary. In the embodiment of the present application, when at least part of the shielding unit is reused as the first line segment, other implementation manners of reducing the area of the region where the first type of pixel driving circuit 101 is located can also be used.

[0073] Exemplarily, Figure 6 is a schematic diagram of a partial top view of another display panel provided by the embodiment of the present application. Figure 6 In the embodiment of the present application, Figure 4 is the same as that in Figure 4 , and only exemplary description is given below to the difference between Figure 6 and Figure 4 . In combination with the description of Figure 4 and Figure 6 , after the position originally used for arranging the first line segment 211 is left, the first light-emitting control transistor M1 and at least part of other structures directly electrically connected to the first light-emitting control transistor M1 are moved to the side of the second light-emitting control transistor M6, and the position of the first via hole H11 electrically connected to the first light-emitting control transistor M1 can remain unchanged. At this time, compared with the prior art, the horizontal distance between the first via hole H11 and the position where the channel region of the first light-emitting control transistor M1 is located is reduced from L4 to L4', that is, under the premise that the width W1 of the channel region of the first light-emitting control transistor M1 remains unchanged, the ratio of the non-channel region of the first light-emitting control transistor M1 to the channel region thereof can be reduced, that is, L4' / W1

[0074] Optionally, Figure 7 is a schematic diagram of a top view of a display panel provided by the embodiment of the present application, as shown in Figure 7 , the shielding unit 30 of the display panel 100 includes a plurality of shielding sub-units (3001 and 3002); each shielding sub-unit (3001 or 3002) overlaps with N pixel driving circuits 10 in the direction perpendicular to the plane where the substrate P1 is located; the pixel driving circuit 10 further includes a storage capacitor Cst; the first plate of the storage capacitor Cst in each pixel driving circuit 10 overlapping with the same shielding sub-unit (3001 or 3002) is an integral structure; in each first type of pixel driving circuit 101, the first plate of each storage capacitor Cst which is an integral structure is electrically connected to the same first line segment 211 through M third via holes H3; wherein M

[0075] Specifically, the first plate of the storage capacitor Cst in the pixel driving circuit 10 is usually electrically connected with a fixed voltage signal, and the second plate of the storage capacitor Cst is electrically connected with the gate of the driving transistor T, so that the storage capacitor Cst can stably store the gate potential of the driving transistor T. In order to reduce the number of signal lines in the display panel 100, the positive power voltage signal electrically connected with the first plate of the first light-emitting control transistor M1 can be multiplexed as the signal line electrically connected with the first plate of the storage capacitor Cst. At this time, the storage capacitor Cst and the first light-emitting control transistor belonging to the same pixel driving circuit 10 can be electrically connected with the same positive power voltage signal line PVDD. At the same time, since the positive power voltage signal transmitted by the positive power voltage signal line PVDD is a fixed voltage signal, even if different pixel driving circuits 10 share the positive power voltage signal line PVDD, the performance of each pixel driving circuit 10 will not be affected. At this time, the first plates of the storage capacitors Cst of each first-type pixel driving circuit 101 that overlap with the same shielding sub-unit (3001 or 3002) can be electrically connected with the same shielding sub-unit (3001 or 3002), and the number of third vias H3 electrically connecting the shielding sub-unit (3001 or 3002) and the first plates of the storage capacitors Cst of the first-type pixel driving circuit 101 can be less than the number of first-type pixel driving circuits 101 overlapping with the shielding sub-unit (3001 or 3002), so as to save space for setting the third vias H3, thereby further reducing the total area of the region where each pixel driving circuit overlaps with the same shielding sub-unit (3001 or 3002).

[0076] It can be understood that when the shielding unit 30 includes a plurality of shielding sub-units (3001 or 3002), each shielding sub-unit (3001 or 3002) described herein overlapping with at least one pixel driving circuit can be understood as each shielding sub-unit overlapping with part of the structure of at least one pixel driving circuit, or can be understood as each shielding sub-unit (3001 or 3002) covering at least one pixel driving circuit 10 in the direction perpendicular to the plane of the substrate P1, that is, each shielding sub-unit (3001 or 3002) can overlap with one, two or more pixel driving circuits 10. At this time, each shielding sub-unit can shield at least one pixel driving circuit 10. The number of pixel driving circuits 10 covered by each shielding sub-unit (3001 or 3002) is not limited in the embodiment of the application. At the same time, any two shielding sub-units can be independent of each other, or any two shielding sub-units can have overlapping or multiplexed parts, which are not limited in the embodiment of the application.

[0077] For example, Figure 7As shown, each shielding sub-unit 3001 (3002) can cover three pixel driving circuits 10, which can be pixel driving circuits 10 for driving three light emitting elements of different colors of the same pixel unit.

[0078] It can be understood that, as shown in Figure 4 , Figure 5 and Figure 7 , when the first signal line 21 is a positive power voltage signal line PVDD, the signal transmitted by the first signal line 21 is a fixed voltage signal; at this time, each shielding sub-unit (3001 or 3002) can include at least one first shielding structure, which can be included in the first conductive layer P2 on the side of the substrate P1, and the first shielding structure can be multiplexed as the first line segment 211, and the first line segment 211 electrically connected by each pixel driving circuit 100 covered by the same shielding sub-unit (3001 or 3002) is an integral structure. In this way, only the shielding unit 30 needs to be provided in the first conductive layer P2, so that each shielding sub-unit (3001, 3002) can play a good shielding role for each pixel driving circuit 10, and at the same time, because the first line segment 211 electrically connected by each pixel driving circuit 100 covered by the same shielding sub-unit (3001 or 3002) is an integral structure, the first line segment 211 has a larger cross-sectional area, thereby facilitating the reduction of the resistance of the first line segment 211, the reduction of the loss of the signal transmitted on the first line segment 211, and the improvement of the display effect of the display panel.

[0079] It should be noted that, as shown in Figure 5 , the first conductive layer P2 of the shielding unit multiplexed as the first line segment in the embodiment of the application can be located between the substrate P1 and the semiconductor layer P3 where the active layer of the middle transistor of the pixel driving circuit is located; or, as shown in Figure 8 , the first conductive layer P2 of the shielding unit multiplexed as the first line segment can also be located between the light emitting element 40 and the third metal layer P6 for setting the second signal line (Data), at this time, in order to facilitate the design of the first via H11, the corresponding lap joint structure can be set in the third metal layer P6 where the second signal line is located; or, the first conductive layer of the shielding unit multiplexed as the first line segment can also be provided between other functional film layers, which is not limited in the embodiment of the application.

[0080] It can be understood that, as shown in Figure 5As shown, the display panel can further include a first metal layer P4 for setting the gate of the driving transistor T, a second metal layer P5 for setting the first plate of the storage capacitor Cst, and an anode metal layer P7, a light emitting layer P8 and a cathode layer P9 for setting the anode 41, the light emitting layer 43 and the cathode 42 of the light emitting element 40 respectively; in addition, the display panel can further include an insulating layer between two adjacent functional film layers, such as the insulating layer P23 between the first conductive layer P2 and the semiconductor layer P3, the insulating layer P34 between the semiconductor layer P3 and the first metal layer P4, the insulating layer P45 between the first metal layer P4 and the second metal layer P5, the insulating layer P56 between the second metal layer P5 and the third metal layer P6, the planarization layer P67 between the third metal layer P6 and the anode metal layer P7, and the pixel definition layer P79 for defining the position of the light emitting element 40. Alternatively, when the first conductive layer P2 of the shielding unit multiplexed as the first line segment is located between the light emitting element 40 and the third metal layer P6 for setting the second signal line (Data), the insulating layer P62 is provided between the third metal layer P6 and the first conductive layer P2, and the planarization layer P27 is provided between the first conductive layer P2 and the anode metal layer P7. Figure 5 Different from the above, as shown in Figure 8 , the third metal layer P6 and the first conductive layer P2 are provided with an insulating layer P62, and the first conductive layer P2 and the anode metal layer P7 have a planarization layer P27.

[0081] It should be noted that, Figure 5 and Figure 8 only the relative position relationship between the film layers is exemplarily shown, and the relative position relationship between the film layers in the embodiments of the present application can be exchanged on the basis of meeting the design requirements, and after the film layers are exchanged, the corresponding insulating layer can be set according to the actual needs. The following is only an exemplary description of the functional film layers involved in the embodiments of the present application, and those skilled in the art can understand that an insulating layer needs to be provided between any two functional layers, and the setting method of the insulating layer will not be described again.

[0082] It can be understood that the above exemplary description of the embodiments of the present application is taken by the first signal line as the positive power voltage signal line, and when the first signal line is electrically connected to the source or drain of the first transistor in the pixel driving circuit, the first signal line can also be a data signal line.

[0083] Optionally, Figure 9 is a partial top view structure schematic diagram of still another display panel provided by the embodiments of the present application, Figure 10 is a sectional structure schematic diagram along the B-B section in Figure 9 , which is combined with reference to Figure 9 and Figure 10When the first signal line 21 is a data signal line Data, the second signal line 22 can be a positive power voltage signal line PVDD; at this time, when at least part of the shielding unit 30 is multiplexed as the data signal line Data electrically connected with the first type of pixel driving circuit (1011, 1012), compared with the prior art, the position originally used for setting the data signal line Data electrically connected with the first type of pixel driving circuit (1011, 1012) in the third metal layer P6 where the second signal line 22 (PVDD) is located is vacated, so that the first type of pixel driving circuit 1011 (or 1012) and the second signal line PVDD electrically connected therewith can be moved in the +X direction, thereby reducing the distance between the two adjacent second signal lines PVDD, and the reduced scale can be determined according to the width of the original data signal line Data; wherein when the width of the positive power voltage signal line PVDD in the prior art is the same as or similar to the width of the data signal line Data, the ratio between the distance L1 between the second signal lines PVDD respectively electrically connected with the adjacent two first type of pixel driving circuits (1011 and 1012) and the width L2 of the second signal line PVDD can also be 6≤L1 / L2≤8.

[0084] Optionally, continuing to combine reference Figure 9 and Figure 10 When the first signal line 21 is a data signal line Data, the at least one first transistor T can include a data writing transistor M2; the pixel driving circuit 10 further includes a driving transistor T; the data writing transistor M2 is used to write the data signal transmitted by the data signal line Data to the gate of the driving transistor T; at this time, when the first type of pixel driving circuits are arranged in sequence along the row direction X of the pixel driving circuit 10 and the adjacent two first type of pixel driving circuits are respectively the first pixel driving circuit 1011 and the second pixel driving circuit 1012, along the first direction Y', the first via H12 of the data writing transistor M2 electrically connected with the first pixel driving circuit 1011 and the active layer Ts of the driving transistor T of the second pixel driving circuit 1012 overlap; wherein the first direction Y' is parallel to the plane where the substrate P1 is located and has a first included angle with the column direction Y of the pixel driving circuit 10.

[0085] Specifically, at least part of the shielding unit 30 is reused as a data signal line Data electrically connected with the first type of pixel driving circuit, that is, the data signal line Data is arranged in the first conductive layer P1, so as to leave the position originally used for arranging the data signal line Data in the third metal layer P6, so as to reduce the distance between two adjacent first type of pixel driving circuits (1011, 10112), and as the distance between the two adjacent first type of pixel driving circuits (1011 surrounding 1012) is shortened, the distance between the devices in the two adjacent first type of pixel driving circuits (1011 and 1012) is shortened, until the areas where the two adjacent first type of pixel driving circuits (1011 and 1012) are located are overlapped; at this time, along the first direction Y', the first via hole H1 electrically connected with the data writing transistor M2 of the first pixel driving circuit 1011 has an overlap with the active layer Ts of the driving transistor T in the second pixel driving circuit 1012, and the active layer Ts specifically refers to the area of the active layer of the driving transistor T which overlaps with the gate of the driving transistor T in the direction perpendicular to the plane where the substrate base plate P1 is located, for example, the area of the “several” active layer of the driving transistor T; at the same time, the pixel driving circuit 10 usually further includes a storage capacitor Cst electrically connected with the gate of the driving transistor T, and the storage capacitor Cst is used for storing the gate potential of the driving transistor T, and one plate (second plate) of the storage capacitor Cst is reused as the gate of the driving transistor T, so that along the first direction, the first via hole H12 electrically connected with the data writing transistor M2 in the first pixel driving circuit 1011 also has an overlap with the storage capacitor Cst. In this way, by arranging the data signal line Data electrically connected with the first type of pixel driving circuit (1011, 1012) in the first conductive layer P2, the area between the first type of pixel driving circuit (1011, 1012) and the signal line electrically connected therewith can be reduced, thereby facilitating the improvement of the resolution of the display panel, and at the same time, the high-transmittance light transmission and display requirements can be met.

[0086] The first direction Y' is a direction having a smaller included angle (first included angle) with the column direction Y of the pixel driving circuit 10, and the first included angle only needs to satisfy that after at least part of the shielding unit 30 is reused as the data signal line Data, the adjacent two pixel driving circuits have an overlap, so that the total area of the areas where the adjacent several pixel driving circuits are located is reduced; for example, the first direction Y' can be approximately parallel to the column direction Y of the pixel driving circuit 10.

[0087] It should be noted that, Figure 10 The accompanying drawings are only exemplary for the embodiments of the present application, Figure 10 In the embodiment of the present application, as shown inFigure 11 As shown, the first conductive layer P2 where the shielding unit 30 multiplexed as the data signal line Data is also located between the film layer P6 where the second signal line (the positive power voltage signal line PVDD) is located and the light emitting element 40, at this time, for the convenience of the design of the first via hole H12, the structure in the film layer P6 can be used as a lap joint structure. Alternatively, the position of the film layer where the shielding unit multiplexed as the data signal line is located can also be set according to the actual situation, and the embodiments of the present application do not make specific limitations thereto.

[0088] It can be understood that the above description is continued in combination with reference to Figure 9 and Figure 10 When the first signal line 21 is the data signal line Data, the signal transmitted by the first signal line is a variable voltage signal, at this time, any two first shielding structures multiplexed as the first line segment 211 in the first conductive layer P1 should be insulated from each other to prevent signal crosstalk.

[0089] Correspondingly, due to the mutual insulation of any two adjacent first line segments 211 in the first conductive layer P1, there will be a gap between any two adjacent first line segments in the first conductive layer P1; at this time, in order to prevent the gap from affecting the shielding effect of the shielding unit 30, other shielding structures can be arranged in the film layer thereof to fill the gap between any two adjacent first line segments.

[0090] Exemplarily, the above description is continued in combination with reference to Figure 9 and Figure 10 When there is a gap between any two adjacent first line segments 211 in the first conductive layer P2, a third shielding structure can be arranged in the anode metal layer P7 used to arrange the anode of the light emitting element 40, and the third shielding structure is used to fill the gap between the two adjacent first line segments 211 to improve the shielding effect of the shielding unit 30.

[0091] Exemplarily, Figure 12 is another partial top view structure schematic diagram of a display panel provided by the embodiments of the present application. In combination with reference to Figure 10 and Figure 12 The pixel driving circuit 10 usually further includes a storage capacitor Cst, the first plate of the storage capacitor Cst is usually located in the second metal layer P5, in addition to this, the second metal layer P5 can further include the second shielding structure 3021 of the shielding unit 30, and in the direction Z of the plane where the vertical substrate P1 is located, the second shielding structure 3021 and the gap of the first shielding structure 211 located in the first conductive layer P2 have an overlap; in this way, it can be ensured that the shielding unit 30 can play a shielding role for each position of the pixel driving circuit 10.

[0092] It should be noted that the first shielding structure located at the second metal layer P5 can exist simultaneously with the third shielding structure located at the anode metal layer P7, or only one of them can be set, and the embodiments of the present application do not make specific limitations thereon.

[0093] It can be understood that the above-mentioned signal line extending along the column direction of the pixel driving circuit is exemplarily described by taking the first signal line as an example, and when the first signal line is electrically connected to the source or drain of the first transistor in the pixel driving circuit, the first signal line can also be a signal line extending along the row direction of the pixel driving circuit.

[0094] Optionally, Figure 13 is a schematic diagram of a partial top view structure of another display panel provided by the embodiments of the present application, Figure 14 is a schematic diagram of a cross-sectional structure along the C-C section in Figure 13 is a schematic diagram of a cross-sectional structure along the C-C section in Figure 13 and Figure 14 As shown in FIG. 1 and FIG. 2, the display panel further includes a semiconductor layer P3 located at one side of the substrate P1; the semiconductor layer P3 includes an active layer of the first transistor T1; a first metal layer P4 located at a side of the semiconductor layer P3 away from the substrate P1; the first metal layer P4 includes a plurality of third signal lines 23; in a direction perpendicular to the plane where the substrate P1 is located, a position of the third signal line 23 in the third signal line 23 that overlaps with the active layer of the first transistor T1 is a gate of the first transistor T1; the first transistor T1 of at least part of the pixel driving circuit 10 in the same row shares the third signal line 23 and the first signal line 21.

[0095] Specifically, since the first signal line 21 extends along the row direction of the pixel driving circuit 10 due to the fact that at least part of the pixel driving circuit 10 in the same row shares the first signal line 21, when at least part of the shielding unit 30 is multiplexed by the first line segment 211 of the first signal line 21 extending along the row direction, a position originally used for arranging the first line segment 211 can be left empty in the column direction Y of the pixel driving circuit 10, so that the pixel driving circuit 10 can be compressed in the column direction Y of the pixel driving circuit 10, thereby reducing the area of the region where the pixel driving circuit is located, which is conducive to high resolution of the display panel, and is conducive to light transmission and display requirements of the high light transmission area.

[0096] It can be understood that when the first signal line is electrically connected to the source or drain of the first transistor and extends along the row direction of the pixel driving circuit, the signal line can be, for example, a reset signal line electrically connected to the initialization transistor and / or the reset transistor.

[0097] Wherein, continue to combine with reference to Figure 13 and Figure 14In some embodiments, the signals transmitted by the reset signal lines Ref are usually the same signals, so that the pixel driving circuits 10 can share the reset signal lines Ref. In this case, the film layer P2 can be a non-patterned whole layer structure, or the film layer P2 can include a plurality of shielding sub-units, each of which can overlap with a plurality of first-type pixel driving circuits 101, so that the plurality of pixel driving circuits 101 can share the reset signal lines Ref. In this way, the shielding performance of the shielding unit 30 can be met, and the reset signal lines Ref electrically connected to the first-type pixel driving circuits 101 can have a larger cross-sectional area, so that the loss of the signals transmitted by the reset signal lines Ref can be reduced, thereby facilitating the improvement of the display effect of the display panel.

[0098] Optionally, the above description is continued by referring to Figure 13 and Figure 14 When the at least one first transistor T1 includes an initialization transistor M4, the first signal line 21 can be a reset signal line electrically connected to the initialization transistor M4. Correspondingly, the pixel driving circuit 10 further includes a storage capacitor Cst; the initialization transistor M4 and the storage capacitor Cst are arranged in sequence along the column direction Y of the pixel driving circuit 10; the first metal layer P4 includes a second plate of the storage capacitor Cst; the second electrode of the initialization transistor M4 and the second plate of the storage capacitor Cst are electrically connected to the first node N1; in this case, the display panel further includes a second metal layer P5 located on the side of the first metal layer P4 away from the substrate P1; the second metal layer P5 includes a first plate of the storage capacitor Cst; a third metal layer P6 located on the side of the second metal layer P5 away from the substrate P1; the third metal layer P6 includes a plurality of fourth signal lines 24; the first plate of the storage capacitor Cst is electrically connected to the fourth signal line 24 through a third via hole H3, and the storage capacitors Cst of at least some pixel driving circuits 10 located in the same column share the fourth signal line 24; the display panel further includes a first conductive layer P2; the first conductive layer P2 includes a first line segment 211; the first conductive layer P2 is located between the substrate P1 and the semiconductor layer P3, wherein the first via hole H13 electrically connected to the initialization transistor M4 is located on the side of the third signal line 23 close to the storage capacitor Cst.

[0099] Specifically, by multiplexing at least part of the shielding unit 30 as the reset signal line Ref electrically connected with the initialization transistor M4 in the first type of pixel driving circuit 101, the reset signal line Ref electrically connected with the initialization transistor M4 in the first type of pixel driving circuit 101 is located in the first conductive layer P2, which can free up the position originally used for setting the reset signal line Ref, that is, compared with the prior art, the area of the region where the first type of pixel driving circuit 101 and the signal line electrically connected therewith is located can be reduced in the column direction Y of the pixel driving circuit 10; for example, when the original reset signal line Ref has a line width of 1 μm ~ 4 μm along the column direction of the pixel driving circuit 10, and the pixel driving circuit 10 and the signal line electrically connected therewith have a width of W μm along the row direction X of the pixel driving circuit 10, the area of the region where the first type of pixel driving circuit 101 and the signal line electrically connected therewith is located can be reduced by at least W μm 2 ~ 4W μm 2 Meanwhile, by arranging the first conductive layer P2 multiplexed as the reset signal line Ref between the substrate P1 and the semiconductor layer P3, the first via H13 can be directly arranged between the first conductive layer P2 and the semiconductor layer P3, that is, the electrical connection between the first electrode of the initialization transistor M4 and the reset signal line Ref can be realized, thereby facilitating the simplification of the process on the basis of improving the resolution and the light transmission area of the high light transmission area of the display panel.

[0100] It should be noted that, Figure 14 only the case where the first conductive layer P2 is located between the substrate P1 and the semiconductor layer P3 is exemplarily shown in the drawings, Figure 14 and in the embodiments of the present application, the first conductive layer P2 can also be between the semiconductor layer P3 and the third metal layer P6.

[0101] For example, as shown in Figure 15 , the first conductive layer P2 is located between the second metal layer P5 and the third metal layer P6, at which time the first via H13 can be directly arranged between the first conductive layer P2 and the semiconductor layer P3, that is, the electrical connection between the first electrode of the initialization transistor M4 and the reset signal line Ref can be realized, thereby facilitating the simplification of the process.

[0102] It can be understood that, in addition to the above-mentioned film layer arrangement, other film layer arrangements can also be used, as long as the electrical connection between the first electrode of the initialization transistor and the reset signal line can be realized and the process can be simplified, those skilled in the art can think of them on the basis of the description in the present application, which all belong to the protection scope of the present application, and will not be repeated here.

[0103] It should be noted that when the distance between the first conductive layer and the semiconductor layer is far, in order to facilitate the setting of the first via hole, the existing film layer between the first conductive layer and the semiconductor layer can also be used to form a lap joint structure, so as to split the first via hole into two sub via holes, thereby reducing the difficulty of setting the first via hole.

[0104] Optionally, Figure 16 is another partial top view structure schematic diagram of a display panel provided by an embodiment of the present application, Figure 17 is a cross-sectional structure schematic diagram along the D-D section of Figure 16 . In combination with Figure 16 and Figure 17 , when the at least one first transistor T1 includes the initialization transistor M4, the pixel driving circuit 10 further includes a storage capacitor Cst; at this time, the initialization transistor M4 and the storage capacitor Cst are arranged in sequence along the column direction Y of the pixel driving circuit 10; the first metal layer P4 includes a second plate of the storage capacitor Cst; the second electrode of the initialization transistor M4 and the second plate of the storage capacitor Cst are electrically connected to the first node N1; correspondingly, the display panel further includes a second metal layer P5 located on the side of the first metal layer P4 away from the substrate P1; the second metal layer P5 includes a first plate of the storage capacitor Cst; a third metal layer P6 located on the side of the second metal layer P5 away from the substrate P1; the third metal layer P6 includes a plurality of fourth signal lines 24 and a plurality of first lap joint structures P601; the first plate of the storage capacitor Cst is electrically connected to the fourth signal line 24 (PVDD) through a third via hole H3, and the storage capacitors Cst of at least part of the pixel driving circuits 10 located in the same column share the fourth signal line 24 (PVDD); a first conductive layer P2 located on the side of the third metal layer P6 away from the substrate P1; the first conductive layer P2 includes a first line segment 211; the first via hole H13 electrically connected to the initialization transistor M4 includes a first sub via hole H131 and a second sub via hole H132; the first electrode of the initialization transistor M4 is electrically connected to the first lap joint structure P601 through the first sub via hole H131, and the first lap joint structure P601 is electrically connected to the first line segment 211 through the second sub via hole H132; wherein the first sub via hole H131 is located on the side of the third signal line 23 close to the storage capacitor Cst, and the second sub via hole H132 is located on the side of the third signal line 23 away from the storage capacitor Cst.

[0105] Thus, when the first conductive layer P2 is located on the side of the third metal layer P6 away from the substrate P1, the first conductive layer P2 has a relatively long distance from the semiconductor layer P3, and the first overlap structure P601 can be arranged in the third metal layer P6 to divide the first via hole H13 into two sub-via holes (the first sub-via hole H131 and the second sub-via hole H132), thereby reducing the punching depth of a single via hole and the difficulty of punching. Meanwhile, the first overlap structure P601 is arranged in the same layer as the fourth signal line 24, which can simplify the process of the display panel, reduce the cost of the display panel, and facilitate low-cost display panels. In addition, the first sub-via hole H131 and the second sub-via hole H132 are arranged on opposite sides of the third signal line 23, so that the first sub-via hole H131 and the second sub-via hole H132 do not affect each other.

[0106] In the above, the first signal line is a reset signal line electrically connected to the first electrode of the initialization transistor. In the embodiment of the present application, when the reset signal line electrically connected to the initialization transistor and the reset signal line electrically connected to the reset transistor are different reset signal lines, the first signal line can also be the reset signal line electrically connected to the reset transistor.

[0107] Optionally, Figure 18 is another partial top view structure schematic diagram of a display panel provided by the embodiment of the present application, Figure 19 is a cross-sectional structure schematic diagram along the direction of E-E in Figure 18 , and Figure 18 and Figure 19 , the display panel further includes a plurality of arrayed light emitting elements 40, each light emitting element 40 can emit light under the driving of the corresponding pixel driving circuit 10. At least one first transistor T1 includes a reset transistor M5; the second electrode of the reset transistor M5 is electrically connected to the anode of the light emitting element 40 through the fourth via hole H4; at this time, in the direction perpendicular to the plane where the substrate P1 is located, the position of the active layer M5S of the reset transistor M5 overlapping with the third signal line 23 is the channel region M5g of the reset transistor M5; the region M5d of the active layer M5S of the reset transistor M5 from the channel region M5g of the reset transistor M5 to the first via hole H14 electrically connected to the reset transistor M5 and the region M5s from the channel region M5g of the reset transistor M5 to the fourth via hole H4 electrically connected to the reset transistor M5 are non-channel regions of the reset transistor M5; the area ratio Sq of the non-channel region (M5s and M5d) of the reset transistor M5 to the channel region M5g of the reset transistor M5 is 1.5≤Sq≤2.

[0108] Specifically, when the first transistor T1 includes the reset transistor M5, the first signal line 21 electrically connected with the source or the drain of the reset transistor M5 is the reset signal line Ref'; at this time, by multiplexing at least part of the shielding unit 30 as the reset signal line Ref' electrically connected with the reset transistor M5 in the first pixel driving circuit 101, the size of the active layer of the reset transistor M5 in the column direction Y of the pixel driving circuit 10 can be shortened at this time, so that the ratio between the area of the non-channel region M5d and M5s of the reset transistor M5 and the area of the channel region M5g thereof is reduced to the range of 1.5-2, and compared with the prior art, the size of the active layer of the reset transistor M5 in the column direction Y of the pixel driving circuit 10 can be relatively shortened by 30%-60%; in this way, when at least part of the shielding unit 30 is multiplexed as the reset signal line Ref' electrically connected with the reset transistor M5, it is beneficial to reduce the size of the reset transistor M5 to reduce the area of the region where the pixel driving circuit 10 is located, so as to relatively increase the number of pixel driving circuits 10 provided in the display panel, which is beneficial to the high resolution of the display panel, and can meet the display requirements of the high light transmission area.

[0109] Optionally, continue to combine with reference to Figure 18 and Figure 19 When the at least one first transistor T1 includes the reset transistor M5, the pixel driving circuit 10 can further include light-emitting control transistors (M1 and M6) and a driving transistor T; and the driving transistor T, the light-emitting control transistors (M1 and M6) and the reset transistor M5 are arranged in sequence along the column direction Y of the pixel driving circuit 10; the light-emitting control transistors include a first light-emitting control transistor M1 and a second light-emitting control transistor M6; correspondingly, the display panel further includes a third metal layer P6 located on the side of the first metal layer P4 away from the substrate P1; the third metal layer P6 includes a plurality of fourth signal lines 24; a display layer (P7, P8 and P9) located on the side of the third metal layer P6 away from the substrate; the display layer (P7, P8 and P9) includes a plurality of arrayed light-emitting elements 40; the display panel further includes a first conductive layer P2; the first conductive layer P2 includes a first line segment 211; the first conductive layer P2 is located between the substrate P1 and the semiconductor layer P3. At this time, the first electrode of the first light-emitting control transistor M1 is electrically connected with the fourth signal line 24 through a fifth via hole H5; the second electrode of the first light-emitting control transistor M1 is electrically connected with the first electrode of the driving transistor T; the first electrode of the second light-emitting control transistor M6 is electrically connected with the second electrode of the driving transistor T, the second light-emitting control transistor M6 and the reset transistor M5 are electrically connected to the second node N2, and are both electrically connected with the anode of the light-emitting element 40 through the fourth via hole H4 at the second node N2; the first via hole H14 electrically connected with the reset transistor M5 is located on the side of the third signal line 23 away from the fourth via hole H4 and the fifth via hole H5.

[0110] Therefore, by arranging the first conductive layer P2 between the substrate P1 and the semiconductor layer P3, the distance between the first conductive layer P2 and the semiconductor layer P3 can be shortened, so that the first via H13 can be directly arranged between the first conductive layer P2 and the semiconductor layer P3, and the electrical connection between the reset transistor M5 and the reset signal line Ref' can be realized, thereby facilitating the simplification of the process on the basis of improving the resolution and the light transmittance area of the display panel.

[0111] It should be noted that, Figure 19 The drawings are only exemplary for the embodiments of the present application, Figure 19 The first conductive layer P2 is arranged between the substrate P1 and the semiconductor layer P3 in the drawings, but in the embodiments of the present application, the first conductive layer P2 can also be arranged between the semiconductor layer P3 and the third metal layer P6.

[0112] For example, as shown in FIG. 6, Figure 20 The first conductive layer P2 is arranged between the second metal layer P5 and the third metal layer P6, and the first via H14 can be directly arranged between the first conductive layer P2 and the semiconductor layer P3, so that the electrical connection between the first electrode of the reset transistor M5 and the reset signal line Ref' can be realized, thereby facilitating the simplification of the process.

[0113] It can be understood that, in addition to the above-mentioned film layer arrangement, other film layer arrangements can also be used, as long as the electrical connection between the first electrode of the reset transistor M5 and the reset signal line Ref' can be realized and the process can be simplified, and the skilled in the art can think of them on the basis of the description in the present application, which all belong to the protection scope of the present application, and will not be repeated here.

[0114] It should be noted that, when the distance between the first conductive layer and the semiconductor layer is far, in order to facilitate the arrangement of the first via, the existing film layer between the first conductive layer and the semiconductor layer can also be used as a lap joint structure to split the first via into two sub vias, thereby reducing the difficulty of arranging the first via.

[0115] Optionally, Figure 21 is another partial top view of a display panel provided by the embodiments of the present application, Figure 22 is a cross-sectional structure schematic view along the F-F section in Figure 21 The first conductive layer P2 is arranged between the substrate P1 and the semiconductor layer P3 in the drawings, but in the embodiments of the present application, the first conductive layer P2 can also be arranged between the semiconductor layer P3 and the third metal layer P6. Figure 21 and Figure 22When the at least one first transistor T1 includes the reset transistor M5, the pixel driving circuit 10 can further include a light-emitting control transistor (M1 and M6) and a driving transistor T; and the driving transistor T, the light-emitting control transistor (M1 and M6) and the reset transistor M5 are arranged in sequence along the column direction Y of the pixel driving circuit 10; the light-emitting control transistor includes a first light-emitting control transistor M1 and a second light-emitting control transistor M6. The display panel further includes a third metal layer P6 located on the side of the first metal layer P4 away from the substrate P1; the third metal layer P6 includes a plurality of fourth signal lines 24 and a plurality of second overlap structures P602; a display layer (P7, P8 and P9) located on the side of the third metal layer P6 away from the substrate P1; the display layer (P7, P8 and P9) includes a plurality of arrayed light-emitting elements; and a first conductive layer P2 located between the display layer (P7, P8 and P9) and the third metal layer P6; the first conductive layer P2 includes the first line segment 211. Correspondingly, the first electrode of the first light-emitting control transistor M1 is electrically connected to the fourth signal line 24 through the fifth via hole H5, and the second electrode of the first light-emitting control transistor M1 is electrically connected to the first electrode of the driving transistor T; the first electrode of the second light-emitting control transistor M6 is electrically connected to the second electrode of the driving transistor T, and the second light-emitting control transistor M6 and the reset transistor M5 are electrically connected to the second node N2 and are both electrically connected to the anode of the light-emitting element 40 through the fourth via hole H4 at the second node N2; at this time, the first via hole H14 electrically connected to the reset transistor M5 includes a third sub-via hole H141 and a fourth sub-via hole H142; the first electrode of the reset transistor M5 is electrically connected to the second overlap structure P602 through the third sub-via hole H141, and the second overlap structure P602 is electrically connected to the first line segment 211 through the fourth sub-via hole H142; wherein the third sub-via hole H141 is located on the side of the third signal line 23 away from the fourth via hole H4; in the direction Z perpendicular to the plane where the substrate P1 is located, the fourth sub-via hole H142 overlaps the area between the fourth via hole H4 and the fifth via hole H5.

[0116] Thus, when the first conductive layer P2 is located between the display layer (P7, P8, and P9) and the third metal layer P6, there is a relatively large distance between the first conductive layer P2 and the semiconductor layer P3. At this time, a second overlapping structure P602 can be set in the third metal layer P6 to divide the first via H14 into two sub-vias (the third sub-via H141 and the fourth sub-via H142), thereby reducing the drilling depth of a single via and reducing the drilling difficulty. At the same time, setting the second overlapping structure P602 in the same layer as the fourth signal line 24 can simplify the manufacturing process of the display panel, reduce the cost of the display panel, and help reduce the cost of the display panel. Furthermore, by placing the third sub-via H141 and the fourth sub-via H142 on opposite sides of the third signal line 23, the third sub-via H141 and the fourth sub-via H142 do not affect each other. When the area between the fourth sub-via H142 and the fourth via H4 and the fifth via H5 overlaps, the space utilization can be improved, which is beneficial to further reduce the area of ​​the pixel driving circuit 10.

[0117] It should be noted that the above description exemplifies the use of multiplexing shielding units for two reset signal lines electrically connected to the initialization transistor and reset transistor of the same pixel driving circuit; however, in the embodiments of this invention, both reset signal lines electrically connected to the initialization transistor and reset transistor of the same pixel driving circuit can reuse shielding units, such as... Figure 23 As shown, when the reset signal lines Ref and Ref', which are electrically connected to the initialization transistor and reset transistor of the same pixel driving circuit 10 respectively, both reuse the shielding unit 30, the size of the area where the pixel driving circuit 10 is located can be further reduced.

[0118] It is understood that the above example of using the first signal line as a signal line electrically connected to the source or drain of the transistor in the pixel driving circuit is used to illustrate the technical solution of the present invention. However, in the embodiments of the present invention, the first signal line can also be a signal line electrically connected to the gate of the transistor in the pixel driving circuit.

[0119] Optional, Figure 24 This is a partial top view structural diagram of another display panel provided in an embodiment of the present invention. Figure 25 It is along Figure 24 A schematic diagram of the cross-sectional structure of section JJ, in conjunction with reference. Figure 24 and Figure 25The pixel driving circuit 10 comprises at least one third transistor T3; the pixel driving circuit 10 electrically connected with the first segment 211 of the first signal line 21 is a first type pixel driving circuit 101; the gate of the third transistor T3 of the first type pixel driving circuit 101 is electrically connected with the first segment 211 through the first via hole H15; the gates of any two third transistors T3 of the same first type pixel driving circuit 101 are insulated from each other.

[0120] Specifically, by insulating the gates of any two third transistors T3 of the same first type pixel driving circuit 101 from each other, only the gate structure of the third transistor T3 is reserved in the film layer P4 where the gate of the third transistor T3 is located, and the first segment 211 electrically connected with the third transistor T3 is arranged in the film layer P2 where the shielding unit 30 is located. Compared with the case that the gate of the third transistor T3 and the signal line electrically connected with the gate of the third transistor T3 are both arranged in the film layer where the gate of the third transistor T3 is located, the region between the two third transistors T3 whose gates are insulated from each other can be emptied, so that other structures of the first type pixel driving circuit 101 can be moved into the region, thereby the size of the first type pixel driving circuit can be compressed, which is conducive to the high resolution of the display panel and the light transmission and display requirements of the high light transmission area.

[0121] Optionally, continuing to combine with reference to Figure 24 and Figure 25 The at least one third transistor T3 can comprise a data writing transistor M2 and a threshold compensation transistor M3; the pixel driving circuit 10 further comprises a driving transistor T and an initialization transistor M4; the data writing transistor M2 and the threshold compensation transistor M3 are arranged in sequence along the row direction X of the pixel driving circuit 10, and the initialization transistor M4, the threshold compensation transistor M3 and the driving transistor T are arranged in sequence along the column direction Y of the pixel driving circuit 10; the second electrode of the data writing transistor M2 is electrically connected with the first electrode of the driving transistor T; the first electrode of the threshold compensation transistor M3 is electrically connected with the second electrode of the driving transistor T; the second electrode of the initialization transistor M4, the second electrode of the threshold compensation transistor M3 and the gate of the driving transistor T are electrically connected with the first node N1; the data writing transistor M3 and the threshold compensation transistor M3 of at least part of the pixel driving circuits 10 located in the same row share the first signal line 21 (Scan2); the gate of the data writing transistor M2 and the gate of the threshold compensation transistor M3 in the first type pixel driving circuit 101 are electrically connected with the same first segment 211.

[0122] Specifically, when the at least one third transistor T3 includes the data writing transistor M2 and the threshold compensation transistor M3, the first signal line 21 electrically connected with the data writing transistor M2 and the threshold compensation transistor M3 is the second scan signal line Scan2; by multiplexing at least part 32 of the shielding unit 30 as the second scan signal line Scan2 electrically connected with the gate of the data writing transistor M2 and the threshold compensation transistor M3 of the first type of pixel driving circuit 101, the first node N1 can be arranged in the region between the threshold compensation transistor M3 and the data writing transistor M2 of the same first type of pixel driving circuit 101, that is, compared with the prior art, part of the structure of the first node N1 can be moved to one side of the driving transistor T, so that the initialization transistor M4 is moved, and then in the column direction Y of the pixel driving circuit 10, the size of the first type of pixel driving circuit 101 can be reduced.

[0123] Optionally, continuing to combine reference Figure 24 and Figure 25 , the display panel 100 includes a semiconductor layer P3 located on one side of the substrate P1; the semiconductor layer P3 includes the active layer of the data writing transistor M2, the threshold compensation transistor M3, the initialization transistor M4 and the driving transistor T; the active layer includes a channel region and a first electrode and a second electrode located on both sides of the channel region; a first metal layer P4 located on the side of the semiconductor layer P3 away from the substrate; the first metal layer P4 includes the gate of the data writing transistor M2, the threshold compensation transistor M3, the initialization transistor M4 and the driving transistor T; in the direction Z perpendicular to the plane where the substrate P1 is located, the position of the active layer overlapping with the gate is the channel region of the active layer; the first node N1 includes a first part N11 and a second part N12; the first part N11 extends along the row direction X of the pixel driving circuit 10, and is used for electrically connecting the second electrode of the threshold compensation transistor M3 and the second electrode of the initialization transistor M4; the second part N12 extends along the column direction Y of the pixel driving circuit 10, and is used for electrically connecting the first part N11 and the gate of the driving transistor T; wherein, in the direction Z perpendicular to the plane where the substrate P1 is located, the first part N11 and the second part N12 do not overlap with the gate.

[0124] Specifically, when the first sub-part N11 is arranged in the same layer as the second electrode of the threshold compensation transistor M3 and the second electrode of the initialization transistor M4, the second electrode of the initialization transistor M4, the first sub-part N11 and the second electrode of the threshold compensation transistor M3 can be arranged in sequence along the row direction X of the pixel driving circuit 10. Since the second scan signal line Scan2 electrically connected with the gate of the threshold compensation transistor M3 and the data writing transistor M2 of the same first type pixel driving circuit 101 and the gate of the threshold compensation transistor M3 and the data writing transistor M2 are arranged in different film layers (P2 and P4), when the sub-part of the first sub-part N11 is arranged in the region between the gate of the threshold compensation transistor M3 and the data writing transistor M2, the first sub-part N11 will not overlap with the structure of the film layer where the gate of the threshold compensation transistor M3 and the data writing transistor M2 are located, so that the position of the first sub-part N11 will not form a transistor, thereby preventing the formation of a transistor due to the overlap between the structure of the film layer where the gate of the threshold compensation transistor M3 and the data writing transistor M2 are located and the first sub-part N11, which affects the performance of the pixel driving circuit 10.

[0125] Optionally, the first sub-part N11 is arranged in the region between the gate of the threshold compensation transistor M3 and the data writing transistor M2. Figure 24 and Figure 25 The active layer of the threshold compensation transistor M3 includes a first channel region M3g1 and a second channel region M3g2; in the second direction X', the second electrode of the initialization transistor M4 and the first sub-part N11 overlap with the first channel region M3g1 and / or the second channel region M3g2; wherein the second direction X' is parallel to the plane where the substrate P1 is located and has a second included angle with the row direction X of the pixel driving circuit 10.

[0126] Specifically, since the gate of the threshold compensation transistor M3 and the data writing transistor M2 are insulated from each other, the first sub-part N11 can be arranged in the region between the gate of the threshold compensation transistor M3 and the data writing transistor M2, i.e. compared with the prior art, the first sub-part N11 and the second electrode of the initialization transistor M4 are both moved to one side of the driving transistor T, so that when the distance between the first sub-part N11 and the second electrode of the initialization transistor M4 and the driving transistor T is Y1, the distance between the first channel region M3g1 of the threshold compensation transistor M3 and the driving transistor is Y2, and the distance between the second channel region M3g2 of the threshold compensation transistor M3 and the driving transistor is Y3, Y1 can be between Y2 and Y3, or Y1 is equivalent to Y2, or Y1 is equivalent to Y3, so that in the direction (second direction X') having a smaller included angle (second included angle) with the row direction X of the pixel driving circuit 10, the second electrode of the initialization transistor M4 and the first sub-part N11 can overlap with the first channel region Mg1 and / or the second channel region Mg2. The second included angle can be a smaller included angle, so that the second direction X' is approximately parallel to the row direction X of the pixel driving circuit 10.

[0127] Optionally, continue to combine reference Figure 24 And Figure 25 When the display panel includes a third metal layer P6 located on the side of the first metal layer P4 away from the substrate P1, the third metal layer P6 can include a second part N12; and the first part N11 is located in the semiconductor layer P3; one end of the second part N12 is electrically connected with the first part N11 through the seventh via H7, and the other end of the second part N12 is electrically connected with the gate of the driving transistor T through the eighth via H8.

[0128] Specifically, by arranging the first part N11 and the second part N12 of the first node N1 in the semiconductor layer P3 and the third metal layer P6 respectively, compared with the prior art, only the structure of the semiconductor layer P3 for arranging the first part N11 needs to be changed, and the structure of the third metal layer P6 for arranging the second part N12 and the structure of the driving transistor T can remain unchanged, which is beneficial to simplify the design of the pixel driving circuit.

[0129] It should be noted that, Figure 24 And Figure 25 The accompanying drawings are only exemplary for the embodiments of the present application, Figure 24 And Figure 25 Only the first part N11 and the second part N12 are respectively located in different film layers, and in the embodiments of the present application, the first part N11 and the second part N12 can be arranged in the same film layer.

[0130] Optionally, Figure 26 is another partial top view structure schematic diagram of a display panel provided by the embodiments of the present application, Figure 27 is a sectional structure schematic diagram along the I-I section of Figure 26 Combine reference Figure 26 And Figure 27 The first part N11 and the second part N12 are both located in the semiconductor layer P3; one end of the second part is electrically connected with the first part, and the other end of the second part is electrically connected with the gate of the driving transistor T through the sixth via H6; wherein when the second channel region M3g2 is located on the side of the first channel region M3g1 close to the driving transistor T, the first part N11 is located on the side of the first channel region M3g1 close to the driving transistor T.

[0131] Therefore, by arranging the first sub-part N11 and the second sub-part N12 in the same film layer (semiconductor layer P3), the first sub-part N11 and the second sub-part N12 can be formed by the same process under the same process, and the first sub-part N11 and the second sub-part N12 can be directly integrated into a structure without the need of arranging a corresponding via for electrically connecting the first sub-part N11 and the second sub-part N12, thereby simplifying the process and reducing the cost of the display panel. Meanwhile, by arranging the first sub-part N11 on the side of the first channel M3g1 close to the driving transistor T, the area on the side of the first sub-part N11 away from the driving transistor T can be left empty for arranging other structures of the first type of pixel driving circuit 101, thereby facilitating the further reduction of the first type of pixel driving circuit 101.

[0132] It should be noted that, since the second electrode of the threshold compensation transistor M3 is electrically connected to the gate of the driving transistor T, and the driving transistor T generates a driving current according to the potential of the gate thereof in the light-emitting stage to drive the light-emitting element 40 to present a corresponding brightness, the gate potential of the driving transistor T directly affects the light-emitting brightness of the light-emitting element 40. Therefore, to prevent the leakage current of the threshold compensation transistor M3 in the light-emitting stage from affecting the gate potential of the driving transistor T, the threshold compensation transistor M3 is usually arranged as a transistor with a double-gate structure to make the threshold compensation transistor M3 have a smaller leakage current. That is, the threshold compensation transistor M3 usually includes a first gate and a second gate, and the first gate overlaps the first channel M3g1 thereof, and the second gate overlaps the second channel M3g2 thereof. In the embodiment of the present application, the first gate and the second gate of the threshold compensation transistor M3 can also be two independent structures.

[0133] Optionally, Figure 28 is another partial top view structural schematic diagram of a display panel provided by the embodiment of the present application, as Figure 28 As shown in the figure, when the gate of the threshold compensation transistor M3 includes a first gate G1 and a second gate G2, the first gate G1 overlaps the first channel region, the second gate G2 overlaps the second channel region, and the first gate and the second gate are insulated from each other, the second gate G2 overlaps the active layer of the driving transistor T in the second direction X'.

[0134] Specifically, by independently setting the first gate G1 and the second gate G2 of the same threshold compensation transistor M3, and electrically connecting the first gate G1 and the second gate G2 to the same first line segment 211 through the first vias H151 and H152 respectively, the first gate G1 and the second gate G2 of the same threshold compensation transistor M3 can synchronously receive the second scan signal. At the same time, when the first gate G1 and the second gate G2 of the same threshold compensation transistor M3 are independently set, the area between the first gate G1 and the second gate can be left empty in the film layer where the first gate G1 and the second gate are located, so as to set other structures of the pixel driving circuit. Compared with the prior art, for example, the driving transistor T can be moved to the area between the first gate G1 and the second gate. At this time, along the column direction Y of the pixel driving circuit, the distance between the active layer of the driving transistor T (the "U" shape shown in the figure) and the first gate and the second gate can be shortened. Thus, the second gate G2 can overlap with the active layer of the driving transistor T only in the direction X' with a small offset angle (second included angle) to the row direction X of the pixel driving circuit. The second included angle can be a small angle, in which case the second direction X' is approximately parallel to the row direction X of the pixel driving circuit 10.

[0135] In addition, the pixel driving circuit 10 usually includes a storage capacitor Cst. The second plate of the storage capacitor Cst usually reuses the gate of the driving transistor T. Therefore, when the second gate G2 overlaps with the active layer of the driving transistor T in the second direction X', the second gate G2 will also overlap with the driving storage capacitor Cst in the second direction X'. Even in the row direction X of the pixel driving circuit 10, the second gate G2 can also overlap with the driving storage capacitor Cst.

[0136] It should be noted that the above-mentioned reduction of leakage current of threshold compensation transistor M3 is achieved by setting it to a dual-gate structure; however, in the embodiments of the present invention, the threshold compensation transistor can also be set to a single-gate structure by changing the material of the threshold compensation transistor, such as a single-gate threshold compensation transistor fabricated using LTPO process, to reduce the leakage current of the threshold compensation transistor.

[0137] For example, Figure 29 This is a partial top view structural diagram of another display panel provided in an embodiment of the present invention. Figure 30 It is along Figure 29 A schematic diagram of a cross-sectional structure of section KK in the middle, combined with reference. Figure 29 and Figure 30, the threshold compensation transistor M3 only includes one gate, at this time, the active layer of the threshold compensation transistor M3 can be arranged in the oxide semiconductor P32, and the active layers of other transistors (the driving transistor T, the data writing transistor M2) can be arranged in the low-temperature polysilicon semiconductor layer P31, so that the other transistors have a faster response speed, and under the premise that the threshold compensation transistor M3 is a single-gate structure, the threshold compensation transistor M3 has a smaller leakage current, and the size of the threshold compensation transistor M3 can be reduced, so that the size of the pixel driving circuit 10 including the threshold compensation transistor M3 can be further reduced. At the same time, when the active layer M3g of the threshold compensation transistor M3 is arranged in the oxide semiconductor P32, and the active layer M2g of the data writing transistor M2 is arranged in the low-temperature polysilicon semiconductor layer P31, the channel type of the threshold compensation transistor M3 is different from the channel type of the data writing transistor M2, so that the gate of the threshold compensation transistor M3 and the gate of the data writing transistor M2 need to be respectively electrically connected to different first line segments 321 (Scan21) and 322 (Scan22) through first vias H1511 and H1512 respectively, so as to ensure that the threshold compensation transistor M3 and the data writing transistor M2 can be turned on at the same time under the control of different second scanning signals.

[0138] Correspondingly, the gate metal layer includes a first gate metal layer P410 and a second gate metal layer P420, the first gate metal layer P410 is provided with the gate of the transistor whose active layer such as the data writing transistor M2 is located in the low-temperature polysilicon semiconductor layer P31, and the material of the first metal layer P410 can be, for example, molybdenum material; the second gate metal layer P420 is provided with the gate of the threshold compensation transistor, and the material of the second gate metal layer P420 can include molybdenum material and titanium material; at the same time, because the low-temperature polysilicon semiconductor layer P31 and the oxide semiconductor P32 are located in different film layers, so that the first electrode of the threshold compensation transistor M3 can be electrically connected to the second electrode of the driving transistor T through the lap joint structure P604 located in the third metal layer P6, and the second electrode of the threshold compensation transistor M3 can be electrically connected to the initialization transistor M4 and the first node N1 through the lap joint structure P605 located in the third metal layer P6.

[0139] In addition, when the first signal line is a signal line electrically connected to the gate of the transistor, the first signal line can also be a first scanning signal line electrically connected to the gate of the initialization transistor. Continue to combine Figure 24 and Figure 25As shown, at least one third transistor T3 can further include an initialization transistor M4, the first signal line 21 includes a first scan signal line Scan1 electrically connected to the gate of the initialization transistor M4, at this time, the partial structure 31 of the shielding unit 30 can be reused as the first scan signal line Scan1 electrically connected to the initialization transistor M4, so that the gate of the initialization transistor M4 can be electrically connected to the first scan signal line Scan1 through the first via hole H16, at this time, the area between the gates of the two adjacent initialization transistors M4 can be used to set other structures to further reduce the area of the first type of pixel driving circuit 101.

[0140] Meanwhile, when the part 31 of the shielding unit 30 and the other part 32 of the shielding unit 30 are reused as different scan signal lines (the first scan signal line Scan1 and the second scan signal line Scan2) respectively, since the first scan signal transmitted by the first scan signal line Scan1 and the second scan signal transmitted by the second scan signal line Scan2 have differences, and the first scan signal and the second scan signal are both variable voltage signals, therefore, the two parts 31 and 32 of the shielding unit 30 should be insulated from each other, that is, the two parts 31 and 32 of the shielding unit 30 in the first conductive layer P2 are arranged in a spaced manner, so that there is a gap between the two parts 31 and 32 of the shielding unit 30, which may affect the shielding effect of the shielding unit 30; at this time, without affecting the setting of the devices and signal lines in the display panel, the gap can be filled with the existing film layer in the display panel, for example, in addition to including the first plate of the storage capacitor Cst, the second metal layer P5 can also include a second shielding structure 33, the second shielding structure 33 overlaps with the gap between the two parts 31 and 32 of the shielding unit 30 in the first conductive layer P2, so as to improve the shielding effect of the shielding unit 30.

[0141] It should be noted that, Figure 24 and Figure 25 Only the second shielding structure 33 in the second metal layer P5 is shown by way of example; in the embodiment of the present application, a third shielding structure can also be arranged in the anode metal layer where the anode of the organic light-emitting element is located, and under the premise of being able to meet the shielding demand of the shielding unit, only one of the second shielding structure and the third shielding structure can be retained, or the second shielding structure and the third shielding structure can exist at the same time. In addition, without affecting the setting of other structures in the display panel, shielding structures can also be arranged in other metal film layers to ensure that the shielding unit 30 has good shielding performance.

[0142] It can be understood that the above-mentioned at least one third transistor includes a threshold compensation transistor, a data writing transistor and an initialization transistor, and the first type of pixel driving circuit is exemplarily described in the reduced case. In the embodiment of the present application, when other control transistors requiring a scanning signal are further included in the pixel driving circuit, the at least one third transistor can further include other transistors.

[0143] Optionally, Figure 31 is a schematic diagram of a partial top view of another display panel provided by the embodiment of the present application, Figure 32 is a schematic diagram of a cross-sectional structure along the L-L cross section of the display panel shown in Figure 31 , and Figure 31 and Figure 32 , the at least one third transistor T3 includes a first light-emitting control transistor M1 and a second light-emitting control transistor M6 arranged in sequence along a row direction X of the pixel driving circuit 10, and the pixel driving circuit further includes a driving transistor T; correspondingly, the display panel further includes a plurality of arrayed light-emitting elements 40 and a plurality of fourth signal lines 24; a first electrode of the first light-emitting control transistor M1 is electrically connected to the fourth signal line 24 through a fifth via hole H5, and the first light-emitting control transistor M1 of at least part of the pixel driving circuits 10 in the same column shares the fourth signal line 24; a second electrode of the first light-emitting control transistor M1 is electrically connected to a first electrode of the driving transistor T; a first electrode of the second light-emitting control transistor M6 is electrically connected to a second electrode of the driving transistor T, and the second light-emitting control transistor M6 is electrically connected to an anode of the light-emitting element 40 through a fourth via hole H4; along a second direction X', the fifth via hole H5 and the fourth via hole H4 overlap with a gate electrode of the first light-emitting control transistor M1 and / or a gate electrode of the second light-emitting control transistor M6; wherein the second direction X' is parallel to a plane in which the substrate P1 is located and has a second included angle with the row direction of the pixel driving circuit 10.

[0144] Specifically, by insulating the gates of the first light-emitting control transistor M1 and the second light-emitting control transistor M6 from each other, that is, by making the first light-emitting control transistor M1 and the second light-emitting control transistor M6 independent of each other, a region between the gate of the first light-emitting control transistor M1 and the gate of the second light-emitting control transistor M6 can be provided with other structures; at this time, the fifth via H5 electrically connecting the first light-emitting control transistor M1 and the fourth signal line 24 (PVDD) and the fourth via H4 electrically connecting the second light-emitting control transistor M6 and the anode of the light-emitting element 40 can be arranged in the region between the gate of the first light-emitting control transistor M1 and the gate of the second light-emitting control transistor M6, without the need for an additional region to arrange the fourth via H4 and the fifth via H5, thereby being able to relatively reduce the area of the region where the first type of pixel driving circuit 101 is located, and thereby being conducive to high resolution of the display panel and meeting the light transmission and display requirements of the high-transmittance region in the display panel. At the same time, when the fourth via H4 and the fifth via H5 are arranged in the region between the gate of the first light-emitting control transistor M1 and the gate of the second light-emitting control transistor M6, the fourth via H4 and the fifth via H5 can simultaneously overlap with the gate of the first light-emitting control transistor M1 and the gate of the second light-emitting control transistor M6, or overlap with one of the gate of the first light-emitting control transistor M1 and the gate of the second light-emitting control transistor M6 in a second direction X' approximately parallel to the row direction X of the pixel driving circuit 10.

[0145] Correspondingly, the first line segment 211 (Emi) electrically connected with the gates of the first light-emitting control transistor M1 and the second light-emitting control transistor in the first type of pixel driving circuit 101 is multiplexed with part 301 of the shielding unit 30, and only the gates of the first light-emitting control transistor M1 and the second light-emitting control transistor M2 are retained in the first metal layer P4, so that the gates of the first light-emitting control transistor M1 and the second light-emitting control transistor M2 need to be electrically connected with part 301 of the shielding unit 30 through the first via H17.

[0146] Optionally, continuing to combine with reference to Figure 31 and Figure 32 , the at least one third transistor T3 includes a reset transistor M5; correspondingly, the display panel further includes a plurality of arrayed light-emitting elements 40 and a plurality of fifth signal lines 25 (Ref'); at this time, the first pole of the reset transistor M5 is electrically connected with the fifth signal line 25 (Ref'), and the reset transistors M5 of at least part of the pixel driving circuits 10 in the same row share the fifth signal line 25 (Ref'); the second pole of the reset transistor M5 is electrically connected with the anode of the light-emitting element 40.

[0147] Thus, in the first metal layer P5 where the gate of the reset transistor M5 is located, only the gate of the reset transistor M5 is reserved, so as to leave a region between the gates of two adjacent reset transistors M5, for setting other structures of the first type of pixel driving circuit 101, thereby facilitating the reduction of the area of the region where the first type of pixel driving circuit 101 is located.

[0148] Optionally, the above description continues to be combined with reference to Figure 31 and Figure 32 When the at least one third transistor T3 includes the reset transistor M5, the display panel can further include a semiconductor layer P3 located on one side of the substrate P1; the semiconductor layer P3 includes an active layer M5g of the reset transistor M5; a first metal layer P4 located on a side of the semiconductor layer P3 away from the substrate P1; the first metal layer P4 includes a gate of the reset transistor M5; in a direction Z perpendicular to a plane where the substrate P1 is located, a position in the active layer of the reset transistor M5 overlapping the gate of the reset transistor M5 is a channel region of the reset transistor M5; a second metal layer P5 located on a side of the first metal layer P4 away from the substrate P1; the second metal layer P5 includes a fifth signal line 25(Ref'); a first electrode of the reset transistor M5 is electrically connected to the fifth signal line 25(Ref') through a ninth via hole H91; a display layer (P7, P8 and P9) located on a side of the second metal layer P5 away from the substrate P1; the display layer (P7, P8 and P9) includes a light emitting element 40; a second electrode of the reset transistor M5 is electrically connected to the light emitting element 40 through a fourth via hole H4; in the active layer of the reset transistor M5, a region M5d from the channel region M5g of the reset transistor M5 to a ninth via hole H92 electrically connected to the reset transistor M5 and a region M5s from the channel region M5g of the reset transistor M5 to the fourth via hole H4 electrically connected to the reset transistor M5 are non-channel regions of the reset transistor M5; an area ratio Sq of the non-channel regions (M5s and M5d) of the reset transistor M5 to the channel region M5g of the reset transistor M5 is 1.5≤Sq≤2.

[0149] Specifically, in the first metal layer P5 where the gate of the reset transistor M5 is located, only the gate of the reset transistor M5 is reserved, and the first line segment 211 (Scan3) electrically connected with the reset transistor M5 is reused as the 302 part of the shielding unit 30, so that the structure located on one side of the gate of the reset transistor M5 is arranged between the gates of the adjacent two reset transistors M5. At this time, the size of the active layer of the reset transistor M5 in the column direction Y of the pixel driving circuit 10 can be shortened, so that the ratio between the area of the non-channel regions M5d and M5s of the reset transistor M5 and the area of the channel region M5g thereof is reduced to the range of 1.5-2. Compared with the prior art, the size of the active layer of the reset transistor M5 in the column direction Y of the pixel driving circuit 10 can be relatively shortened by 30%-60%. In this way, when at least part of the shielding unit 30 is reused as the reset signal line Ref' electrically connected with the reset transistor M5, the size of the reset transistor M5 can be reduced to reduce the area of the region where the pixel driving circuit 10 is located, so that the number of pixel driving circuits 10 arranged in the display panel can be relatively increased, which is beneficial to the high resolution of the display panel and can meet the display requirements of the high light transmission area.

[0150] It should be noted that, Figure 31 and Figure 32 are only schematic drawings of the embodiments of the present application, Figure 31 and Figure 32 In the above-mentioned embodiments, the first electrode of the reset transistor M5 needs to be electrically connected with the fifth signal line 25 (ref') through the third lap joint structure P603. At this time, the first electrode of the reset transistor M5 can pass through the ninth via hole H92 and the third lap joint structure P603, and pass through the tenth via hole H91 and the fifth signal line 25 (ref') through the third lap joint structure P603.

[0151] It can be understood that, Figure 31 In the above-mentioned embodiments, the ninth via hole H92 and the tenth via hole H91 are only schematically shown as being located on the same side of the fifth signal line 25 (ref'), but in the embodiments of the present application, the ninth via hole H92 and the tenth via hole H91 can also be located on the opposite sides of the fifth signal line 25 (ref') (as shown in Figure 33 .

[0152] It should be further noted that in the embodiments of the present application, the at least one third transistor T3 can only include the first light-emitting control transistor M1 and the second light-emitting control transistor M6, can only include the reset transistor M5, or can include the first light-emitting control transistor M1, the second light-emitting control transistor M6 and the reset transistor M5; or, in the first type of pixel driving circuit, all the transistors that need to be electrically connected with the scan signal line are third transistors (as shown in Figure 34);In the premise of being able to realize the area reduction of the area where the first type of pixel driving circuit is located, the embodiment of the present application does not make specific limitation.

[0153] In addition, in the embodiment of the present application, all pixel driving circuits in the display panel can be the first type of pixel driving circuit, at this time, compared with the prior art, the size of the area where each first type of pixel driving circuit and the signal line electrically connected thereto is reduced, which is beneficial to increase the number of pixel driving circuits in the display panel, and further improve the resolution of the display panel; at the same time, when the display panel includes a high light transmission area, because the size of the first type of pixel driving circuit is reduced, the area that needs to be shaded is reduced, that is, the area that needs to be set with shielding units is reduced, so that the light transmission area of the high light transmission area is increased, thereby meeting the light transmission and display requirements of the high light transmission area. Alternatively, only part of the pixel driving circuits in the display panel are the first type of pixel driving circuit, at this time, the resolution of the display panel can also be improved, and the light transmission and display requirements of the high light transmission area can also be met.

[0154] Exemplarily, Figure 35 is a structural schematic diagram of a display panel provided by an embodiment of the present application. As shown in Figure 35 , the display panel 100 includes a display area 110; the pixel driving circuit 10 is located in the display area 110; the display area 110 includes an optical component setting area 112 and a first display area 111 surrounding the optical component setting area 112; the pixel driving circuit 10 located in the optical component setting area 112 is electrically connected with the first line segment 211. In this way, the pixel driving circuit 10 in the optical component setting area 112 can have a smaller size, so that the light transmission area of the optical component setting area can be increased, thereby meeting the light transmission and display requirements of the optical component setting area 112.

[0155] Optionally, Figure 36 is another partial top view structural schematic diagram of a display panel provided by an embodiment of the present application. As shown in Figure 36 , when the shielding unit includes a plurality of shielding sub-units (3001, 3002), and each shielding sub-unit (3001, 3002) covers at least one of the pixel driving circuits in the direction perpendicular to the plane where the substrate base plate is located, the vertical projection of each shielding sub-unit (3001, 3002) on the substrate base plate is a first projection; the edge of the first projection is arc-shaped, so as to prevent diffraction when light transmits through the gap between two adjacent shielding sub-units, thereby improving the display effect of the display panel; at the same time, when the display panel includes a high light transmission area, and the high light transmission area is used to set an optical sensor, by setting the projection of the light shielding sub-unit set in the high light transmission area as arc-shaped, the accuracy of the light signal collected by the optical sensor can be improved.

[0156] Optionally, continuing to refer to Figure 36When the shielding unit includes a plurality of shielding sub-units (3001, 3002), two adjacent shielding sub-units (3001 and 3002) can be connected by a connecting line 50, which can be a transparent conducting line; at this time, the display panel further includes a transparent conducting layer on the side of the substrate, and the transparent conducting layer includes a plurality of connecting lines 50 for connecting different shielding sub-units. The transparent conducting layer can be an indium tin oxide layer in the anode layer of the light-emitting element. In this way, the area between the two adjacent shielding sub-units (3001 and 3002) can be fully transparent to light, and the transparent area will not be reduced due to the presence of the connecting line.

[0157] It should be noted that the connecting line connecting the two shielding sub-units (3001 and 3002) can also be a non-transparent connecting line; at this time, the connecting line can be in the form of a curve to prevent diffraction when light passes through the area between the signal lines.

[0158] Based on the same inventive concept, the embodiments of the present application also provide a display device, which includes the display panel provided by the embodiments of the present application, and therefore has the technical features of the display panel provided by the embodiments of the present application and can achieve the beneficial effects of the display panel provided by the embodiments of the present application. The same parts can be referred to the above description of the display panel provided by the embodiments of the present application, which will not be repeated here.

[0159] Optionally, Figure 37 is a structural schematic diagram of a display device provided by the embodiments of the present application, Figure 38 is a cross-sectional structural schematic diagram along the M-M section of Figure 37 , and Figure 37 and Figure 38 , the display device 200 includes a display panel 100 and an optical sensor 210; the display area 110 of the display panel 100 includes an optical component arrangement area 112 for arranging the optical sensor 210.

[0160] It can be understood that the display device provided by the embodiments of the present application can be a mobile phone, a tablet computer, a smart wearable device (for example, a smart watch), and other display devices with light signal collection function known to those skilled in the art, and the embodiments of the present application do not limit this.

[0161] Note that the above merely describes preferred embodiments of the present application and the principles of the technology applied. Those skilled in the art will understand that the present application is not limited to the specific embodiments described herein, and that various obvious changes, modifications, combinations and substitutions can be made by those skilled in the art without departing from the scope of the present application. Therefore, although the present application has been described in detail through the above embodiments, the present application is not limited to the above embodiments, and can include more other equivalent embodiments without departing from the concept of the present application, and the scope of the present application is determined by the scope of the claims.

Claims

1. A display panel, characterized by, The display panel comprises: a plurality of arrayed pixel driving circuits, a plurality of first signal lines and a shielding unit; the pixel driving circuit is electrically connected with the first signal line; a substrate substrate; the pixel driving circuit, the first signal line and the shielding unit are located on one side of the substrate substrate; at least part of the pixel driving circuit and the shielding unit overlap in a direction perpendicular to the plane where the substrate substrate is located; the first signal line comprises a first line segment, and at least part of the shielding unit is multiplexed as the first line segment, wherein the first line segment is electrically connected with the pixel driving circuit through a first via hole; the display panel further comprises a first conductive layer, and the first line segment of the first signal line is arranged in the first conductive layer used to arrange the shielding unit.

2. The display panel of claim 1, wherein, The pixel driving circuit comprises at least one first transistor; the pixel driving circuit electrically connected with the first line segment of the first signal line is a first type of pixel driving circuit; the first electrode of the first transistor of the first type of pixel driving circuit is electrically connected with the first line segment through a first via hole; the first electrode is a source electrode or a drain electrode.

3. The display panel of claim 2, wherein, Further comprising: a plurality of second signal lines; the pixel driving circuit further comprises a second transistor; the first electrode of the second transistor is electrically connected with the second signal line, and the second transistors of at least part of the pixel driving circuits located in the same column share the second signal line; the distance between two second signal lines respectively electrically connected with two first type of pixel driving circuits located in the same row and adjacent to each other along the row direction of the pixel driving circuit is L1, and the line width of the second signal line is L2; wherein 6≤ L1 / L2 ≤ 8.

4. The display panel of claim 2, wherein, Further comprising: a plurality of arrayed light emitting elements; the at least one first transistor comprises a first light emitting control transistor; the pixel driving circuit further comprises a second light emitting control transistor and a driving transistor; the second electrode of the first light emitting control transistor is electrically connected with the first electrode of the driving transistor; the first electrode of the second light emitting control transistor is electrically connected with the second electrode of the driving transistor, and the second electrode of the second light emitting control transistor is electrically connected with the anode of the light emitting element through a second via hole; when the first electrode is a source electrode, the second electrode is a drain electrode; or, when the first electrode is a drain electrode, the second electrode is a source electrode; the first via hole electrically connected with the first light emitting control transistor and the second via hole overlap in a first direction; wherein the first direction is parallel to the plane where the substrate substrate is located and has a first included angle with the column direction of the pixel driving circuit.

5. The display panel of claim 2, wherein, the shielding unit comprises a plurality of shielding sub-units; in the direction perpendicular to the plane where the substrate substrate is located, each shielding sub-unit overlaps with N pixel driving circuits; The pixel driving circuit further comprises a storage capacitor; a first plate of the storage capacitor in each of the pixel driving circuits has an integrated structure with the same shielding sub-unit; in each of the first type of pixel driving circuits, the first plate of the storage capacitor in the integrated structure is electrically connected to the same first line segment through M third vias; wherein M < N, and M and N are positive integers.

6. The display panel of claim 2, wherein, The at least one first transistor comprises a data writing transistor; the pixel driving circuit further comprises a driving transistor; the data writing transistor is configured to write a data signal transmitted by the first signal line to a gate of the driving transistor; Two adjacent first type of pixel driving circuits arranged in sequence along a row direction of the pixel driving circuit are a first pixel driving circuit and a second pixel driving circuit respectively; In a first direction, the first via electrically connecting the data writing transistor of the first pixel driving circuit overlaps with an active layer of the driving transistor of the second pixel driving circuit; wherein the first direction is parallel to a plane in which the substrate substrate is located and has a first included angle with a column direction of the pixel driving circuit.

7. The display panel of claim 2, wherein, Comprise: A semiconductor layer located on one side of the substrate substrate; the semiconductor layer comprises an active layer of the first transistor; A first metal layer located on a side of the semiconductor layer away from the substrate substrate; the first metal layer comprises a plurality of third signal lines; in a direction perpendicular to a plane in which the substrate substrate is located, a position of the third signal line overlapping with the active layer of the first transistor is a gate of the first transistor; The first transistors of at least part of the pixel driving circuits located in the same row share the third signal line and the first signal line.

8. The display panel of claim 7, wherein, Further comprise: The pixel driving circuit further comprises a storage capacitor; the at least one first transistor comprises an initialization transistor; the initialization transistor and the storage capacitor are arranged in sequence along a column direction of the pixel driving circuit; the first metal layer comprises a second plate of the storage capacitor; a second electrode of the initialization transistor and the second plate of the storage capacitor are electrically connected to a first node; wherein when the first electrode is a source electrode, the second electrode is a drain electrode, or when the first electrode is a drain electrode, the second electrode is a source electrode; The display panel further comprises: A second metal layer located on a side of the first metal layer away from the substrate substrate; the second metal layer comprises a first plate of the storage capacitor; A third metal layer located on a side of the second metal layer away from the substrate substrate; the third metal layer comprises a plurality of fourth signal lines; the first plate of the storage capacitor is electrically connected to the fourth signal line through a third via, and the storage capacitors of at least part of the pixel driving circuits located in the same column share the fourth signal line; The first conductive layer comprises the first line segment; the first conductive layer is located between the substrate substrate and the semiconductor layer, or the first conductive layer is located between the third metal layer and the semiconductor layer; Wherein, the first via electrically connected with the initialization transistor is located on a side of the third signal line close to the storage capacitor.

9. The display panel of claim 7, wherein, The pixel driving circuit further comprises a storage capacitor; the at least one first transistor comprises an initialization transistor; the initialization transistor and the storage capacitor are arranged in sequence along a column direction of the pixel driving circuit; the first metal layer comprises a second plate of the storage capacitor; a second electrode of the initialization transistor and the second plate of the storage capacitor are electrically connected to a first node; when the first electrode is a source electrode, the second electrode is a drain electrode, or when the first electrode is a drain electrode, the second electrode is a source electrode; The display panel further comprises: a second metal layer located on a side of the first metal layer away from the substrate; the second metal layer comprises a first plate of the storage capacitor; a third metal layer located on a side of the second metal layer away from the substrate; the third metal layer comprises a plurality of fourth signal lines and a plurality of first overlap structures; the first plate of the storage capacitor is electrically connected to the fourth signal line through a third via, and at least part of the storage capacitors of the pixel driving circuits located in the same column share the fourth signal line; a first conductive layer located on a side of the third metal layer away from the substrate; the first conductive layer comprises the first line segment; The first via electrically connected to the initialization transistor comprises a first sub-via and a second sub-via; the first electrode of the initialization transistor is electrically connected to the first overlap structure through the first sub-via, and the first overlap structure is electrically connected to the first line segment through the second sub-via; wherein the first sub-via is located on a side of the third signal line close to the storage capacitor, and the second sub-via is located on a side of the third signal line away from the storage capacitor.

10. The display panel of claim 7, wherein, Further comprising: a plurality of arrayed light emitting elements; The at least one first transistor comprises a reset transistor; a second electrode of the reset transistor is electrically connected to an anode of the light emitting element through a fourth via; when the first electrode is a source electrode, the second electrode is a drain electrode, or when the first electrode is a drain electrode, the second electrode is a source electrode; In a direction perpendicular to a plane in which the substrate is located, a position of an active layer of the reset transistor overlapping with the third signal line is a channel region of the reset transistor; a region of the active layer of the reset transistor from the channel region of the reset transistor to the first via electrically connected to the reset transistor and from the channel region of the reset transistor to the fourth via electrically connected to the reset transistor is a non-channel region of the reset transistor; an area ratio Sq of the non-channel region of the reset transistor to the channel region of the reset transistor is 1.5 ≤ Sq ≤ 2.

11. The display panel of claim 7, wherein, Further comprising: a third metal layer located on a side of the first metal layer away from the substrate; the third metal layer comprises a plurality of fourth signal lines; a display layer located on a side of the third metal layer away from the substrate; the display layer comprises a plurality of arrayed light emitting elements; The display panel further comprises a first conductive layer; the first conductive layer comprises the first line segment; the first conductive layer is located between the substrate substrate and the semiconductor layer, or the first conductive layer is located between the third metal layer and the semiconductor layer; The at least one first transistor comprises a reset transistor; the pixel drive circuit further comprises a light-emitting control transistor and a drive transistor; the drive transistor, the light-emitting control transistor and the reset transistor are arranged in sequence along the column direction of the pixel drive circuit; the light-emitting control transistor comprises a first light-emitting control transistor and a second light-emitting control transistor; the first electrode of the first light-emitting control transistor is electrically connected to the fourth signal line through a fifth via, and the second electrode of the first light-emitting control transistor is electrically connected to the first electrode of the drive transistor; the first electrode of the second light-emitting control transistor is electrically connected to the second electrode of the drive transistor, and the second light-emitting control transistor and the reset transistor are electrically connected to a second node and are electrically connected to the anode of the light-emitting element through a fourth via at the second node; wherein, when the first electrode is a source electrode, the second electrode is a drain electrode, or when the first electrode is a drain electrode, the second electrode is a source electrode; The first via electrically connected to the reset transistor is located on the side of the third signal line away from the fourth via and the fifth via.

12. The display panel of claim 7, wherein, Further comprising: A third metal layer located on the side of the first metal layer away from the substrate substrate; the third metal layer comprises a plurality of fourth signal lines and a plurality of second overlap structures; A display layer located on the side of the third metal layer away from the substrate substrate; the display layer comprises a plurality of arrayed light-emitting elements; And a first conductive layer located between the display layer and the third metal layer; the first conductive layer comprises the first line segment; The at least one first transistor comprises a reset transistor; the pixel drive circuit further comprises a light-emitting control transistor and a drive transistor; the drive transistor, the light-emitting control transistor and the reset transistor are arranged in sequence along the column direction of the pixel drive circuit; the light-emitting control transistor comprises a first light-emitting control transistor and a second light-emitting control transistor; the first electrode of the first light-emitting control transistor is electrically connected to the fourth signal line through a fifth via, and the second electrode of the first light-emitting control transistor is electrically connected to the first electrode of the drive transistor; the first electrode of the second light-emitting control transistor is electrically connected to the second electrode of the drive transistor, and the second light-emitting control transistor and the reset transistor are electrically connected to a second node and are electrically connected to the anode of the light-emitting element through a fourth via at the second node; wherein, when the first electrode is a source electrode, the second electrode is a drain electrode, or when the first electrode is a drain electrode, the second electrode is a source electrode; The first via hole in electrical connection with the reset transistor comprises a third sub-via hole and a fourth sub-via hole; the first electrode of the reset transistor is electrically connected with the second overlap structure through the third sub-via hole, and the second overlap structure is electrically connected with the first line segment through the fourth sub-via hole; wherein the third sub-via hole is located on the side of the third signal line away from the fourth via hole; in the direction perpendicular to the plane where the substrate substrate is located, the fourth sub-via hole overlaps with the region between the fourth via hole and the fifth via hole.

13. The display panel of claim 1, wherein, The pixel driving circuit comprises at least one third transistor; The pixel driving circuit in electrical connection with the first line segment of the first signal line is a first type of pixel driving circuit; the gate of the third transistor of the first type of pixel driving circuit is electrically connected with the first line segment through a first via hole; the gates of any two third transistors of the same first type of pixel driving circuit are insulated from each other.

14. The display panel of claim 13, wherein, The pixel driving circuit further comprises a driving transistor and an initialization transistor; the at least one third transistor comprises a data writing transistor and a threshold compensation transistor; the data writing transistor and the threshold compensation transistor are arranged in sequence along the row direction of the pixel driving circuit, and the initialization transistor, the threshold compensation transistor and the driving transistor are arranged in sequence along the column direction of the pixel driving circuit; The second electrode of the data writing transistor is electrically connected with the first electrode of the driving transistor; the first electrode of the threshold compensation transistor is electrically connected with the second electrode of the driving transistor; the second electrode of the initialization transistor, the second electrode of the threshold compensation transistor and the gate of the driving transistor are electrically connected to a first node; wherein the first electrode is a source electrode, and the second electrode is a drain electrode; or, the first electrode is a drain electrode, and the second electrode is a source electrode; The data writing transistor and the threshold compensation transistor of at least part of the pixel driving circuits in the same row share the first signal line; the gates of the data writing transistor and the threshold compensation transistor in the first type of pixel driving circuit are electrically connected with the same first line segment.

15. The display panel of claim 14, wherein, Comprise: A semiconductor layer located on one side of the substrate substrate; the semiconductor layer comprises the active layers of the data writing transistor, the threshold compensation transistor, the initialization transistor and the driving transistor; the active layer comprises a channel region and first and second electrodes located on both sides of the channel region; A first metal layer located on the side of the semiconductor layer away from the substrate substrate; the first metal layer comprises the gates of the data writing transistor, the threshold compensation transistor, the initialization transistor and the driving transistor; in the direction perpendicular to the plane where the substrate substrate is located, the position of the active layer overlapping with the gate is the channel region of the active layer; The first node comprises a first subpart and a second subpart; the first subpart extends along a row direction of the pixel driving circuit, and is configured to electrically connect the second electrode of the threshold compensation transistor and the second electrode of the initialization transistor; the second subpart extends along a column direction of the pixel driving circuit, and is configured to electrically connect the first subpart and the gate electrode of the driving transistor; In a direction perpendicular to a plane in which the substrate substrate is located, the first subpart and the second subpart do not overlap with the gate electrode.

16. The display panel of claim 15, wherein, The active layer of the threshold compensation transistor comprises a first channel region and a second channel region; In a second direction, the second electrode of the initialization transistor and the first subpart overlap with the first channel region and / or the second channel region; the second direction is parallel to a plane in which the substrate substrate is located and has a second included angle with the row direction of the pixel driving circuit.

17. The display panel of claim 16, wherein, The first subpart and the second subpart are both located in the semiconductor layer; one end of the second subpart is electrically connected with the first subpart, and the other end of the second subpart is electrically connected with the gate electrode of the driving transistor through a sixth via hole; The second channel region is located on a side of the first channel region close to the driving transistor; and the first subpart is located on a side of the first channel region close to the driving transistor.

18. The display panel of claim 16, wherein, Further comprising: a third metal layer located on a side of the first metal layer away from the substrate substrate; the third metal layer comprises the second subpart; The first subpart is located in the semiconductor layer; One end of the second subpart is electrically connected with the first subpart through a seventh via hole, and the other end of the second subpart is electrically connected with the gate electrode of the driving transistor through an eighth via hole.

19. The display panel of claim 16, wherein, The gate electrode of the threshold compensation transistor comprises a first gate electrode and a second gate electrode; the first gate electrode overlaps with the first channel region, and the second gate electrode overlaps with the second channel region; the first gate electrode and the second gate electrode are insulated from each other; In the second direction, the second gate electrode overlaps with the active layer of the driving transistor.

20. The display panel of claim 13, wherein, Further comprising: a plurality of arrayed light emitting elements and a plurality of fourth signal lines; The pixel driving circuit further comprises a driving transistor; the at least one third transistor comprises a first light emitting control transistor and a second light emitting control transistor arranged in sequence along a row direction of the pixel driving circuit; a first electrode of the first light emitting control transistor is electrically connected with the fourth signal line through a fifth via hole, and at least part of the first light emitting control transistors of the pixel driving circuit in the same column share the fourth signal line; a second electrode of the first light emitting control transistor is electrically connected with a first electrode of the driving transistor; a first electrode of the second light emitting control transistor is electrically connected with a second electrode of the driving transistor, and the second light emitting control transistor is electrically connected with an anode of the light emitting element through a fourth via hole; wherein the first electrode is a source electrode, and the second electrode is a drain electrode, or the first electrode is a drain electrode, and the second electrode is a source electrode. In a second direction, the fifth via and the fourth via overlap with a gate of the first light emitting control transistor and / or a gate of the second light emitting control transistor; the second direction is parallel to a plane in which the substrate substrate is located and has a second included angle with a row direction of the pixel driving circuit.

21. The display panel of claim 13, wherein, Further comprising: a plurality of arrayed light emitting elements and a plurality of fifth signal lines; the at least one third transistor comprises a reset transistor; a first electrode of the reset transistor is electrically connected with the fifth signal line, and at least part of the reset transistors of the pixel driving circuits in the same row share the fifth signal line; a second electrode of the reset transistor is electrically connected with an anode of the light emitting element; the first electrode is a source electrode, and the second electrode is a drain electrode, or the first electrode is a drain electrode, and the first electrode is a source electrode.

22. The display panel of claim 21, wherein, Comprising: a semiconductor layer located on one side of the substrate substrate; the semiconductor layer comprises an active layer of the reset transistor; a first metal layer located on a side of the semiconductor layer away from the substrate substrate; the first metal layer comprises a gate of the reset transistor; in a direction perpendicular to a plane in which the substrate substrate is located, a position of the active layer of the reset transistor overlapping with the gate of the reset transistor is a channel region of the reset transistor; a second metal layer located on a side of the first metal layer away from the substrate substrate; the second metal layer comprises the fifth signal line; a first electrode of the reset transistor is electrically connected with the fifth signal line through a ninth via; a display layer located on a side of the second metal layer away from the substrate substrate; the display layer comprises the light emitting element; a second electrode of the reset transistor is electrically connected with the light emitting element through a fourth via; in the active layer of the reset transistor, from the channel region of the reset transistor to the ninth via electrically connected with the reset transistor and from the channel region of the reset transistor to the fourth via electrically connected with the reset transistor, a region is a non-channel region of the reset transistor; an area ratio Sq of the non-channel region of the reset transistor to the channel region of the reset transistor is 1.5 ≤ Sq ≤ 2.

23. The display panel of claim 1, wherein, Comprising: the shielding unit comprises a plurality of shielding sub-units; in a direction perpendicular to a plane in which the substrate substrate is located, each shielding sub-unit covers at least one pixel driving circuit.

24. The display panel of claim 23, wherein, Further comprising: a first conductive layer located on one side of the substrate substrate; each shielding sub-unit comprises at least one first shielding structure; the first conductive layer comprises the first shielding structure; the first shielding structure is multiplexed as the first line segment; the first signal line is used for transmitting a fixed voltage signal; the first line segment electrically connected with each pixel driving circuit covered by the same shielding sub-unit is an integrated structure.

25. The display panel of claim 23, wherein, Further comprising: a first conductive layer located on one side of the substrate substrate; each shielding sub-unit comprises at least one first shielding structure; the first conductive layer comprises the first shielding structure; the first shielding structure is multiplexed as the first line segment; the first signal line is used for transmitting a variable voltage signal; any two first line segments are insulated from each other.

26. The display panel of claim 25, wherein, Further comprising: a second metal layer located on one side of the substrate substrate; each of the shielding sub-units further comprises at least one second shielding structure; the second metal layer comprises the second shielding structure; in a direction perpendicular to the plane where the substrate substrate is located, the second shielding structure and the first shielding structure have an overlap in the gap; the pixel driving circuit comprises a storage capacitor, and the second metal layer further comprises a first plate of the storage capacitor.

27. The display panel of claim 25, wherein, Further comprising: a plurality of arrayed light emitting elements; an anode metal layer located on one side of the substrate substrate; each of the shielding sub-units further comprises at least one third shielding structure; the anode metal layer comprises the third shielding structure and anodes of the light emitting elements; in a direction perpendicular to the plane where the substrate substrate is located, the third shielding structure and the first shielding structure have an overlap in the gap.

28. The display panel of claim 23, wherein, the vertical projection of each of the shielding sub-units on the substrate substrate is a first projection; an edge of the first projection is arc-shaped.

29. The display panel of claim 23, wherein, Further comprising: a transparent conductive layer located on one side of the substrate substrate; the transparent conductive layer comprises a plurality of connection lines; the connection lines are used to connect the pixel driving circuits that overlap with different shielding sub-units.

30. The display panel of claim 23, wherein, Further comprising: a plurality of connection lines; the connection lines are used to connect the pixel driving circuits that overlap with different shielding sub-units; wherein the connection lines are curved lines.

31. The display panel of claim 1, wherein, Further comprising: a display area; the pixel driving circuit is located in the display area; the display area comprises an optical component arrangement area and a first display area surrounding the optical component arrangement area; the pixel driving circuit located in the optical component arrangement area is electrically connected with the first line segment.

32. A display device, characterized in that, Including: the display panel of any one of claims 1-31.

33. The display device of claim 32, wherein, Further comprising: an optical sensor; the display panel further comprises a display area; the display area comprises an optical component arrangement area; the optical sensor is arranged in the optical component arrangement area.

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