Display substrate and display device

Abstract

A display substrate comprises: a substrate and a plurality of first lead signal lines. The substrate comprises a display area and a peripheral area surrounding the display area, the peripheral area comprising a first frame area located on one side of the display area. The plurality of first lead signal lines are located in the first frame area. At least one of the plurality of first lead signal lines comprises: a first trace, a second trace, and a third trace arranged in a stacked manner, the second trace being electrically connected to the first trace and the third trace. The orthographic projection of the first trace on the substrate, the orthographic projection of the second trace on the substrate, and the orthographic projection of the third trace on the substrate at least partially overlap.

Description

Technical Field

[0001] This article relates to but is not limited to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] Organic light-emitting diodes (OLEDs) and quantum-dot light-emitting diodes (QLEDs) are active light-emitting display devices with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high response speed, light weight, flexibility and low cost. Summary of the Invention

[0003] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0004] Embodiments of the present disclosure provide a display substrate and a display device.

[0005] On the one hand, an embodiment of the present disclosure provides a display substrate, comprising: a substrate and a plurality of first lead-out signal lines. The substrate includes a display area and a peripheral area surrounding the display area, the peripheral area including a first frame area located on one side of the display area. The plurality of first lead-out signal lines are located in the first frame area. At least one of the plurality of first lead-out signal lines includes: a first trace, a second trace, and a third trace arranged in a stacked manner, the second trace being electrically connected to the first trace and the third trace. The orthographic projection of the first trace on the substrate, the orthographic projection of the second trace on the substrate, and the orthographic projection of the third trace on the substrate at least partially overlap.

[0006] In some exemplary embodiments, the peripheral region further includes a second frame region located on both sides of the first frame region; the plurality of first lead-out signal lines include a plurality of first drive lead-out signal lines. The display substrate further includes: a plurality of sub-pixels located in the display region; a plurality of gate lines located in the display region and electrically connected to the plurality of sub-pixels; and a plurality of shift registers located in the second frame region and electrically connected to the plurality of gate lines, and the plurality of shift registers are electrically connected to the plurality of first drive lead-out signal lines.

[0007] In some exemplary embodiments, the display substrate further includes: a plurality of data lines located in the display area; the plurality of first lead-out signal lines include a plurality of first data lead-out lines located in the first frame area and electrically connected to the plurality of data lines in the display area; and the plurality of first data lead-out lines are located between the plurality of first drive lead-out signal lines in the first frame area.

[0008] In some exemplary embodiments, the first border region includes: a first sub-region, a bending region, and a second sub-region sequentially arranged in a direction away from the display region; and the plurality of first drive lead-out signal lines are located in the first sub-region.

[0009] In some exemplary embodiments, the display substrate further comprises: a plurality of drive connection lines located in the bending area; the plurality of drive connection lines are electrically connected to the plurality of first drive lead-out signal lines, and the plurality of drive connection lines are located on a side of the plurality of first drive lead-out signal lines away from the substrate.

[0010] In some exemplary embodiments, the drive connection line is electrically connected to the first, second and third lines of the corresponding first drive lead-out signal line through a first connection electrode; the first connection electrode is located on a side of the first, second and third lines away from the substrate.

[0011] In some exemplary embodiments, the display substrate further includes a plurality of second drive lead signal lines located in the second sub-region, wherein the plurality of second drive lead signal lines are electrically connected to the plurality of first drive lead signal lines through the plurality of drive connection lines.

[0012] In some exemplary embodiments, at least one of the plurality of second drive lead-out signal lines includes: a fourth route, a fifth route, and a sixth route that are stacked; the fourth route and the first route are in the same layer structure, the fifth route and the second route are in the same layer structure, and the sixth route and the third route are in the same layer structure.

[0013] In some exemplary embodiments, the third route of the first lead-out signal line is located on a side of the second route away from the substrate, and the first route is located on a side of the second route close to the substrate; the width of the first route of the first lead-out signal line is greater than the width of the second route, and the width of the second route is greater than the width of the third route.

[0014] In some exemplary embodiments, the third route of the first lead-out signal line is located on a side of the second route away from the substrate, and the first route is located on a side of the second route close to the substrate; the width of the second route of the first lead-out signal line is greater than the width of the first route, and the width of the first route is greater than the width of the third route.

[0015] In some exemplary embodiments, the first routing line of the first lead-out signal line is located in the first gate metal layer, the second routing line is located in the second gate metal layer, and the third routing line is located in the third gate metal layer; the first gate metal layer, the second gate metal layer, and the third gate metal layer are located in different layers.

[0016] In some exemplary embodiments, the display substrate further includes: a second power line located in the first border area; the second power line does not overlap with the orthographic projection of the plurality of first drive lead-out signal lines on the substrate in the first sub-area, and the second power line is located on a side of the plurality of first drive lead-out signal lines away from the substrate.

[0017] In some exemplary embodiments, the display substrate further includes: a second power auxiliary line located in a first sub-area of ​​the first border area; the second power line includes in the first sub-area: a first sub-power line and a second sub-power line, and the first sub-power line and the second sub-power line are electrically connected through the second power auxiliary line; the orthographic projection of the second power auxiliary line on the substrate at least partially overlaps with the orthographic projection of the multiple first drive signal lead lines on the substrate.

[0018] In some example embodiments, the second auxiliary power line is located on a side of the first and second sub power lines away from the substrate.

[0019] In some exemplary embodiments, the second power auxiliary line is located in the second source-drain metal layer, the first sub-power line and the second sub-power line are located in the first source-drain metal layer, and the first source-drain metal layer and the second source-drain metal layer are located in different layers.

[0020] On the other hand, an embodiment of the present disclosure provides a display device including the display substrate as described above.

[0021] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings are intended to provide a further understanding of the technical solutions of the present disclosure and constitute part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure and do not constitute a limitation of the technical solutions of the present disclosure. The shapes and sizes of one or more components in the accompanying drawings do not reflect the actual scale and are intended only to illustrate the contents of the present disclosure.

[0023] Figure 1 is a structural schematic diagram of a display device;

[0024] Figure 2 is a planar schematic diagram of a display substrate;

[0025] Figure 3 A schematic diagram of a partial cross-sectional structure of a display area of ​​a display substrate;

[0026] Figure 4 A schematic diagram of a first border area according to at least one embodiment of the present disclosure;

[0027] Figure 5 and Figure 6 for Figure 4 A partial enlarged schematic diagram of the middle area U1;

[0028] Figure 7 for Figure 6 Schematic diagram of the local section along the Q-Q' direction;

[0029] Figure 8 and Figure 9 is a cross-sectional schematic diagram of a first driving lead-out signal line according to at least one embodiment of the present disclosure;

[0030] Figure 10 A schematic diagram of the connection between the first driving lead-out signal line of the first sub-region and the bent connection line of the bent region according to at least one embodiment of the present disclosure;

[0031] Figure 11 for Figure 10 A schematic diagram of the first frame area after the first source and drain metal layer is formed;

[0032] Figure 12 for Figure 10 A schematic diagram of the first frame area after the fifth insulating layer is formed;

[0033] Figure 13 for Figure 10 A schematic diagram of the first border region after the third gate metal layer is formed;

[0034] Figure 14 for Figure 10 A schematic diagram of the first border region after the second gate metal layer is formed;

[0035] Figure 15 for Figure 10 A schematic diagram of forming a first border region of a first gate metal layer;

[0036] Figure 16 for Figure 12 Schematic diagram of the local section along the R-R' direction;

[0037] Figure 17 for Figure 4 A partial schematic diagram of the middle area U2;

[0038] Figure 18 2 is a partial cross-sectional diagram of a second driving lead-out signal line according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0039] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a variety of different forms. A person skilled in the art can easily understand that the method and content can be transformed into other forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments and features in the embodiments of the present disclosure can be combined with each other in any manner.

[0040] In the drawings, the size of one or more components, layer thicknesses, or regions may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to these dimensions, and the shapes and sizes of one or more components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0041] In this specification, ordinal numbers such as "first," "second," and "third" are provided to avoid confusion among constituent elements, and are not intended to limit the number. In this disclosure, "plurality" means two or more.

[0042] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and is not intended to indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the orientation of the constituent elements being described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced depending on the circumstances.

[0043] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed connections, removable connections, or integral connections; they can refer to mechanical connections or connections; they can refer to direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the meaning of these terms in this disclosure based on the circumstances.

[0044] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables transmission of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with multiple functions.

[0045] In this specification, a transistor refers to a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode), and current can flow through the drain, channel region, and source. In this specification, the channel region refers to the region through which current primarily flows.

[0046] In this specification, the first electrode can be referred to as the drain and the second electrode as the source, or vice versa. The functions of "source" and "drain" are sometimes interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, the terms "source" and "drain" can be interchanged. Furthermore, the gate electrode can also be referred to as the control electrode.

[0047] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0048] In this specification, circles, ellipses, triangles, rectangles, trapezoids, pentagons or hexagons are not in the strict sense, but may be approximate circles, approximate ellipses, approximate triangles, approximate rectangles, approximate trapezoids, approximate pentagons or approximate hexagons, etc. There may be some small deformations caused by tolerances, such as chamfers, arc edges and deformations.

[0049] In the present disclosure, "about" and "substantially" are used without strict limits and allow for process and measurement errors. In the present disclosure, "substantially the same" means that the numerical values ​​differ by less than 10%.

[0050] In this disclosure, "A extends along direction B" means that A may include a main portion and a secondary portion connected to the main portion, the main portion being a line, line segment, or strip, extending along direction B, and the length of the main portion extending along direction B being greater than the length of the secondary portion extending along other directions. In this disclosure, "A extends along direction B" means "the main portion of A extends along direction B."

[0051] Figure 1 is a schematic diagram of the structure of a display device. In some examples, such as Figure 1 As shown, the display device may include: a timing controller 21, a data driver 22, a scan driver circuit 23, a light-emitting driver circuit 24, and a sub-pixel array 25. In some examples, the sub-pixel array 25 may include a plurality of sub-pixels PX arranged in a regular pattern. The scan driver circuit 23 may be configured to provide scan signals to the sub-pixels PX along scan lines; the data driver 22 may be configured to provide data voltages to the sub-pixels PX along data lines; the light-emitting driver circuit 24 may be configured to provide light-emitting control signals to the sub-pixels PX along light-emitting control lines; and the timing controller 21 may be configured to control the scan driver circuit 23, the light-emitting driver circuit 24, and the data driver 22.

[0052] In some examples, such as Figure 1As shown, the timing controller 21 can provide grayscale values ​​and control signals suitable for the specifications of the data driver 22 to the data driver 22; the timing controller 21 can provide scan clock signals, scan start signals, etc. suitable for the specifications of the scan driver 23 to the scan driver circuit 23; and the timing controller 21 can provide light-emission clock signals, light-emission start signals, etc. suitable for the specifications of the light-emission driver circuit 24 to the light-emission driver circuit 24. The data driver 22 can use the grayscale values ​​and control signals received from the timing controller 21 to generate data voltages to be supplied to the data lines D1 to Di. For example, the data driver 22 can sample the grayscale values ​​using the clock signals and apply data voltages corresponding to the grayscale values ​​to the data lines D1 to Di on a sub-pixel row basis. The scan driver circuit 23 can generate scan signals to be supplied to the scan lines S1 to Sj using the scan clock signals, scan start signals, etc. received from the timing controller 21. For example, the scan driver circuit 23 can sequentially supply scan signals having on-level pulses to the scan lines. In some examples, the scan driver 23 may include a shift register that can generate a scan signal by sequentially transmitting a scan start signal provided in the form of an on-level pulse to the next-stage circuit under the control of a scan clock signal. The light-emitting drive circuit 24 can generate a light-emitting control signal to be provided to the light-emitting control lines E1 to Eo based on the light-emitting clock signal, light-emitting start signal, etc. received from the timing controller 21. For example, the light-emitting drive circuit 24 can sequentially provide a light-emitting control signal having an off-level pulse to the light-emitting control lines. The light-emitting drive circuit 24 may include a shift register that generates a light-emitting control signal by sequentially transmitting a light-emitting start signal provided in the form of an off-level pulse to the next-stage circuit under the control of a clock signal. Wherein, i, j, and o are all natural numbers.

[0053] In some examples, a display device may include a display substrate. A scan driver circuit and a light-emitting driver circuit may be directly disposed on the display substrate. For example, the scan driver circuit may be disposed on the left side frame of the display substrate, and the light-emitting driver circuit may be disposed on the right side frame of the display substrate; alternatively, the scan driver circuit and the light-emitting driver circuit may be disposed on both the left and right sides of the display substrate. In some examples, the scan driver circuit and the light-emitting driver circuit may be formed together with the sub-pixels during the process of forming the sub-pixels.

[0054] In some examples, the data driver can be provided on a separate chip or printed circuit board to be connected to the sub-pixels via signal access pins on the display substrate. For example, the data driver can be formed using a chip on glass, a chip on plastic, a chip on film, etc. to form a first frame provided on the display substrate to be connected to the signal access pins. The timing controller can be provided separately from the data driver or integrated with the data driver. However, this embodiment is not limited to this. In some examples, the data driver can be provided directly on the display substrate.

[0055] Figure 2 is a schematic plan view of a display substrate. In some examples, such as Figure 2 As shown, the display substrate may include: a display area AA, a peripheral area surrounding the display area AA. The peripheral area may include a first border area B1 located on one side of the display area AA and a second border area B2 located on the other side of the display area AA. The second border area B2 may be located on at least both sides of the first border area B1. The first border area B1 may be, for example, a lower border of the display substrate, and the second border area B2 may include an upper border, a left border, and a right border of the display substrate. In some examples, the display area AA may be a flat area including a plurality of sub-pixels PX constituting a pixel array, and the plurality of sub-pixels PX are configured to display dynamic pictures or still images. The display area may be referred to as an effective area. In some examples, the display substrate may be a flexible substrate, and thus the display substrate may be deformable, such as curling, bending, folding, or rolling up.

[0056] In some examples, the second border area B2 may include a circuit area, a power line area, a crack dam area, and a cutting area arranged in sequence along the direction of the display area AA. The circuit area can be connected to the display area AA and can include at least a gate drive circuit (for example, including multiple cascaded shift registers), and the multiple shift registers can be electrically connected to the multiple gate lines in the display area AA. The power line area is connected to the circuit area and can include at least a low-level power line, which can extend in a direction parallel to the edge of the display area and be connected to the cathode of the display area AA. The crack dam area can be connected to the power line area and can include at least a plurality of cracks set on the composite insulating layer. The cutting area can be connected to the crack dam area and can include at least a cutting groove set on the composite insulating layer. The cutting groove can be configured so that after all the film layers of the display substrate are prepared, the cutting arrangement can be cut along the cutting groove respectively.

[0057] In some examples, a first isolation dam and a second isolation dam may be provided in the first border area B1 and the second border area B2. The first isolation dam and the second isolation dam may extend in a direction parallel to the edge of the display area to form an annular structure surrounding the display area AA. The edge of the display area is the edge of the display area close to the first border area or the second border area.

[0058] In some examples, such as Figure 2 As shown, the display area AA may include at least a plurality of sub-pixels PX, a plurality of gate lines GL, and a plurality of data lines DL. The plurality of gate lines GL may extend along a first direction X, and the plurality of data lines DL may extend along a second direction Y. The orthographic projections of the plurality of gate lines GL and the plurality of data lines DL on the substrate intersect to form a plurality of sub-pixel areas, and a sub-pixel PX is provided in each sub-pixel area. The plurality of data lines DL are electrically connected to the plurality of sub-pixels PX, and the plurality of data lines DL may be configured to provide data signals to the plurality of sub-pixels PX. The plurality of data lines DL may extend to the binding area B1. The plurality of gate lines GL are electrically connected to the plurality of sub-pixels PX, and the plurality of gate lines GL may be configured to provide gate control signals to the plurality of sub-pixels PX. In some examples, the gate control signals may include scan signals and light-emitting control signals.

[0059] In some examples, such as Figure 2 As shown, the first direction X may be the extending direction (row direction) of the gate lines GL in the display area AA, and the second direction Y may be the extending direction (column direction) of the data lines DL in the display area AA. The first direction X and the second direction Y may be perpendicular to each other.

[0060] In some examples, a pixel unit in display area AA may include three sub-pixels, where the three sub-pixels are red, green, and blue. However, this embodiment is not limited to this. In some examples, a pixel unit may include four sub-pixels, where the four sub-pixels are red, green, blue, and white.

[0061] In some examples, the shape of the sub-pixels can be a rectangle, a diamond, a pentagon, or a hexagon. When a pixel unit includes three sub-pixels, the three sub-pixels can be arranged horizontally, vertically, or in a triangular pattern; when a pixel unit includes four sub-pixels, the four sub-pixels can be arranged horizontally, vertically, or in a square pattern. However, this embodiment is not limited to this.

[0062] In some examples, a sub-pixel may include: a pixel circuit and a light-emitting element electrically connected to the pixel circuit. The pixel circuit may include multiple transistors and at least one capacitor. For example, the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure. In the above circuit structure, T refers to a thin film transistor, C refers to a capacitor, the number before T represents the number of thin film transistors in the circuit, and the number before C represents the number of capacitors in the circuit. In some examples, the multiple transistors in the pixel circuit may be P-type transistors, or may be N-type transistors. Using transistors of the same type in the pixel circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the product yield. In other examples, the multiple transistors in the pixel circuit may include P-type transistors and N-type transistors.

[0063] In some examples, multiple transistors in the pixel circuit may use low-temperature polysilicon thin-film transistors, or may use oxide thin-film transistors, or may use low-temperature polysilicon thin-film transistors and oxide thin-film transistors. The active layer of the low-temperature polysilicon thin-film transistor uses low-temperature polysilicon (LTPS), and the active layer of the oxide thin-film transistor uses oxide semiconductor (Oxide). Low-temperature polysilicon thin-film transistors have the advantages of high mobility and fast charging, and oxide thin-film transistors have the advantages of low leakage current. Integrating low-temperature polysilicon thin-film transistors and oxide thin-film transistors on a display substrate, i.e., LTPS+Oxide (LTPO for short) display substrate, can take advantage of the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.

[0064] In some examples, the light-emitting element may be any one of a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a micro-LED (including mini-LED or micro-LED), etc. For example, the light-emitting element may be an OLED, and the light-emitting element may emit red light, green light, blue light, or white light, etc. when driven by its corresponding pixel circuit. The color of the light emitted by the light-emitting element may be determined according to needs. In some examples, the light-emitting element may include: an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting element may be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited to this.

[0065] Figure 3This is a schematic diagram of a partial cross-sectional structure of a display area of ​​a display substrate. Figure 3 The structure of three sub-pixels of a display substrate is shown. In this example, an LTPO display substrate is used as an example. The multiple transistors in the pixel circuit can be low-temperature polysilicon thin-film transistors and oxide thin-film transistors.

[0066] In some examples, such as Figure 3 As shown, in a direction perpendicular to the display substrate, the display substrate may include: a substrate 101, and a circuit structure layer 102, a light-emitting structure layer 103, a packaging structure layer 104, and a packaging cover plate 200 sequentially disposed on the substrate 101. In some possible implementations, the display substrate may include other film layers, such as spacers, a touch structure layer, etc., which are not limited in this disclosure.

[0067] In some examples, the substrate 101 can be a rigid substrate, such as a glass substrate; or it can be a flexible substrate, such as one made of an insulating material such as a resin. Furthermore, the substrate can have a single-layer structure or a multi-layer structure. When the substrate has a multi-layer structure, inorganic materials such as silicon nitride, silicon oxide, and silicon oxynitride can be placed between multiple layers in a single layer or multiple layers. However, this embodiment is not limited to this.

[0068] In some examples, the circuit structure layer 102 of each sub-pixel may include a plurality of transistors and storage capacitors constituting a pixel circuit. Figure 3In the figure, each sub-pixel includes a low-temperature polysilicon thin film transistor (for example, a first transistor 105), an oxide thin film transistor (for example, a second transistor 106), and a storage capacitor (for example, a first capacitor 107) as an example for illustration. In some possible implementations, the circuit structure layer 102 of each sub-pixel may include: a first semiconductor layer (for example, an active layer including a low-temperature polysilicon thin film transistor) disposed on the substrate 101; a first insulating layer 11 (or referred to as a first gate insulating layer) covering the active layer; a first gate metal layer (for example, including a gate electrode of a low-temperature polysilicon thin film transistor and a first capacitor electrode of a storage capacitor) disposed on the first insulating layer 11; a second insulating layer 12 (or referred to as a second gate insulating layer) covering the first gate metal layer; a second gate metal layer (for example, including a second capacitor electrode of a storage capacitor) disposed on the second insulating layer 12; a third insulating layer 13 (or referred to as a third gate insulating layer) covering the second gate metal layer; a second semiconductor layer (for example, a gate electrode of a low-temperature polysilicon thin film transistor) disposed on the third insulating layer 13 The present invention also provides the following components: a first source-drain metal layer (for example, a source electrode and a drain electrode of a low-temperature polysilicon thin-film transistor and an oxide thin-film transistor) provided on the fifth insulating layer 15; a second source-drain metal layer (for example, a pixel connection electrode connected to the anode of the light-emitting element) provided on the sixth insulating layer 16; and a seventh insulating layer 17 (for example, a second flat layer) covering the second source-drain metal layer. A first pixel via and a second pixel via are provided on the fifth insulating layer 15. The fifth insulating layer 15, the fourth insulating layer 14, the third insulating layer 13, the second insulating layer 12, and the first insulating layer 11 within the first pixel via are removed, exposing the surface of the first semiconductor layer. The source electrode and the drain electrode of the low-temperature polysilicon thin-film transistor can be connected to the active layer through the first pixel via, respectively. The fifth insulating layer 15 and the fourth insulating layer 14 within the second pixel via can be removed, exposing the surface of the second semiconductor layer. The source electrode and the drain electrode of the oxide thin-film transistor can be connected to the active layer through the second pixel via, respectively. A third pixel via can be provided on the sixth insulating layer 16. The pixel connection electrode located on the second source and drain metal layer can be electrically connected to the transistor of the pixel circuit through the third pixel via. A fourth pixel via can be provided on the seventh insulating layer 17. The anode of the light-emitting element can be electrically connected to the pixel connection electrode located on the second source and drain metal layer through the fourth pixel via.

[0069] In some examples, such as Figure 3As shown, the first to fifth insulating layers 11 to 15 may be made of inorganic insulating materials, and the sixth insulating layer 16 and the seventh insulating layer 17 may be made of organic insulating materials. However, this embodiment is not limited thereto.

[0070] In some examples, such as Figure 3 As shown, the light-emitting structure layer 103 may include an anode layer, a pixel definition layer, an organic light-emitting layer, and a cathode. The anode layer may include the anode of the light-emitting element. The anode may be disposed on the seventh insulating layer 17 and electrically connected to the pixel connection electrode through a fourth pixel via provided in the seventh insulating layer 17. The pixel definition layer is disposed on the anode layer and the seventh insulating layer 17. The pixel definition layer is provided with a pixel opening, which exposes at least a portion of the surface of the anode. The organic light-emitting layer is at least partially disposed within the pixel opening and is connected to the anode. The cathode is disposed on the organic light-emitting layer and is connected to the organic light-emitting layer. The organic light-emitting layer emits light of a corresponding color when driven by the anode and cathode.

[0071] In some examples, such as Figure 3 As shown, the encapsulation structure layer 104 may include a stacked first encapsulation layer, a second encapsulation layer and a third encapsulation layer. The first encapsulation layer and the third encapsulation layer may be made of inorganic materials, the second encapsulation layer may be made of organic materials, and the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to ensure that external water vapor cannot enter the light-emitting structure layer 103.

[0072] In some examples, the organic light-emitting layer may include at least a hole injection layer, a hole transport layer, a light-emitting layer, and a hole blocking layer stacked on the anode. In some examples, the hole injection layers of all sub-pixels may be a common layer connected together, the hole transport layers of all sub-pixels may be a common layer connected together, the light-emitting layers of adjacent sub-pixels may have a small overlap or may be isolated, and the hole blocking layer may be a common layer connected together. However, this embodiment is not limited to this.

[0073] In some implementations, with the increasing adoption of OLED panels, the demand for narrower bezels is growing. Narrower corners are becoming a trend in small-sized display products. However, the lower corner area includes multiple lead-out traces, especially for LTPO display substrates. The large number of lead-out signal lines makes narrowing the lower corners difficult.

[0074] This embodiment provides a display substrate, comprising: a substrate and a plurality of first lead signal lines. The substrate includes a display area and a peripheral area surrounding the display area, the peripheral area including a first frame area located on one side of the display area. The plurality of first lead signal lines are located in the first frame area. At least one of the plurality of first lead signal lines includes: a first trace, a second trace, and a third trace arranged in a stacked manner. The second trace is electrically connected to the first trace and the third trace. The orthographic projection of the first trace on the substrate, the orthographic projection of the second trace on the substrate, and the orthographic projection of the third trace on the substrate at least partially overlap.

[0075] The display substrate provided in this embodiment can reduce the routing load and shrink the wiring space in the first border area by adopting a three-layer routing stacking design for at least one first lead-out signal line in the first border area, thereby effectively reducing the lower rounded corner border and achieving narrowing of the lower rounded corner border.

[0076] In some exemplary embodiments, the peripheral area may further include a second frame area located on both sides of the first frame area, and the plurality of first lead-out signal lines may include a plurality of first drive lead-out signal lines. The display substrate also includes: a plurality of sub-pixels and a plurality of gate lines located in the display area, and a plurality of shift registers located in the second frame area. The plurality of gate lines are electrically connected to the plurality of sub-pixels. The plurality of shift registers are electrically connected to the plurality of gate lines, and the plurality of shift registers are electrically connected to the plurality of first drive lead-out signal lines. In this example, by setting the plurality of first drive lead-out signal lines in the first frame area to a stacked structure of three layers of wiring, the wiring load can be reduced and the wiring space of the first frame area can be reduced.

[0077] In some exemplary embodiments, the display substrate may further include a plurality of data lines located in the display area. The plurality of first lead-out signal lines may include a plurality of first data lead-out lines located in the first border area, and the plurality of first data lead-out lines are electrically connected to the plurality of data lines in the display area. The plurality of first data lead-out lines are located between the plurality of first drive lead-out signal lines in the first border area. For example, the plurality of first drive lead-out signal lines may be divided into two groups, and the plurality of first data lead-out lines may be located between the two groups of first drive lead-out signal lines. In this example, by setting the plurality of first data lead-out lines in the first border area to adopt a stacked structure of three layers of wiring, the wiring space in the first border area can be further reduced, which is conducive to achieving a narrowed lower rounded corner border.

[0078] In some exemplary embodiments, the first border region may include a first sub-region, a bending region, and a second sub-region sequentially arranged in a direction away from the display region. Multiple first drive lead signal lines may be located in the first sub-region. By reducing the size of the first drive lead signal lines located in the first sub-region, a narrowed lower rounded border may be achieved.

[0079] In some exemplary embodiments, the display substrate further comprises: a plurality of driving connection lines located in the bending region, the plurality of driving connection lines being electrically connected to the plurality of first driving lead signal lines, and the plurality of driving connection lines being located on a side of the plurality of first driving lead signal lines away from the substrate.

[0080] In some exemplary embodiments, the display substrate further includes: a plurality of second drive lead signal lines located in the second sub-region. The plurality of second drive lead signal lines are electrically connected to the plurality of first drive lead signal lines through a plurality of drive connection lines. In some examples, at least one second drive lead signal line may include: a fourth line, a fifth line, and a sixth line arranged in a stacked manner. The fourth line and the first line may be in the same layer structure, the fifth line and the second line may be in the same layer structure, and the sixth line and the third line may be in the same layer structure. In this example, the second drive lead signal line is designed with a stacked structure, which is beneficial to reducing the length of the second sub-region along the first direction, and has positive benefits for the space and shape of the display substrate.

[0081] In some exemplary embodiments, the first routing line of the first drive lead signal line can be located in the first gate metal layer, the second routing line can be located in the second gate metal layer, and the third routing line can be located in the third gate metal layer. The first gate metal layer, the second gate metal layer, and the third gate metal layer can be located in different layers. This embodiment facilitates the preparation of the display substrate and avoids the need to add new routing lines and film layers.

[0082] The solution of this embodiment is described below through some examples. In the following examples, a flexible substrate is used as an example for description.

[0083] Figure 4 Schematic diagram of the first border area of ​​at least one embodiment of the present disclosure. In some examples, such as Figure 4As shown, along the direction away from the display area AA, the first frame area may include: a first sub-area B11, a bending area B12 and a second sub-area B13. The two ends of the first sub-area B11 along the first direction X can be connected to the second frame areas B2 on the left and right sides. For example, the connecting area between the first sub-area B11 and the left second frame area B2 can form a lower fillet on the left, and the connecting area between the first sub-area B11 and the right second frame area B2 can form a lower fillet on the right. The first sub-area B11 can also be referred to as the first fan-out area. The first sub-area B11 can be connected to the display area AA and include at least a first power line, a second power line, a plurality of first data lead lines and a plurality of first drive lead signal lines 32. The plurality of first data lead lines can be configured to be electrically connected to the data lines of the display area AA and extend in a fan-out routing manner. The first power line can be configured to connect the high-level power line of the display area AA, and the second power line can be configured to connect the low-level power line in the second frame area B2. A gate drive circuit may be provided in the second border area B2. The gate drive circuit may include multiple shift registers. The gate drive circuit may be electrically connected to multiple drive signal lines 31. The multiple drive signal lines 31 may be electrically connected to multiple first drive lead signal lines 32 through a first electrostatic discharge circuit 30. The first electrostatic discharge circuit 30 may be located in the second border area B2 near the lower fillet area. For example, multiple first drive lead signal lines may be configured to provide clock signals and voltage signals to the gate drive circuit in the second border area B2. However, this embodiment is not limited to this.

[0084] In some examples, such as Figure 4 As shown, the bending region B12 can be connected between the first sub-region B11 and the second sub-region B13. The bending region B12 may include a composite insulating layer having a groove, and the groove may be configured to bend the first border region toward the back of the display area AA. For example, the bending region B12 may include at least a plurality of drive connection lines 33 electrically connected to the plurality of first drive lead signal lines 32, and a plurality of data connection lines electrically connected to the plurality of first data lead lines.

[0085] In some examples, such as Figure 4As shown, the second sub-area B13 may include a second fan-out area B131, a first circuit area B132, a third fan-out area B133, a driver chip area B134, and a binding pin area B135, which are arranged in sequence along a direction away from the display area AA. The second fan-out area B131 may include a plurality of fan-out lines (for example, including: a plurality of second drive lead-out signal lines, a plurality of second data lead-out lines, and the plurality of second data lead-out lines may be located between the plurality of second drive lead-out signal lines). The first circuit area B132 may include at least a second electrostatic discharge circuit, and the second electrostatic discharge circuit may be configured to prevent electrostatic damage to the display substrate by eliminating static electricity. The third fan-out area B133 may include a plurality of fan-out lines (for example, including a plurality of third data lead-out lines). The driver chip area B134 can be provided with a driver chip (IC, Integrated Circuit), and the driver chip area B134 can include a plurality of driver chip pins. The driver chip can be electrically connected to the data line of the display area AA through the driver chip pins and data lead lines (for example, including a third data lead line, a second data lead line and a first data lead line), and can be configured to generate a signal required for driving the sub-pixel and provide the drive signal to the data line of the display area. For example, the drive signal can be a data signal that drives the luminous brightness of the sub-pixel. The binding pin area B135 can include a plurality of binding pins, and the binding pins can be configured to be bound and connected to at least one corresponding circuit board (for example, a flexible printed circuit board (FPC)). The driver chip pins in the driver chip area B134 can be electrically connected to the binding pins in the binding pin area B135 through pin connection lines.

[0086] Figure 5 and Figure 6 for Figure 4 A partially enlarged schematic diagram of the middle area U1. Figure 5 A partial schematic diagram of the region U1 after the first source / drain metal layer is formed is shown. Figure 6 FIG. 1 shows a partial schematic diagram of the region U1 after the second source / drain metal layer is formed. Figure 5 and Figure 6 In the figure, the plurality of first data lead lines 41 are shown as a whole. The plurality of first data lead lines 41 can be electrically connected to the data lines DL extending from the display area AA, and configured to provide data signals to the data lines DL. Figure 6 The cross-hatched area in FIG. 1 shows the area where the sixth insulating layer is removed. Figure 7 for Figure 6 Schematic diagram of the local cross-section along the Q-Q' direction. Figure 7 In the example, the cross-sectional structure of five first drive lead-out signal lines is used as an example. In this example, the width of the line is the length in a direction perpendicular to the extending length direction in an extending plane parallel to the line.

[0087] In some examples, such as Figures 4 to 6 As shown, the multiple first drive lead signal lines 32 can be arranged in sequence along a direction away from the display area AA and extend from the lower fillet area to the bend area B12. For example, the multiple first drive lead signal lines 32 may include: multiple clock signal lines (for example, a first clock signal line GCK that provides a first clock signal to the gate drive circuit and a second clock signal line GCB that provides a second clock signal), and multiple voltage lines (for example, a first voltage line VGH1, a second voltage line VGH2, a third voltage line VGL1, and a fourth voltage line VGL2 configured to provide a voltage to the gate drive circuit). In this example, the multiple first lead signal lines using a three-layer routing stacking design are described using the multiple first drive lead signal lines as an example. In other examples, the plurality of first lead signal lines may further include: a plurality of first data lead lines; or, the plurality of first lead signal lines may further include: a plurality of initial signal lines (for example, including a first initial signal line INIT1, a second initial signal line INIT2, and a third initial signal line INIT3 that provide initial signals to pixel circuits in the display area); or, the plurality of first lead signal lines may further include: a plurality of first data lead lines and a plurality of initial signal lines. This embodiment is not limited to this.

[0088] In some examples, such as Figure 5 and Figure 6 As shown, the first sub-area B11 may include: a first power line 51 and a second power line. The first power line 51 and the second power line may be of the same layer structure, and the second power line may be located on the side of the first power line 51 away from the display area AA. The second power line in the first sub-area B11 may include: a first sub-power line 521 and a second sub-power line 522. The first sub-power line 521 may extend along the lower fillet area to the second frame area, and the second sub-power line 522 may extend toward the side of the bending area B12. The orthographic projections of the first sub-power line 521 and the second sub-power line 522 of the first sub-area B11 on the substrate may not overlap with the orthographic projections of the multiple first drive lead signal lines 32 on the substrate. In other words, the first sub-power line 521 and the second sub-power line 522 may be arranged across the opposite sides of the multiple first drive lead signal lines 32 along the first direction X.

[0089] In some examples, such as Figure 5 and Figure 6As shown, the first sub-area B11 may further include: a first power auxiliary connection line 53 and a second power auxiliary connection line 54. The first power auxiliary connection line 53 and the second power auxiliary connection line 54 may be of the same layer structure and are located on the side of the first power line 51 and the second power line away from the substrate. The first power auxiliary connection line 53 may be electrically connected to the first power line 51 whose orthographic projection overlaps with the first power line 51 through a via hole opened in the sixth insulating layer. A portion of the second power auxiliary connection line 54 close to the display area may be electrically connected to the first sub-power line 521 and the second sub-power line 522 whose orthographic projection overlaps with the second power line 51 through a via hole opened in the sixth insulating layer, and a portion of the second power auxiliary connection line 54 away from the display area (corresponding to the portion from which the sixth insulating layer is removed) may be directly electrically connected to the first sub-power line 521 and the second sub-power line 522 of the second power line whose orthographic projection overlaps with the second power line 51.

[0090] In some examples, such as Figure 6 As shown, the first power auxiliary connection line 53 and the second power auxiliary connection line 54 can be provided with a plurality of vias. By providing the plurality of vias, the first power auxiliary connection line 53 and the second power auxiliary connection line 54 can be prevented from making large-area contact with the sixth insulating layer, thereby preventing the sixth insulating layer from bursting, thereby improving the preparation effect of the display substrate.

[0091] In some examples, such as Figure 6 and Figure 7As shown, taking a first drive output signal line 32 as an example, the first drive output signal line 32 may include a first line 321, a second line 322, and a third line 323 arranged in a stacked manner. The first line 321 may be located on the side of the second line 322 closer to the substrate 10, and the third line 323 may be located on the side of the second line 322 farther from the substrate 10. A second insulating layer 12 may be provided between the first line 321 and the second line 322, and a third insulating layer 13 and a fourth insulating layer 14 may be provided between the second line 322 and the third line 323. The orthographic projections of the first line 321, the second line 322, and the third line 323 on the substrate 101 may at least partially overlap. In this example, the first line 321 may be located in the first gate metal layer, the second line 322 may be located in the second gate metal layer, and the third line 323 may be located in the third gate metal layer. In the preparation process of the pixel circuit in the display area of ​​this example, three stacked lines of the first drive lead signal line can be prepared simultaneously, which can simplify the preparation process. In this example, by adopting a stacked design for the first drive lead signal line, the purpose of reducing the line width of the first drive lead signal line can be achieved, thereby reducing the wiring space. In some examples, the first data lead line 41 can be located in the first gate metal layer or the second gate metal layer, and adjacent first data lead lines 41 in the plurality of first data lead lines 41 can be located in different layers. For example, the plurality of first data lead lines 41 are arranged in a manner of alternating between being located in the first gate metal layer and being located in the second gate metal layer. However, this embodiment is not limited to this. In other examples, at least one first data lead line 41 can adopt the same three-layer routing stacking design as the first drive lead signal line, which can further reduce the wiring space of the first border area.

[0092] In some examples, such as Figure 7 As shown, the third trace 323 can be covered by the fifth insulating layer 15. Since the fifth insulating layer 15 adopts an inorganic insulating material, the stacking design of the first drive lead-out signal line easily leads to a large step difference, which makes the fifth insulating layer 15 adopting an inorganic insulating material easy to break, thereby causing a short circuit. In this example, the second power line located in the first source and drain metal layer is disconnected, that is, it is disconnected into a first sub-power line 521 and a second sub-power line 522 above the first drive lead-out signal line. The first sub-power line 521 and the second sub-power line 522 can be electrically connected through the second power auxiliary connection line 54 located in the second source and drain metal layer, thereby realizing the transmission of the second power signal in the first frame area, ensuring the transmission continuity of the second power signal, and avoiding the occurrence of a short circuit.

[0093] Figure 8 and Figure 9 This is a cross-sectional diagram of the first drive lead signal line of at least one embodiment of the present disclosure. Figure 8 and Figure 9Here, only one first driving lead signal line is used as an example for illustration.

[0094] In some examples, such as Figure 8 As shown, the width of the second trace 322 of the first drive lead signal line can be greater than the width of the third trace 323, and the width of the first trace 321 can be greater than the width of the second trace 322. The stacked first trace 321, second trace 322, and third trace 323 form a right trapezoidal structure in the cross-sectional direction. The distance that the left edge of the first trace 321 protrudes from the left edge of the second trace 322 can be L1, and the distance that the left edge of the second trace 322 protrudes from the left edge of the third trace 323 can be L3; the distance that the right edge of the first trace 321 protrudes from the right edge of the second trace 322 can be L2, and the distance that the right edge of the second trace 322 protrudes from the right edge of the third trace 323 can be L4. For example, L1 can be approximately equal to L2, and L3 can be approximately equal to L4. For example, L1 can be greater than or equal to 1 micron, and L3 can be greater than or equal to 2 microns. The stacked design of this example can ensure the stability of the trace structure.

[0095] In some examples, such as Figure 9 As shown, the width of the second trace 322 of the first drive lead-out signal line can be greater than the width of the first trace 321, and the width of the first trace 321 can be greater than the width of the third trace 323. The distance that the left edge of the second trace 322 protrudes from the left edge of the third trace 323 can be L5, and the distance that the left edge of the second trace 322 protrudes from the left edge of the first trace 321 can be L7; the distance that the right edge of the second trace 322 protrudes from the right edge of the third trace 323 can be L6, and the distance that the right edge of the second trace 322 protrudes from the right edge of the first trace 321 can be L8. For example, L5 can be approximately equal to L6, and L7 can be approximately equal to L8. For example, L7 can be greater than or equal to 1 micron, and L6 can be greater than or equal to 2 microns. The stacked design of this example ensures that the third trace can be routed in a relatively flat position on the second trace.

[0096] Figure 10 This is a schematic diagram of the connection between the first driving lead-out signal line of the first sub-region and the bent connection line of the bent region according to at least one embodiment of the present disclosure. Figure 11 for Figure 10 Schematic diagram of the first border area after the first source and drain metal layer is formed. Figure 12 for Figure 10 Schematic diagram of the first border area after the fifth insulating layer is formed. Figure 13 for Figure 10 Schematic diagram of the first border area after the third gate metal layer is formed. Figure 14 for Figure 10Schematic diagram of the first border area after the second gate metal layer is formed. Figure 15 for Figure 10 Schematic diagram of forming a first border area of ​​a first gate metal layer. Figure 16 for Figure 12 Schematic diagram of the local cross-section along the R-R' direction.

[0097] In some examples, such as Figures 10 to 15 As shown, the extension directions of the first line 321, the second line 322 and the third line 323 of the first drive lead-out signal line can be substantially the same. The end of the first line 321 close to the bending area B12 can protrude from the second line 322. The end of the second line 322 close to the bending area B12 can protrude from the third line 323. A plurality of first connection electrodes 35 can be set in the boundary area between the first sub-area B11 and the bending area B12. The first connection electrodes 35 can be located in the first source and drain metal layer and arranged in sequence along the first direction X. Figure 11 、 Figure 12 and Figure 16 As shown, the first connecting electrode 35 can be electrically connected to the first trace 321 through multiple first vias V1, can be electrically connected to the second trace 322 through multiple second vias V2, and can be electrically connected to the third trace 323 through the third via V3. The electrical connection between the first trace 321, the second trace 322, and the third trace 323 is achieved through the first connecting electrode 35. The second insulating layer 12, the third insulating layer 13, the fourth insulating layer 14, and the fifth insulating layer 15 in the first via V1 can be removed to expose the surface of the first trace 321; the third insulating layer 13, the fourth insulating layer 14, and the fifth insulating layer 15 in the second via V2 can be removed to expose the surface of the second trace 322; the fifth insulating layer 15 in the third via V3 can be removed to expose the surface of the third trace 323. In some examples, such as Figure 12 As shown, the plurality of first via holes V1 may be aligned and arranged along the first direction X, and the plurality of second via holes V2 may be aligned and arranged along the first direction X. This embodiment is not limited to this.

[0098] In some examples, such as Figure 10 As shown, the bending connection line 33 located in the second source-drain metal layer can be electrically connected to the first connection electrode 35 located in the first source-drain metal layer through the fourth via V4. The bending connection line 33 can be a curved line, thereby realizing the bendability of the bending area B12.

[0099] Figure 17 for Figure 4 A partial schematic diagram of the region U2 in FIG. Figure 17As shown, the second sub-region B13 may include a plurality of second drive signal lines 34. The plurality of second drive signal lines 34 may be electrically connected to the plurality of first drive signal lines 32 of the first sub-region B11 through the meandering connection lines 33.

[0100] Figure 18 This is a partial cross-sectional diagram of a second drive lead-out signal line according to at least one embodiment of the present disclosure. This example uses the cross-sectional structure of a second drive lead-out signal line as an example. In some examples, such as Figure 18 As shown, the second drive lead signal line 34 may include: a fourth line 341, a fifth line 342, and a sixth line 343 arranged in a stacked manner. The orthographic projections of the fourth line 341, the fifth line 342, and the sixth line 343 on the substrate 101 at least partially overlap. For example, the fourth line 341 and the first line of the first drive lead signal line may be on the same layer, the fifth line 342 and the second line of the first drive lead signal line may be on the same layer, and the sixth line 343 and the third line of the first drive lead signal line may be on the same layer. The structure of the second drive lead signal line can refer to the structure of the first drive lead signal line, and therefore will not be further described here. The connection method between the second drive lead signal line 34 and the bent connection line 33 can refer to the connection method between the first drive lead signal line 32 and the bent connection line 33. For example, the three lines of the second drive lead signal line 34 can be electrically connected to the bent connection line 33 located in the second source / drain metal layer through a connecting electrode located in the first source / drain metal layer, so it will not be repeated here.

[0101] In some examples, such as Figure 17 As shown, the bending area B12 may also include a plurality of data connection lines 42. The plurality of first data lead lines 41 in the first sub-area B11 may be electrically connected to the plurality of second data lead lines 43 located in the second sub-area B13 through the plurality of data connection lines 42. The plurality of data connection lines 42 may be located on the side of the plurality of bending connection lines 33 away from the edge of the display substrate. The plurality of first data lead lines 41 may be located between the plurality of first drive lead signal lines 32, and the plurality of second data lead lines 43 may be located between the plurality of second drive lead signal lines 34. The plurality of data connection lines 42 may be located in the second source and drain metal layer. The plurality of first data lead lines 41 and the plurality of second data lead lines 43 may be located in the first gate metal layer or the second gate metal layer; or adjacent first data lead lines 41 may be alternately located in the first gate metal layer and the second gate metal layer, and adjacent second data lead lines 43 may be alternately located in the first gate metal layer and the second gate metal layer. In other examples, the plurality of first data lead lines 41 may adopt a structure of three stacked layers of wiring. In other examples, the plurality of second data lead lines 43 may adopt a structure of three stacked layers of wiring. However, this embodiment is not limited thereto.

[0102] In some examples, by setting the second driving lead signal line to a stacked structure, the wiring design width can be reduced, the load can be reduced, and the width L0 of the first frame area along the first direction X can be narrowed (eg, Figure 4 As shown in FIG. 1 , the distance between the second drive lead signal line and the edge of the first frame region may be L10. For example, L10 may be approximately 360 microns. In this way, L0 may be reduced by 720 microns. Reducing L0 can have positive benefits on both the space and shape of the display substrate.

[0103] At least one embodiment of the present disclosure further provides a display device comprising the display substrate described above. The display device may be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system.

[0104] The drawings in this disclosure only relate to the structures involved in this disclosure, and other structures may refer to the general design. In the absence of conflict, the embodiments of the present disclosure, that is, the features in the embodiments, can be combined with each other to obtain new embodiments. It should be understood by those skilled in the art that the technical solutions of this disclosure can be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of this disclosure, and should be included in the scope of the claims of this application.

Claims

1. A display substrate, characterized in that: include: a substrate comprising a display area and a peripheral area surrounding the display area, wherein the peripheral area comprises a first frame area located on one side of the display area; The first frame area includes: a first sub-area, a bending area, and a second sub-area sequentially arranged in a direction away from the display area; A plurality of first lead signal lines are located in the first border area; at least one of the plurality of first lead signal lines includes: a first line, a second line, and a third line arranged in a stacked manner, the second line being electrically connected to the first line and the third line, and the orthographic projection of the first line, the orthographic projection of the second line, and the orthographic projection of the third line on the substrate at least partially overlapping; a second insulating layer is provided between the first line and the second line, a third insulating layer and a fourth insulating layer are provided between the second line and the third line, and a fifth insulating layer is provided on a side of the third line away from the substrate, the fifth insulating layer being made of an inorganic insulating material; The plurality of first lead-out signal lines include a plurality of first drive lead-out signal lines; the plurality of first drive lead-out signal lines are located in the first sub-area; The display substrate also includes: a second power line located in the first frame area, and a second power auxiliary line located in the first sub-area of ​​the first frame area, the second power line does not overlap with the orthographic projection of the multiple first drive lead signal lines on the substrate in the first sub-area, and the second power line is located on the side of the multiple first drive lead signal lines away from the substrate; the second power line includes in the first sub-area: a first sub-power line and a second sub-power line, the first sub-power line and the second sub-power line are electrically connected through the second power auxiliary line; the orthographic projection of the second power auxiliary line on the substrate at least partially overlaps with the orthographic projection of the multiple first drive lead signal lines on the substrate; the second power auxiliary line is located on the side of the first sub-power line and the second sub-power line away from the substrate, and the first sub-power line and the second sub-power line are located on the side of the fifth insulating layer away from the substrate.

2. The display substrate according to claim 1, wherein: The peripheral area further includes a second frame area located on both sides of the first frame area; The display substrate further includes: A plurality of sub-pixels are located in the display area; a plurality of gate lines, located in the display area and electrically connected to the plurality of sub-pixels; A plurality of shift registers are located in the second frame area and are electrically connected to the plurality of gate lines. The plurality of shift registers are electrically connected to the plurality of first drive lead-out signal lines.

3. The display substrate according to claim 2, wherein: The display substrate further includes: a plurality of data lines located in the display area; The plurality of first lead signal lines include a plurality of first data lead lines, which are located in the first frame area and electrically connected to the plurality of data lines in the display area; The plurality of first data lead lines are located between the plurality of first drive lead signal lines in the first frame area.

4. The display substrate according to claim 1, wherein The display substrate further includes: a plurality of driving connection lines located in the bending area; the plurality of driving connection lines are electrically connected to the plurality of first driving lead signal lines, and the plurality of driving connection lines are located on a side of the plurality of first driving lead signal lines away from the substrate.

5. The display substrate according to claim 4, wherein: The driving connection line is electrically connected to the first, second and third lines of the corresponding first driving lead-out signal line through the first connecting electrode; the first connecting electrode is located on the side of the first, second and third lines away from the substrate.

6. The display substrate according to claim 4, wherein: The display substrate further includes: a plurality of second driving lead-out signal lines located in the second sub-area; The plurality of second driving signal lines are electrically connected to the plurality of first driving signal lines through the plurality of driving connection lines.

7. The display substrate according to claim 6, wherein: At least one of the plurality of second drive lead-out signal lines includes: a fourth routing line, a fifth routing line, and a sixth routing line arranged in a stacked manner; the fourth routing line and the first routing line are in the same layer structure, the fifth routing line and the second routing line are in the same layer structure, and the sixth routing line and the third routing line are in the same layer structure.

8. The display substrate according to claim 1, wherein: The first routing line of the first lead-out signal line is located in the first gate metal layer, the second routing line is located in the second gate metal layer, and the third routing line is located in the third gate metal layer; the first gate metal layer, the second gate metal layer and the third gate metal layer are located in different layers.

9. The display substrate according to claim 1, wherein: The second power auxiliary line is located in the second source-drain metal layer, the first sub-power line and the second sub-power line are located in the first source-drain metal layer, and the first source-drain metal layer and the second source-drain metal layer are located in different layers.

10. A display device, characterized in that: The display substrate comprises the display substrate according to any one of claims 1 to 9.

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