Voltage regulated sot-mram memory cell and sot-mram memory

Abstract

The application provides a voltage-regulated SOT-MRAM memory cell and SOT-MRAM memory, the SOT-MRAM memory cell comprising: a spin-orbit torque generation layer, a top electrode, and a magnetic tunnel junction between the spin-orbit torque generation layer and the top electrode, the magnetic tunnel junction comprising: a free layer on the spin-orbit torque generation layer, the free layer having a direction-variable perpendicular magnetization; a barrier layer on the free layer; a reference layer on the barrier layer, having a direction-fixed perpendicular magnetization; a spacer layer on the reference layer; a bias layer on the spacer layer, having a magnetization opposite to the magnetization direction of the reference layer, for generating a bias field to the free layer, wherein the saturation magnetization of the bias layer is higher than the saturation magnetization of the reference layer; and a regulation layer on the bias layer, for changing the magnetic anisotropy of the bias layer by using the VCMA effect when a voltage across the magnetic tunnel junction is applied between the top electrode and the spin-orbit torque generation layer.

Description

Technical Field

[0001] This invention relates to the field of MRAM memory technology, and more particularly to a voltage-regulated SOT-MRAM memory cell and an SOT-MRAM memory. Background Technology

[0002] SOT-MRAM is a new type of memory that combines non-volatility, high speed, long data retention time, and long lifespan. Its separate read / write circuitry gives it a longer lifespan and higher reliability compared to STT-MRAM. In SOT-MRAM, devices with a vertically magnetized free layer exhibit higher thermal stability and a smaller area, resulting in better miniaturization capabilities compared to those with an in-plane magnetized free layer. However, SOT-MRAM devices with a vertically magnetized free layer require an external magnetic field to achieve deterministic switching. Integrating a magnetic field within the chip is not conducive to high-density integration and can also cause crosstalk to other devices, affecting stability.

[0003] To achieve SOT-MRAM flipping without an external magnetic field, researchers have proposed using schemes such as asymmetric structures, STT assistance, and pulse modulation to establish an equivalent magnetic field to replace the external magnetic field. However, the actual flipping effect of existing schemes is not ideal. Summary of the Invention

[0004] To address the aforementioned issues, this invention provides a voltage-regulated SOT-MRAM memory cell that achieves deterministic switching without the need for an external magnetic field, while effectively reducing power consumption and increasing switching speed.

[0005] On one hand, the present invention provides a voltage-regulated SOT-MRAM memory cell, comprising: a spin-orbit moment generation layer, a top electrode, and a magnetic tunnel junction located between the spin-orbit moment generation layer and the top electrode, wherein the magnetic tunnel junction comprises:

[0006] A free layer, located on the spin orbit moment generating layer, the free layer having a variable direction of vertical magnetization;

[0007] A barrier layer is located on the free layer;

[0008] A reference layer is located on the barrier layer, and the reference layer has a fixed-direction vertical magnetization;

[0009] A spacer layer is located on the reference layer;

[0010] A bias layer, located on the spacer layer, has a magnetization opposite to that of the reference layer, for generating a bias field on the free layer, wherein the saturation magnetization of the bias layer is higher than that of the reference layer.

[0011] An adjustment layer, located on the bias layer, is used to change the magnetic anisotropy of the bias layer by means of the VCMA effect when a voltage across the magnetic tunnel junction is applied between the top electrode and the spin orbital moment generating layer.

[0012] Optionally, the magnetization direction of the bias layer is along the vertical direction or has an angle with the vertical direction.

[0013] Optionally, the conditioning layer is magnesium oxide or aluminum oxide.

[0014] On the other hand, the present invention provides a voltage-regulated SOT-MRAM memory cell, comprising: a spin orbital moment generation layer, a top electrode, and a magnetic tunnel junction located between the spin orbital moment generation layer and the top electrode, wherein the magnetic tunnel junction comprises:

[0015] A free layer, located on the spin orbit moment generating layer, the free layer having a variable direction of vertical magnetization;

[0016] A barrier layer is located on the free layer;

[0017] A reference layer is located on the barrier layer, and the reference layer has a fixed-direction vertical magnetization;

[0018] A spacer layer is located on the reference layer;

[0019] A bias layer, located on the spacer layer, has a magnetization opposite to that of the reference layer, for generating a bias field on the free layer, wherein the saturation magnetization of the bias layer is lower than that of the reference layer.

[0020] An adjustment layer, located between the barrier layer and the reference layer, is used to change the magnetic anisotropy of the reference layer by means of the VCMA effect when a voltage across the magnetic tunnel junction is applied between the top electrode and the spin orbital moment generating layer.

[0021] Optionally, the magnetization direction of the reference layer is along the vertical direction or has an angle with the vertical direction.

[0022] Optionally, the conditioning layer is magnesium oxide or aluminum oxide.

[0023] On the other hand, the present invention provides a voltage-regulated SOT-MRAM memory cell, comprising: a spin orbital moment generation layer, a top electrode, and a magnetic tunnel junction located between the spin orbital moment generation layer and the top electrode, wherein the magnetic tunnel junction comprises:

[0024] A free layer, located on the spin orbit moment generating layer, the free layer having a variable direction of vertical magnetization;

[0025] A barrier layer is located on the free layer;

[0026] A reference layer is located on the barrier layer, and the reference layer has a fixed-direction vertical magnetization;

[0027] An antiferromagnetic coupling layer is located on the reference layer;

[0028] The pinning layer, located on the antiferromagnetic coupling layer, has a magnetization direction opposite to that of the reference layer, and the saturation magnetization of the reference layer is higher than that of the pinning layer.

[0029] A spacer layer is located on the stapled layer;

[0030] A bias layer, located on the spacer layer, has a magnetization opposite to that of the reference layer, for generating a bias field on the free layer, wherein the saturation magnetization of the reference layer is higher than that of the bias layer.

[0031] An adjustment layer, located on the bias layer, is used to change the magnetic anisotropy of the bias layer by means of the VCMA effect when a voltage across the magnetic tunnel junction is applied between the top electrode and the spin orbital moment generating layer.

[0032] Optionally, the conditioning layer is magnesium oxide or aluminum oxide.

[0033] On the other hand, the present invention provides a voltage-regulated SOT-MRAM memory cell, comprising: a spin orbital moment generation layer, a top electrode, and a magnetic tunnel junction located between the spin orbital moment generation layer and the top electrode, wherein the magnetic tunnel junction comprises:

[0034] A free layer, located on the spin orbit moment generating layer, the free layer having a variable direction of vertical magnetization;

[0035] A barrier layer is located on the free layer;

[0036] A reference layer is located on the barrier layer, and the reference layer has a fixed-direction vertical magnetization;

[0037] An antiferromagnetic coupling layer is located on the reference layer;

[0038] The pinning layer, located on the antiferromagnetic coupling layer, has a magnetization direction opposite to that of the reference layer, and the saturation magnetization of the reference layer is higher than that of the pinning layer.

[0039] A spacer layer is located on the stapled layer;

[0040] A bias layer, located on the spacer layer, has magnetization in the same direction as the reference layer, and is used to generate a bias field on the free layer. The saturation magnetization of the bias layer is higher than that of the pinned layer.

[0041] An adjustment layer, located on the bias layer, is used to change the magnetic anisotropy of the bias layer by means of the VCMA effect when a voltage across the magnetic tunnel junction is applied between the top electrode and the spin orbital moment generating layer.

[0042] Optionally, the conditioning layer is magnesium oxide or aluminum oxide.

[0043] On the other hand, the present invention provides a SOT-MRAM memory, which includes a plurality of voltage-regulated SOT-MRAM memory cells as described above, and the plurality of SOT-MRAM memory cells share the same spin-orbit moment generation layer.

[0044] The voltage-regulated SOT-MRAM memory cell provided by this invention primarily utilizes the VCMA effect. Under the VCMA effect, the anisotropy of the magnetic layer adjacent to the regulating layer changes, altering the bias field of the entire device's magnetic layers (excluding the free layer) at the free layer. When current flows through the spin orbital moment generation layer adjacent to the free layer, the magnetization direction of the free layer flips to the horizontal direction. After the current in the spin orbital moment generation layer is removed, the free layer flips back to the corresponding direction under the guidance of the bias field, achieving a deterministic flip. In the SOT-MRAM memory cell provided by this invention, the current flowing through the spin orbital moment generation layer is only used to first flip the magnetization of the free layer to the horizontal direction; therefore, a higher current can be used, thereby increasing the flipping speed. Attached Figure Description

[0045] Figure 1 This is a schematic diagram of the structure of a SOT-MRAM memory cell according to an embodiment of the present invention;

[0046] Figure 2 for Figure 1 A schematic diagram illustrating the principle of writing antiparallel (AP) data into a SOT-MRAM memory cell;

[0047] Figure 3 for Figure 1 A schematic diagram illustrating the principle of writing parallel (P) data into a SOT-MRAM memory cell;

[0048] Figure 4 This is a schematic diagram of the structure of a SOT-MRAM memory cell according to an embodiment of the present invention;

[0049] Figure 5 This is a schematic diagram of the structure of a SOT-MRAM memory cell according to an embodiment of the present invention;

[0050] Figure 6 This is a schematic diagram of the structure of a SOT-MRAM memory cell according to an embodiment of the present invention;

[0051] Figure 7 This is a schematic diagram of the structure of a SOT-MRAM memory cell according to an embodiment of the present invention;

[0052] Figure 8 This is a schematic diagram of the structure of a SOT-MRAM memory cell according to an embodiment of the present invention;

[0053] Figure 9 This is a schematic diagram of the structure of an SOT-MRAM memory according to an embodiment of the present invention. Detailed Implementation

[0054] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0055] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0056] In this application, the terms "upper," "lower," "left," "right," "front," "rear," "top," "bottom," "inner," "outer," "middle," "vertical," "horizontal," "lateral," and "longitudinal" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are primarily for the purpose of better describing this application and its embodiments, and are not intended to limit the indicated device, element, or component to having a specific orientation, or to be constructed and operated in a specific orientation.

[0057] Furthermore, in addition to indicating location or positional relationship, some of the aforementioned terms may also have other meanings. For example, the term "above" may also be used in some cases to indicate a certain dependency or connection relationship. Those skilled in the art can understand the specific meaning of these terms in this application based on the specific circumstances.

[0058] Furthermore, the terms "installation," "setup," "equipped with," "connection," "linking," and "socketing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral structure; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium, or an internal connection between two devices, components, or parts. Those skilled in the art can understand the specific meaning of these terms in this application based on the specific circumstances.

[0059] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0060] Example 1

[0061] Figure 1 This is a schematic diagram of the structure of a voltage-regulated SOT-MRAM memory cell provided in an embodiment of the present invention. Figure 1 As shown, the voltage-regulated SOT-MRAM memory cell 10 includes a spin orbit moment generation layer 101, a top electrode 103, and a magnetic tunnel junction 102 located between the spin orbit moment generation layer 101 and the top electrode 103. In this embodiment, the spin orbit moment generation layer 101 can be a layer of heavy metal that generates a spin orbit moment effect when current passes through it, flipping the magnetization direction of adjacent free layers.

[0062] The magnetic tunnel junction 102 includes: a free layer 1021, a barrier layer 1022, a reference layer 1023, a spacer layer 1024, a bias layer 1025, and a regulating layer 1026. The free layer 1021 is located near the spin-orbit moment generation layer 101 and is situated on top of it. The free layer 1021 has a variable-direction vertical magnetization. The barrier layer 1022 is located on the free layer 1021 and is typically made of MgO. The reference layer 1023 is located on the barrier layer 1022 and has a fixed-direction vertical magnetization. The spacer layer 1024 is located on the reference layer 1023 and can be made of Ru or Ir; in this embodiment, it serves as an antiferromagnetic coupling layer. The bias layer 1025 is located on the spacer layer 1024 and is made of a ferromagnetic material. The bias layer 1025 has a magnetization opposite to that of the reference layer 1023 and is used to generate a bias field on the free layer 1021. The saturation magnetization of the bias layer 1025 is higher than that of the reference layer 1023. Figure 1In this configuration, reference layer 1023 is magnetized vertically downwards, and bias layer 1025 is magnetized vertically upwards. The arrow representing the magnetization direction of bias layer 1025 is wider than the arrow representing the magnetization direction of reference layer 1023, indicating that the saturation magnetization of bias layer 1025 is higher than that of reference layer 1023. In subsequent embodiments, unless otherwise specified, the width of the arrows representing the magnetization direction carries this meaning; a wider arrow indicates a higher saturation magnetization. Adjustment layer 1026, also known as the VCMA effect layer, is located on bias layer 1025. It is used to change the magnetic anisotropy of bias layer 1025 using the VCMA effect when a voltage is applied between the top electrode 103 and the spin-orbit moment generation layer 101 across the transmagnetic tunnel junction 102.

[0063] In this embodiment, the reference layer 1023 and the bias layer 1025 can be ferromagnetic metals, such as cobalt iron (CoFe), cobalt iron boron (CoFeB), or nickel iron (NiFe), and can be single or mixed metal materials. x O or other materials that can produce a VCMA effect with adjacent magnetic layers (bias layer 1025 in this embodiment).

[0064] To better understand the structure of the voltage-regulated SOT-MRAM memory cell provided in the above embodiments, the following describes in detail how it implements data writing.

[0065] 1. Write AP process, that is, write data to make the free layer and the reference layer antiparallel AP state.

[0066] First step, such as Figure 2 As shown in (a), a voltage is applied across the two ends of the spin orbit torque generating layer (i.e., SOT layer) 101, so that a current exists in the SOT layer 101, generating a spin orbit torque on the adjacent free layer 1021, and the magnetization of the free layer 1021 flips from the vertical direction to the horizontal direction.

[0067] The second step, as Figure 2 As shown in (b), the SOT layer current is removed, and a voltage +V is applied to the top electrode 103. The magnetic anisotropy of the bias layer 1025 remains unchanged or is enhanced due to the VCMA effect. Since the saturation magnetization of the bias layer 1025 is higher than that of the reference layer 1023, the bias field effect of the bias layer 1025 on the free layer 1021 is higher than that of the reference layer. The free layer 1021 is subjected to an upward bias, and finally the free layer flips to the AP state under the bias.

[0068] 2. Write P process, which is to write data to make the free layer and the reference layer parallel P state.

[0069] First step, such as Figure 3As shown in (a), a voltage is applied across the two ends of the spin orbit torque generating layer (i.e., SOT layer) 101, so that a current exists in the SOT layer 101, generating a spin orbit torque on the adjacent free layer 1021, and the magnetization of the free layer 1021 flips from the vertical direction to the horizontal direction.

[0070] The second step, as Figure 3 As shown in (b), when the SOT layer current is removed and a voltage -V is applied to the top electrode 103, the magnetic anisotropy of the bias layer 1025 is weakened due to the VCMA effect, and the magnetization direction is tilted. At this time, the influence of the reference layer 1023 on the bias field of the free layer is higher than that of the bias layer, and the free layer 1021 is subjected to a downward bias. Finally, the free layer 1021 flips to the P state under the bias.

[0071] In addition, as one implementation method, such as Figure 4 As shown, the initial magnetization direction of the bias layer 1025 is not completely perpendicular, but has an angle with the perpendicular direction. That is, the magnetic anisotropy of the bias layer 1025 decreases when no top voltage is applied, and the sum of the magnetic field biases of the bias layer 1025 and the reference layer 1023 in the free layer is 0.

[0072] The process of writing data is similar to that described above.

[0073] When writing the AP state, current flows through the SOT layer. The SOT effect flips the free layer into the in-plane state. When +V is applied to the top electrode, the anisotropy of the bias layer is enhanced, and the bias layer's bias effect on the free layer is greater than that of the reference layer. After the SOT effect, the free layer is flipped into the AP state under the influence of the bias layer.

[0074] When a P-state is written and current flows through the SOT layer, the SOT effect flips the free layer into the in-plane. When a -V is applied to the top electrode, the anisotropy of the bias layer weakens, the magnetization direction tilts at a larger angle, and it may even tilt into the in-plane. The bias effect of the reference layer on the free layer is greater than that of the bias layer. After the SOT effect, the free layer is flipped into the P state under the influence of the reference layer.

[0075] In this embodiment, the adjustment layer is disposed on the bias layer and adjacent to the bias layer. When the polarity of the top electrode voltage is different, the VCMA effect has different effects on the magnetic anisotropy of the bias layer. After the SOT current passes through, the magnetization direction of the free layer is different.

[0076] Example 2

[0077] Figure 5 This is a schematic diagram of a voltage-regulated SOT-MRAM memory cell provided in another embodiment of the present invention. Figure 5As shown, the voltage-regulated SOT-MRAM memory cell 20 includes a spin orbit moment generation layer 201, a top electrode 203, and a magnetic tunnel junction 202 located between the spin orbit moment generation layer 201 and the top electrode 203. In this embodiment, the spin orbit moment generation layer 201 can be a layer of heavy metal that generates a spin orbit moment effect when current passes through it, flipping the magnetization direction of adjacent free layers.

[0078] The magnetic tunnel junction 202 includes: a free layer 2021, a barrier layer 2022, a regulating layer 2023, a reference layer 2024, a spacer layer 2025, and a bias layer 2026. The free layer 2021 is located near the spin-orbit moment generation layer 201 and is situated on top of it. The free layer 2021 has a variable-direction vertical magnetization. The barrier layer 2022 is located on the free layer 2021 and is typically made of MgO. The reference layer 2024 is located on the barrier layer 2022 and has a fixed-direction vertical magnetization. The spacer layer 2025 is located on the reference layer 2024 and can be made of Ru or Ir; in this embodiment, it serves as an antiferromagnetic coupling layer. The bias layer 2026 is located on the spacer layer 2025 and is made of a ferromagnetic material. The bias layer 2026 has a magnetization opposite to that of the reference layer 2024 and is used to generate a bias field on the free layer 2021. The saturation magnetization of the bias layer 2026 is lower than that of the reference layer 2024. Figure 5 In this configuration, the reference layer 2024 is magnetized vertically downwards, and the bias layer 2026 is magnetized vertically upwards. The adjustment layer 2023, also known as the VCMA effect layer, is located between the barrier layer 2022 and the reference layer 2024. It is used to change the magnetic anisotropy of the reference layer 2024 by utilizing the VCMA effect when a voltage is applied between the top electrode 203 and the spin-orbit moment generation layer 201 through the transmagnetic tunnel junction 202.

[0079] In this embodiment, the reference layer 2024 and the bias layer 2026 can be ferromagnetic metals, such as cobalt iron (CoFe), cobalt iron boron (CoFeB), or nickel iron (NiFe), and can be single or mixed metal materials. The adjustment layer 2023 can be made of magnesium oxide (MgO) or aluminum oxide (Al). x O or other materials that can produce a VCMA effect with adjacent magnetic layers (reference layer 2024 in this embodiment).

[0080] The principle of writing data to the voltage-regulated SOT-MRAM memory cell provided in this embodiment is briefly described as follows:

[0081] When 0 / -V is applied to the top electrode 203, the anisotropy of the reference layer 2024 is enhanced, and the bias effect on the free layer 2021 is higher than that on the bias layer 2026. After the SOT effect, the magnetization of the free layer flips to the horizontal direction, and then the free layer is affected by the reference layer and flips to the P state.

[0082] When +V is applied to the top electrode 203, the anisotropy of the reference layer 2024 is weakened, and the bias effect on the free layer 2021 is lower than that on the bias layer 2026. After the SOT effect, the magnetization of the free layer flips to the horizontal direction, and then the free layer is affected by the bias layer and flips to the AP state.

[0083] In addition, as one implementation method, such as Figure 6 As shown, the initial magnetization direction of the reference layer 2024 is not perfectly perpendicular; it forms an angle with the perpendicular direction. This means that the magnetic anisotropy of the reference layer 2024 decreases when no top voltage is applied, and the sum of the magnetic field biases of the reference layer 2024 and the bias layer 2026 in the free layer is 0. (Data writing process reference...) Figure 5 The embodiments are described in detail below.

[0084] In this embodiment, the adjustment layer 2023 is disposed between the barrier layer 2022 and the reference layer 2024, and is adjacent to the reference layer. When the polarity of the top electrode voltage is different, the VCMA effect has different effects on the magnetic anisotropy of the reference layer. After the SOT current passes through, the magnetization direction of the free layer is different.

[0085] Example 3

[0086] Figure 7 This is a schematic diagram of the structure of a voltage-regulated SOT-MRAM memory cell provided in an embodiment of the present invention. Figure 7 As shown, the voltage-regulated SOT-MRAM memory cell 30 includes a spin orbit moment generation layer 301, a top electrode 303, and a magnetic tunnel junction 302 located between the spin orbit moment generation layer 301 and the top electrode 303. In this embodiment, the spin orbit moment generation layer 301 can be a layer of heavy metal that generates a spin orbit moment effect when current passes through it, flipping the magnetization direction of adjacent free layers.

[0087] The magnetic tunnel junction 302 includes: a free layer 3021, a barrier layer 3022, a reference layer 3023, an antiferromagnetic coupling layer 3024, a pinning layer 3025, a spacer layer 3026, a bias layer 3027, and a regulating layer 3028. The free layer 3021 is located near the spin-orbit moment generating layer 301 and is situated on top of it. The free layer 3021 has variable-direction vertical magnetization. The barrier layer 3022 is located on the free layer 3021 and is typically made of MgO. The reference layer 3023 is located on the barrier layer 3022 and has fixed-direction vertical magnetization. The antiferromagnetic coupling layer 3024 is located on the reference layer 3023 and serves as antiferromagnetic coupling. The pinning layer 3025 is located on the antiferromagnetic coupling layer 3024 and has a magnetization direction opposite to that of the reference layer 3023, used to fix the magnetization direction of the reference layer 3023. Spacer layer 3026 is located on pinned layer 3025. In this embodiment, spacer layer 3026 has ferromagnetic coupling or no coupling. Bias layer 3027 is located on spacer layer 3026 and has magnetization opposite to that of reference layer 3023. It is used to generate a bias field on free layer 3021, wherein the saturation magnetization of reference layer 3023 is higher than that of pinned layer 3025, and the saturation magnetization of reference layer 3023 is higher than that of bias layer 3027. Adjustment layer 3028 is located on bias layer 3027 and is used to change the magnetic anisotropy of bias layer 3027 by utilizing the VCMA effect when a voltage of transmagnetic tunnel junction 302 is applied between top electrode 303 and spin orbital moment generating layer 301.

[0088] In this embodiment, the reference layer 3023, pinning layer 3025, and bias layer 3027 can be ferromagnetic metals, such as cobalt iron (CoFe), cobalt iron boron (CoFeB), or nickel iron (NiFe), and can be single or mixed metal materials formed from at least one of these materials. x O or other materials that can produce a VCMA effect with adjacent magnetic layers (bias layer 3027 in this embodiment).

[0089] The principle of writing data to the voltage-regulated SOT-MRAM memory cell provided in this embodiment is briefly described as follows:

[0090] When 0 / +V is applied to the top electrode 303, the bias layer 3027 is affected by the VCMA effect, and the anisotropy of the bias layer 3027 is enhanced. The bias layer 3027 and the pinned layer 3025 have a stronger bias effect on the free layer 3021 than the reference layer 3023. After the SOT effect, the free layer is flipped to the AP state by the upward bias.

[0091] When -V is applied to the top electrode 303, the bias layer 3027 is affected by the VCMA effect, and the anisotropy of the bias layer 3027 is weakened. The bias effect of the bias layer 3027 and the pinned layer 3025 on the free layer 3021 is weaker than that of the reference layer 3023. After the SOT effect, the free layer is flipped to the P state by the downward bias.

[0092] Example 4

[0093] Figure 8 This is a schematic diagram of the structure of a voltage-regulated SOT-MRAM memory cell provided in an embodiment of the present invention. Figure 8 As shown, the voltage-regulated SOT-MRAM memory cell 40 includes a spin orbit moment generation layer 401, a top electrode 403, and a magnetic tunnel junction 402 located between the spin orbit moment generation layer 401 and the top electrode 403. In this embodiment, the spin orbit moment generation layer 401 can be a layer of heavy metal that generates a spin orbit moment effect when current passes through it, flipping the magnetization direction of adjacent free layers.

[0094] The magnetic tunnel junction 402 includes: a free layer 4021, a barrier layer 4022, a reference layer 4023, an antiferromagnetic coupling layer 4024, a pinning layer 4025, a spacer layer 4026, a bias layer 4027, and a regulating layer 4028. The free layer 4021 is located near the spin-orbit moment generating layer 401 and is situated on top of it. The free layer 4021 has variable-direction vertical magnetization. The barrier layer 4022 is located on the free layer 4021 and is typically made of MgO. The reference layer 4023 is located on the barrier layer 4022 and has fixed-direction vertical magnetization. The antiferromagnetic coupling layer 4024 is located on the reference layer 4023 and serves as an antiferromagnetic coupling layer. The pinning layer 4025 is located on the antiferromagnetic coupling layer 4024 and has a magnetization direction opposite to that of the reference layer 4023, used to fix the magnetization direction of the reference layer 4023. The saturation magnetization of the reference layer 4023 is higher than that of the pinned layer 4025. A spacer layer 4026 is located on the pinned layer 4025. In this embodiment, the spacer layer 4026 has antiferromagnetic coupling, causing the bias layer 4027 and the pinned layer 4025 to form antiferromagnetic coupling. The bias layer 4027 is located on the spacer layer 4026 and has the same magnetization direction as the reference layer 4023. It is used to generate a bias field on the free layer 4021, wherein the saturation magnetization of the bias layer 4027 is higher than that of the pinned layer 4025. An adjustment layer 4028 is located on the bias layer 4027 and is used to change the magnetic anisotropy of the bias layer 4027 by utilizing the VCMA effect when a voltage is applied between the top electrode 403 and the spin-orbit moment generation layer 401 through the transmagnetic tunnel junction 402.

[0095] In this embodiment, the reference layer 4023, pinning layer 4025, and bias layer 4027 can be ferromagnetic metals, such as cobalt iron (CoFe), cobalt iron boron (CoFeB), or nickel iron (NiFe), and can be single or mixed metal materials formed from at least one of these materials. x O or other materials that can produce a VCMA effect with adjacent magnetic layers (bias layer 4027 in this embodiment).

[0096] The principle of writing data to the voltage-regulated SOT-MRAM memory cell provided in this embodiment is briefly described as follows:

[0097] When 0 / +V is applied to the top electrode 403, the bias layer 4027 is affected by the VCMA effect, and the anisotropy of the bias layer 4027 is enhanced. The bias layer 4027 and the reference layer 4023 have a stronger bias effect on the free layer 4021 than the pinned layer 4025. After the SOT effect, the free layer flips to the P state.

[0098] When -V is applied to the top electrode 403, the bias layer 4027 is affected by the VCMA effect, and the anisotropy of the bias layer 4027 is weakened. The bias effect of the bias layer 4027 and the reference layer 4023 on the free layer 4021 is weaker than that of the pinned layer 4025. After the SOT effect, the free layer flips to the AP state.

[0099] This invention provides a SOT-MRAM memory, including a plurality of voltage-regulated SOT-MRAM memory cells as described above, such as... Figure 9 The diagram illustrates a scenario involving n memory cells sharing the same spin-orbit moment generation layer, with different voltages V1, V2, and V3 applied to the top. n It controls the data stored in different storage units.

[0100] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A voltage-regulated SOT-MRAM memory cell, characterized in that, include: A spin orbital moment generating layer, a top electrode, and a magnetic tunnel junction located between the spin orbital moment generating layer and the top electrode, the magnetic tunnel junction comprising: A free layer, located on the spin orbit moment generating layer, the free layer having a variable direction of vertical magnetization; A barrier layer is located on the free layer; A reference layer is located on the barrier layer, and the reference layer has a fixed-direction vertical magnetization; A spacer layer is located on the reference layer; A bias layer, located on the spacer layer, has a magnetization opposite to that of the reference layer, for generating a bias field on the free layer, wherein the saturation magnetization of the bias layer is higher than that of the reference layer. An adjustment layer, located on the bias layer, is used to change the magnetic anisotropy of the bias layer by means of the VCMA effect when a voltage across the magnetic tunnel junction is applied between the top electrode and the spin orbital moment generating layer.

2. The voltage-regulated SOT-MRAM memory cell according to claim 1, characterized in that, The magnetization direction of the bias layer is either along the vertical direction or has an angle with the vertical direction.

3. The voltage-regulated SOT-MRAM memory cell according to claim 1, characterized in that, The regulating layer is magnesium oxide or aluminum oxide.

4. A voltage-regulated SOT-MRAM memory cell, characterized in that, include: A spin orbital moment generating layer, a top electrode, and a magnetic tunnel junction located between the spin orbital moment generating layer and the top electrode, the magnetic tunnel junction comprising: A free layer, located on the spin orbit moment generating layer, the free layer having a variable direction of vertical magnetization; A barrier layer is located on the free layer; A reference layer is located on the barrier layer, and the reference layer has a fixed-direction vertical magnetization; A spacer layer is located on the reference layer; A bias layer, located on the spacer layer, has a magnetization opposite to that of the reference layer, for generating a bias field on the free layer, wherein the saturation magnetization of the bias layer is lower than that of the reference layer. An adjustment layer, located between the barrier layer and the reference layer, is used to change the magnetic anisotropy of the reference layer by means of the VCMA effect when a voltage across the magnetic tunnel junction is applied between the top electrode and the spin orbital moment generating layer.

5. The voltage-regulated SOT-MRAM memory cell according to claim 4, characterized in that, The magnetization direction of the reference layer is either along the vertical direction or has an angle with the vertical direction.

6. The voltage-regulated SOT-MRAM memory cell according to claim 4, characterized in that, The regulating layer is magnesium oxide or aluminum oxide.

7. A voltage-regulated SOT-MRAM memory cell, characterized in that, include: A spin orbital moment generating layer, a top electrode, and a magnetic tunnel junction located between the spin orbital moment generating layer and the top electrode, the magnetic tunnel junction comprising: A free layer, located on the spin orbit moment generating layer, the free layer having a variable direction of vertical magnetization; A barrier layer is located on the free layer; A reference layer is located on the barrier layer, and the reference layer has a fixed-direction vertical magnetization; An antiferromagnetic coupling layer is located on the reference layer; The pinning layer, located on the antiferromagnetic coupling layer, has a magnetization direction opposite to that of the reference layer, and the saturation magnetization of the reference layer is higher than that of the pinning layer. A spacer layer is located on the stapled layer; A bias layer, located on the spacer layer, has a magnetization opposite to that of the reference layer, for generating a bias field on the free layer, wherein the saturation magnetization of the reference layer is higher than that of the bias layer. An adjustment layer, located on the bias layer, is used to change the magnetic anisotropy of the bias layer by means of the VCMA effect when a voltage across the magnetic tunnel junction is applied between the top electrode and the spin orbital moment generating layer.

8. The voltage-regulated SOT-MRAM memory cell according to claim 7, characterized in that, The regulating layer is magnesium oxide or aluminum oxide.

9. A voltage-regulated SOT-MRAM memory cell, characterized in that, include: A spin orbital moment generating layer, a top electrode, and a magnetic tunnel junction located between the spin orbital moment generating layer and the top electrode, the magnetic tunnel junction comprising: A free layer, located on the spin orbit moment generating layer, the free layer having a variable direction of vertical magnetization; A barrier layer is located on the free layer; A reference layer is located on the barrier layer, and the reference layer has a fixed-direction vertical magnetization; An antiferromagnetic coupling layer is located on the reference layer; The pinning layer, located on the antiferromagnetic coupling layer, has a magnetization direction opposite to that of the reference layer, and the saturation magnetization of the reference layer is higher than that of the pinning layer. A spacer layer is located on the stapled layer; A bias layer, located on the spacer layer, has magnetization in the same direction as the reference layer, and is used to generate a bias field on the free layer. The saturation magnetization of the bias layer is higher than that of the pinned layer. An adjustment layer, located on the bias layer, is used to change the magnetic anisotropy of the bias layer by means of the VCMA effect when a voltage across the magnetic tunnel junction is applied between the top electrode and the spin orbital moment generating layer.

10. The voltage-regulated SOT-MRAM memory cell according to claim 9, characterized in that, The regulating layer is magnesium oxide or aluminum oxide.

11. A SOT-MRAM memory, characterized in that, The SOT-MRAM memory includes a plurality of voltage-regulated SOT-MRAM memory cells as described in any one of claims 1 to 10, wherein the plurality of SOT-MRAM memory cells share the same spin-orbit moment generation layer.

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