Display panel and display device

Abstract

A display panel and a display device, comprising a display area (AA) and a non-display area (BB) surrounding the display area (AA), wherein the display area (AA) comprises: a plurality of sub-pixels (P1) arranged in an array, wherein the sub-pixel (P1) comprises a pixel circuit (100) and a light-emitting device (L1); a control end of an anode reset transistor (T7) is electrically connected to a control end of a reset transistor (T1) in a sub-pixel (P1) in a next row; and the non-display area (BB) comprises: a row of dummy sub-pixels (P2), wherein each dummy sub-pixel (P2) corresponds to a sub-pixel column one by one, and the dummy sub-pixel (P2) comprises a dummy pixel circuit (2 00) and a dummy light-emitting device (L2), the dummy light-emitting device (L2) does not emit light; the dummy pixel circuit (200) comprises a dummy anode reset transistor (T7'), a first end of the dummy anode reset transistor (T7') is electrically connected to an initialization signal line (Vinit), a second end of the dummy anode reset transistor (T7') is electrically connected to an anode of the dummy light-emitting device (L2), and a cathode of the dummy light-emitting device (L2) is electrically connected to a first power supply terminal (VSS); and a control end of each dummy anode reset transistor (T7') is electrically connected to a control end of a reset transistor (T1) in a first row of sub-pixels (P1) correspondingly.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) is one of the hot topics in the field of flat panel display research today. Compared with Liquid Crystal Display (LCD), OLED display has the advantages of low energy consumption, low production cost, self-luminescence, wide viewing angle and fast response speed. At present, OLED display has begun to replace traditional LCD display in the display field of mobile phones, tablet computers, digital cameras, etc. Summary of the invention

[0003] A display panel provided by an embodiment of the present disclosure includes a display area and a non-display area surrounding the display area, wherein the display area includes:

[0004] A plurality of sub-pixels arranged in an array, wherein the sub-pixels include a pixel circuit and a light-emitting device, wherein the pixel circuit is used to drive the light-emitting device to emit light; the pixel circuit includes a driving transistor, an anode reset transistor and a reset transistor, wherein a first end of the anode reset transistor is electrically connected to an initialization signal line, a second end of the anode reset transistor is electrically connected to an anode of the light-emitting device, and a cathode of the light-emitting device is electrically connected to a first power supply terminal; a first end of the reset transistor is electrically connected to a gate of the driving transistor, and a second end of the reset transistor is electrically connected to the initialization signal line;

[0005] In a column of sub-pixels, the control end of the anode reset transistor in the sub-pixels in the previous row is electrically connected to the control end of the reset transistor in the sub-pixels in the next row;

[0006] The non-display area includes:

[0007] a row of dummy sub-pixels, each of the dummy sub-pixels corresponding to the sub-pixel column one by one, the dummy sub-pixels comprising a dummy pixel circuit and a dummy light-emitting device, the dummy light-emitting device does not emit light; the dummy pixel circuit comprises a dummy anode reset transistor, a first end of the dummy anode reset transistor is electrically connected to the initialization signal line, a second end of the dummy anode reset transistor is electrically connected to an anode of the dummy light-emitting device, and a cathode of the dummy light-emitting device is electrically connected to the first power supply terminal;

[0008] The control end of each of the dummy anode reset transistors is electrically connected to the control end of the reset transistor in the first row of sub-pixels.

[0009] Optionally, in the above display panel provided by the embodiment of the present disclosure, the dummy pixel circuit further includes: a dummy driving transistor, a dummy reset transistor, a first dummy light emitting control transistor and a second dummy light emitting control transistor; wherein,

[0010] The control end of the dummy reset transistor, the control end of the first dummy light emitting control transistor and the control end of the second dummy light emitting control transistor are all electrically connected to the cut-off signal end;

[0011] A first end of the dummy reset transistor is electrically connected to the gate of the dummy drive transistor, and a second end of the dummy reset transistor is electrically connected to the initialization signal line;

[0012] A first terminal of the first dummy light emitting control transistor is electrically connected to a second power supply terminal, and a second terminal of the first dummy light emitting control transistor is electrically connected to a first electrode of the dummy driving transistor;

[0013] A first terminal of the second dummy light emission control transistor is electrically connected to the second electrode of the dummy driving transistor, and a second terminal of the second dummy light emission control transistor is electrically connected to the anode of the dummy light emitting device.

[0014] Optionally, in the above-mentioned display panel provided by the embodiment of the present disclosure, the dummy reset transistor, the first dummy light emission control transistor and the second dummy light emission control transistor are all P-type transistors, and the cut-off signal terminal is the second power supply terminal.

[0015] Optionally, in the above display panel provided by the embodiment of the present disclosure, it further includes a high-level voltage line and a low-level voltage line;

[0016] The dummy reset transistor, the first dummy light emission control transistor and the second dummy light emission control transistor are all P-type transistors, and the cutoff signal terminal is electrically connected to the high-level voltage line.

[0017] Optionally, in the above-mentioned display panel provided in the embodiment of the present disclosure, it further includes a plurality of reset signal lines, a plurality of scan signal lines, a plurality of initialization signal lines and a dummy scan signal line; wherein a row of the sub-pixels corresponds to one of the scan signal lines, one of the reset signal lines and one of the initialization signal lines, and the dummy sub-pixels corresponds to one of the dummy scan signal lines and one of the initialization signal lines;

[0018] The control end of the dummy anode reset transistor is electrically connected to the dummy scan signal line;

[0019] The control terminal of the reset transistor is electrically connected to the reset signal line.

[0020] Optionally, in the above display panel provided by the embodiment of the present disclosure, in a column of sub-pixels, a scan signal line corresponding to a previous row of sub-pixels is electrically connected to a reset signal line corresponding to a next row of sub-pixels;

[0021] The dummy scanning signal line is electrically connected to the reset signal line corresponding to the sub-pixels in the first row.

[0022] Optionally, in the above-mentioned display panel provided in the embodiment of the present disclosure, the display panel further includes a plurality of data signal lines; the pixel circuit further includes a data writing transistor, a first end of the data writing transistor is electrically connected to the data signal line, a control end of the data writing transistor is electrically connected to the scanning signal line, and a second end of the data writing transistor is electrically connected to the first electrode of the driving transistor; one column of the sub-pixels is electrically connected to one data signal line;

[0023] The dummy pixel circuit also includes a dummy data write transistor, a first end of the dummy data write transistor is electrically connected to the data signal line, a control end of the dummy data write transistor is electrically connected to the dummy scan signal line, and a second end of the dummy data write transistor is electrically connected to the first electrode of the dummy drive transistor; each of the dummy sub-pixels is electrically connected to the data signal line of the corresponding column.

[0024] Optionally, in the above-mentioned display panel provided by the embodiment of the present disclosure, the dummy pixel circuit further includes a dummy threshold compensation transistor and a dummy storage capacitor; the first end of the dummy threshold compensation transistor is electrically connected to the gate of the dummy drive transistor, the control end of the dummy threshold compensation transistor is electrically connected to the control end of the dummy anode reset transistor, and the second end of the dummy threshold compensation transistor is electrically connected to the second electrode of the dummy drive transistor; the first end of the dummy storage capacitor is electrically connected to the second power supply end, and the second end of the dummy storage capacitor is electrically connected to the gate of the dummy drive transistor;

[0025] The pixel circuit further includes: a first light emission control transistor, a second light emission control transistor, a threshold compensation transistor and a storage capacitor; wherein,

[0026] The control end of the first light emitting control transistor is electrically connected to the light emitting control end, the first end of the first light emitting control transistor is electrically connected to the second power supply end, and the second end of the first light emitting control transistor is electrically connected to the first electrode of the driving transistor;

[0027] The control end of the second light emitting control transistor is electrically connected to the light emitting control end, the first end of the second light emitting control transistor is electrically connected to the second electrode of the driving transistor, and the second end of the second light emitting control transistor is electrically connected to the anode of the light emitting device;

[0028] The first end of the threshold compensation transistor is electrically connected to the gate of the driving transistor, the control end of the threshold compensation transistor is electrically connected to the control end of the anode reset transistor, and the second end of the threshold compensation transistor is electrically connected to the second electrode of the driving transistor;

[0029] The first end of the storage capacitor is electrically connected to the second power supply end, and the second end of the storage capacitor is electrically connected to the gate of the driving transistor.

[0030] Optionally, in the above display panel provided by the embodiment of the present disclosure, all transistors are P-type transistors.

[0031] Correspondingly, an embodiment of the present disclosure further provides a display device, comprising the above-mentioned display panel provided by an embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 A schematic diagram of a top view structure of a display panel provided in an embodiment of the present disclosure;

[0033] Figure 2 For the corresponding Figure 1 One of the structural schematic diagrams of the pixel circuit and the dummy pixel circuit in the display panel shown;

[0034] Figure 3 For the corresponding Figure 1 The second structural schematic diagram of the pixel circuit and the dummy pixel circuit in the display panel shown;

[0035] Figure 4 A schematic diagram of a top view structure of a dummy sub-pixel region in a display panel provided by an embodiment of the present disclosure;

[0036] Figure 5A-5H They are Figure 4 A schematic diagram of the top view structure of each corresponding film layer;

[0037] Figure 6 A schematic diagram of the structure of a display device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. And in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present disclosure.

[0039] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. "Include" or "comprising" and other similar words used in the present disclosure mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and other similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Inside", "outside", "upper", "lower", etc. are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0040] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual proportions, and are only intended to illustrate the present disclosure. The same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions.

[0041] The pixel circuit is the core technology of the OLED display panel and has important research significance. In order to meet the requirements of pixel circuit reset and pixel uniform light emission, the pixel circuit usually needs to connect multiple signal lines. The luminous brightness of the OLED display screen is closely related to the signal line load. The display panel generally includes multiple sub-pixels arranged in an array, each sub-pixel includes a pixel circuit and a light-emitting device. The commonly used pixel circuit is a 7T1C structure, that is, 7 thin-film transistors and 1 storage capacitor. The pixel circuit is generally connected to the scan signal line, reset signal line, initialization signal line, data signal line, light control signal line, etc. The signal on the scan signal line is generally given by the gate drive circuit (GOA). The GOA includes multiple cascaded shift registers, and the output end of each shift register is electrically connected to the scan signal line of the corresponding row to achieve line-by-line scanning. As for the reset signal, in the related design, the reset signal of the first row of pixels in the display area is outputted separately by the GOA of the 0th level, that is, the reset signal line of the first row of pixels is connected to the output end of the GOA of the 0th level, while in the pixels of the second row and below, the reset signal line is connected to the scanning signal line of the previous row, which causes the load of the reset signal line of the first row of pixels to be inconsistent with the load of the reset signal lines of other rows, resulting in uneven display brightness of the display panel. Therefore, it is necessary to perform load compensation on the load of the reset signal line of the first row of pixels.

[0042] In view of this, an embodiment of the present disclosure provides a display panel, such as Figure 1-Figure 3 As shown, it includes a display area AA and a non-display area BB surrounding the display area AA, and the display area AA includes:

[0043] A plurality of sub-pixels P1 are arranged in an array, and the sub-pixel P1 includes a pixel circuit 100 and a light-emitting device L1, and the pixel circuit 100 is used to drive the light-emitting device L1 to emit light; the pixel circuit 100 includes a driving transistor T3, an anode reset transistor T7 and a reset transistor T1, a first end of the anode reset transistor T7 is electrically connected to an initialization signal line Vinit, a second end of the anode reset transistor T7 is electrically connected to an anode of the light-emitting device L1, and a cathode of the light-emitting device L1 is electrically connected to a first power supply terminal VSS; a first end of the reset transistor T1 is electrically connected to a gate of the driving transistor T3, and a second end of the reset transistor T1 is electrically connected to the initialization signal line Vinit;

[0044] In a column of sub-pixels P1, the control end of the anode reset transistor T7 in the previous row of sub-pixels P1 is electrically connected to the control end of the reset transistor T1 in the next row of sub-pixels P1;

[0045] The non-display area BB includes:

[0046] A row of dummy sub-pixels P2, each dummy sub-pixel P2 corresponds to a column of sub-pixels P1 one by one, the dummy sub-pixel P2 includes a dummy pixel circuit 200 and a dummy light-emitting device L2, and the dummy light-emitting device L2 does not emit light; the dummy pixel circuit 200 includes a dummy anode reset transistor T7', a first end of the dummy anode reset transistor T7' is electrically connected to the initialization signal line Vinit, a second end of the dummy anode reset transistor T7' is electrically connected to the anode of the dummy light-emitting device L2, and a cathode of the dummy light-emitting device L2 is electrically connected to the first power supply terminal VSS;

[0047] The control end of each dummy anode reset transistor T7 ′ is electrically connected to the control end of the reset transistor T1 in the first row of sub-pixels P1 .

[0048] In the display panel provided by the embodiment of the present disclosure, since the control end of the anode reset transistor T7 in the upper row of sub-pixels P1 is electrically connected to the control end of the reset transistor T1 in the lower row of sub-pixels P1, the present disclosure sets a row of dummy sub-pixels P2 in the non-display area BB, and electrically connects the control end of its dummy anode reset transistor T7' to the control end of the reset transistor T1 in the first row of sub-pixels P1 accordingly, so that the control end of the reset transistor T1 of the first row of sub-pixels P1 receives a signal source that is the same as the signal source received by the control end of the reset transistor T1 in the other rows of sub-pixels P1, so that the load of the reset signal line connected to the first row of reset transistors T1 is consistent with the load of the reset signal line connected to the other rows of reset transistors T1, thereby improving the uniformity of the display brightness of the display panel.

[0049] Specifically, the light emitting device may include at least one of an organic light emitting diode (OLED) and a quantum dot light emitting diode (QLED).

[0050] Specifically, embodiments of the present invention Figure 2 and Figure 3 In the description, the first row of sub-pixels, the second row of sub-pixels and the dummy row of sub-pixels located above the first row of sub-pixels are taken as an example, and the connection relationship between the third row of sub-pixels and other rows of sub-pixels is the same as the connection relationship between the second row of sub-pixels.

[0051] In a specific implementation, in the above display panel provided in the embodiment of the present disclosure, if Figure 2 and Figure 3 As shown, the dummy pixel circuit 200 further includes: a dummy driving transistor T3', a dummy reset transistor T1', a first dummy light emitting control transistor T5' and a second dummy light emitting control transistor T6'; wherein,

[0052] The control end of the dummy reset transistor T1', the control end of the first dummy light-emitting control transistor T5' and the control end of the second dummy light-emitting control transistor T6' are all electrically connected to the cut-off signal end 01; the signal of the cut-off signal end 01 can make the dummy reset transistor T1', the first dummy light-emitting control transistor T5' and the second dummy light-emitting control transistor T6' always in the off state, so that the dummy light-emitting device L2 does not emit light, and does not affect the light-emitting effect of the display area AA;

[0053] A first end of the dummy reset transistor T1 ′ is electrically connected to the gate of the dummy driving transistor T3 ′, and a second end of the dummy reset transistor T1 ′ is electrically connected to the initialization signal line Vinit;

[0054] A first terminal of the first dummy light emitting control transistor T5' is electrically connected to the second power supply terminal VDD, and a second terminal of the first dummy light emitting control transistor T5' is electrically connected to a first electrode of the dummy driving transistor T3';

[0055] A first end of the second dummy light emitting control transistor T6 ′ is electrically connected to the second electrode of the dummy driving transistor T3 ′, and a second end of the second dummy light emitting control transistor T6 ′ is electrically connected to the anode of the dummy light emitting device L2 .

[0056] In a specific implementation, in the above display panel provided in the embodiment of the present disclosure, if Figure 2As shown, the dummy reset transistor T1', the first dummy light-emitting control transistor T5' and the second dummy light-emitting control transistor T6' can all be P-type transistors. Since the P-type transistor is turned off under the action of a high potential, and the voltage of the second voltage terminal VDD is a high voltage, the cut-off signal terminal O1 can be the second power supply terminal VDD, that is, the control terminal of the dummy reset transistor T1', the control terminal of the first dummy light-emitting control transistor T5' and the control terminal of the second dummy light-emitting control transistor T6' are all electrically connected to the second voltage terminal VDD. Under the control of the second voltage terminal VDD, the dummy reset transistor T1', the first dummy light-emitting control transistor T5' and the second dummy light-emitting control transistor T6' are always in the off state, thereby ensuring that the dummy light-emitting device L2 does not emit light.

[0057] In a specific implementation, in the above display panel provided in the embodiment of the present disclosure, if Figure 3 As shown, it also includes a high level voltage line VGH;

[0058] like Figure 3 As shown, the dummy reset transistor T1', the first dummy light-emitting control transistor T5' and the second dummy light-emitting control transistor T6' are all P-type transistors. Since the P-type transistor is turned off under the action of a high potential, and the VGH voltage is much higher than the VDD voltage, the cutoff signal terminal 01 is electrically connected to the high-level voltage line VGH, which can better ensure that the dummy reset transistor T1', the first dummy light-emitting control transistor T5' and the second dummy light-emitting control transistor T6' are always in the off state, further ensuring that the dummy light-emitting device L2 does not emit light.

[0059] It should be noted that the display panel generally includes an anti-static circuit structure, and the high-level voltage line VGH is electrically connected to the anti-static circuit structure. The present disclosure can ensure that the transistor T1', the first virtual light-emitting control transistor T5' and the second virtual light-emitting control transistor T6' are always in the off state by electrically connecting the control end of the virtual reset transistor T1', the control end of the first virtual light-emitting control transistor T5' and the control end of the second virtual light-emitting control transistor T6' to the high-level voltage line VGH.

[0060] In a specific implementation, in the above display panel provided in the embodiment of the present disclosure, if Figure 2 and Figure 3As shown, it also includes a plurality of reset signal lines (Reset1, Reset2, Reset3, ...), a plurality of scan signal lines (Gate1, Gate2, ...), a plurality of initialization signal lines Vinit and a dummy scan signal line Gate0; wherein, a row of sub-pixels P1 (for example, the first row of sub-pixels) corresponds to a scan signal line Gate1, a reset signal line Reset1 and an initialization signal line Vinit, and a dummy sub-pixel P2 corresponds to a dummy scan signal line Gate0 and an initialization signal line Vinit;

[0061] The control end of the dummy anode reset transistor T7' is electrically connected to the dummy scanning signal line Gate0;

[0062] The control end of the reset transistor T1 is electrically connected to the reset signal line Reset1 .

[0063] In a specific implementation, in the above display panel provided in the embodiment of the present disclosure, if Figure 2 and Figure 3 As shown, in a column of sub-pixels P1, the scanning signal line corresponding to the sub-pixels in the previous row is electrically connected to the reset signal line corresponding to the sub-pixels in the next row; for example, the scanning signal line Gate1 corresponding to the sub-pixels P1 in the first row is electrically connected to the reset signal line Reset2 corresponding to the sub-pixels P1 in the second row, the scanning signal line Gate2 corresponding to the sub-pixels P1 in the second row is electrically connected to the reset signal line Reset3 corresponding to the sub-pixels P1 in the third row, the scanning signal line Gate3 corresponding to the sub-pixels P1 in the third row is electrically connected to the reset signal line Reset4 corresponding to the sub-pixels P1 in the fourth row, and so on;

[0064] The dummy scanning signal line Gate0 is electrically connected to the reset signal line Reset1 corresponding to the first row of sub-pixels P1, so that the reset signal line Reset1 corresponding to the first row of sub-pixels P1 is given by the dummy scanning signal line Gate0 of the previous row, and the signals of the dummy scanning signal line Gate0 and the scanning signal lines (Gate1, Gate2...) are all output by the GOA circuit. Therefore, the reset signal source of the control end of the reset transistor T1 in all rows of sub-pixels in the display area AA is the same, thereby ensuring the uniformity of the display brightness of the display panel.

[0065] In a specific implementation, in the above display panel provided in the embodiment of the present disclosure, if Figure 2 and Figure 3As shown, the display panel further includes a plurality of data signal lines Data; the pixel circuit 100 further includes a data writing transistor T4, a first end of the data writing transistor T4 is electrically connected to the data signal line Data, a control end of the data writing transistor T4 is electrically connected to the scanning signal line (for example, the control end of the data writing transistor T4 in the first row of sub-pixels is electrically connected to the scanning signal line Gate1), and a second end of the data writing transistor T4 is electrically connected to the first electrode of the driving transistor T3; a column of sub-pixels P1 is electrically connected to a data signal line Data;

[0066] The dummy pixel circuit 200 also includes a dummy data write transistor T4', a first end of the dummy data write transistor T4' is electrically connected to the data signal line Data, a control end of the dummy data write transistor T4' is electrically connected to the dummy scan signal line Gate0, and a second end of the dummy data write transistor T4' is electrically connected to the first electrode of the dummy drive transistor T3'; each dummy sub-pixel P2 is electrically connected to the data signal line Data of the corresponding column.

[0067] In a specific implementation, in the above display panel provided in the embodiment of the present disclosure, if Figure 2 and Figure 3 As shown, the dummy pixel circuit 200 further includes a dummy threshold compensation transistor T2' and a dummy storage capacitor C'; the first end of the dummy threshold compensation transistor T2' is electrically connected to the gate of the dummy driving transistor T3', the control end of the dummy threshold compensation transistor T2' is electrically connected to the control end of the dummy anode reset transistor T7', and the second end of the dummy threshold compensation transistor T2' is electrically connected to the second electrode of the dummy driving transistor T3'; the first end of the dummy storage capacitor C' is electrically connected to the second power supply terminal VDD, and the second end of the dummy storage capacitor C' is electrically connected to the gate of the dummy driving transistor T3';

[0068] The pixel circuit 100 further includes: a first light emission control transistor T5, a second light emission control transistor T6, a threshold compensation transistor T2 and a storage capacitor C; wherein,

[0069] The control end of the first light-emitting control transistor T5 is electrically connected to the light-emitting control end EM. For example, the control end of the first light-emitting control transistor T5 in the first row of sub-pixels P1 is electrically connected to the light-emitting control end EM1, and the control end of the first light-emitting control transistor T5 in the second row of sub-pixels P1 is electrically connected to the light-emitting control end EM2, and so on. The first end of the first light-emitting control transistor T5 is electrically connected to the second power supply end VDD, and the second end of the first light-emitting control transistor T5 is electrically connected to the first electrode of the driving transistor T3.

[0070] The control end of the second light emitting control transistor T6 is electrically connected to the light emitting control end EM. For example, the control end of the second light emitting control transistor T6 in the first row of sub-pixels P1 is electrically connected to the light emitting control end EM1, and the control end of the second light emitting control transistor T6 in the second row of sub-pixels P1 is electrically connected to the light emitting control end EM2, and so on. The first end of the second light emitting control transistor T6 is electrically connected to the second electrode of the driving transistor T3, and the second end of the second light emitting control transistor T6 is electrically connected to the anode of the light emitting device L1.

[0071] The first end of the threshold compensation transistor T2 is electrically connected to the gate of the driving transistor T3, the control end of the threshold compensation transistor T2 is electrically connected to the control end of the anode reset transistor T7, and the second end of the threshold compensation transistor T2 is electrically connected to the second electrode of the driving transistor T3;

[0072] A first terminal of the storage capacitor C is electrically connected to the second power supply terminal VDD, and a second terminal of the storage capacitor C is electrically connected to the gate of the driving transistor T3.

[0073] In the specific implementation, in order to unify the manufacturing process, in the above-mentioned display panel provided in the embodiment of the present disclosure, as Figure 2 and Figure 3 As shown, all transistors may be P-type transistors.

[0074] Specifically, in the display panel provided by the embodiment of the present disclosure, the P-type transistor is turned on by a low-level signal and is turned off by a high-level signal.

[0075] Specifically, in the display panel provided in the embodiment of the present disclosure, each of the above transistors may be a thin film transistor (TFT) or a metal oxide semiconductor field effect transistor (MOS), which is not limited here. And according to the different types of the above transistors and the different signals of the gates of the transistors, the control end of each transistor is used as the gate, and the first end of the above switch transistor may be used as the source and the second end as the drain, or the first end of the switch transistor may be used as the drain and the second end as the source, which is not specifically distinguished here.

[0076] Specifically, Figure 4 As shown, Figure 4 for Figure 3The layout structure of a 7T1C dummy pixel circuit in a corresponding dummy sub-pixel. When manufacturing the 7T1C dummy pixel circuit, it is necessary to sequentially manufacture an active layer 1, a first metal layer 2, a second metal layer 3, a first insulating layer 4, a third metal layer 5, a second insulating layer 6, an anode 7, a pixel defining layer 8 and other graphics on a substrate (not shown). The first metal layer 2 includes a scanning signal line Gate0, a light-emitting control signal line EM and a plate of a storage capacitor C', the second metal layer 3 includes a data signal line Data, a high-level voltage line VGH and a VDD power line, and the third metal layer 5 includes an initialization signal line Vinit and another plate of a storage capacitor C' electrically connected to the second power supply terminal VDD; the initialization signal line Vinit and the light-emitting control signal line EM have the same extension direction, and the extension directions of the VDD power line and the light-emitting control signal line EM cross each other. Figure 4 The top view structural diagrams of each membrane layer are shown in Figure 5A-5H As shown. Figure 3 The structure shown, Figure 4 The dummy row gate line Gate0 is connected to the first reset signal line Reset1 of the first row of sub-pixels to ensure that the reset signal of the first row of sub-pixels and the reset signals of other rows of sub-pixels are derived from the signal on the gate line electrically connected to the previous row of pixels; the Reset0 and EM of the dummy sub-pixels are both connected to VGH to control T1', T5' and T6' to always be in a closed state.

[0077] It should be noted that Figure 5D The diagram shows the via region of the first insulating layer 4. Fig. 5F The diagram shows the via region of the second insulating layer 6. Figure 5H The diagram shows the opening area of ​​the pixel definition layer 8 .

[0078] It should be noted that Figure 5A-5H Only a top view schematic diagram of the main film layers in the dummy sub-pixel region is shown. Of course, each dummy sub-pixel region also includes a buffer layer, other insulating layers and other film layer structures.

[0079] In a specific implementation, the display panel provided in the embodiment of the present disclosure is an organic light emitting display panel.

[0080] Based on the same disclosed concept, the embodiment of the present disclosure further provides a display device, including the above-mentioned display panel provided by the embodiment of the present disclosure. The principle of solving the problem by the display device is similar to that of the above-mentioned array substrate, so the implementation of the display device can refer to the implementation of the above-mentioned array substrate, and the repeated parts will not be repeated here.

[0081] In specific implementation, the above-mentioned display device provided in the embodiment of the present disclosure may be a full-screen display device, or may also be a flexible display device, etc., which is not limited here.

[0082] In a specific implementation, the display device provided in the embodiment of the present disclosure may be as follows: Figure 6 The full-screen mobile phone shown. Of course, the display device provided in the embodiment of the present disclosure can also be any product or component with a display function, such as a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc. Other essential components of the display device should be understood by ordinary technicians in the field, and will not be repeated here, nor should they be used as a limitation to the present disclosure.

[0083] In the display panel provided by the embodiment of the present disclosure, since the control end of the anode reset transistor in the upper row of sub-pixels is electrically connected to the control end of the reset transistor in the lower row of sub-pixels, the present disclosure sets a row of dummy sub-pixels in the non-display area, and electrically connects the control end of the dummy anode reset transistor to the control end of the reset transistor in the first row of sub-pixels accordingly, so that the control end of the reset transistor of the first row of sub-pixels receives a signal source that is the same as the signal source received by the control end of the reset transistor in the other rows of sub-pixels, so that the load of the reset signal line connected to the reset transistor of the first row is consistent with the load of the reset signal line connected to the reset transistor of the other rows, thereby improving the uniformity of the display brightness of the display panel.

[0084] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present disclosure.

[0085] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if these modifications and variations of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to include these modifications and variations.

Claims

1. A display panel, wherein: The device comprises a display area and a non-display area surrounding the display area, wherein the display area comprises: A plurality of sub-pixels arranged in an array, wherein the sub-pixels include a pixel circuit and a light-emitting device, wherein the pixel circuit is used to drive the light-emitting device to emit light; the pixel circuit includes a driving transistor, an anode reset transistor and a reset transistor, wherein a first end of the anode reset transistor is electrically connected to an initialization signal line, a second end of the anode reset transistor is electrically connected to an anode of the light-emitting device, and a cathode of the light-emitting device is electrically connected to a first power supply terminal; a first end of the reset transistor is electrically connected to a gate of the driving transistor, and a second end of the reset transistor is electrically connected to the initialization signal line; In a column of sub-pixels, the control end of the anode reset transistor in the sub-pixels in the previous row is electrically connected to the control end of the reset transistor in the sub-pixels in the next row; The non-display area includes: a row of dummy sub-pixels, each of the dummy sub-pixels corresponding to the sub-pixel column one by one, the dummy sub-pixels comprising a dummy pixel circuit and a dummy light-emitting device, the dummy light-emitting device does not emit light; the dummy pixel circuit comprises a dummy anode reset transistor, a first end of the dummy anode reset transistor is electrically connected to the initialization signal line, a second end of the dummy anode reset transistor is electrically connected to an anode of the dummy light-emitting device, and a cathode of the dummy light-emitting device is electrically connected to the first power supply terminal; The control end of each of the dummy anode reset transistors is electrically connected to the control end of the reset transistor in the first row of sub-pixels; It also includes a plurality of reset signal lines, a plurality of scan signal lines, a plurality of initialization signal lines and a dummy scan signal line; wherein one row of sub-pixels corresponds to one scan signal line, one reset signal line and one initialization signal line, and one dummy sub-pixel corresponds to one dummy scan signal line and one initialization signal line; The control end of the dummy anode reset transistor is electrically connected to the dummy scan signal line; The control terminal of the reset transistor is electrically connected to the reset signal line; In a column of sub-pixels, the scanning signal line corresponding to the sub-pixels in the previous row is electrically connected to the reset signal line corresponding to the sub-pixels in the next row; The dummy scanning signal line is electrically connected to the reset signal line corresponding to the sub-pixels in the first row.

2. The display panel according to claim 1, wherein: The dummy pixel circuit further includes: a dummy driving transistor, a dummy reset transistor, a first dummy light emitting control transistor and a second dummy light emitting control transistor; wherein, The control end of the dummy reset transistor, the control end of the first dummy light emitting control transistor and the control end of the second dummy light emitting control transistor are all electrically connected to the cut-off signal end; A first end of the dummy reset transistor is electrically connected to the gate of the dummy drive transistor, and a second end of the dummy reset transistor is electrically connected to the initialization signal line; A first terminal of the first dummy light emitting control transistor is electrically connected to a second power supply terminal, and a second terminal of the first dummy light emitting control transistor is electrically connected to a first electrode of the dummy driving transistor; A first terminal of the second dummy light emission control transistor is electrically connected to the second electrode of the dummy driving transistor, and a second terminal of the second dummy light emission control transistor is electrically connected to the anode of the dummy light emitting device.

3. The display panel according to claim 2, wherein: The dummy reset transistor, the first dummy light emission control transistor and the second dummy light emission control transistor are all P-type transistors, and the cut-off signal terminal is the second power supply terminal.

4. The display panel according to claim 2, wherein: Also included is a high level voltage line; The dummy reset transistor, the first dummy light emission control transistor and the second dummy light emission control transistor are all P-type transistors, and the cutoff signal terminal is electrically connected to the high-level voltage line.

5. The display panel according to claim 2, wherein: The display panel further includes a plurality of data signal lines; the pixel circuit further includes a data writing transistor, a first end of the data writing transistor is electrically connected to the data signal line, a control end of the data writing transistor is electrically connected to the scanning signal line, and a second end of the data writing transistor is electrically connected to the first electrode of the driving transistor; one column of the sub-pixels is electrically connected to one data signal line; The dummy pixel circuit also includes a dummy data write transistor, a first end of the dummy data write transistor is electrically connected to the data signal line, a control end of the dummy data write transistor is electrically connected to the dummy scan signal line, and a second end of the dummy data write transistor is electrically connected to the first electrode of the dummy drive transistor; each of the dummy sub-pixels is electrically connected to the data signal line of the corresponding column.

6. The display panel according to claim 5, wherein: The dummy pixel circuit further includes a dummy threshold compensation transistor and a dummy storage capacitor; a first end of the dummy threshold compensation transistor is electrically connected to the gate of the dummy drive transistor, a control end of the dummy threshold compensation transistor is electrically connected to the control end of the dummy anode reset transistor, and a second end of the dummy threshold compensation transistor is electrically connected to the second electrode of the dummy drive transistor; a first end of the dummy storage capacitor is electrically connected to the second power supply end, and a second end of the dummy storage capacitor is electrically connected to the gate of the dummy drive transistor; The pixel circuit further includes: a first light emission control transistor, a second light emission control transistor, a threshold compensation transistor and a storage capacitor; wherein, The control end of the first light emitting control transistor is electrically connected to the light emitting control end, the first end of the first light emitting control transistor is electrically connected to the second power supply end, and the second end of the first light emitting control transistor is electrically connected to the first electrode of the driving transistor; The control end of the second light emitting control transistor is electrically connected to the light emitting control end, the first end of the second light emitting control transistor is electrically connected to the second electrode of the driving transistor, and the second end of the second light emitting control transistor is electrically connected to the anode of the light emitting device; The first end of the threshold compensation transistor is electrically connected to the gate of the driving transistor, the control end of the threshold compensation transistor is electrically connected to the control end of the anode reset transistor, and the second end of the threshold compensation transistor is electrically connected to the second electrode of the driving transistor; The first end of the storage capacitor is electrically connected to the second power supply end, and the second end of the storage capacitor is electrically connected to the gate of the driving transistor.

7. The display panel according to claim 6, wherein: All transistors are P-type transistors.

8. A display device, wherein: Comprising the display panel as described in any one of claims 1-7.

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