A method for quantitatively estimating porosity of a diode solder layer based on a differential function

Abstract

The application provides a method for quantitatively estimating diode solder layer porosity based on a differential function, first, diode devices with different porosities are prepared as calibration samples, a transient thermal resistance test method is used to obtain the differential function curve and thermal resistance value of the calibration samples, and the relationship between thermal resistance and porosity is determined; then, a diode with unknown solder porosity is taken as a sample to be tested, the differential function curve and thermal resistance value of the sample to be tested are tested; finally, the thermal characteristic information of the calibration sample and the sample to be tested is compared, and the porosity range of the sample to be tested is determined. Through the method, the porosity characteristics of the solder layer of the sample to be tested can be accurately reflected, and the reliability and product yield of the device leaving the factory are improved. The application solves the problem that the existing transient thermal resistance test method cannot quantitatively determine the solder layer porosity range, can quantitatively analyze multiple samples to be tested with unknown solder porosity, and statistically analyzes the solder porosity results of multiple samples to be tested, which is helpful for in-depth analysis of the solder process of the batch of products.

Description

TECHNICAL FIELD

[0001] The present application relates to the detection technology field in the semiconductor field, and particularly relates to a method for quantitatively estimating porosity of a diode solder layer based on a differential function. BACKGROUND

[0002] With the continuous development of components, the trend of miniaturization of electronic packaging is more and more obvious. The solder layer is an important part of the component packaging structure, which not only ensures the electrical connection between the chip and the shell substrate, but also realizes the mechanical support of the chip. With the continuous reduction of the size of the components, the reliability of the solder layer connection may become one of the weakest links in the components. Under the test environment of temperature thermal cycle, mechanical impact, fatigue creep and extreme vibration, thermal stress and internal stress will be generated in the solder layer. These residual stresses will cause porosity in the solder layer and failure. The failure of the solder layer may cause the disconnection between the chip and the shell substrate, and may also cause the chip to fall off, so the reliability of the solder layer is crucial to the stability of the device and the entire single machine system. If the porosity defects in the solder layer cannot be detected in time before the components are installed, it will pose a safety hazard to the entire machine such as a spacecraft.

[0003] Currently, the main technologies for detecting solder layer porosity in electronic components, both domestically and internationally, can be categorized into acoustic scanning microscopy, infrared thermography, and transient thermal resistance testing. Acoustic scanning microscopy is primarily used for detecting porosity in the solder layer of molded devices, but it cannot detect porosity in the solder layer of open-cell devices. When porosity exists within the solder, the temperature distribution on the solder surface changes. Infrared thermography can characterize this temperature distribution change caused by the porosity. However, if the solder is located inside the device cavity, the device must be opened to detect the porosity using infrared thermography, making it a destructive testing method unsuitable for screening tests. Compared to the previous two methods, the transient thermal resistance test method has significant advantages, enabling non-destructive testing of solder layer porosity defects in molded and unmolded devices. Patent No. 201510078344.9, "A Rapid Evaluation Method for the Heat Dissipation Performance of the Die-bonding Layer of a High-Power LED Device," discloses a method for detecting defects in the die-bonding layer of a device. This method first transforms the measured device voltage curve into a time constant spectrum, and then extracts characteristic parameters representing the die-bonding layer, thereby identifying the presence of defects in the die-bonding layer. However, this patent can only qualitatively determine the presence of porosity defects in the die-bonding layer, making it difficult to determine the proportion of porosity defects and assess the impact of porosity on the device's thermal resistance and heat dissipation performance. Porosity is crucial for determining the quality of the solder layer process. Only by quantitatively determining the range of solder layer porosity and simultaneously identifying the maximum solder layer thermal resistance when the porosity reaches a critical value can we determine whether the device meets the screening criteria, avoid failure risks during subsequent use, and improve the device's service reliability. Summary of the Invention

[0004] The purpose of this invention is to provide a method for quantitatively estimating the porosity of diode solder layers based on differential functions, so as to solve the problem that existing transient thermal resistance technology cannot quantitatively determine the range of solder layer porosity.

[0005] To solve the above-mentioned technical problems, the technical solution of the present invention is: to provide a method for quantitatively estimating the porosity of diode solder layers based on differential functions, characterized by comprising the following steps:

[0006] Step S1: Prepare calibration samples with different solder porosities;

[0007] Step S2: Determine the K coefficient of the calibration sample obtained in step S1;

[0008] Step S3: Monitor the PN junction voltage drop of the calibration sample obtained in step S1, obtain the differential function curve of the calibration sample through mathematical transformation, and extract the thermal resistance parameter;

[0009] Step S4: Superimpose the differential function curves of different calibration samples to determine the relationship between solder thermal resistance, total thermal resistance and porosity;

[0010] Step S5, open and grind the calibration sample obtained in step S1, and verify the solder layer porosity;

[0011] Step S6, determine the K coefficient of the unknown solder porosity sample to be tested;

[0012] Step S7, monitor the PN junction voltage drop of the sample to be tested in step S6, obtain the differential function curve of the sample to be tested by mathematical transformation, and extract the thermal resistance parameter;

[0013] Step S8, compare the parameters of the calibration sample and the sample to be tested, and determine the solder layer porosity range of the sample to be tested.

[0014] Further, the step S1 comprises:

[0015] Step S11, coating different areas of solder on the pad area on the top surface of the tube shell substrate as the solder area, and the uncoated area represents the porosity area;

[0016] Step S12, covering the porosity area with a ceramic sheet to prevent the solder from flowing into the porosity area during heating;

[0017] Step S13, placing a diode chip on the pad area covered with a ceramic sheet, placing the entire sample on a heating tube for reflow soldering, melting the solder in the solder area and connecting the diode chip and the tube shell substrate, and naturally cooling to room temperature;

[0018] Step S14, removing the ceramic sheet and bonding the diode chip and the tube shell substrate;

[0019] Step S15, capping the entire sample to obtain calibration samples with solder porosities of 0%, 10%, 20%, and 50%.

[0020] Further, the step S2 comprises:

[0021] Step S21, connecting the calibration sample according to the diode transient thermal resistance test circuit diagram, loading the test current on the single calibration sample, and monitoring the voltage drop change of the sample PN junction with a voltage sensor;

[0022] Step S22, placing the single calibration sample in an oil tank, the oil tank temperature being equal to the sample PN junction temperature, adjusting the oil tank temperature change, recording the PN junction voltage drop- junction temperature curve of the sample in real time, and obtaining the K coefficient of the calibration sample.

[0023] Further, the step S3 comprises:

[0024] Step S31, after the single calibration sample tube shell substrate bottom is coated with the heat-conducting silicone grease, the calibration sample is fixed on the constant temperature Cu block cold plate;

[0025] Step S32, the sample is loaded with heating current, and after the sample junction temperature reaches the thermal steady state, the heating current is quickly switched to the test current, and the voltage sensor is used to monitor the PN junction voltage drop curve of the sample;

[0026] Step S33, using the K coefficient of the calibration sample obtained in step S2, the PN junction voltage drop curve is converted into a transient cooling curve;

[0027] Step S34, the transient cooling curve is converted into a differential function curve by mathematical transformation;

[0028] Step S35, the differential function curves corresponding to the solder porosities of 0%, 10%, 20% and 50% calibration samples are w1, w2, w3 and w4 respectively; in each differential function curve, the horizontal coordinate thermal resistance value from the origin to the first main peak represents the chip PN junction thermal resistance, i.e. x1, x2, x3 or x4; the horizontal coordinate thermal resistance value from the first main peak to the second main peak represents the solder thermal resistance, i.e. h1, h2, h3 or h4; the horizontal coordinate thermal resistance value from the second main peak to the rightmost end of the differential function curve represents the sum of the thermal resistances of the tube shell substrate, the heat-conducting silicone grease and the Cu block cold plate, i.e. m1, m2, m3 or m4; the horizontal coordinate thermal resistance value from the origin to the rightmost end of the differential function curve represents the total thermal resistance of the calibration sample, i.e. z1, z2, z3 or z4.

[0029] Further, the step S4 comprises:

[0030] Step S41, in the superimposed differential function curve, the chip PN junction thermal resistances corresponding to different solder porosity samples are the same, i.e. x1=x2=x3=x4; the differential function curve segments from the origin to the first main peak also overlap each other;

[0031] Step S42, the solder thermal resistances corresponding to different solder porosity samples are different, and as the porosity increases from 0%, 10%, 20% to 50%, the solder thermal resistance increases from h1, h2, h3 to h4, the differential function curve segment from the first main peak to the second main peak shifts to the right and up, and the shift amount is related to the porosity, the greater the porosity, the greater the shift amount;

[0032] Step S43, the sum of the thermal resistances of the tube shell substrate, the heat-conducting silicone grease and the Cu block cold plate corresponding to different solder porosity samples is the same, i.e. m1=m2=m3=m4;

[0033] Step S44, as the porosity increases from 0%, 10%, 20% to 50% in turn, the total thermal resistance of the calibration sample from the origin to the right end of the differential function curve increases from z1, z2, z3 to z4 in turn. For any two calibration samples with different porosities, the difference between the total thermal resistances is equal to the difference between the corresponding solder thermal resistances, i.e. z4-z1=h4-h1; z3-z1=h3-h1; z2-z1=h2-h1.

[0034] Further, the step S5 comprises:

[0035] All the calibration samples are opened and ground, the chips are removed from the solder surface, the actual area of the pores and the area of the pads are measured, and the solder porosity is calculated. If the solder porosity is consistent with the design value in the step S1, it indicates that the solder porosity design method and the preparation process are reasonable.

[0036] Further, the step S6 comprises:

[0037] Step S61, according to the diode transient thermal resistance test circuit diagram, the to-be-tested sample is circuit-connected, a test current is loaded to the to-be-tested sample, and the voltage sensor is used to monitor the voltage drop change of the PN junction of the sample;

[0038] Step S62, the to-be-tested sample is placed in an oil tank, the temperature of the oil tank is equal to the PN junction temperature of the sample, the temperature of the oil tank is adjusted, the PN junction voltage drop-temperature curve of the sample is recorded in real time, and the K coefficient of the to-be-tested sample is obtained.

[0039] Further, the step S7 comprises:

[0040] Step S71, after the to-be-tested sample is coated with a heat-conducting silicone grease at the bottom of the tube shell substrate, the to-be-tested sample is fixed on a constant-temperature Cu block cold plate;

[0041] Step S72, a heating current is loaded to the to-be-tested sample, after the junction temperature of the sample reaches a thermal steady state, the heating current is rapidly switched to a test current, and the PN junction voltage drop curve of the sample is monitored by using the voltage sensor;

[0042] Step S73, the PN junction voltage drop curve is converted into a transient cooling curve by using the K coefficient of the to-be-tested sample obtained in the step S6;

[0043] Step S74, the transient cooling curve is converted into a differential function curve w by mathematical transformation, and the solder thermal resistance h and the total thermal resistance z are obtained.

[0044] Further, the step S8 comprises:

[0045] Step S81, if the solder thermal resistance h and the total thermal resistance z of the unknown solder porosity sample satisfy the condition A: h=h1, z=z1, and the differential function curves w and w1 coincide, there is no porosity in the solder layer of the to-be-tested sample.

[0046] Step S82, if the condition B: h1≤h≤h2, z1≤z≤z2, and the differential function curve w is between w1 and w2 are met, the porosity of the solder layer of the sample to be measured is in the range of 0-10%;

[0047] Step S83, if the condition C: h2≤h≤h3, z2≤z≤z3, and the differential function curve w is between w2 and w3 are met, the porosity of the solder layer of the sample to be measured is in the range of 10-20%;

[0048] Step S84, if the condition D: h3≤h≤h4, z3≤z≤z4, and the differential function curve w is between w3 and w4 are met, the porosity of the solder layer of the sample to be measured is in the range of 20-50%;

[0049] Step S85, if the condition E: h4≤h, z4≤z, and the differential function curve w is on the right side of w4 are met, the porosity of the solder layer of the sample to be measured is in the range of 50-100%.

[0050] The method for quantitatively estimating the porosity of the solder layer of the diode provided by the present application has the following advantages:

[0051] 1) The differential function curve and the thermal resistance value of the known solder porosity calibration sample in the present application can be used as a basis for determining whether the unknown solder porosity sample to be measured meets the screening conditions, solving the problem that the traditional thermal resistance test method cannot quantitatively determine the solder porosity.

[0052] 2) The present application not only designs and prepares calibration samples with different solder porosities and determines the relationship between the porosity and the thermal resistance, but also opens and grinds the calibration samples after the test for reverse verification, reducing the error between the designed porosity and the actual porosity in the solder layer and improving the accuracy of the porosity determination.

[0053] 3) The calibration samples designed and prepared in the present application can obtain different solder porosities by adjusting the proportion of the solder area and the porosity area. Under the premise of ensuring that the chip reaches the minimum bonding strength, the solder layer porosity can be changed in the range of 0-80%. In addition, by increasing the number of calibration samples with different porosities, the distribution density of the differential function curve of different porosities can be increased, and the determination range of the porosity of the sample to be measured is more accurate.

[0054] 4) For diode devices of the same model and the same packaging structure produced in batches, the present application can quantitatively analyze multiple unknown solder porosity samples to be measured, and statistically analyze and compare the solder porosity results of multiple samples to be measured, which is helpful for in-depth analysis of the solder process of the batch of products. BRIEF DESCRIPTION OF DRAWINGS

[0055] The application will be further described with reference to the drawings.

[0056] Figure 1 A flow chart of the method for quantitatively estimating the porosity of the solder layer of a diode according to a preferred embodiment of the application;

[0057] Figure 2 A schematic diagram of coating the solder on the top surface of a tube base as a solder area according to a preferred embodiment of the application;

[0058] Figure 3 A schematic diagram of covering the porosity area with a ceramic sheet according to a preferred embodiment of the application;

[0059] Figure 4 A schematic diagram of soldering a diode chip and a tube base according to a preferred embodiment of the application;

[0060] Figure 5 A schematic diagram of bonding a diode chip and a tube base according to a preferred embodiment of the application;

[0061] Figure 6 A schematic diagram of capping the entire sample according to a preferred embodiment of the application;

[0062] Figure 7 A schematic diagram of calibration samples with solder porosities of 0%, 10%, 20%, and 50% according to a preferred embodiment of the application;

[0063] Figure 8 A circuit diagram of a transient thermal resistance test of a diode according to a preferred embodiment of the application;

[0064] Figure 9 A cross-sectional view of a one-dimensional heat dissipation path of a diode device during a transient thermal resistance test according to a preferred embodiment of the application;

[0065] Figure 10 A differential function curve of a calibration sample with a solder porosity of 0% according to a preferred embodiment of the application;

[0066] Figure 11 A superimposed differential function curve of calibration samples with solder porosities of 0%, 10%, 20%, and 50% according to a preferred embodiment of the application. DETAILED DESCRIPTION

[0067] The method for quantitatively estimating the porosity of the solder layer of a diode according to the application will be further described in detail below with reference to the drawings and specific embodiments. The advantages and features of the application will be more apparent according to the following description and claims. It should be noted that the drawings are very simplified and use non-precise ratios, only for the purpose of conveniently and clearly assisting the description of the embodiments of the application.

[0068] The core idea of ​​this invention is to propose a method for quantitatively estimating the porosity of diode solder layers based on differential functions: First, diode devices with different porosities are prepared as calibration samples. The differential function curve and thermal resistance value of the calibration samples are obtained by transient thermal resistance testing to determine the relationship between thermal resistance and porosity. Then, a diode with unknown solder porosity is used as the test sample, and its differential function curve and thermal resistance value are tested. Finally, the parameters of the calibration sample and the test sample are compared to determine the porosity range of the diode sample to be tested.

[0069] Example 1

[0070] Figure 1 This is a flowchart illustrating a preferred embodiment of the method for quantitatively estimating diode solder layer porosity based on a differential function. The method for quantitatively determining solder porosity based on a differential function curve includes the following steps:

[0071] Step S1: Prepare calibration samples with different solder porosities;

[0072] Step S2: Determine the K coefficient of the calibration sample;

[0073] Step S3: Monitor the PN junction voltage drop of the calibration sample, obtain the differential function curve of the calibration sample through mathematical transformation, and extract the thermal resistance parameter;

[0074] Step S4: Superimpose the differential function curves of different calibration samples to determine the relationship between solder thermal resistance, total thermal resistance and porosity;

[0075] Step S5: Unpack and grind the calibration sample to verify the porosity of the solder layer;

[0076] Step S6: Determine the K coefficient of the test sample with unknown solder porosity;

[0077] Step S7: Monitor the PN junction voltage drop of the sample under test, obtain the differential function curve of the sample under test through mathematical transformation, and extract the thermal resistance parameter;

[0078] Step S8: Determine the porosity range of the solder layer of the sample to be tested.

[0079] In this embodiment, the specific steps are as follows:

[0080] (1) Figure 2 This is a schematic diagram illustrating a preferred embodiment of the present invention, showing the application of solder to the upper surface of a substrate as a solder area. Figure 2 As shown, in step S11, solder of different areas is first coated on the pad area 112 on the upper surface of the tube shell substrate 111 as solder area 113, and the uncoated area represents the pore area 114.

[0081] Figure 3A schematic diagram of covering the aperture area with a ceramic sheet for the preferred embodiment of the present application. As shown in Figure 3 In step S12, the aperture area 114 is covered with a ceramic sheet 115 to prevent the solder from flowing into the aperture area 114 during the heating process.

[0082] Figure 4 A schematic diagram of soldering the diode chip and the tube base substrate for the preferred embodiment of the present application. As shown in Figure 4 In step S13, the diode chip 116 is placed on the pad area 112 covered with the ceramic sheet 115, and the entire sample is placed on a heating tube 117 for reflow soldering, so that the solder in the solder area 113 melts and connects the diode chip 116 and the tube base substrate 111, and then naturally cools to room temperature.

[0083] Figure 5 A schematic diagram of bonding the diode chip and the tube base substrate for the preferred embodiment of the present application. As shown in Figure 5 In step S14, the ceramic sheet 115 is removed, and the diode chip 116 and the tube base substrate 111 are bonded 118.

[0084] Figure 6 A schematic diagram of capping the entire sample for the preferred embodiment of the present application. As shown in Figure 6 In step S15, the entire sample is capped to form a tube cover plate 119, and calibration samples with solder porosities of 0%, 10%, 20%, and 50% are obtained.

[0085] Figure 7 A schematic diagram of calibration samples with solder porosities of 0%, 10%, 20%, and 50% for the preferred embodiment of the present application.

[0086] (2) Figure 8 A circuit diagram of diode transient thermal resistance testing for the preferred embodiment of the present application. As shown in Figure 8 121 is a diode calibration sample with temperature-sensitive characteristics, VF voltage sensor 122 of T3ster equipment is used to monitor the PN junction voltage drop of the diode, IH constant current source 123 is used as the heating current, and IM constant current source 124 is used as the test current. The actual directions of the heating current and the test current are the same, and VF, IH, and IM are all positive (+).

[0087] In step S21, the calibration sample is connected according to the diode transient thermal resistance testing circuit diagram, and T3ster equipment is used to load only 5mA of test current 124 on a single calibration sample, without loading heating current 123. VF voltage sensor 122 is used to monitor the PN junction voltage drop of the single calibration sample 121 in real time.

[0088] In step S22, a single calibration sample 121 is placed in an oil bath, the oil bath temperature being equal to the sample's PN junction temperature. The oil bath temperature is adjusted to gradually increase the device's PN junction temperature from 20°C to 170°C at a heating rate of 5°C / minute. The interval between temperature monitoring points is set to 5°C. After the device junction temperature stabilizes at each temperature monitoring point, the corresponding PN junction voltage drop is measured. After the test, the PN junction voltage drop-junction temperature curve, i.e., the K-coefficient curve, is plotted.

[0089] (3) Figure 9 This is a cross-sectional view of the one-dimensional heat dissipation path of the diode device during transient thermal resistance testing, according to a preferred embodiment of the present invention. Figure 9 As shown, 116 is the diode chip, 113 is the solder area, 114 is the pore area, 111 is the tube shell substrate, 119 is the tube shell cover plate, 136 is the thermal grease, and 137 is the Cu block cold plate.

[0090] In step S31, after applying thermally conductive silicone grease 136 to the bottom of the single calibration sample substrate 111, the calibration sample is fixed on the Cu block cold plate 137, and the temperature of the Cu block cold plate is maintained at 20°C. During the transient thermal resistance test, the diode device satisfies a one-dimensional heat dissipation path. The heat generated by the diode chip 116 is mainly conducted outward through the heat dissipation path of solder area 113-substrate 111-thermally conductive silicone grease 136-Cu block cold plate 137.

[0091] In step S32, a heating current of 10A is applied to the calibration sample 121 using a T3ster device. After the sample junction temperature reaches thermal steady state, the heating current 123 is quickly switched to a test current of 5mA 124. The PN junction voltage drop curve of the calibration sample 121 is monitored using a VF voltage sensor 122 until the PN junction voltage drop of the device reaches a stable value.

[0092] In step S33, the K coefficient of the sample is calibrated using step S2, and the PN junction voltage drop curve is converted into a transient cooling curve.

[0093] In step S34, the transient cooling curve is converted into a differential function curve through mathematical transformation.

[0094] In step S35, the differential function curves corresponding to the calibration samples with solder porosity of 0%, 10%, 20%, and 50% are w1, w2, w3, and w4, respectively. Figure 10The differential function curve w1 of the solder porosity 0% calibration sample of the preferred embodiment of the present application. In the differential function curve, the horizontal coordinate is thermal resistance value, and the vertical coordinate is thermal capacity value. The horizontal coordinate thermal resistance value corresponding to the first main peak from the origin represents the chip PN junction thermal resistance x1. The horizontal coordinate thermal resistance value corresponding to the second main peak from the first main peak represents the solder thermal resistance h1. The horizontal coordinate thermal resistance value corresponding to the second main peak to the right end of the differential function curve represents the sum of the package substrate, thermal conductive silicone grease and Cu block cold plate thermal resistance m1. The horizontal coordinate thermal resistance value corresponding to the origin to the right end of the differential function curve represents the total thermal resistance z1 of the calibration sample (z1 = x1 + h1 + m1). The PN junction thermal resistances of the 10%, 20% and 50% solder porosity calibration samples are x2, x3 and x4 respectively; the solder thermal resistances are h2, h3 and h4 respectively; the sums of the package substrate, thermal conductive silicone grease and Cu block cold plate thermal resistances are m2, m3 and m4 respectively; and the total thermal resistances are z2, z3 and z4 respectively (z2 = x2 + h2 + m2; z3 = x3 + h3 + m3; z4 = x4 + h4 + m4).

[0095] (4) Figure 11 The differential function curve superimposition of the solder porosities 0%, 10%, 20% and 50% of the preferred embodiment of the present application.

[0096] In step S41, the chip PN junction thermal resistances corresponding to different solder porosities in the superimposed differential function curve are the same (x1 = x2 = x3 = x4), and the differential function curve segments from the origin to the first main peak are also mutually overlapped;

[0097] In step S42, the solder thermal resistances corresponding to different solder porosities are different, and as the porosities increase from 0%, 10%, 20% to 50% in turn, the solder thermal resistances increase from h1, h2, h3 to h4 in turn, the differential function curve segments from the first main peak to the second main peak are shifted to the right and up, and the shift amount is related to the porosity, the greater the porosity, the greater the shift amount;

[0098] In step S43, the sums of the package substrate, thermal conductive silicone grease and Cu block cold plate thermal resistances corresponding to different solder porosities are the same (m1 = m2 = m3 = m4), although the corresponding differential function curve segments are not mutually overlapped, but the basic trend is consistent;

[0099] In step S44, as the porosities increase from 0%, 10%, 20% to 50% in turn, the total thermal resistances of the calibration samples from the origin to the right end of the differential function curve increase from z1, z2, z3 to z4 in turn. For any two porosity calibration samples, the difference between the total thermal resistances is equal to the difference between the corresponding solder thermal resistances (z4 - z1 = h4 - h1; z3 - z1 = h3 - h1; z2 - z1 = h2 - h1).

[0100] (5) Open and grind all calibration samples, remove the diode chip from the solder surface, measure the actual area of the hole Q and the pad area T, and calculate the solder porosity R (R = Q / T). If the solder porosity R is consistent with the test design value of 0%, 10%, 20%, and 50% in step S1, it indicates that the solder porosity design method and preparation process are reasonable.

[0101] (6) In step S61, the sample to be tested is connected according to the diode transient thermal resistance test circuit diagram, and a test current is loaded on the sample to be tested. The voltage sensor is used to monitor the voltage drop change of the PN junction of the sample;

[0102] In step S62, the sample to be tested is placed in an oil tank, and the oil tank temperature is equal to the PN junction temperature of the sample. The oil tank temperature is adjusted, and the PN junction voltage drop-temperature curve of the sample is recorded in real time to obtain the K coefficient of the sample to be tested.

[0103] (7) In step S71, after the heat-conducting silicone grease is coated on the bottom of the substrate of the sample to be tested, the sample to be tested is fixed on the constant-temperature Cu block cold plate;

[0104] In step S72, a heating current is loaded on the sample to be tested. After the junction temperature of the sample reaches a thermal steady state, the heating current is quickly switched to a test current, and the PN junction voltage drop curve of the sample is monitored by using a voltage sensor;

[0105] In step S73, the PN junction voltage drop curve is converted into a transient cooling curve using the K coefficient of the sample to be tested obtained in step S6;

[0106] In step S74, the transient cooling curve is converted into a differential function curve w through mathematical transformation to obtain the solder thermal resistance h and the total thermal resistance z.

[0107] (8) Determine the porosity range of the solder layer of the sample to be tested:

[0108] In step S81, if the solder thermal resistance h and the total thermal resistance z of the unknown solder porosity sample satisfy the condition A (h = h1, z = z1), and the differential function curves w and w1 coincide, then there is no porosity in the solder layer of the sample to be tested;

[0109] In step S82, if the condition B (h1≤h≤h2, z1≤z≤z2) is satisfied, and the differential function curve w is located between w1 and w2, then the porosity of the solder layer of the sample to be tested is in the range of 0-10%;

[0110] In step S83, if the condition C (h2≤h≤h3, z2≤z≤z3) is satisfied, and the differential function curve w is located between w2 and w3, then the porosity of the solder layer of the sample to be tested is in the range of 10-20%;

[0111] In step S84, if the condition D (h3≤h≤h4, z3≤z≤z4) is satisfied and the differential function curve w is between w3 and w4, then the porosity of the solder layer of the sample under test is in the range of 20-50%;

[0112] In step S85, if the condition E (h4≤h, z4≤z) is satisfied and the differential function curve w is on the right side of w4, then the porosity of the solder layer of the sample under test is in the range of 50-100%.

[0113] According to the above determination basis, the porosity range of the solder layer of the sample under test can be quantitatively determined, and the maximum thermal resistance of the solder layer when the porosity reaches the critical value can be determined, and whether the sample under test reaches the screening condition can be determined.

[0114] The contents not described in detail in the specification belong to the prior art known to those skilled in the art. It is obvious for those skilled in the art that the present application is not limited to the details of the above exemplary embodiments, and the present application can be implemented in other specific forms without departing from the spirit or essential characteristics of the present application. Therefore, the embodiments should be regarded as exemplary and non-limiting, the scope of the present application is defined by the appended claims rather than the above description, and all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be included in the present application.

Claims

1. A method for quantitatively estimating porosity of a diode solder layer based on a differential function, characterized by, The method comprises the following steps: Step S1, preparing calibration samples with different solder porosities; Step S2, measuring the K coefficient of the calibration sample obtained in step S1; Step S3, monitoring the PN junction voltage drop of the calibration sample obtained in step S1, obtaining the differential function curve of the calibration sample through mathematical transformation, and extracting the thermal resistance parameter; Step S4, superimposing the differential function curves of different calibration samples to determine the relationship between the solder thermal resistance, the total thermal resistance and the porosity; Step S5, opening and grinding the calibration sample obtained in step S1 to verify the solder layer porosity; Step S6, measuring the K coefficient of the unknown solder porosity sample to be tested; Step S7, monitoring the PN junction voltage drop of the sample to be tested in step S6, obtaining the differential function curve of the sample to be tested through mathematical transformation, and extracting the thermal resistance parameter; Step S8, comparing the parameters of the calibration sample and the sample to be tested to determine the solder layer porosity range of the sample to be tested; The step S1 comprises: Step S11, coating different areas of solder as solder areas on the pad area of the top surface of the tube shell substrate, and the uncoated area represents the porosity area; Step S12, covering the porosity area with a ceramic sheet to prevent the solder from flowing into the porosity area during heating; Step S13, placing a diode chip on the pad area covered with a ceramic sheet, placing the entire sample on a heating tube for reflow soldering, melting the solder in the solder area and connecting the diode chip and the tube shell substrate, and naturally cooling to room temperature; Step S14, removing the ceramic sheet and bonding the diode chip and the tube shell substrate; Step S15, capping the entire sample to obtain calibration samples with solder porosities of 0%, 10%, 20% and 50%, respectively; The step S2 comprises: Step S21, connecting the calibration sample according to the diode transient thermal resistance test circuit diagram, loading a test current on a single calibration sample, and monitoring the voltage drop change of the sample PN junction using a voltage sensor; Step S22, placing a single calibration sample in an oil tank, the oil tank temperature being equal to the sample PN junction temperature, adjusting the oil tank temperature change, and recording the PN junction voltage drop-temperature curve of the sample in real time to obtain the K coefficient of the calibration sample; The step S3 comprises: Step S31, after coating a heat-conducting silicone grease on the bottom of the tube shell substrate of a single calibration sample, fixing the calibration sample on a constant-temperature Cu block cold plate; Step S32, loading a heating current on the sample, rapidly switching the heating current to a test current after the sample junction temperature reaches a thermal steady state, and monitoring the PN junction voltage drop curve of the sample using a voltage sensor; Step S33, converting the PN junction voltage drop curve to a transient cooling curve using the K coefficient of the calibration sample obtained in step S2; Step S34, converting the transient cooling curve to a differential function curve through mathematical transformation; The differential function curves corresponding to the solder porosity calibration samples of 0%, 10%, 20% and 50% are w1, w2, w3 and w4 respectively; in each differential function curve, the thermal resistance value of the abscissa corresponding to the chip PN junction thermal resistance from the origin to the first main peak represents the chip PN junction thermal resistance, i.e. x1, x2, x3 or x4; the thermal resistance value of the abscissa corresponding to the solder thermal resistance from the first main peak to the second main peak represents the solder thermal resistance, i.e. h1, h2, h3 or h4; the thermal resistance value of the abscissa corresponding to the sum of the thermal resistances of the package substrate, the heat-conducting silicone grease and the Cu block cold plate from the second main peak to the right end of the differential function curve represents the sum of the thermal resistances of the package substrate, the heat-conducting silicone grease and the Cu block cold plate, i.e. m1, m2, m3 or m4; the thermal resistance value of the abscissa corresponding to the total thermal resistance of the calibration sample from the origin to the right end of the differential function curve represents the total thermal resistance of the calibration sample, i.e. z1, z2, z3 or z4; The step S4 comprises: In the superimposed differential function curve, the chip PN junction thermal resistances corresponding to different solder porosity samples are the same, i.e. x1=x2=x3=x4; the differential function curve segment from the origin to the first main peak is also mutually overlapped; The solder thermal resistances corresponding to different solder porosity samples are different, and the solder thermal resistance increases from h1, h2, h3 to h4 as the porosity increases from 0%, 10%, 20% to 50% in turn, and the differential function curve segment from the first main peak to the second main peak shifts to the right and upward, and the shift amount is related to the porosity, and the greater the porosity, the greater the shift amount; The sum of the thermal resistances of the package substrate, the heat-conducting silicone grease and the Cu block cold plate corresponding to different solder porosity samples is the same, i.e. m1=m2=m3=m4; As the porosity increases from 0%, 10%, 20% to 50% in turn, the total thermal resistance of the calibration sample from the origin to the right end of the differential function curve increases from z1, z2, z3 to z4 in turn, and for any two porosity calibration samples, the difference between the total thermal resistances is equal to the difference between the corresponding solder thermal resistances, i.e. z4-z1=h4-h1; z3-z1=h3-h1; z2-z1=h2-h1; The step S6 comprises: Step S61, according to the diode transient thermal resistance test circuit diagram, the circuit of the to-be-tested sample is connected, a test current is loaded to the to-be-tested sample, and a voltage sensor is used to monitor the voltage drop change of the sample PN junction; Step S62, the to-be-tested sample is placed in an oil tank, the oil tank temperature is equal to the sample PN junction temperature, the oil tank temperature is adjusted, the PN junction voltage drop-temperature curve of the sample is recorded in real time, and the K coefficient of the to-be-tested sample is obtained; The step S7 comprises: Step S71, after the heat-conducting silicone grease is coated on the bottom of the package substrate of the to-be-tested sample, the to-be-tested sample is fixed on the constant-temperature Cu block cold plate; Step S72, a heating current is loaded to the to-be-tested sample, after the sample junction temperature reaches a thermal steady state, the heating current is rapidly switched to a test current, and a voltage sensor is used to monitor the PN junction voltage drop curve of the sample; Step S73, the PN junction voltage drop curve is converted into a transient cooling curve by using the K coefficient of the to-be-tested sample obtained in the step S6. Step S74, converting the transient temperature curve into a differential function curve w by mathematical transformation, obtaining the solder thermal resistance h and the total thermal resistance z; The step S8 includes: Step S81, if the solder thermal resistance h and the total thermal resistance z of the unknown solder porosity sample satisfy the condition A: h=h1, z=z1, and the differential function curves w and w1 coincide, then the solder layer of the sample to be measured is free of porosity; Step S82, if the condition B: h1≤h≤h2, z1≤z≤z2, and the differential function curve w is between w1 and w2 is satisfied, then the porosity of the solder layer of the sample to be measured is in the range of 0-10%; Step S83, if the condition C: h2≤h≤h3, z2≤z≤z3, and the differential function curve w is between w2 and w3 is satisfied, then the porosity of the solder layer of the sample to be measured is in the range of 10-20%; Step S84, if the condition D: h3≤h≤h4, z3≤z≤z4, and the differential function curve w is between w3 and w4 is satisfied, then the porosity of the solder layer of the sample to be measured is in the range of 20-50%; Step S85, if the condition E: h4≤h, z4≤z, and the differential function curve w is on the right side of w4 is satisfied, then the porosity of the solder layer of the sample to be measured is in the range of 50-100%.

2. The method for quantitatively evaluating porosity of a diode solder layer based on a differential function according to claim 1, wherein The step S5 includes: All the calibration samples are opened and ground, the chip is removed from the solder surface, the actual area of the hole and the area of the pad are measured, and the solder porosity is calculated; if the solder porosity is consistent with the design value of the step S1 test, it indicates that the solder porosity design method and the preparation process are reasonable.

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