FPGA-based integrated circuit testing system and method

Abstract

The present invention discloses an FPGA-based integrated circuit test system, belonging to the field of integrated circuit testing. The integrated circuit test system is integrated on the FPGA and includes an interface function unit, a configurable scan chain module, a function configuration module, an IO function mapping control module, a system control module, and a data sampling and uploading module. The interface function unit modularizes the interface function; the configurable scan chain module configures the simulation sequence information of the scan chain; the function configuration module configures the functions of the interface function unit and the configurable scan chain module of the FPGA; the IO function mapping control module remaps the IO pins of the test system connected to the integrated circuit to match the function; the system control module receives the configuration information of the host computer and controls the initialization and enabling of the interface function of the configuration interface function unit; the data sampling and uploading module reads the status of the status control module and uploads the scan chain test and function test results to the host computer via the serial port.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit testing, and in particular to an integrated circuit testing system and method based on FPGA. Background Art

[0002] Traditional verification testing requires technicians to have solid professional knowledge, use devices such as logic analyzers or microcontrollers to provide data signal stimulation, use devices such as oscilloscopes to view the waveform output of the logic design and measure the operating frequency, and use various measuring instruments for communication modules to perform complex and repetitive manual wiring and manually compare measurement results.

[0003] The reasons for choosing FPGA-based testing methods to perform functional and performance testing on SoC chips are based on the following three aspects: 1. Most companies that provide high-end chip testing technology and produce high-precision testing equipment are located abroad. The testing tools produced by some large companies, such as Texas Instruments, are not disclosed to the public due to commercial confidentiality, resulting in high costs and technical monopoly problems; 2. SoC chips are developing in a trend of high density, high speed, and multi-functions, and the compatibility of test systems is more favored by the market; 3. FPGA-based test application platforms have the characteristics of high system performance, good flexibility, and low cost, which are more conducive to product versatility. Summary of the Invention

[0004] The purpose of the present invention is to provide an integrated circuit testing system and method based on FPGA to solve the problems in the background technology.

[0005] To solve the above technical problems, the present invention provides an FPGA-based integrated circuit test system, which is integrated on the FPGA and includes an interface function unit, a configurable scan chain module, a function configuration module, an IO function mapping control module, a system control module, and a data sampling and uploading module;

[0006] The interface function unit modularizes the interface function, configures the initialization parameters of the interface, and enables the interface to be sent to the system control module through the host computer to realize the function configuration;

[0007] The configurable scan chain module receives control information from the system control module via the AXI bus, configures simulation sequence information of the scan chain, and sends the scan chain test results and status to the system control module via the AXI bus;

[0008] The function configuration module receives control information from the system control module via the AIX bus and configures the interface function unit of the FPGA and the function of the configurable scan chain module;

[0009] The IO function mapping control module receives configuration information of the system control module through the AXI bus, and remaps the IO pins of the test system connected to the integrated circuit to match the function;

[0010] The system control module is connected to an external host computer via a serial port, receives configuration information from the host computer, and controls the initialization and enabling of the interface function of the configuration interface function unit through the AIX bus according to the configuration information input online, and controls the initialization and enabling of the configurable scan chain module at the same time;

[0011] The data sampling upload module accesses the interface function unit and the state control module of the configurable scan chain module through the AXI bus, reads the state of the state control module, and finally uploads the scan chain test and function test results to the host computer through the serial port.

[0012] In one embodiment, the interface function unit includes a configurable enable submodule, a configurable parameter submodule and various interface unit functional entity modules; the various interface unit functional entity modules are IIC, UART, SPI, QSPI and 1553B communications, and the functional configuration module receives configuration information from the system control module through the AXI bus configuration to configure the interface function unit.

[0013] In one embodiment, the configurable scan chain module includes a configurable scan chain parameterization submodule, a configurable scan chain enabling submodule and a configurable scan chain functional entity, which is sent to the system control module by the host computer to enable the configurable scan chain module and dynamically configure the scan chain configuration function parameters.

[0014] In one embodiment, the function configuration module includes a parameter cache submodule and a parameter reading and writing submodule. The parameter reading and writing submodule reads the function parameter information and enable information issued by the system control module, performs parameter configuration, enablement and function switching on the interface function unit and the configurable scan chain module; and caches the parameter information in the parameter cache submodule.

[0015] In one embodiment, the IO function mapping control module includes an IO configuration submodule, an IO multiplexing control submodule and a mapping unit; the IO multiplexing control submodule is connected to the interface function unit and the configurable scan chain module. The IO configuration submodule configures the IO multiplexing control submodule based on information from the upstream AXI bus, and interconnects and maps the interface of the interface function unit or the configurable scan chain module with the mapping unit of the pin, and connects them to the integrated circuit under test.

[0016] In one embodiment, the system control module includes a host computer communication transceiver control submodule, a data processing submodule and an enable control submodule; the communication transceiver control submodule completes the reception of instructions and parameters from the host computer and the return of the results of the integrated circuit to be tested, the data processing submodule controls the packaging and sending of information from the upstream and the packaging and uploading of downstream information, and the enable control submodule completes the enable control of the interface function unit, the configurable scan chain module, the function configuration module, the IO function mapping control module, and the data sampling and upload module.

[0017] In one embodiment, the data sampling and uploading module includes a data sampling submodule and a data uploading submodule; during the test of the interface functional unit, the data sampling submodule reads the test information of the interface functional unit through the AXI bus to complete the test data sampling statistics; during the scan chain test, the data sampling submodule reads the status information in the status control module of the configurable scan chain functional entity in the configurable scan chain module through the AXI bus to complete data sampling; for the completed sampling data, the data information is transmitted to the host computer communication transceiver control submodule in the system control module, and the results of the integrated circuit to be tested are sent to the host computer.

[0018] The present invention also provides an integrated circuit testing method based on FPGA, comprising the following steps:

[0019] Step S1: sending the general interface function or scan chain original excitation parameters required by the integrated circuit to be tested to the function configuration module through the communication interface, and the function configuration module caches the configuration information;

[0020] Step S2: According to the requirements of the IC under test, when testing normal functions, the host computer issues a normal function test instruction, the system control module parses the instruction, resets the IC under test, enables normal function testing of the IC under test and the test system, maps the interface of the configurable test system to the corresponding interface, tests the universal interface, and completes interface detection between the test system and the IC under test. The test system detects the interface communication data and compares it to check whether it is correct.

[0021] When testing the scan chain function, the system control module parses the instruction, resets the IC under test, enables the scan chain function test of the IC under test and the test system, and sends the scan chain sequence with initialized parameters to the IC under test. When the scan chain data is returned, the test system uploads the scan chain test results to the host computer.

[0022] Step S3: According to the protocol requirements, the detected integrated circuit result information is transmitted to the host computer through the data sampling upload module via the communication interface. When an error occurs, the error information is uploaded to the host computer. When no error occurs, the number of correct passes is sent to the host computer, and the next round of detection is carried out.

[0023] The FPGA-based integrated circuit testing system and method provided by the present invention have the following beneficial effects:

[0024] (1) The parameter configuration of the IC to be tested can be configured and tested in real time, which is fast. Both normal interface functions and scan chain detection can be realized, and the detection is efficient.

[0025] (2) Using FPGA-based development, functions and pins can be remapped, making the system highly reusable, compatible, and cost-effective;

[0026] (3) It can effectively screen out defective integrated circuits to improve product quality. It is also compatible with general interface function testing to further detect the functional quality of the chip, thereby improving product quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 This is an overall block diagram of an integrated circuit test system based on FPGA proposed by the present invention.

[0028] Figure 2 It is a schematic diagram of the internal structure of the system control module, function configuration module and data sampling and uploading module.

[0029] Figure 3 It is the internal structure block diagram of the interface functional unit.

[0030] Figure 4 This is the internal block diagram of the configurable scan chain module.

[0031] Figure 5 This is the internal block diagram of the IO function mapping control module.

[0032] Figure 6 It is a flow chart of an integrated circuit testing method based on FPGA proposed by the present invention. DETAILED DESCRIPTION

[0033] The following is a detailed description of the FPGA-based integrated circuit test system and method proposed by the present invention, with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are highly simplified and not to exact scale, and are intended solely to facilitate and clearly illustrate the embodiments of the present invention.

[0034] The present invention provides a novel FPGA-based integrated circuit test system, the overall block diagram is as follows Figure 1 As shown, the system includes an interface function unit, a configurable scan chain module, a function configuration module, an IO function mapping control module, a system control module, and a data sampling and uploading module.

[0035] The general interface functions or original excitation parameters of the scan chain required by the IC to be tested are sent to the system control module through the communication interface. Figure 2 In the system control module shown, the host computer communication transceiver control submodule transmits information from the host computer to the data processing submodule and the enable control submodule. The data processing submodule unpacks the information received from the host computer communication transceiver control submodule and sends the enable information to the enable control submodule. In conjunction with the enable control submodule, the parameter information is sent to the function configuration module. The enable control submodule also controls the enabling of the data sampling and upload module. After the parameter cache submodule in the function configuration module caches the parameter information, the parameter read / write submodule sends the parameter information to the AXI bus for transmission to downstream devices.

[0036] like Figure 3 As shown, the interface functional unit includes a configurable enabling submodule, a configurable parameter submodule, and various interface entity submodules. The configurable enabling submodule and the configurable parameter submodule receive parameter configuration information and enabling information from the upstream of the AXI bus, and configure and enable each interface unit functional entity module. The interfaces supported for enabling and initializing include UART, SPI, QSPI, IIC, and 1553B interfaces. The initialization parameters and enabling of the configured interfaces can be sent to the system control module via the host computer to implement functional configuration. The communication interface of the interface unit functional entity module is connected to the IO function mapping control module.

[0037] like Figure 4 As shown, the configurable scan chain module includes a configurable scan chain parameterization submodule, a configurable scan chain enable submodule, and a configurable scan chain functional entity. The configurable scan chain parameterization submodule and the configurable scan chain enable submodule receive parameter configuration information and enable information from the upstream AXI bus, configure and enable the configurable scan chain functional entity, initialize its parameters, and implement functional configuration. The data transceiver interface of the configurable scan chain functional entity is connected to the IO function mapping control module.

[0038] like Figure 5 As shown, the IO function mapping control module includes an IO configuration submodule, an IO multiplexing control submodule, and a mapping unit. The IO configuration submodule receives parameter configuration information and enable information from the upstream AXI bus. The IO multiplexing control submodule is connected to the interface function unit and the configurable scan chain module. The IO configuration submodule configures the IO multiplexing control submodule based on the information from the upstream AXI bus, interconnects and maps the interface of the interface function unit or the configurable scan chain module with the pin mapping unit, and connects them to the integrated circuit under test.

[0039] The present invention also provides a novel FPGA-based integrated circuit testing method, the process of which is as follows: Figure 6 As shown, the following steps are included:

[0040] Step S1: sending the general interface function or scan chain original excitation parameters required by the integrated circuit to be tested to the function configuration module through the communication interface, and the function configuration module caches the configuration information;

[0041] Step S2: According to the requirements of the IC under test, when testing normal functions, the host computer issues a normal function test instruction, the system control module parses the instruction, resets the IC under test, enables normal function testing of the IC under test and the test system, maps the interface of the configurable test system to the corresponding interface, tests the universal interface, and completes interface detection between the test system and the IC under test. The test system detects the interface communication data and compares it to check whether it is correct.

[0042] When testing the scan chain function, the system control module parses the instruction, resets the IC under test, enables the scan chain function test of the IC under test and the test system, and sends the scan chain sequence with initialized parameters to the IC under test. When the scan chain data is returned, the test system uploads the scan chain test results to the host computer.

[0043] Step S3: According to the protocol requirements, the detected integrated circuit result information is transmitted to the host computer through the data sampling upload module via the communication interface. When an error occurs, the error information is uploaded to the host computer. When no error occurs, the number of correct passes is sent to the host computer, and the next round of detection is carried out.

[0044] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. An integrated circuit test system based on FPGA, characterized in that: The integrated circuit test system is integrated on FPGA, including interface function unit, configurable scan chain module, function configuration module, IO function mapping control module, system control module, and data sampling and uploading module; The interface function unit modularizes the interface function, configures the initialization parameters of the interface, and enables the interface to be sent to the system control module through the host computer to realize the function configuration; The configurable scan chain module receives control information from the system control module via the AXI bus, configures simulation sequence information of the scan chain, and sends the scan chain test results and status to the system control module via the AXI bus; The function configuration module receives control information from the system control module via the AIX bus and configures the interface function unit of the FPGA and the function of the configurable scan chain module; The IO function mapping control module receives configuration information of the system control module through the AXI bus, and remaps the IO pins of the test system connected to the integrated circuit to match the function; The system control module is connected to an external host computer via a serial port, receives configuration information from the host computer, and controls the initialization and enabling of the interface function of the configuration interface function unit through the AIX bus according to the configuration information input online, and controls the initialization and enabling of the configurable scan chain module at the same time; The data sampling upload module accesses the interface function unit and the state control module of the configurable scan chain module through the AXI bus, reads the state of the state control module, and finally uploads the scan chain test and function test results to the host computer through the serial port; The system control module includes a host computer communication transceiver control submodule, a data processing submodule and an enable control submodule; the communication transceiver control submodule completes the reception of host computer instructions and parameters and the return of the results of the integrated circuit to be tested; the data processing submodule controls the packaging and sending of upstream information and the packaging and uploading of downstream information; the enable control submodule completes the enable control of the interface function unit, the configurable scan chain module, the function configuration module, the IO function mapping control module, and the data sampling and upload module.

2. The FPGA-based integrated circuit test system according to claim 1, wherein: The interface function unit includes a configurable enable submodule, a configurable parameter submodule and various interface unit functional entity modules; the various interface unit functional entity modules are IIC, UART, SPI, QSPI and 1553B communications, and the function configuration module receives configuration information from the system control module through the AXI bus configuration to configure the interface function unit.

3. The FPGA-based integrated circuit test system according to claim 1, wherein: The configurable scan chain module includes a configurable scan chain parameterization submodule, a configurable scan chain enabling submodule and a configurable scan chain functional entity, which is sent to the system control module by the host computer to enable the configurable scan chain module and dynamically configure the scan chain configuration function parameters.

4. The FPGA-based integrated circuit test system according to claim 1, wherein: The function configuration module includes a parameter cache submodule and a parameter reading and writing submodule. The parameter reading and writing submodule reads the function parameter information and enable information issued by the system control module, and performs parameter configuration, enablement and function switching on the interface function unit and the configurable scan chain module. And the parameter information is cached in the parameter cache submodule.

5. The FPGA-based integrated circuit test system according to claim 4, wherein: The IO function mapping control module includes an IO configuration submodule, an IO multiplexing control submodule, and a mapping unit; the IO multiplexing control submodule is connected to the interface function unit and the configurable scan chain module. The IO configuration submodule configures the IO multiplexing control submodule based on information from the upstream AXI bus, interconnects and maps the interface of the interface function unit or the configurable scan chain module with the pin mapping unit, and connects them to the integrated circuit under test.

6. The FPGA-based integrated circuit test system according to claim 1, wherein: The data sampling and uploading module includes a data sampling submodule and a data uploading submodule; during the test of the interface functional unit, the data sampling submodule reads the test information of the interface functional unit through the AXI bus to complete the test data sampling statistics; during the scan chain test, the data sampling submodule reads the status information in the state control module of the configurable scan chain functional entity in the configurable scan chain module through the AXI bus to complete the data sampling; For the completed sampling data, the data information is transmitted to the host computer communication transceiver control submodule in the system control module, and the results of the integrated circuit to be tested are sent to the host computer.

7. A testing method for an integrated circuit testing system based on the FPGA according to claim 1, characterized in that: The steps include: Step S1: sending the general interface function or scan chain original excitation parameters required by the integrated circuit to be tested to the function configuration module through the communication interface, and the function configuration module caches the configuration information; Step S2: According to the requirements of the IC under test, when testing normal functions, the host computer issues a normal function test instruction, the system control module parses the instruction, resets the IC under test, enables normal function testing of the IC under test and the test system, maps the interface of the configurable test system to the corresponding interface, tests the universal interface, and completes interface detection between the test system and the IC under test. The test system detects the interface communication data and compares it to check whether it is correct. When testing the scan chain function, the system control module parses the instruction, resets the IC under test, enables the scan chain function test of the IC under test and the test system, and sends the scan chain sequence with initialized parameters to the IC under test. When the scan chain data is returned, the test system uploads the scan chain test results to the host computer. Step S3: According to the protocol requirements, the detected integrated circuit result information is transmitted to the host computer through the data sampling upload module via the communication interface. When an error occurs, the error information is uploaded to the host computer. When no error occurs, the number of correct passes is sent to the host computer, and the next round of detection is carried out.

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