A method for low-power automatic voltage regulation of chips

Abstract

This invention discloses a method for automatic low-power voltage regulation of a chip, comprising: initializing the voltage regulation module by writing preset data into the internal FIFO of the voltage regulation module; the chip's low-power control module notifying the voltage regulation module to step down and enter a low-power mode; the voltage regulation module sending a step-down command to a peripheral device based on the internal FIFO data; when the chip enters the low-power mode, the voltage regulation module monitoring the chip's wake-up interrupt command; upon receiving a wake-up interrupt command, the voltage regulation module sending a boost command to the peripheral device based on the internal FIFO data. The method and design of this invention, through automatic hardware voltage regulation, eliminates the need for CPU intervention, achieving a lower operating voltage for the chip in low-power mode and significantly reducing chip power consumption.

Description

Technical Field

[0001] This invention discloses a method for automatic voltage regulation of chips under low power consumption, which relates to the field of chip design technology, and in particular to a technology for automatic voltage regulation by hardware in the case of low power consumption without software control. Background Technology

[0002] Low power consumption is currently a key focus in the chip industry. Under the same performance conditions, lower power consumption is more beneficial for reducing costs and improving product competitiveness. A common low-power design approach is to reduce the chip voltage to the lowest permissible value when the chip is not in operation, thereby saving power.

[0003] In current technology, power management chips (PMIC / CPLD) are generally connected to the main chip through low-speed peripherals, such as SPMI and I2C. In normal operating mode, the CPU can send voltage adjustment commands via SPMI / I2C, but in low-power mode, the CPU cannot operate and therefore cannot send voltage adjustment commands.

[0004] Existing technologies lack chip designs that regulate voltage by controlling an external power supply chip via peripheral devices, especially technologies that allow automatic voltage regulation in hardware under low power consumption conditions without software control. Summary of the Invention

[0005] The technical problem to be solved by this invention is: in order to overcome the problem of voltage regulation in the low power mode of existing chips, this invention provides a method for automatic voltage regulation of chips in low power mode, which realizes automatic voltage regulation without CPU participation in low power mode, greatly reduces the operating voltage of chips in low power mode, and achieves the purpose of making chips more energy-efficient.

[0006] To solve the above-mentioned technical problems, the present invention adopts the following technical solution:

[0007] A method for low-power automatic voltage regulation of a chip, characterized by comprising the following steps:

[0008] Step 1: Initialize the voltage regulator module by writing the preset data into the internal FIFO of the voltage regulator module;

[0009] Step 2: The chip's low-power control module notifies the voltage regulation module to reduce the voltage and enter low-power mode;

[0010] Step 3: The voltage regulation module sends a step-down command to the peripheral device based on the internal FIFO data;

[0011] Step 4: When the chip enters low-power mode, the voltage regulation module monitors the chip's wake-up interrupt instruction;

[0012] Step 5: Upon receiving the wake-up interrupt command, the voltage regulation module sends a boost command to the peripheral device based on the internal FIFO data.

[0013] As a further preferred option, in step one, before the voltage regulation module works, the CPU or other master writes the preset data into the module's internal FIFO through the APB interface.

[0014] As a further preferred option, the preset data is divided into write address and write data, each with its own independent FIFO.

[0015] As a further preferred option, the specific content of the preset data is the APB write command for the chip peripheral control external power supply control chip voltage regulation.

[0016] As a further preferred option, the size of the internal FIFO is set according to the specific project requirements.

[0017] As a further preferred option, in step two, the chip's low-power control module controls other modules inside the chip to enter a low-power mode before notifying the voltage regulation module to reduce the voltage.

[0018] As a further preferred option, after the chip enters low-power mode and the voltage regulation module completes the voltage reduction, the chip retains one low-frequency clock source as the working clock of the voltage regulation module, and the other high-frequency clocks are turned off.

[0019] As a further preferred option, the wake-up interrupt instruction is configured according to the specific project requirements.

[0020] As a further preferred option, after the chip receives a wake-up interrupt, the voltage regulation module first sends a boost command, and other modules only start working after the boost is completed.

[0021] As a further preferred option, the chip's low-power module and voltage regulation module need to handshake when the chip enters or exits low-power mode to ensure correct timing.

[0022] Compared with the prior art, the present invention has the following technical effects: The method and design of the present invention achieve a lower operating voltage of the chip in low power mode without the need for CPU intervention through automatic hardware voltage regulation, which significantly reduces the power consumption of the chip. Attached Figure Description

[0023] Figure 1 This is a flowchart of the process of the present invention.

[0024] Figure 2 This is a schematic diagram of the module connection inside the chip according to the present invention.

[0025] Wherein: ① is the APB interface between the voltage regulation module and the chip's internal bus; ② and ③ are the handshake signals between the voltage regulation module and the chip's low-power control module; ④ is the chip's interrupt wake-up signal; and ⑤ is the APB interface between the voltage regulation module and the peripheral SPMI / I2C.

[0026] Figure 3 This is a schematic diagram of the internal structure of the module of the present invention.

[0027] Wherein: ① is the APB interface for data writing; ② is the request signal input from the low-power control module; ③ is the response signal from the voltage regulation module to the low-power control module; ④ is the chip wake-up interrupt signal; ⑤ is the APB interface for sending commands to the downstream SPMI / I2C; ⑥ and ⑦ are the data written to the two FIFOs by the APB interface respectively; ⑧ and ⑨ are the handshake signals between the interrupt monitor and the low-power interface; ⑩ is the handshake signal between the interrupt monitor and the FIFO controller. Data read from inside the FIFO; A signal to prepare for a downstream response; Send a read data command to the FIFO controller. Detailed Implementation

[0028] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0029] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings:

[0030] This invention discloses a method for automatic voltage regulation of a chip with low power consumption, the specific workflow of which is as follows: Figure 1 As shown:

[0031] After the chip is powered on, the voltage regulation module is initialized and configured, and the preset data is written into the module's internal FIFO (First Input First Output, a first-in-first-out queue in the data structure) before it starts working.

[0032] When the chip enters low-power mode, the low-power control module and the voltage regulation module complete a handshake. The voltage regulation module sends the APB write command to the peripheral SPMI / I2C based on the internal FIFO data. The peripheral SPMI / I2C sends a command to the external PMIC / CPLD of the chip to complete the voltage reduction operation.

[0033] After the chip's voltage reduction is complete, internal functional modules such as the CPU and SRAM enter a low-power mode and cease operation. For example, if the chip's normal operating voltage is 0.75V, the voltage can be reduced to 0.5V to meet the minimum voltage required for SRAM data storage. The voltage regulation module monitors the chip's wake-up interrupt instructions; at this time, the chip only needs to maintain one low-frequency clock cycle.

[0034] Upon receiving the wake-up interrupt command, the voltage regulation module sends an APB write command to the peripheral SPMI / I2C based on the internal FIFO data. The peripheral SPMI / I2C then sends a command to the external PMIC / CPLD to complete the boost operation.

[0035] After the chip boosts the voltage, the voltage regulation module and the low-power control module complete the handshake, and the low-power control module enables the CPU, SRAM and other functional modules to enter normal working mode.

[0036] In this invention, the connection diagram of the voltage regulation module inside the chip is as follows: Figure 2 As shown: ① is the APB interface between the voltage regulator module and the chip's internal bus; the bus writes data to the voltage regulator module's internal FIFO through this channel. ② and ③ are handshake signals between the voltage regulator module and the chip's low-power control module, mainly completing buck and boost handshakes. ④ is the chip's interrupt wake-up signal. ⑤ is the APB interface between the voltage regulator module and the peripheral SPMI / I2C; this interface only supports write commands.

[0037] In this invention, the internal structure of the voltage regulating module is shown in the schematic diagram below. Figure 3 As shown: ① is the APB interface for data writing. When writing data, the data FIFO path ⑥ and the address FIFO path ⑦ can be selected. The data FIFO and the address FIFO have independent address spaces. The data FIFO stores the APB write data that the voltage regulator module writes to SPMI / I2C, and the address FIFO stores the APB address that the voltage regulator module writes to SPMI / I2C.

[0038] ② represents the request signal input from the low-power control module, and ③ represents the response signal from the voltage regulation module to the low-power control module. When entering low-power mode, the low-power control module initiates a request, and the voltage regulation module sends a response signal after completing the voltage reduction. When exiting low-power mode, the voltage regulation module withdraws the response signal after completing the voltage boost, and the low-power control module subsequently withdraws the request.

[0039] ④ This is the chip wake-up interrupt signal. After the chip voltage is stepped down, the voltage regulation module monitors for wake-up interrupts. If a wake-up interrupt is received, the voltage regulation module will perform a boost operation.

[0040] ⑧ and ⑨ are handshake signals between the interrupt monitor and the low-power interface. When the chip is operating normally, the voltage regulation module does not start and will not send commands to SPMI / I2C via APB.

[0041] ⑩ is the handshake signal between the interrupt monitor and the FIFO controller. The interrupt monitor selects either a boost command or a buck command based on the mode. After sending the command, the FIFO controller replies with an ACK signal.

[0042] Send a read data command to the FIFO controller. Simultaneously, read one data entry from both the data FIFO and the address FIFO to form an APB write command, and then... Send to the APB interface.

[0043] ⑤ This is the APB interface for sending commands to downstream SPMI / I2C. After the APB write command is completed, it is used through... The system sends a completion signal to the FIFO controller. The FIFO controller can then send the next command or send an acknowledgment signal to the interrupt monitor.

[0044] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of the present invention. The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent substitutions, and improvements made to the above embodiments within the spirit and principles of the present invention, without departing from the scope of the present invention, are still within the protection scope of the present invention.

Claims

1. A method for low-power automatic voltage regulation of a chip, characterized in that, Includes the following steps: Step 1: Initialize the voltage regulator module by writing the preset data into the internal FIFO of the voltage regulator module; Before the voltage regulation module starts working, the CPU or other master writes the preset data into the module's internal FIFO through the APB interface; The preset data is divided into write address and write data, each with its own independent FIFO; The specific content of the preset data is the APB write command for the chip peripheral control external power control chip voltage regulation. Step 2: Before notifying the voltage regulation module to reduce the voltage, the chip's low-power control module first controls other modules inside the chip to enter low-power mode, and then notifies the voltage regulation module to reduce the voltage and enter low-power mode. After the chip enters low-power mode and the voltage regulation module completes the voltage reduction, the chip retains one low-frequency clock source as the working clock of the voltage regulation module, and the other high-frequency clocks are turned off. Step 3: The voltage regulation module sends a step-down command to the peripheral device based on the internal FIFO data; Step 4: When the chip enters low-power mode, the voltage regulation module monitors the chip's wake-up interrupt instruction; Step 5: Upon receiving the wake-up interrupt command, the voltage regulation module sends a boost command to the peripheral device based on the internal FIFO data.

2. The method for low-power automatic voltage regulation of a chip as described in claim 1, characterized in that: The size of the internal FIFO is set according to the specific project requirements.

3. The method for low-power automatic voltage regulation of a chip as described in claim 1, characterized in that: The wake-up interrupt instruction is configured according to the specific project requirements.

4. The method for automatic low-power voltage regulation of a chip as described in claim 1, characterized in that: After the chip receives the wake-up interrupt, the voltage regulation module first sends a boost command, and other modules only start working after the boost is completed.

5. The method for automatic low-power voltage regulation of a chip as described in claim 1, characterized in that: When a chip enters or exits low-power mode, the low-power module and the voltage regulation module need to handshake to ensure correct timing.

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