Layout of a semiconductor structure

Abstract

The embodiment of the application provides a layout of a semiconductor structure, comprising: a column decoder, wherein the column decoder comprises a first P-type transistor region, a second P-type transistor region, a first N-type transistor region, a second N-type transistor region and a NAND gate region; wherein the first P-type transistor region is located above the first N-type transistor region, the second P-type transistor region is located above the first P-type transistor region, and the second N-type transistor region is located above the second P-type transistor region; the NAND gate region is adjacent to the first P-type transistor region, and the NAND gate region is also adjacent to the second P-type transistor region; by adjacently arranging the two P-type transistor regions, the height of the semiconductor structure can be reduced; and by arranging the NAND gate region near the two P-type transistor regions and the first N-type transistor region, the height of the semiconductor structure can be further reduced.

Description

Technical Field

[0001] This application relates to, but is not limited to, a layout of a semiconductor structure. Background Technology

[0002] As market demands for semiconductor device performance increase, the size of semiconductor devices is becoming smaller and smaller. To adapt to this trend of shrinking semiconductor device size, it is necessary to further optimize the layout of semiconductor structures. Summary of the Invention

[0003] This application aims to provide a layout of a smaller semiconductor structure.

[0004] This application provides a layout of a semiconductor structure, including: a column decoder;

[0005] The column decoder includes a first P-type transistor region, a second P-type transistor region, a first N-type transistor region, a second N-type transistor region, and a NAND gate region;

[0006] The first P-type transistor region is located above the first N-type transistor region, the second P-type transistor region is located above the first P-type transistor region, and the second N-type transistor region is located above the second P-type transistor region; the NAND gate region is adjacent to the first P-type transistor region, the NAND gate region is also adjacent to the second P-type transistor region, and the NAND gate region is also adjacent to the first N-type transistor region.

[0007] In one embodiment, the first P-type transistor region includes a first region and a second region, and the second P-type transistor region includes a third region and a fourth region;

[0008] The first and second regions are arranged symmetrically from left to right, and the gate extension direction of the P-type transistor in the first region is the same as that of the P-type transistor in the second region; the third and fourth regions are arranged symmetrically from left to right, and the gate extension direction of the P-type transistor in the third region is the same as that of the P-type transistor in the fourth region.

[0009] In one embodiment, the gate extension direction of the P-type transistor in the first region is the same as the gate extension direction of the P-type transistor in the third region; and the size of the first region and the size of the third region are not equal.

[0010] In one embodiment, the NAND gate region includes a third P-type transistor region;

[0011] The third P-type transistor region is located between the first and second regions, and is also located between the third and fourth regions; and the gate extension direction of the P-type transistor in the third P-type transistor region is the same as the gate extension direction of the P-type transistor in the first region.

[0012] In one embodiment, the semiconductor structure further includes a capacitor region;

[0013] The capacitor region is located above the third P-type transistor region, between the first and second regions, and also between the third and fourth regions.

[0014] In one embodiment, the semiconductor structure further includes a closed N-type guard ring;

[0015] The closed N-type protective ring surrounds the first P-type transistor region and the second P-type transistor region.

[0016] In one embodiment, the first N-type transistor region includes a fifth region and a sixth region;

[0017] The fifth and sixth regions are arranged symmetrically from left to right, and the gate extension direction of the N-type transistors in the fifth region is the same as that of the N-type transistors in the sixth region.

[0018] In one embodiment, the NAND gate region further includes a third N-type transistor region and a fourth N-type transistor region;

[0019] The third N-type transistor region is located below the fifth region, and the fourth N-type transistor region is located below the sixth region.

[0020] In one embodiment, the gate extension direction of the N-type transistor in the third N-type transistor region is the same as the gate extension direction of the N-type transistor in the fifth region; and the width of the N-type transistor in the third N-type transistor region in the gate extension direction is equal to the width of the N-type transistor in the fifth region in the gate extension direction.

[0021] The gate extension direction of the N-type transistor in the fourth N-type transistor region is the same as that of the N-type transistor in the sixth region; and the width of the N-type transistor in the fourth N-type transistor region in the gate extension direction is equal to the width of the N-type transistor in the sixth region in the gate extension direction.

[0022] In one embodiment, the gate extension direction of the N-type transistor in the third N-type transistor region is perpendicular to the gate extension direction of the N-type transistor in the fifth region; and the width of the N-type transistor in the third N-type transistor region in the gate extension direction is greater than the width of the N-type transistor in the fifth region in the gate extension direction.

[0023] The gate extension direction of the N-type transistor in the fourth N-type transistor region is perpendicular to the gate extension direction of the N-type transistor in the sixth region; and the width of the N-type transistor in the fourth N-type transistor region in the gate extension direction is greater than the width of the N-type transistor in the sixth region in the gate extension direction.

[0024] In one embodiment, the semiconductor structure further includes a first P-type guard ring having a first opening;

[0025] The first P-type protective ring surrounds the region consisting of the first N-type transistor region, the third N-type transistor region, and the fourth N-type transistor region on three sides, and the first opening faces the first P-type transistor region.

[0026] In one embodiment, the second N-type transistor region includes a seventh region and an eighth region;

[0027] The seventh and eighth regions are arranged symmetrically on the left and right, and the gate extension direction of the N-type transistor in the seventh region is the same as that of the N-type transistor in the eighth region.

[0028] In one embodiment, the semiconductor structure further includes a second P-type guard ring having a second opening and a third P-type guard ring having a third opening;

[0029] The second P-type protection ring surrounds the seventh region on three sides, and the second opening faces the second P-type transistor region; the third P-type protection ring surrounds the eighth region on three sides, and the third opening faces the second P-type transistor region.

[0030] In one embodiment, the substrate potential of the first P-type transistor region is equal to the substrate potential of the second P-type transistor region.

[0031] In one embodiment, the semiconductor structure further includes a memory array;

[0032] The storage array is located above the column decoder, and the width of the storage array along the left-to-right direction is equal to the width of the column decoder along the left-to-right direction.

[0033] In one embodiment, the column decoder further includes output metal lines;

[0034] The output metal line extends from bottom to top, with one end connected to the drain of the second P-type transistor and the other end connected to the column select line of the memory array.

[0035] The semiconductor structure layout provided in this application includes a column decoder. The column decoder includes a first P-type transistor region, a second P-type transistor region, a first N-type transistor region, a second N-type transistor region, and a NAND gate region. The first and second P-type transistor regions are arranged adjacent to each other. The second N-type transistor region is located above the second P-type transistor region, and the first N-type transistor region is located below the first P-type transistor region. This arrangement ensures that even with a small gap between the column decoder and the memory array, the distance between the N-type wells of the second P-type transistors and the N-type wells in the memory array meets the minimum N-type well spacing requirement. This effectively shortens the height of the semiconductor structure from top to bottom, reducing its size. Furthermore, placing the NAND gate region near the first P-type transistor region, the second P-type transistor region, and the first N-type transistor region fully utilizes the width of the memory array from left to right, reducing the impact of the NAND gate region on the height of the entire semiconductor structure layout from top to bottom, thereby further reducing the size of the semiconductor structure. Attached Figure Description

[0036] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0037] Figure 1 A layout of a semiconductor structure provided in one embodiment of this application;

[0038] Figure 2 A circuit schematic diagram of a column decoder provided in one embodiment of this application;

[0039] Figure 3 Provided for this application Figure 2 The layout of the decoder in the illustrated embodiment;

[0040] Figure 4 A layout of a column decoder provided in one embodiment of this application;

[0041] Figure 5 A layout of a column decoder provided in another embodiment of this application;

[0042] Figure 6 A layout of a column decoder provided in another embodiment of this application;

[0043] Figure 7 Provided for this application Figures 4 to 6 The circuit diagram of the decoder in the illustrated embodiment is shown.

[0044] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0045] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0046] like Figure 1 As shown, a semiconductor structure layout provided in one embodiment of this application includes a column decoder 100 and a memory array 200. The memory array 200 is located above the column decoder 100, and the output metal line O of the column decoder 100 is connected to the column select line of the memory array 200 to input a column select signal to the memory array 200.

[0047] In one embodiment, the width of the memory array 200 along the left-to-right direction is equal to the width of the column decoder 100 along the left-to-right direction, which can effectively reduce the layout size of the semiconductor structure.

[0048] In one embodiment, an N-type guard ring 302 with a third power supply terminal VPP is arranged near the storage array, and a P-type guard ring 301 with a ground terminal is also arranged. The third power supply terminal VPP is used to supply power to the storage array.

[0049] like Figure 2 As shown, an embodiment of this application provides a column decoder 100 including a first P-type transistor PM1, a second P-type transistor PM2, a first N-type transistor NM1, a second N-type transistor NM2, and a NAND gate.

[0050] In this configuration, the source and substrate of the first P-type transistor PM1 are both connected to the first power supply terminal VDD. The drain of the first N-type transistor NM1 is connected to the drain of the first P-type transistor PM1. The gate of the first N-type transistor NM1 is connected to the gate of the first P-type transistor PM1 to form the first input terminal IN1 of the column decoder. The source of the first N-type transistor NM1 is connected to the output terminal of the NAND gate. The substrate of the first N-type transistor NM1 is connected to the ground terminal VSS. The first input terminal of the NAND gate is the second input terminal IN2 of the column decoder, and the second input terminal of the NAND gate is the third input terminal IN3 of the column decoder.

[0051] The source terminal of the second P-type transistor PM2 is connected to the second power supply terminal VYS, the substrate terminal of the second P-type transistor PM2 is connected to the third power supply terminal VPP, the drain terminal of the second N-type transistor NM2 is connected to the drain terminal of the second P-type transistor PM2 to form the output terminal OUT of the column decoder 100, the gate terminal of the second N-type transistor NM2 is connected to the gate terminal of the second P-type transistor PM2 and then connected to the drain terminal of the first P-type transistor PM1, and the source terminal and substrate terminal of the second N-type transistor NM2 are connected to the ground terminal VSS.

[0052] In one embodiment, reference continues Figure 1 The output metal line O of the column decoder extends from bottom to top. One end of the output metal line is connected to the drain of the second P-type transistor PM2, and the other end of the output metal line is connected to the column select line of the memory array.

[0053] Figure 3 Provided for this application Figure 2 The layout of the column decoder in the illustrated embodiment includes a first P-type transistor region P1, a second P-type transistor region P2, a first N-type transistor region N1, a second N-type transistor region N2, and a NAND gate region NAND.

[0054] Specifically, the second P-type transistor region P2 is located above the second N-type transistor region N2, the second N-type transistor region N2 is located above the first N-type transistor region N1, and the first N-type transistor region N1 is located above the first P-type transistor region P1. NAND gate regions are located to the right of the first N-type transistor region N1 and the first P-type transistor region P1.

[0055] Since the drain terminal of the first N-type transistor NM1 is connected to the drain terminal of the first P-type transistor PM1, the first N-type transistor region N1 and the first P-type transistor region P1 are usually arranged adjacent to each other. Furthermore, since the drain terminal of the second N-type transistor NM2 is connected to the drain terminal of the second P-type transistor PM2 to form the output terminal OUT of the column decoder 100, the second N-type transistor region N2 and the second P-type transistor region P2 are usually arranged adjacent to each other, and the second N-type transistor region N2 and the second P-type transistor region P2 are located above the first N-type transistor region N1 and the first P-type transistor region P1. An output metal line O extending from bottom to top is provided above the second N-type transistor region N2 and the second P-type transistor region P2.

[0056] In one embodiment, a capacitor region 105 is provided to the right of the second P-type transistor region P2 to filter the voltage provided from the first power supply terminal VDD to the third power supply terminal VPP, so as to stabilize the voltage provided from the first power supply terminal VDD to the third power supply terminal VPP.

[0057] In one embodiment, an L-shaped N-type protective ring 101 is provided near the second P-type transistor region P2, a T-shaped P-type protective ring 103 is provided between the first N-type transistor region N1 and the second N-type transistor region N2, and a U-shaped P-type protective ring 104 is provided to the right of the second N-type transistor region N2. An L-shaped P-type protective ring 102 is provided near the first P-type transistor region P1.

[0058] In the above embodiments, the first power supply terminal VDD connected to the substrate of the first P-type transistor PM1 has a different voltage than the third power supply terminal VPP connected to the substrate of the second P-type transistor PM2. When arranging the first P-type transistor PM1 and the second P-type transistor PM2 in the column decoder, the distance between the N-type wells of the first P-type transistor PM1 and the N-type wells of the second P-type transistor PM2 needs to be sufficiently large to meet the minimum N-type well spacing. The distance between the N-type guard ring in the column selector and the N-type guard ring of the third power supply terminal VPP of the memory array also needs to be sufficiently large so that the distance between the N-type well of the second P-type transistor PM2 and the N-type wells in the memory array also meets the minimum N-type well spacing. Based on the above analysis, the semiconductor structure layout provided in the above embodiments has a relatively large height from top to bottom, and the overall size of the semiconductor structure is also relatively large.

[0059] like Figures 4 to 7 As shown in the figure, this application provides a layout of a semiconductor structure, which includes a column decoder. The column decoder includes a first P-type transistor region P1, a second P-type transistor region P2, a first N-type transistor region N1, a second N-type transistor region N2, and a NAND gate region.

[0060] In this configuration, the first P-type transistor region P1 is located above the first N-type transistor region N1, the second P-type transistor region P2 is located above the first P-type transistor region P1, and the second N-type transistor region N2 is located above the second P-type transistor region P2. The NAND gate region is adjacent to the first P-type transistor region P1, the second P-type transistor region P2, and the first N-type transistor region N1.

[0061] In the above embodiments, the first P-type transistor region P1 and the second P-type transistor region P2 are arranged adjacent to each other, which reduces the distance between P-type transistors and N-type transistors due to process limitations. At the same time, all P-type transistors can be surrounded by a protective ring, resulting in better isolation and providing a cleaner environment for the P-type transistors, thus reducing the impact of latch-up effects.

[0062] By positioning the second N-type transistor region N2 above the second P-type transistor region P2, and the first N-type transistor region N1 below the first P-type transistor region P1, even with a small gap between the column decoder and the memory array, the distance between the N-type well of the second P-type transistor PM2 and the N-type wells in the memory array can still meet the minimum N-type well spacing. This effectively shortens the height of the semiconductor structure from top to bottom, reducing its size. Furthermore, arranging the second N-type transistor region N2 and the second P-type transistor region P2 adjacently facilitates the connection between the drain terminals of the second N-type transistor NM2 and the second P-type transistor PM2.

[0063] Furthermore, the width of the column decoder in the left-to-right direction is affected by the width of the memory array in the left-to-right direction. The NAND gate region is arranged adjacent to the first P-type transistor region P1, the second P-type transistor region P2, and the first N-type transistor region N1. This can make full use of the width of the memory array in the left-to-right direction and reduce the influence of the NAND gate region on the height of the entire semiconductor structure layout in the top-to-bottom direction, thereby further reducing the size of the semiconductor structure.

[0064] In one embodiment, reference Figure 5 and Figure 7 The column decoder also includes an output metal line 206, which extends from bottom to top. One end of the output metal line 206 is connected to the drain of the second P-type transistor PM2, and the other end is connected to the column select line of the memory array. By extending the output metal line 206 from bottom to top, it is convenient to connect the output metal line 206 of the column decoder to the memory array.

[0065] In one embodiment, the semiconductor structure further includes a first metal layer at the top, a second metal layer at the next top, and a third metal layer at the third layer, wherein the output metal line 206 of the column decoder is located in the second metal layer. With this arrangement, the output metal line 206 of the column decoder can be connected to the column select line of the memory array via the first, second, and third metal layers.

[0066] In one embodiment, for each transistor region, the number of multi-finger structures in each transistor region can be increased, and the width of the multi-finger structures in the gate extension direction can be reduced, wherein the gate extension direction is from top to bottom, so as to double the transistor index without changing the total width of the transistor in the gate extension direction, thereby halving the width of a single transistor in the gate extension direction, thereby achieving the effect of reducing the total height of the column decoder.

[0067] In one embodiment, reference Figure 7 The substrate potential of the first P-type transistor region P1 is equal to the substrate potential of the second P-type transistor region P2. For example, connect the substrates of the first P-type transistor region P1 and the second P-type transistor region P2 to the first power supply terminal VDD. Connect the source terminal of the first P-type transistor region P1 to the first power supply terminal VDD, and the source terminal of the second P-type transistor region P2 to the second power supply terminal VYS. Normally, the voltage at the first power supply terminal VDD is the same as the voltage at the second power supply terminal VYS. Making the substrate potential of the first P-type transistor region P1 equal to the substrate potential of the second P-type transistor region P2 will not affect the conduction or cutoff of the second P-type transistor PM2.

[0068] In one embodiment, reference continues Figure 4 The first P-type transistor region P1 includes a first region 201 and a second region 202, wherein the first region 201 and the second region 202 are arranged symmetrically from left to right, and the gate extension direction of the P-type transistor in the first region 201 is the same as the gate extension direction of the P-type transistor in the second region 202. This arrangement reduces the maximum distance d1 from left to right between the P-type transistor in the first region 201 and the boundary of the entire first P-type transistor region P1, and also reduces the maximum distance from left to right between the P-type transistor in the second region 202 and the boundary of the entire first P-type transistor region P1. This facilitates the setting of an N-type protection ring around the first P-type transistor P1, thereby reducing the occurrence of transistor latch-up.

[0069] The second P-type transistor region P2 includes a third region 203 and a fourth region 204. The third region 203 and the fourth region 204 are arranged symmetrically from left to right, and the gate extension direction of the P-type transistor in the third region 203 is the same as that of the P-type transistor in the fourth region 204. This arrangement reduces the maximum distance d1 from left to right between the P-type transistor in the third region 203 and the boundary of the entire second P-type transistor region P2, and also reduces the maximum distance from left to right between the P-type transistor in the fourth region 204 and the boundary of the entire second P-type transistor region P2. This facilitates the formation of an N-type protective ring around the second P-type transistor PM2, thereby reducing the occurrence of transistor latch-up.

[0070] In one embodiment, the first P-type transistor region P1 includes a first region 201 and a second region 202, and the second P-type transistor region P2 includes a third region 203 and a fourth region 204. The first region 201 and the second region 202 are arranged symmetrically from left to right, and the gate extension direction of the P-type transistors in the first region 201 is the same as the gate extension direction of the P-type transistors in the second region 202. The third region 203 and the fourth region 204 are also arranged symmetrically from left to right, and the gate extension direction of the P-type transistors in the third region 203 is the same as the gate extension direction of the P-type transistors in the fourth region 204. The gate extension direction of the P-type transistors in the first region 201 is the same as the gate extension direction of the P-type transistors in the third region 203, and the sizes of the first region 201 and the third region 203 are not equal. By making the gate extension directions of the P-type transistors in the first region 201, the second region 202, the third region 203, and the fourth region 204 the same, it is beneficial for semiconductor structure manufacturing. Since the first P-type transistor PM1 is located one stage above the second P-type transistor PM2, the source and drain currents of the first P-type transistor PM1 and the second P-type transistor PM2 are different, making the size of the first region 201 and the size of the third region 203 unequal. This results in different driving capabilities of the first P-type transistor PM1 and the second P-type transistor PM2, which can improve the working reliability of the semiconductor structure.

[0071] In one embodiment, the NAND gate region includes a third P-type transistor region P3, wherein the third P-type transistor region P3 is located between the first region 201 and the second region 202, and also between the third region 203 and the fourth region 204. The gate extension direction of the P-type transistors within the third P-type transistor region P3 is the same as the gate extension direction of the P-type transistors within the first region 201. This arrangement reduces the maximum distance from left to right between the transistors in the first P-type transistor region P1 and the boundary of the entire first P-type transistor region P1, and also reduces the maximum distance from left to right between the transistors in the second P-type transistor region P2 and the boundary of the entire first P-type transistor region P1. This facilitates the placement of an N-type guard ring around the first P-type transistor PM1, thereby reducing the occurrence of transistor latch-up.

[0072] In one embodiment, the semiconductor structure further includes a capacitor region 105, and the NAND gate region includes a third P-type transistor region P3. The capacitor region 105 is located above the third P-type transistor region P3. This arrangement facilitates the connection of the third P-type transistor with other transistors within the NAND gate region, reducing parasitic resistance. The capacitor region is positioned between the first region 201 and the second region 202, and between the third region 203 and the fourth region 204. This arrangement reduces the maximum distance from left to right between the transistors in the first P-type transistor region P1 and the boundary of the entire first P-type transistor region P1, and also reduces the maximum distance from left to right between the transistors in the second P-type transistor region P2 and the boundary of the entire first P-type transistor region P1, thereby reducing transistor latch-up.

[0073] In one embodiment, the semiconductor structure further includes a closed N-type guard ring 111, which surrounds the first P-type transistor region P1 and the second P-type transistor region P2. That is, the closed N-type guard ring 111 surrounds the first region 201 and the second region 202, and surrounds the third region 203 and the fourth region 204. With this arrangement, the furthest distance d1 from left to right between the P-type transistors in the first region 201 and the N-type guard ring 111 is less than half the width of the N-type guard ring 111 from left to right. The furthest distance d2 from bottom to top between the P-type transistors in the first region 201 and the N-type guard ring 111 is less than half the height of the N-type guard ring 111 from bottom to top, which is more conducive to reducing transistor latch-up. Furthermore, the closed N-type guard ring 111 forms a closed isolation ring, providing better isolation for the internal first P-type transistor region P1 and the second P-type transistor region P2.

[0074] In one embodiment, the first N-type transistor region N1 includes a fifth region 205 and a sixth region 206. The fifth region 205 and the sixth region 206 are arranged symmetrically from left to right, and the gate extension direction of the N-type transistor in the fifth region 205 is the same as that of the N-type transistor in the sixth region 206. This arrangement reduces the distance from the N-type transistor in the fifth region 205 to the boundary of the entire first N-type transistor region N1 from left to right, and also reduces the distance from the N-type transistor in the sixth region 206 to the boundary of the entire first N-type transistor region N1 from left to right. This facilitates the placement of a P-type protective ring around the first N-type transistor NM1 and further reduces the occurrence of transistor latch-up.

[0075] In one embodiment, reference Figure 6 The NAND gate region also includes a third N-type transistor region N3 and a fourth N-type transistor region N4. The third N-type transistor region N3 is located below the fifth region 205, and the fourth N-type transistor region N4 is located below the sixth region 206.

[0076] Specifically, the gate extension direction of the N-type transistor in the third N-type transistor region N3 is the same as that of the N-type transistor in the fifth region 205. Furthermore, the width of the N-type transistor in the third N-type transistor region N3 in the gate extension direction is equal to the width of the N-type transistor in the fifth region 205 in the gate extension direction.

[0077] The gate extension direction of the N-type transistor in the fourth N-type transistor region N4 is the same as that of the N-type transistor in the sixth region 206. Furthermore, the width of the N-type transistor in the fourth N-type transistor region N4 in the gate extension direction is equal to the width of the N-type transistor in the sixth region 206 in the gate extension direction.

[0078] The width of the N-type transistor in the third N-type transistor region N3 in the gate extension direction is determined according to the minimum width of the transistor by the Design Rule Check (DRC).

[0079] In the above technical solution, by setting the gate extension direction of the N-type transistor in the third N-type transistor region N3 to be the same as the gate extension direction of the N-type transistor in the fifth region 205, and the gate extension direction of the N-type transistor in the fourth N-type transistor region N4 to be the same as the gate extension direction of the N-type transistor in the sixth region 206, it is beneficial to simplify the semiconductor structure fabrication process.

[0080] By setting the width of the N-type transistor in the third N-type transistor region N3 in the gate extension direction to be equal to the width of the N-type transistor in the fifth region 205 in the gate extension direction, and the width of the N-type transistor in the fourth N-type transistor region N4 in the gate extension direction to be equal to the width of the N-type transistor in the sixth region 206 in the gate extension direction, the height of the column decoder in the top-to-bottom direction can be shortened.

[0081] In one embodiment, reference continues Figure 4 and Figure 5 The NAND gate region also includes a third N-type transistor region N3 and a fourth N-type transistor region N4. The third N-type transistor region N3 is located below the fifth region 205, and the fourth N-type transistor region N4 is located below the sixth region 206.

[0082] Specifically, the gate extension direction of the N-type transistor in the third N-type transistor region N3 is perpendicular to the gate extension direction of the N-type transistor in the fifth region 205. Furthermore, the width of the N-type transistor in the third N-type transistor region N3 in the gate extension direction is greater than the width of the N-type transistor in the fifth region 205 in the gate extension direction.

[0083] The gate extension direction of the N-type transistor in the fourth N-type transistor region N4 is perpendicular to the gate extension direction of the N-type transistor in the sixth region 206. Furthermore, the width of the N-type transistor in the fourth N-type transistor region N4 in the gate extension direction is greater than the width of the N-type transistor in the sixth region 206 in the gate extension direction.

[0084] In the above technical solution, the gate extension direction of the N-type transistor in the third N-type transistor region N3 is perpendicular to the gate extension direction of the N-type transistor in the fifth region 205, and the gate extension direction of the N-type transistor in the fourth N-type transistor region N4 is perpendicular to the gate extension direction of the N-type transistor in the sixth region 206. This can increase the width of the N-type transistors in the third N-type transistor region N3 and the fourth N-type transistor region N4 in the gate extension direction, reduce the number of N-type transistors in the third N-type transistor region N3 and the fourth N-type transistor region N4, and will not increase the height of the column decoder in the top-to-bottom direction.

[0085] In one embodiment, the width of the N-type transistors in the third N-type transistor region N3 and the fourth N-type transistor region N4 in the gate extension direction can be half the width of the column decoder in the left-to-right direction.

[0086] In one embodiment, the semiconductor structure further includes a first P-type guard ring 112 with a first opening. The first P-type guard ring 112 surrounds the region composed of the first N-type transistor region N1, the third N-type transistor region N3, and the fourth N-type transistor region N4 on three sides, and the first opening faces the first P-type transistor region P1. This configuration makes the structure of the first P-type guard ring 112 simple and easy to manufacture, and can effectively provide an isolation environment for the transistors in the first N-type transistor region N1, the third N-type transistor region N3, and the fourth N-type transistor region N4, reducing the impact of latch-up effects.

[0087] In one embodiment, the second N-type transistor region N2 includes a seventh region 207 and an eighth region 208, wherein the seventh region 207 and the eighth region 208 are arranged symmetrically from left to right, and the gate extension direction of the N-type transistor in the seventh region 207 is the same as the gate extension direction of the N-type transistor in the eighth region 208. This arrangement reduces the distance from the N-type transistor in the seventh region 207 to the boundary of the entire second N-type transistor region N2 from left to right, and also reduces the distance from the N-type transistor in the eighth region 208 to the boundary of the entire second N-type transistor region N2 from left to right. This facilitates the setting of a P-type protective ring around the second N-type transistor NM2 and further reduces the occurrence of transistor latch-up.

[0088] In one embodiment, the semiconductor structure further includes a first P-type guard ring 113 with a second opening and a third P-type guard ring 114 with a third opening. The first P-type guard ring 113 surrounds the seventh region 207 on three sides, and the second opening faces the second P-type transistor region P2. The third P-type guard ring 114 surrounds the eighth region 208 on three sides, and the third opening faces the second P-type transistor region P2. By providing two P-type guard rings in the second N-type transistor region N2, the spacing between the P-type guard rings and the transistors in the second N-type transistor region N2 can be reduced, providing an isolation environment for the transistors in the second N-type transistor region N2 and reducing the impact of latch-up effects.

[0089] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0090] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A layout of a semiconductor structure, characterized in that, The semiconductor structure comprises: a column decoder; wherein the column decoder comprises a first P-type transistor region, a second P-type transistor region, a first N-type transistor region, a second N-type transistor region, and a NAND gate region; wherein the first P-type transistor region is above the first N-type transistor region, the second P-type transistor region is above the first P-type transistor region, and the second N-type transistor region is above the second P-type transistor region; the NAND gate region is adjacent to the first P-type transistor region, the NAND gate region is also adjacent to the second P-type transistor region, and the NAND gate region is also adjacent to the first N-type transistor region; the first P-type transistor region comprises a first region and a second region, and the second P-type transistor region comprises a third region and a fourth region; wherein the first region and the second region are arranged symmetrically left and right, and the extending direction of the gate of the P-type transistor in the first region is the same as that in the second region; the third region and the fourth region are arranged symmetrically left and right, and the extending direction of the gate of the P-type transistor in the third region is the same as that in the fourth region.

2. The layout of a semiconductor structure according to claim 1, wherein, the extending direction of the gate of the P-type transistor in the first region is the same as that in the third region; and the size of the first region is not equal to that of the third region.

3. The layout of a semiconductor structure of claim 2, wherein, the NAND gate region comprises a third P-type transistor region; wherein the third P-type transistor region is between the first region and the second region, the third P-type transistor region is also between the third region and the fourth region; and the extending direction of the gate of the P-type transistor in the third P-type transistor region is the same as that in the first region.

4. The layout of a semiconductor structure according to claim 3, wherein, The semiconductor structure further comprises a capacitor region; wherein the capacitor region is above the third P-type transistor region, the capacitor region is between the first region and the second region, and the capacitor region is also between the third region and the fourth region.

5. The layout of a semiconductor structure according to any one of claims 1 to 4, wherein, The semiconductor structure further comprises a closed N-type guard ring; wherein the closed N-type guard ring surrounds the first P-type transistor region and the second P-type transistor region.

6. The layout of a semiconductor structure according to any one of claims 1 to 4, wherein, The first N-type transistor region comprises a fifth region and a sixth region; wherein the fifth region and the sixth region are arranged symmetrically left and right, and the extending direction of the gate of the N-type transistor in the fifth region is the same as that in the sixth region.

7. The layout of a semiconductor structure according to claim 6, wherein, The NAND gate region further comprises a third N-type transistor region and a fourth N-type transistor region; wherein the third N-type transistor region is below the fifth region, and the fourth N-type transistor region is below the sixth region.

8. The layout of a semiconductor structure according to claim 7, wherein, The gate extending direction of the N-type transistor in the third N-type transistor region is the same as the gate extending direction of the N-type transistor in the fifth region; and the width of the N-type transistor in the third N-type transistor region in the gate extending direction is equal to the width of the N-type transistor in the fifth region in the gate extending direction; The gate extending direction of the N-type transistor in the fourth N-type transistor region is the same as the gate extending direction of the N-type transistor in the sixth region; and the width of the N-type transistor in the fourth N-type transistor region in the gate extending direction is equal to the width of the N-type transistor in the sixth region in the gate extending direction.

9. The layout of a semiconductor structure of claim 7, wherein, The gate extending direction of the N-type transistor in the third N-type transistor region is perpendicular to the gate extending direction of the N-type transistor in the fifth region; and the width of the N-type transistor in the third N-type transistor region in the gate extending direction is greater than the width of the N-type transistor in the fifth region in the gate extending direction; The gate extending direction of the N-type transistor in the fourth N-type transistor region is perpendicular to the gate extending direction of the N-type transistor in the sixth region; and the width of the N-type transistor in the fourth N-type transistor region in the gate extending direction is greater than the width of the N-type transistor in the sixth region in the gate extending direction.

10. The layout of a semiconductor structure of claim 7, wherein, The semiconductor structure further comprises a first P-type guard ring provided with a first opening; The first P-type guard ring surrounds the region composed of the first N-type transistor region, the third N-type transistor region and the fourth N-type transistor region on three sides, and the first opening faces the first P-type transistor region.

11. The layout of a semiconductor structure according to any one of claims 1 to 2, wherein, The second N-type transistor region comprises a seventh region and an eighth region; The seventh region and the eighth region are symmetrically arranged left and right, and the gate extending direction of the N-type transistor in the seventh region is the same as the gate extending direction of the N-type transistor in the eighth region.

12. The layout of a semiconductor structure of claim 11, wherein, The semiconductor structure further comprises a second P-type guard ring provided with a second opening and a third P-type guard ring provided with a third opening; The second P-type guard ring surrounds the seventh region on three sides, and the second opening faces the second P-type transistor region; the third P-type guard ring surrounds the eighth region on three sides, and the third opening faces the second P-type transistor region.

13. The layout of a semiconductor structure of any of claims 1 to 2, wherein, The substrate end potential of the first P-type transistor region is equal to the substrate end potential of the second P-type transistor region.

14. The layout of a semiconductor structure of any of claims 1 to 2, wherein, The semiconductor structure further comprises a storage array; The storage array is located above the column decoder, and the width of the storage array along the left-to-right direction is equal to the width of the column decoder along the left-to-right direction.

15. The layout of a semiconductor structure of claim 14, wherein, The column decoder further comprises an output metal line; The output metal line extends along the bottom-to-top direction, one end of the output metal line is connected with the drain of the second P-type transistor, and the other end of the output metal line is connected with a column selection line of the storage array.

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