Display panel and display device

Abstract

Embodiments of the present application disclose a display panel and a display device; the display panel comprises data wires, power supply wires, a power supply bus and test connecting lines; the display panel comprises a first wire group, a second wire group and a third wire group arranged periodically in sequence; each of the first wire group and the second wire group is a single wire; the third wire group comprises at least one power supply wire and three wires of at least one data wire; by changing the arrangement and combination of the wires to 3 / 1 / 1, the three wires in the third wire group can be directly subjected to open / short circuit detection through the test connecting lines, and the single wire in the first wire group and the second wire group can be independently detected without short-circuiting the remaining wire lines in the detection; after the detection is completed, the test connecting lines do not need to be etched, thereby avoiding the risk of etching the wires or the connecting lines, and improving the yield quality of the display panel.

Description

Technical Field

[0001] This application relates to the field of displays, specifically to a display panel and a display device. Background Technology

[0002] In recent years, the quality of display panels has received increasing attention from consumers. Connectivity inspection of the metal trace film layer is essential and crucial. Common defects in the metal trace film layer are generally two types of anomalies: open circuits due to broken lines or short circuits caused by metal residue. These anomalies will appear as dark lines, bright lines, and dotted lines during subsequent LED illumination, significantly reducing the quality of the display panel. Therefore, OST (open short circuit test) is included in the display panel manufacturing process to check for the above-mentioned anomalies. Thus, the detection rate of OST is particularly important. Generally, during OST testing, a portion of the circuitry is short-circuited for testing. After the test, the traces that do not need to be connected are etched off. The efficiency and quality of this trace etching affect the overall production efficiency and quality of the display panel.

[0003] Therefore, there is an urgent need for a display panel and display device to solve the above-mentioned technical problems. Summary of the Invention

[0004] This application provides a display panel and display device that can eliminate the current process of etching traces after OST testing.

[0005] This application provides a display panel, including:

[0006] Data routing is arranged along the first direction;

[0007] The power supply traces are arranged along the first direction;

[0008] The power bus is arranged along the second direction;

[0009] A test connection cable is positioned between the power supply trace and the power bus.

[0010] Wherein, the first direction and the second direction are at an angle, the display panel includes a first wiring group, a second wiring group and a third wiring group, in the second direction, the first wiring group, the second wiring group and the third wiring group are arranged in sequence and periodically, the first wiring group and the second wiring group each contain a single wiring, the third wiring group includes three wirings including at least one power wiring and at least one data wiring.

[0011] In some embodiments, the display panel further includes sensing lines arranged along a first direction; wherein, a single line in the first wiring group and the second wiring group is the data line and the sensing line, respectively.

[0012] In some embodiments, the power trace includes a first power trace and a second power trace, wherein the voltage of the first power trace is different from the voltage of the second power trace; wherein, the power traces of two adjacent third trace groups are the first power trace and the second power trace in sequence.

[0013] In some embodiments, the power bus includes a first power bus and a second power bus, the first power bus being electrically connected to the first power trace, and the second power bus being electrically connected to the second power trace; wherein the first power bus, the second power bus, the first power trace, the second power trace, the test connection line, and the data trace are arranged on the same layer.

[0014] In some embodiments, the display panel includes: a substrate; a first metal layer located on the substrate, the first metal layer including a first power bus, a second power bus, a first power trace, a second power trace, a test connection line, and a data trace; a first insulating layer located on the side of the first metal layer away from the substrate, the first insulating layer including a plurality of first openings and a plurality of second openings; a second metal layer located on the side of the first insulating layer away from the substrate, the second metal layer including a first jumper and a second jumper; the first power bus including a first upper power bus and a first lower power bus, the second power bus including a second upper power bus and a second lower power bus, the first upper power bus and the second upper power bus... The first lower power bus and the second lower power bus are located at one end of the display panel, and at the other end of the display panel. The first upper power bus is located on the side of the second upper power bus away from the first lower power bus, and the first lower power bus is located on the side of the second lower power bus closer to the first upper power bus. The first upper power bus is directly connected to the corresponding first power trace via the test connection line, the second lower power bus is directly connected to the corresponding second power trace via the test connection line, the first lower power bus is connected to the corresponding first power trace via the first jumper, and the second upper power bus is connected to the corresponding second power trace via the second jumper.

[0015] In some embodiments, the first metal layer further includes a plurality of light-shielding portions, the light-shielding portions corresponding to the thin-film transistors of the display panel; the second metal layer further includes a gate layer or a source / drain layer.

[0016] In some embodiments, in the third routing group, the three routing lines are, in sequence, one data routing line, the power routing line, and another data routing line, and the sub-pixels corresponding to the two data routing lines in the third routing group have different emission colors.

[0017] In some embodiments, in adjacent first, second, and third data routing groups, the sub-pixels corresponding to any two data routing lines emit different colors.

[0018] In some embodiments, the distance between two traces in any two adjacent trace groups in the first trace group, the second trace group, and the third trace group in the second direction is greater than the distance between two adjacent traces in the third trace group in the second direction.

[0019] This application also provides a display device, including a display panel as described in any of the above and a device body, wherein the device body and the display panel are integrated into one unit.

[0020] The beneficial effects of this application are as follows: By changing the arrangement of the traces to 3 / 1 / 1, the third trace group, which includes three traces, is configured to include at least one power trace and at least one data trace. The test connection line connects the power trace and the power bus. The three traces in the third trace group can be directly tested for open and short circuits through the test connection line. The single traces in the first and second trace groups can be tested independently. During the test, it is not necessary to short-circuit the other traces. After the test is completed, it is not necessary to etch the test connection line, thus avoiding the risk of trace or connection line etching, improving the yield of the circuit, improving the process efficiency, and improving the yield and quality of the display panel. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a top view of the display panel provided in an embodiment of this application;

[0023] Figure 2 This is a schematic diagram of the structure of the display panel provided in the embodiments of this application;

[0024] Figure 3 This is a schematic diagram of the structure of the display device provided in the embodiments of this application. Detailed Implementation

[0025] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In addition, it should be understood that the specific embodiments described herein are only for illustration and explanation of this application and are not intended to limit this application. In this application, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, specifically the drawing directions in the accompanying drawings; while "inner" and "outer" refer to the outline of the device.

[0026] In recent years, the quality of display panels has received increasing attention from consumers. Connectivity inspection of the metal trace film layer is essential and crucial. Common defects in the metal trace film layer are generally two types of anomalies: open circuits due to broken lines or short circuits caused by metal residue. These anomalies will appear as dark lines, bright lines, and dotted lines during subsequent LED illumination, significantly reducing the quality of the display panel. Therefore, OST (open short circuit test) is included in the display panel manufacturing process to check for the above-mentioned anomalies. Thus, the detection rate of OST is particularly important. Generally, during OST testing, a portion of the circuitry is short-circuited for testing. After the test, the traces that do not need to be connected are etched off. The efficiency and quality of this trace etching affect the overall production efficiency and quality of the display panel.

[0027] Please see Figure 1 , Figure 2 This application provides a display panel 100, including:

[0028] Data routing 200, arranged along the first direction;

[0029] The power supply trace is 500mm long and is arranged along the first direction.

[0030] Power bus 300, arranged along the second direction;

[0031] Test connection cable 400 is located between the power supply trace 500 and the power bus 300;

[0032] Wherein, the first direction and the second direction form an angle, and the display panel 100 includes a first wiring group 10, a second wiring group 20 and a third wiring group 30. In the second direction, the first wiring group 10, the second wiring group 20 and the third wiring group 30 are arranged in a periodic sequence. The first wiring group 10 and the second wiring group 20 each contain a single wiring. The third wiring group 30 includes three wirings, including at least one power wiring 500 and at least one data wiring 200.

[0033] This application changes the arrangement of the traces to 3 / 1 / 1, setting the third trace group, which includes three traces, to include at least one power trace and at least one data trace. The test connection line connects the power trace and the power bus. The three traces in the third trace group can be directly tested for open and short circuits through the test connection line. The individual traces in the first and second trace groups can be tested independently. During the test, it is not necessary to short-circuit the other traces. After the test is completed, it is not necessary to etch the test connection line, thus avoiding the risk of trace or connection line etching, improving the yield of the circuit, improving the process efficiency, and improving the yield and quality of the display panel.

[0034] The technical solution of this application will now be described in conjunction with specific embodiments.

[0035] In this embodiment, please refer to Figure 1 , Figure 2 The display panel 100 includes a data trace 200 arranged along a first direction, a power bus 300 arranged along a second direction, and a test connection line 400 disposed between the power trace 500 and the power bus 300; wherein the first direction and the second direction form an angle, the display panel 100 includes a first trace group 10, a second trace group 20 and a third trace group 30, wherein in the second direction, the first trace group 10, the second trace group 20 and the third trace group 30 are arranged periodically in sequence, the first trace group 10 and the second trace group 20 each contain a single trace, and the third trace group 30 includes three traces, including at least one power trace 500 and at least one data trace 200.

[0036] For ease of description, the first direction is parallel to the Y-axis, and the second direction is parallel to the X-axis.

[0037] Generally, the power bus 300 includes a first power bus 310 and a second power bus 320. The voltage lines include a first voltage line and a second voltage line. The display panel 100 also includes sensing lines 600 arranged along a first direction.

[0038] For example, the display panel 100 includes a plurality of sub-pixels arranged in an array. The sub-pixels are any one of red, green, and blue sub-pixels. The light emission color of each column of sub-pixels is the same. The data traces are any one of red, green, and blue data traces. The column direction is the first direction. A first power trace and a red data trace form a first group. A green data trace and a blue data trace form a second group. A second power trace and a sensing line form a third group. In the second direction, the first group, the second group, and the third group are arranged alternately. The first group, the second group, and the third group are all located between two adjacent columns of sub-pixels.

[0039] The first, second, and third groups can form a 2 / 2 / 2 routing arrangement. The higher the resolution subpixel density, the closer the two routing lines in each group are, making them prone to short circuits.

[0040] In OST testing, for example, the red data trace, blue data trace, and second power trace are interconnected. The red data trace is connected to the second power bus through a test connection, the blue data trace is connected to the second power bus through a test connection, and the second power trace is connected to the second power bus. The first power trace, green data trace, and sensing line are disconnected from each other.

[0041] The voltage drop across the three interconnected traces is low, resulting in a low potential. Under normal circumstances, the three disconnected traces are in a floating state, resulting in a higher voltage drop and a high potential. The three disconnected traces can be measured separately. If there is a short circuit caused by a residual short circuit between two closely spaced traces in a certain group, the electrical signal of the floating trace will be pulled low by the electrical signal of the short-circuited trace, thus detecting the defect. However, after completing the open and short circuit test, the test traces of the 2 / 2 / 2 type trace arrangement need to be etched away. The efficiency and quality of the etching of these test traces affect the overall production efficiency and quality of the display panel.

[0042] For this embodiment, please refer to Figure 1By changing the arrangement of the traces to a 3 / 1 / 1 arrangement, the trace group that is prone to short circuits is the third trace group 30, which contains three traces. The third trace group 30 is set to include at least one power trace 500 and at least one data trace 200. The test connection line 400 connects the power trace 500 and the power bus 300. The three traces in the third trace group 30 can be directly tested for open and short circuits through the test connection line 400. The individual traces in the first trace group 10 and the second trace group 20 can be tested independently. During the test, it is not necessary to short-circuit the other traces. After the test is completed, the test connection line 400 is a normal display connection line and does not need to be etched to disconnect it. Especially for thick metal lines (such as thick copper lines), which are difficult to etch, the risk of trace or connection line etching is avoided, the yield of the circuit is improved, the process efficiency is improved, and the yield quality of the display panel 100 is improved.

[0043] In some embodiments, please refer to Figure 1 The display panel 100 further includes sensing lines 600 arranged along a first direction; wherein, the individual lines in the first wiring group 10 and the second wiring group 20 are the data wiring line 200 and the sensing line 600, respectively.

[0044] The sensing line 600 is arranged in a single line to avoid the influence of the data line 200 on the sensing line 600 and to ensure the performance of the sensing line 600.

[0045] In some embodiments, please refer to Figure 1 The power trace 500 includes a first power trace 510 and a second power trace 520. The voltage of the first power trace 510 is different from the voltage of the second power trace 520. The power traces 500 of two adjacent third trace groups 30 are the first power trace 510 and the second power trace 520, respectively.

[0046] The power bus 300 includes a first power bus 310 and a second power bus 320. The first power bus 310 can be a VDD bus, and the second power bus 320 can be a VSS bus. The voltage lines include a first voltage line and a second voltage line. The first power trace 510 can be a VDD trace, and the second power trace 520 can be a VSS trace. Both the VSS and VDD traces can be constant voltage lines. Alternating the VDD and VSS traces periodically can avoid the superposition of the same voltage and also facilitates the neat arrangement of the wires.

[0047] In some embodiments, please refer to Figure 1 , Figure 2The power bus 300 includes a first power bus 310 and a second power bus 320. The first power bus 310 is electrically connected to the first power trace 510, and the second power bus 320 is electrically connected to the second power trace 520. The first power bus 310, the second power bus 320, the first power trace 510, the second power trace 520, the test connection line 400, and the data trace 200 are arranged on the same layer.

[0048] By setting all traces, buses, and test connections 400 to the same layer, most traces will not cross. A single layer of metal can be used to pattern the traces, thus enhancing the overall circuit integration.

[0049] In some embodiments, please refer to Figure 1 , Figure 2 The display panel 100 includes: a substrate 110; a first metal layer 120 located on the substrate 110, the first metal layer 120 including a first power bus 310, a second power bus 320, a first power trace 510, a second power trace 520, a test connection line 400, and a data trace 200; a first insulating layer 130 located on the side of the first metal layer 120 away from the substrate 110, the first insulating layer 130 including a plurality of first openings 131 and a plurality of second openings; and a second metal layer located on the side of the first insulating layer 130 away from the substrate 110, the second metal layer including a first jumper 108 and a second jumper 109.

[0050] The first power bus 310 includes a first upper power bus 311 and a first lower power bus 312, and the second power bus 320 includes a second upper power bus 321 and a second lower power bus 322. The first upper power bus 311 and the second upper power bus 321 are disposed at one end of the display panel 100, and the first lower power bus 312 and the second lower power bus 322 are disposed at the other end of the display panel 100. The first upper power bus 311 is disposed on the side of the second upper power bus 321 away from the first lower power bus 312, and the first lower power bus 312 is disposed on the side of the second lower power bus 322 close to the first upper power bus 311.

[0051] Specifically, the first upper power bus 311 is directly connected to the corresponding first power trace 510 via the test connection line 400, the second lower power bus 322 is directly connected to the corresponding second power trace 520 via the test connection line 400, the first lower power bus 312 is connected to the corresponding first power trace 510 via the first jumper 108, and the second upper power bus 321 is connected to the corresponding second power trace 520 via the second jumper 109.

[0052] The power bus 300, which is connected to the corresponding power trace 500 via the test connection line 400, is located on the side close to the connection end of the power trace 500. When the first metal layer 120 is formed, the power bus 300 that needs to be tested for open and short circuits can be connected to the corresponding power trace 500 for testing. If the power bus 300 on the side away from the connection end of the power trace 500 wants to be connected to the power trace 500, a cross-layer metal wire jumper needs to be set to connect it.

[0053] In some embodiments, please refer to Figure 2 The first metal layer 120 further includes a plurality of light-shielding portions, which correspond to the thin-film transistors of the display panel 100; the second metal layer further includes a gate layer 104 or a source-drain layer 106. In the figure, the second metal layer is illustrated as an example of the second metal layer further including a source-drain layer 106, which is easy to understand. The illustration of the second metal layer further including a gate layer 104 is not shown.

[0054] The first metal layer 120 may include a light-shielding portion, which is a metal material, used to shield the channel of the active layer of the thin-film transistor to avoid the photoelectric effect of light on the channel. The second metal layer may include a gate layer 104 or a source-drain layer 106, that is, the first jumper 108 and the second jumper 109 may be fabricated using the metal of the gate layer 104 or the source-drain layer 106.

[0055] In some embodiments, please refer to Figure 1 In the third wiring group 30, the three wirings are, in order, a data wiring 200, a power wiring 500, and another data wiring 200.

[0056] In the third wiring group 30, the power supply trace 500 is disposed between two adjacent data traces 200. The constant voltage characteristic of the power supply trace 500 can be used to reduce signal crosstalk between data traces 200 and improve the display effect.

[0057] In some embodiments, please refer to Figure 1 The sub-pixels 700 corresponding to the two data traces 200 in the third trace group 30 have different emission colors.

[0058] The data trace 200 corresponds to a column of sub-pixels 700. The light emission color of the sub-pixels 700 in the same column is the same, which can make the pixel arrangement more regular.

[0059] In some embodiments, please refer to Figure 1 In adjacent first routing group 10, second routing group 20 and third routing group 30, the light emission color of the sub-pixels corresponding to any two data routing lines 200 is different.

[0060] The first wiring group 10, the second wiring group 20 and the third wiring group 30 correspond to a cyclic arrangement period, the sub-pixels 700 are arranged more regularly, it is convenient to set the data wiring 200 corresponding to sub-pixels with different light emission colors, which is conducive to the regular arrangement of lines.

[0061] In some embodiments, please refer to Figure 1 The distance between two traces in any two adjacent trace groups in the first trace group 10, the second trace group 20, and the third trace group 30 in the second direction is greater than the distance between two adjacent traces in the third trace group 30 in the second direction.

[0062] Both the first wiring group 10 and the second wiring group 20 are single-wire configurations. Increasing the distance between the two wires of any two adjacent wiring groups in the second direction helps reduce the risk of line abnormalities in the first wiring group 10 and the second wiring group 20. For open and short circuit detection in the third wiring group 30, a test connection line 400 that does not require subsequent etching can be used to connect the power line 500 of the three wirings to the power bus 300 for OST detection.

[0063] In some embodiments, please refer to Figure 1 The display panel 100 includes a plurality of sub-pixels 700 arranged in a matrix; wherein the first wiring group 10, the second wiring group 20 and the third wiring group 30 are respectively disposed between two adjacent columns of the sub-pixels 700.

[0064] The 700 subpixels are arranged more neatly, making it easier to set up routing. At the same time, the distance between adjacent routing groups is increased to avoid the risk of short circuits.

[0065] For example, please see Figure 1The display panel 100 includes a plurality of sub-pixels 700 arranged in an array. The sub-pixels 700 are any one of red sub-pixels 700, green sub-pixels 700, and blue sub-pixels 700. The light emission color of each column of sub-pixels 700 is the same. The data traces 200 are any one of red data traces R, green data traces G, and blue data traces B. The column direction is the first direction. The first trace group 10 includes green data traces G, the second trace group 20 includes the sensing line 600, and the third trace group 30 includes a first power trace 510 (or a second power trace 520), red data traces R, and blue data traces B. In the second direction, the first trace group 10, the second trace group 20, and the third trace group 30 are arranged alternately. The first trace group 10, the second trace group 20, and the third trace group 30 are all disposed between two adjacent columns of sub-pixels 700.

[0066] The routing arrangement is changed to 3 / 1 / 1. The third routing group 30, which includes three routing lines, is configured to include at least one power routing line 500 and at least one data routing line 200. The test connection line 400 connects the power routing line 500 and the power bus 300. The three routing lines in the third routing group 30 can be directly tested for open and short circuits through the test connection line 400. The voltage drop of the two data routing lines 200 is low, and they are at a low potential. Under normal circumstances, the power routing line 500 is in a floating state, with a higher voltage drop, and is at a high potential. Once there is a short circuit caused by a residual short circuit between any data routing line 200 and the power routing line 500 in the third routing group 30, the electrical signal of the floating routing line will be pulled low by the electrical signal of the short-circuited routing line, thereby detecting the defect.

[0067] Individual traces in the first trace group 10 and the second trace group 20 can be tested independently. For example, if a voltage is given to a trace and it does not match the given voltage, the defect can be detected. Since the traces in the first trace group 10 and the second trace group 20 are far away from the other traces, the other traces do not need to be short-circuited during the test to complete the test. After the test is completed, there is no need to etch the extra traces, avoiding the risk of etching traces or connecting lines, improving the yield of the circuit, improving the process efficiency, and improving the yield quality of the display panel 100.

[0068] In some embodiments, please refer to Figure 2 The display panel 100 also includes a planarization layer 107 located on the second metal layer. The planarization layer 107 can fill the first opening 131 and the second opening for reinforcement. Generally, the material of the planarization layer 107 is an organic material, which can fill the holes well and at the same time provide openings for better bending resistance.

[0069] In some embodiments, please refer to Figure 2 The display panel 100 further includes a first interlayer insulating layer 101 located on the surface of the first metal layer 120 away from the substrate 110, an active layer 102 located on the first interlayer insulating layer 101, a gate insulating layer 103 located on the active layer 102, a gate layer 104 located on the gate insulating layer 103, a second interlayer insulating layer 105 located on the gate layer 104, and a source-drain layer 106 located on the gate insulating layer 103.

[0070] In some embodiments, the gate layer 104 includes a plurality of gates, and the first metal layer 120 further includes a light-shielding portion corresponding to the gate.

[0071] In some embodiments, please refer to Figure 2 Taking the second metal layer including the source and drain layer 106 as an example, the first insulating layer 130 may include the second inter-insulating layer 105 and the gate insulating layer 103, and the first opening 131 and the second opening penetrate the second inter-insulating layer 105 and the gate insulating layer 103.

[0072] In some embodiments, the display panel 100 may be a liquid crystal display panel 100 or a self-emissive display panel 100.

[0073] In some embodiments, the display panel 100 may be a liquid crystal display panel 100, and the display panel 100 further includes a liquid crystal layer, a color filter layer, and upper and lower polarizing layers. The display module further includes a backlight unit corresponding to the display panel 100.

[0074] In some embodiments, the display panel 100 is a self-emissive display panel 100. The display panel 100 further includes a light-emitting device layer.

[0075] In some embodiments, the light-emitting device layer may include OLED (Organic Light-Emitting Diode) material, or Micro LED or Mini LED, without specific limitations.

[0076] In some embodiments, the light-emitting device layer may include OLED (Organic Light-Emitting Diode) material, the light-emitting device layer includes an anode layer on the planarization layer 107, a light-emitting material layer on the anode layer, and a cathode layer on the light-emitting material layer, the display panel 100 further includes a pixel definition layer disposed on the same layer as the light-emitting material layer, a polarizing layer on the light-emitting device layer, and a flexible cover plate on the polarizing layer, and the display panel 100 further includes a corresponding adhesive layer between the polarizing layer and the flexible cover plate.

[0077] This application changes the arrangement of the traces to 3 / 1 / 1, setting the third trace group, which includes three traces, to include at least one power trace and at least one data trace. The test connection line connects the power trace and the power bus. The three traces in the third trace group can be directly tested for open and short circuits through the test connection line. The individual traces in the first and second trace groups can be tested independently. During the test, it is not necessary to short-circuit the other traces. After the test is completed, it is not necessary to etch the test connection line, thus avoiding the risk of trace or connection line etching, improving the yield of the circuit, improving the process efficiency, and improving the yield and quality of the display panel.

[0078] Please see Figure 3 The present invention also provides a display device 1, including a display panel 100 as described above and a device body 2, wherein the device body 2 and the display panel 100 are integrated into one unit.

[0079] For the specific structure of the display panel 100, please refer to any of the above-described embodiments of the display panel 100 and the accompanying drawings, which will not be repeated here.

[0080] In this embodiment, the main body 2 of the device may include a middle frame, frame adhesive, etc., and the display device 1 may be a display terminal such as a mobile phone, tablet, or television, which is not limited here.

[0081] This application discloses a display panel and a display device. The display panel includes data traces, power traces, a power bus, and test connection lines. The display panel includes a first trace group, a second trace group, and a third trace group arranged in a sequential and periodic manner. The first and second trace groups each contain a single trace, while the third trace group includes at least one power trace and at least one data trace. By changing the arrangement of the traces to 3 / 1 / 1, the three traces in the third trace group can be directly tested for open and short circuits through the test connection lines. The single traces in the first and second trace groups can be tested independently. During testing, it is not necessary to short-circuit the other traces. After testing, it is not necessary to etch the test connection lines, thus avoiding the risk of trace or connection line etching and improving the yield and quality of the display panel.

[0082] The above provides a detailed description of a display panel and display device provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. Those skilled in the art may make changes to the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A display panel, characterized in that, include: Data routing is arranged along the first direction; The power supply traces are arranged along the first direction; The power bus is arranged along the second direction; A test connection cable is positioned between the power supply trace and the power bus. Wherein, the first direction and the second direction are at an angle, the display panel includes a first wiring group, a second wiring group and a third wiring group, in the second direction, the first wiring group, the second wiring group and the third wiring group are arranged in sequence and periodically, the first wiring group and the second wiring group each contain a single wiring, the third wiring group includes three wirings including at least one power wiring and at least one data wiring.

2. The display panel according to claim 1, characterized in that, The display panel also includes sensing lines arranged along the first direction; In this configuration, the individual traces in the first trace group and the second trace group are respectively the data trace and the sensing trace.

3. The display panel according to claim 2, characterized in that, The power trace includes a first power trace and a second power trace, wherein the voltage of the first power trace is different from the voltage of the second power trace. The power traces of two adjacent third trace groups are, in sequence, the first power trace and the second power trace.

4. The display panel according to claim 3, characterized in that, The power bus includes a first power bus and a second power bus, the first power bus is electrically connected to the first power trace, and the second power bus is electrically connected to the second power trace. The first power bus, the second power bus, the first power trace, the second power trace, the test connection line, and the data trace are arranged on the same layer.

5. The display panel according to claim 4, characterized in that, The display panel includes: Substrate; A first metal layer is located on the substrate, and the first metal layer includes a first power bus, a second power bus, a first power trace, a second power trace, a test connection line, and a data trace. A first insulating layer is located on the side of the first metal layer away from the substrate, and the first insulating layer includes a plurality of first openings and a plurality of second openings; A second metal layer is located on the side of the first insulating layer away from the substrate, and the second metal layer includes a first jumper and a second jumper. The first power bus includes a first upper power bus and a first lower power bus, and the second power bus includes a second upper power bus and a second lower power bus. The first upper power bus and the second upper power bus are disposed at one end of the display panel, and the first lower power bus and the second lower power bus are disposed at the other end of the display panel. The first upper power bus is located on the side of the second upper power bus away from the first lower power bus, and the first lower power bus is located on the side of the second lower power bus closer to the first upper power bus. Specifically, the first lower power bus is directly connected to the corresponding first power trace via the test connection line, the second upper power bus is directly connected to the corresponding second power trace via the test connection line, the first upper power bus is connected to the corresponding first power trace via the first jumper, and the second lower power bus is connected to the corresponding second power trace via the second jumper.

6. The display panel according to claim 5, characterized in that, The first metal layer also includes a plurality of light-shielding portions, which correspond to the thin-film transistors of the display panel; The second metal layer also includes a gate layer or a source / drain layer.

7. The display panel according to claim 2, characterized in that, In the third routing group, the three routing lines are, in order, a data routing line, a power routing line, and another data routing line. The sub-pixels corresponding to the two data routing lines in the third routing group have different emission colors.

8. The display panel according to claim 7, characterized in that, In adjacent first, second, and third data routing groups, the emission colors of the sub-pixels corresponding to any two data routing lines are different.

9. The display panel according to claim 1, characterized in that, The distance between two traces in any two adjacent trace groups in the first trace group, the second trace group, and the third trace group in the second direction is greater than the distance between two adjacent traces in the third trace group in the second direction.

10. A display device, characterized in that, The device includes a display panel and a device body as described in any one of claims 1 to 9, wherein the device body and the display panel are integrated as one unit.

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