Pixel circuit, driving method thereof, display substrate and display device

Abstract

Embodiments of the present disclosure provide a pixel circuit and a driving method thereof, a display substrate and a display device, and relate to the technical field of display. The pixel circuit can improve the brightness reduction phenomenon caused by the aging of the light emitting element, and prolong the service life. The pixel circuit comprises a data writing sub-circuit, a driving sub-circuit, a storage sub-circuit, a first compensation sub-circuit, a second compensation sub-circuit and a light emitting control sub-circuit. The data writing sub-circuit is coupled with a data signal end, a scanning signal end and a first node. The driving sub-circuit is coupled with a first voltage end, a second node and a third node. The storage sub-circuit is coupled between the first node and the second node. The first compensation sub-circuit is coupled with a first control signal end, the first node and a first pole of the light emitting element. The second compensation sub-circuit is coupled with a second control signal end, the second node and the third node. The light emitting control sub-circuit is coupled with an enable signal end, the third node and the first pole of the light emitting element. A second pole of the light emitting element is coupled with a second voltage end.

Description

[0001] This application is a divisional application. The original application was filed on November 27, 2020, with application number 202011354558.1. The entire contents of the original application are incorporated into this application by reference. Technical Field

[0002] The present disclosure relates to the field of display technology, and in particular to a pixel circuit and a driving method thereof, a display substrate, and a display device. Background Art

[0003] Currently, most display devices pursue high resolution and image quality. Self-luminous display devices, represented by organic light emitting diode (OLED) displays, are a hot topic in current research due to their advantages such as self-luminescence, low energy consumption, wide viewing angle, and fast response speed. Summary of the Invention

[0004] Embodiments of the present disclosure provide a pixel circuit and a driving method thereof, a display substrate, and a display device, which can improve the brightness reduction phenomenon caused by aging of light-emitting elements and extend the service life of the light-emitting elements.

[0005] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0006] In a first aspect, embodiments of the present disclosure provide a pixel circuit. The pixel circuit includes a data write subcircuit, a driver subcircuit, a storage subcircuit, a first compensation subcircuit, a second compensation subcircuit, and a light-emitting control subcircuit. The data write subcircuit is coupled to a data signal terminal, a scan signal terminal, and a first node; the data write subcircuit is configured to write a data signal received at the data signal terminal to the first node in response to a scan signal received at the scan signal terminal. The driver subcircuit is coupled to a first voltage terminal, a second node, and a third node; the driver subcircuit is configured to generate a drive current in response to a voltage at the second node. The storage subcircuit is coupled between the first node and the second node; the storage subcircuit is configured to store a voltage. The first compensation subcircuit is coupled to a first control signal terminal, the first node, and a first electrode of a light-emitting element; the first compensation subcircuit is configured to transmit a second voltage from the second voltage terminal and a threshold voltage of the light-emitting element to the first node in response to a first control signal received at the first control signal terminal. The second compensation subcircuit is coupled to the second control signal terminal, the second node, and the third node. The second compensation subcircuit is configured to transmit the first voltage from the first voltage terminal and the threshold voltage of the driver subcircuit to the second node in response to a second control signal received at the second control signal terminal. The light emission control subcircuit is coupled to the enable signal terminal, the third node, and the first electrode of the light emitting element. The light emission control subcircuit is configured to output the drive current transmitted to the third node to the light emitting element in response to an enable signal received at the enable signal terminal. The second electrode of the light emitting element is coupled to the second voltage terminal.

[0007] In some embodiments, the pixel circuit further includes a potential maintaining subcircuit coupled between the first voltage terminal and the first node; the potential maintaining subcircuit is configured to maintain the potential of the first node.

[0008] In some embodiments, the potential maintaining sub-circuit includes a first capacitor; a first terminal of the first capacitor is coupled to the first node, and a second terminal of the first capacitor is coupled to the first voltage terminal.

[0009] In some embodiments, the first compensation subcircuit includes a first transistor; the control electrode of the first transistor is coupled to the first control signal terminal, the first electrode of the first transistor is coupled to the first node, and the second electrode of the first transistor is coupled to the first electrode of the light-emitting element.

[0010] In some embodiments, the second compensation sub-circuit includes a second transistor; a control electrode of the second transistor is coupled to the second control signal terminal, a first electrode of the second transistor is coupled to the third node, and a second electrode of the second transistor is coupled to the second node.

[0011] In some embodiments, the first control signal terminal and the second control signal terminal are the same control signal terminal.

[0012] In some embodiments, the pixel circuit further comprises at least one of a first initialization subcircuit, a second initialization subcircuit, and a third initialization subcircuit. The first initialization subcircuit is coupled to a first reset signal terminal, a first initialization signal terminal, and the first node; in response to a first reset signal received at the first reset signal terminal, the first initialization subcircuit is configured to transmit a first initialization signal received at the first initialization signal terminal to the first node to initialize the potential of the first node. The second initialization subcircuit is coupled to a second reset signal terminal, a second initialization signal terminal, and the second node; in response to a second reset signal received at the second reset signal terminal, the second initialization subcircuit is configured to transmit a second initialization signal received at the second initialization signal terminal to the second node to initialize the potential of the second node. The third initialization subcircuit is coupled to a third reset signal terminal, a third initialization signal terminal, and the first electrode of the light-emitting element; in response to a third reset signal received at the third reset signal terminal, the third initialization subcircuit is configured to transmit a third initialization signal received at the third initialization signal terminal to the first electrode of the light-emitting element to initialize the potential of the first electrode of the light-emitting element.

[0013] In some embodiments, the pixel circuit includes the first initialization sub-circuit, the second initialization sub-circuit, and the third initialization sub-circuit. The first reset signal terminal, the second reset signal terminal, and the third reset signal terminal are the same reset signal terminal, and / or the first initialization signal terminal, the second initialization signal terminal, and the third initialization signal terminal are the same initialization signal terminal.

[0014] In some embodiments, the first initialization sub-circuit includes a third transistor; the control electrode of the third transistor is coupled to the first reset signal terminal, the first electrode of the third transistor is coupled to the first initialization signal terminal, and the second electrode of the third transistor is coupled to the first node.

[0015] In some embodiments, the second initialization sub-circuit includes a fourth transistor; the control electrode of the fourth transistor is coupled to the second reset signal terminal, the first electrode of the fourth transistor is coupled to the second initialization signal terminal, and the second electrode of the fourth transistor is coupled to the second node.

[0016] In some embodiments, the third initialization sub-circuit includes a fifth transistor; the control electrode of the fifth transistor is coupled to the third reset signal terminal, the first electrode of the fifth transistor is coupled to the third initialization signal terminal, and the second electrode of the fifth transistor is coupled to the first electrode of the light-emitting element.

[0017] In some embodiments, the data writing sub-circuit includes a sixth transistor; the control electrode of the sixth transistor is coupled to the scan signal end, the first electrode of the sixth transistor is coupled to the data signal end, and the second electrode of the sixth transistor is coupled to the first node.

[0018] In some embodiments, the storage sub-circuit includes a second capacitor; a first terminal of the second capacitor is coupled to the first node, and a second terminal of the second capacitor is coupled to the second node.

[0019] In some embodiments, the driving sub-circuit drives a transistor; a control electrode of the driving transistor is coupled to the second node, a first electrode of the driving transistor is coupled to the first voltage terminal, and a second electrode of the driving transistor is coupled to the third node.

[0020] In some embodiments, the light-emitting control subcircuit includes a seventh transistor; the control electrode of the seventh transistor is coupled to the enable signal terminal, the first electrode of the seventh transistor is coupled to the third node, and the second electrode of the seventh transistor is coupled to the first electrode of the light-emitting element.

[0021] In a second aspect, an embodiment of the present disclosure provides a driving method for a pixel circuit, applicable to the pixel circuit described in any of the above embodiments. The driving method comprises: during a compensation phase of an image frame, the second compensation subcircuit transmits a first voltage from the first voltage terminal and a threshold voltage of the driving subcircuit to the second node in response to a second control signal received at the second control signal terminal; the first compensation subcircuit transmits a second voltage from the second voltage terminal and a threshold voltage of the light-emitting element to the first node in response to the first control signal received at the first control signal terminal; during a write phase of the image frame, the data write subcircuit writes a data signal received at the data signal terminal to the first node in response to a scan signal received at the scan signal terminal; and during a light-emitting phase of the image frame, the driving subcircuit is turned on in response to the voltage at the second node to generate a driving current; and the light-emitting control subcircuit outputs the driving current transmitted to the third node to the light-emitting element in response to an enable signal received at the enable signal terminal to drive the light-emitting element to emit light.

[0022] In some embodiments, the pixel circuit further includes: at least one of a first initialization subcircuit, a second initialization subcircuit, and a third initialization subcircuit; the first initialization subcircuit is coupled to the first reset signal terminal, the first initialization signal terminal, and the first node; the second initialization subcircuit is coupled to the second reset signal terminal, the second initialization signal terminal, and the second node; the third initialization subcircuit is coupled to the third reset signal terminal, the third initialization signal terminal, and the first pole of the light-emitting element. Before the compensation phase of the image frame, the driving method further includes at least one of the following steps: in the reset phase of the image frame, the first initialization sub-circuit transmits the first initialization signal received at the first initialization signal terminal to the first node in response to the first reset signal received at the first reset signal terminal, so as to initialize the potential of the first node; in the reset phase of the image frame, the second initialization sub-circuit transmits the second initialization signal received at the second initialization signal terminal to the second node in response to the second reset signal received at the second reset signal terminal, so as to initialize the potential of the second node; and, in the reset phase of the image frame, the third initialization sub-circuit transmits the third initialization signal received at the third initialization signal terminal to the first pole of the light-emitting element in response to the third reset signal received at the third reset signal terminal, so as to initialize the potential of the first pole of the light-emitting element.

[0023] In a third aspect, embodiments of the present disclosure provide a display substrate comprising a substrate, a pixel circuit as described in any of the above embodiments disposed on the substrate, and a light-emitting element disposed on the substrate; the light-emitting element is coupled to the pixel circuit.

[0024] In some embodiments, the pixel circuit further includes a potential-maintaining subcircuit coupled to the first voltage terminal and the first node; the potential-maintaining subcircuit is configured to maintain the potential of the first node; and the potential-maintaining subcircuit includes a first capacitor. The storage subcircuit in the pixel circuit includes a second capacitor. The display substrate further includes a first conductor layer and a second conductor layer sequentially stacked on the substrate. The first conductor layer and the second conductor layer are insulated from each other; the first conductor layer includes: a first conductor pattern and a second conductor pattern that are not connected to each other; the second conductor layer includes: a third conductor pattern; the orthographic projection of the third conductor pattern on the substrate overlaps with the orthographic projection of the first conductor pattern on the substrate to form the first capacitor; the orthographic projection of the third conductor pattern on the substrate overlaps with the orthographic projection of the second conductor pattern on the substrate to form the second capacitor.

[0025] In a fourth aspect, embodiments of the present disclosure provide a display device comprising the display substrate described in the above embodiments and a driver chip coupled to the display substrate; the driver chip is configured to provide signals required to drive the pixel circuits in the display substrate.

[0026] The embodiments of the present disclosure provide a pixel circuit and a driving method thereof, a display substrate and a display device, wherein the pixel circuit is used to compensate for the threshold voltage V oled_th , so that the driving current flowing through the light-emitting element is equal to its own threshold voltage V oled_th Thus, when the luminous brightness of the light-emitting element decreases due to aging, the threshold voltage V oled_th After the increase, the driving current flowing through the light-emitting element also increases, thereby compensating for the driving current of the light-emitting element, improving the brightness reduction problem of the light-emitting element due to aging, and extending the service life of the light-emitting element, thereby improving the display quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. However, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and do not limit the actual size of the products involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signals, etc.

[0028] Figure 1 This is the lifespan attenuation characteristic curve of OLED;

[0029] Figure 2 A schematic diagram of wiring of a display substrate in a self-luminous display device provided by a technical solution;

[0030] Figure 3 is a structural diagram of a display device according to some embodiments;

[0031] Figure 4 is a structural diagram of a display substrate according to some embodiments;

[0032] Figure 5 is a structural diagram of a sub-pixel according to some embodiments;

[0033] Figure 6 is a circuit diagram of a pixel circuit according to some embodiments;

[0034] Figure 7 A circuit diagram of a pixel circuit according to some other embodiments;

[0035] Figures 8A to 8D is a circuit diagram of a pixel circuit according to yet other embodiments;

[0036] 9A to 9D is a circuit diagram of a pixel circuit according to yet other embodiments;

[0037] Figure 10 is a circuit diagram of a pixel circuit according to yet other embodiments;

[0038] Figure 11 is a circuit diagram of a pixel circuit according to yet other embodiments;

[0039] Figure 12 for Figure 11 The signal timing diagram of the pixel circuit shown;

[0040] Figure 13A for Figure 11 The schematic diagram of the working state of the pixel circuit in the reset phase is shown;

[0041] Figure 13B for Figure 11 The schematic diagram of the working state of the pixel circuit in the compensation stage is shown;

[0042] Figure 13C for Figure 11 The schematic diagram of the working state of the pixel circuit in the writing phase is shown;

[0043] Figure 13D for Figure 11 The schematic diagram of the working state of the pixel circuit in the light-emitting stage is shown;

[0044] Figure 14 A feedback schematic diagram of two pixel circuits provided for a technical solution;

[0045] Figure 15 A diagram comparing the feedback principle of a pixel circuit provided according to some embodiments with the feedback principle of a pixel circuit provided by a technical solution;

[0046] Figure 16 for Figure 11 Schematic diagram of a simulation model of a pixel circuit shown;

[0047] Figure 17 for Figure 11 Schematic diagram of simulation signals of the pixel circuit shown;

[0048] Figure 18 is a structural diagram of a display substrate according to some other embodiments;

[0049] Figure 19 is a schematic diagram of a layout of a display substrate according to some embodiments;

[0050] 20A to 20D for Figure 19 Schematic diagram of the layout of each layer;

[0051] Figure 21 is a flow chart of a driving method of a pixel circuit according to some embodiments; and

[0052] Figure 22 is a flow chart of a driving method for a pixel circuit according to some other embodiments. DETAILED DESCRIPTION

[0053] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. However, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0054] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0055] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise stated, "multiple" means two or more. In addition, the singular forms "one" and "the" as used in this specification and the appended claims may also include plural indicators, unless the content clearly states otherwise. In the description of the embodiments of the present disclosure, unless otherwise stated, "multiple" means two or more.

[0056] It will be understood that when a layer or an element is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or one or more intervening layers or elements may also be present. Additionally, it will be understood that when a layer or an element is referred to as being "under" another layer or substrate, it can be directly under the other layer or substrate, or one or more intervening layers or elements may also be present. Similarly, it will be understood that when a layer or an element is referred to as being between two layers or elements, it can be the only layer or element between the two layers or elements, or one or more intervening layers may also be present.

[0057] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical contact or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in physical contact or there is an electrical signal path, for example, the two components are connected through a signal line, or there may be other electrical components or circuits between the two components, but there is a signal path between the two components through other electrical components. However, the term "coupled" or "communication coupling" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0058] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0059] As used herein, the term "if" is optionally interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined that" or "if [stated condition or event] is detected" are optionally interpreted to mean "upon determining" or "in response to determining" or "upon detecting [stated condition or event]" or "in response to detecting [stated condition or event]," depending on the context.

[0060] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0061] As used herein, "about" or "approximately" includes the stated value and the average value that is within an acceptable range of deviation from the particular value, where the acceptable range of deviation is determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0062] Self-luminous display devices, comprised of multiple light-emitting elements, have attracted widespread attention due to their high brightness and wide color gamut. The photoelectric conversion characteristics of a light-emitting element (including its efficiency, uniformity, and color coordinates) vary with the current flowing through it.

[0063] Taking an organic light emitting diode (OLED) as an example, the fact that OLEDs are subjected to a DC bias for a long time during the light-emitting process accelerates the polarization of the OLED's light-emitting material, which in turn accelerates the aging of the light-emitting material. This causes the OLED's built-in electric field (i.e., the electric field formed by the semiconductor due to internal forces) to rapidly increase, which in turn increases the OLED's resistance and threshold voltage (i.e., the critical voltage at which it can emit light, also known as the critical voltage across the diode), ultimately increasing the voltage difference between the OLED's anode and cathode. Thus, when the data signal remains unchanged, the actual current flowing through the OLED decreases, reducing the OLED's actual light brightness and making it difficult to achieve the set brightness, thereby reducing the quality of the image displayed by the self-luminous display device.

[0064] When the ratio of the actual brightness of the light emitted by the OLED to the initial brightness (i.e., the maximum brightness of the light that the OLED can emit at the beginning of use) is too low, for example, when the ratio drops to 0.8 (i.e., the actual brightness of the light that the OLED can emit is 80% of the initial brightness), it cannot meet the display requirements, and it is difficult to use the self-luminous display device to continue to display the image, which shortens the lifespan of the self-luminous display device containing the OLED. Therefore, as the threshold voltage of the OLED increases, its service life will be greatly reduced.

[0065] Figure 1 This is the lifespan attenuation characteristic curve of OLED. Figure 1 As shown, the horizontal axis represents time (hours, h), the vertical axis on the left is the voltage (V) of the anode surface of the OLED obtained by constant current test, and the vertical axis on the right is the life span of the OLED (percentage).

[0066] Since the voltage applied to the cathode of the OLED is usually a constant DC voltage, by measuring the change in the surface voltage of the anode of the OLED over time, it is possible to characterize the change in the voltage difference between the anode and cathode of the OLED over time, that is, to characterize the change in the threshold voltage of the OLED over time. Figure 1 It can be seen that as the use time of OLED increases, the threshold voltage of OLED gradually increases, that is, the life of OLED gradually decreases.

[0067] For some products with a long service life, such as car displays, ship displays, and laptop computers, the lifespan of the light-emitting element (such as the above-mentioned OLED) itself limits its further application in the above-mentioned long service life products, thereby limiting the application fields of the self-luminous display device.

[0068] To extend the lifespan of light-emitting elements, a related art method provides a current compensation method. This method measures the current or voltage of the light-emitting element (e.g., OLED) in each sub-pixel during the light-emitting phase. The method then calculates and compensates for any shortfall in the actual current flowing through the OLED in the data signal input to that sub-pixel. This increases the OLED's current and brightness, thereby extending the OLED's lifespan.

[0069] The above method is also called an external compensation method because it compensates the current of the OLED from outside the sub-pixel.

[0070] Since testing the current of an OLED requires connecting the anode of the OLED and the sensing signal line in series, which is a difficult process, when using an external compensation method, the anode of the OLED and the sensing signal line are usually connected in parallel.

[0071] Figure 2 The following is a schematic diagram of the wiring of a display substrate in a self-luminous display device provided by a technical solution. Figure 2 As shown, the display substrate 100' has a display area (Active Area, AA) and a peripheral area located on at least one side outside the AA area. A plurality of sub-pixels (such as red sub-pixel P1, green sub-pixel P2 and blue sub-pixel P3, etc.) and a plurality of sensing signal lines (Sense) coupled to the plurality of sub-pixels are arranged in the AA area. The peripheral area includes a bonding area (B). The sensing signal line Sense extends to the bonding area B and is connected to the integrated circuit (IC). Figure 2 (not shown) coupled to transmit the voltage signal of the anode surface of the OLED in the corresponding sub-pixel.

[0072] This requires an increased number of ICs to calculate the data signals used to compensate for the OLED's current, significantly increasing costs. Furthermore, because the external compensation method measures the OLED's anode surface voltage at the pad in bonding area B, the signal strength changes after being transmitted via the longer sensing signal line Sense, affecting the measured voltage on the OLED's anode surface. This reduces the accuracy of the external compensation method and makes it difficult to effectively extend the life of the light-emitting element.

[0073] Based on this, in order to improve the phenomenon of reduced luminance of light-emitting elements (such as OLEDs) due to aging, extend the service life of OLEDs, and improve the display quality of a display device having the OLEDs, an embodiment of the present disclosure provides a display device.

[0074] Exemplarily, the display device may be any device that displays either moving (e.g., video) or stationary (e.g., still images), and whether text or images. More specifically, the display device may be one of a variety of electronic devices, and the embodiments may be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, video cameras, game consoles, watches, clocks, calculators, television monitors, flat-panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigation systems, cockpit controls and / or displays, camera view displays (e.g., displays for rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays for images of a piece of jewelry), etc. The embodiments of the present disclosure do not impose any particular restrictions on the specific form of the above-mentioned display device.

[0075] Figure 3 FIG is a structural diagram of a display device according to some embodiments. Figure 3 As shown, the display device 200 includes a display substrate 100 .

[0076] The display substrate 100 has an active area (AA) and a peripheral area W. The peripheral area W is located on at least one side outside the AA area.

[0077] The display substrate 100 includes a plurality of sub-pixels P disposed in the AA region. For example, the plurality of sub-pixels P may be arranged in an array. Figure 3 The sub-pixels P arranged in a row in the X direction (e.g., row direction) are called sub-pixels in the same row. Figure 3 The sub-pixels P arranged in a row along the Y direction (eg, the column direction) are referred to as sub-pixels in the same column.

[0078] Figure 4 FIG. 1 is a structural diagram of a display substrate according to some embodiments. Figure 4 As shown, the display substrate 100 further includes a substrate 100a. The aforementioned pixel circuit 101 and the light emitting element L are both disposed on the substrate 100a.

[0079] It should be understood that for ease of illustration, Figure 4 In the figure, only a single layer is used to represent the pixel circuit 101 and the light emitting element L, and their specific structures will be described in detail in subsequent embodiments.

[0080] Exemplarily, the substrate 100a may include: a rigid substrate (or hard substrate) made of materials such as glass, or a flexible substrate made of materials such as polyimide (PI), polyethylene terephthalate (PET), polycarbonate (PC), polymethyl methacrylate (PMMA), or polyether sulfone resin (PES).

[0081] Furthermore, in some examples, the display substrate 100 further includes a thin film such as a buffer layer disposed on the substrate 100a to prevent impurity ions that may be present in the substrate 100a from migrating toward the pixel circuit 101 during the process of fabricating the pixel circuit 101. That is, the pixel circuit 101 is disposed on the surface of the thin film such as the buffer layer that faces away from the substrate 100a.

[0082] Figure 5 FIG is a structural diagram of a sub-pixel according to some embodiments. Figure 5 As shown, each sub-pixel P includes: a light emitting element L and a pixel circuit 101 coupled to the light emitting element L. The pixel circuit 101 is configured to provide a driving current to the light emitting element L to drive the light emitting element L to operate (ie, emit light).

[0083] For example, Figure 5 As shown, the first electrode of the light emitting element L is coupled to the pixel circuit 101, and the second electrode of the light emitting element L is coupled to the second voltage terminal V2. The second voltage terminal V2 is configured to transmit a second voltage. For example, the second voltage is a DC reference voltage (Voltage Source Source, V SS ), for example, the second voltage V SS is -3V. Alternatively, the second voltage V SS The second voltage terminal V2 only needs to provide 0V or a negative voltage to the second electrode of the light emitting element L.

[0084] Exemplarily, the light-emitting element L includes a current-driven element. Further, the light-emitting element L may be a current-driven light-emitting diode, such as a micro light-emitting diode (Micro LED), a mini light-emitting diode (Mini LED), a quantum dot light-emitting diode (Quantum Light Emitting Diode, QLED), or an organic light-emitting diode (Organic Light Emitting Diode, OLED). Exemplarily, the first electrode and the second electrode of the light-emitting element L are the anode and cathode of the light-emitting diode, respectively.

[0085] Figure 6 FIG. 1 is a circuit diagram of a pixel circuit according to some embodiments. Figure 6 As shown, the pixel circuit 101 includes: a data writing sub-circuit 10 , a driving sub-circuit 20 , a storage sub-circuit 30 , a first compensation sub-circuit 41 , a second compensation sub-circuit 42 and a light emitting control sub-circuit 50 .

[0086] The data writing sub-circuit 10 is coupled to the data signal terminal Data, the scan signal terminal Scan and the first node N1 and is configured to write a data signal received at the data signal terminal Data into the first node N1 in response to a scan signal received at the scan signal terminal Scan.

[0087] The driving sub-circuit 20 is coupled to the first voltage terminal V1, the second node N2, and the third node N3. The driving sub-circuit 20 is configured to generate a driving current I in response to a voltage at the second node N2.

[0088] The storage sub-circuit 30 is coupled between the first node N1 and the second node N2 and is configured to store a voltage.

[0089] The first compensation sub-circuit 41 is coupled to the first control signal terminal Q1, the first node N1, and the first electrode of the light-emitting element L. The first compensation sub-circuit 41 is configured to transmit the second voltage from the second voltage terminal V2 and the threshold voltage of the light-emitting element L to the first node N1 in response to the first control signal received at the first control signal terminal Q1.

[0090] The second compensation sub-circuit 42 is coupled to the second control signal terminal Q2, the second node N2, and the third node N3. The second compensation sub-circuit 42 is configured to transmit the first voltage from the first voltage terminal V1 and the threshold voltage Vth of the driver sub-circuit 20 to the second node N2 in response to the second control signal received at the second control signal terminal Q2.

[0091] The light emitting control sub-circuit 50 is coupled to the enable signal terminal EM, the third node N3, and the first electrode of the light emitting element L. The light emitting control sub-circuit 50 is configured to output the driving current I transmitted to the third node N3 to the light emitting element L in response to the enable signal received at the enable signal terminal EM.

[0092] The second electrode of the light emitting element L is coupled to the second voltage terminal V2.

[0093] It should be understood that in the pixel circuit 101 provided in the embodiment of the present disclosure, the first node N1, the second node N2, and the third node N3 and other nodes do not necessarily represent actual existing components. In some examples, these nodes represent the junction points of related couplings (i.e., electrical connections) in the equivalent circuit diagram of the pixel circuit. That is, these nodes are nodes formed by the equivalent junction points of related electrical connections in the circuit diagram.

[0094] For example, the light emitting element L is an OLED, and the threshold voltage of the light emitting element L is the threshold voltage V oled_th The following describes the working process of the pixel circuit 101 by taking the light-emitting element L as an OLED as an example. It should be understood that the light-emitting element L can also be other current-driven elements such as Micro LED, Mini LED or QLED, and the embodiments of the present disclosure are not limited to this.

[0095] When the pixel circuit 101 provided by the embodiment of the present disclosure is in operation:

[0096] In the compensation phase U2 of an image frame F, the second compensation sub-circuit 42 receives a second control signal at the second control signal terminal Q2, and converts the first voltage (e.g., the power supply voltage, Voltage DrainDrain, V DD ) and the threshold voltage Vth of the driving sub-circuit 20 are transmitted to the second node N2. In addition, in the compensation phase U2 of the image frame F, the first compensation sub-circuit 41 receives the first control signal at the first control signal terminal Q1 and converts the second voltage V from the second voltage terminal V2 to SS and the threshold voltage V of the light-emitting element L oled_th Transmitted to the first node N1.

[0097] For example, the first voltage V from the first voltage terminal V1 DD is a DC voltage, for example, a DC high level voltage. DD When the second voltage V SS is a low level voltage; for example, the first voltage V DD is 4.6V, the second voltage V SSis -3V.

[0098] Thus, in the compensation phase U2, the voltage V N2 Equal to V DD +Vth, the voltage of the first node N1 V N1 Equal to V SS +V oled_th Since the storage sub-circuit 30 is coupled between the first node N1 and the second node N2, that is, the voltage difference ΔV across the storage sub-circuit 30 is V N2 -V N1 , that is, ΔV is equal to V DD +Vth-V SS -V oled_th .

[0099] In the writing phase U3 of the image frame F, the data writing sub-circuit 10 responds to the scanning signal received at the scanning signal terminal Scan and writes the data signal V received at the data signal terminal Data to the data signal terminal Data. data Write to the first node N1.

[0100] In the writing phase U3, due to the data signal V data The data is directly written into the first node N1 by the data writing sub-circuit 10, so that the voltage V N1 Directly changes to V data , that is, V N1 =V data .

[0101] Since the storage sub-circuit 30 relies on the capacitor it has to store voltage, the voltage V at the first node N1 is stored by utilizing the bootstrap effect of the capacitor (i.e., the voltage at both ends of the capacitor cannot change suddenly, and when the voltage at one end increases, the voltage at the other end remains at the voltage difference with the previous end). N1 becomes V data , that is, V N1 =V data After that, the voltage V N2 Finally stabilizes to V N2 =V data +ΔV=V data +V DD +Vth-V SS -V oled_th .

[0102] Since the voltage difference (V data +Vth-V SS -V oled_th ) is greater than the threshold voltage Vth of the driving sub-circuit 20. Therefore, the driving sub-circuit 20 responds to the voltage V N2It is turned on and generates a driving current I, which satisfies the following formula:

[0103] I=1 / 2·μ·C ox ·W / L·(V gs -Vth) 2 ;

[0104] =1 / 2·μ·C ox ·W / L·(V N2 -V DD -Vth) 2 ;

[0105] =1 / 2·μ·C ox ·W / L·(V data +V DD +Vth-V SS -V oled_th -V DD -Vth) 2 ;

[0106] =1 / 2·μ·C ox ·W / L·(V data -V SS -V oled_th ) 2 ;

[0107] =1 / 2·μ·C ox ·W / L·(V SS +V oled_th -V data ) 2 ;

[0108] Among them, μ, C ox , W and L are fixed constants related to the process parameters and geometric dimensions of the driver sub-circuit 20. Specifically, μ, C ox , W and L are the field effect mobility, gate insulation layer unit area capacitance, channel width and channel length of the driving transistor in the driving sub-circuit 20 respectively. gs is the gate-source voltage difference of the driving transistor in the driving sub-circuit 20 .

[0109] In the light-emitting phase U4 of the image frame F, the light-emitting control subcircuit 50 outputs the driving current I transmitted to the third node N3 to the light-emitting element L in response to the enable signal received at the enable signal terminal EM, so as to drive the light-emitting element L to emit light.

[0110] From the above formula, it can be seen that the driving current I that finally flows through the light emitting element L is not related to the threshold voltage Vth of the driving sub-circuit 20, but is related to the threshold voltage V oled_thAs the light emitting element L is used for a longer time, the light emitting efficiency of the light emitting element L decreases due to material aging, and the threshold voltage V oled_th will increase, and the threshold voltage V oled_th The increase of the data signal V data In other words, the current of the light-emitting element L is compensated.

[0111] Based on this, the pixel circuit 101 provided in the embodiment of the present disclosure can improve the phenomenon of reduced luminous brightness of the light-emitting element L (such as OLED) due to aging by using the circuit structure of the pixel circuit 101 itself through the timing control of various signals, so that the driving current I flowing through the OLED and its own threshold voltage V oled_th positively correlated, so that when the threshold voltage V oled_th When the voltage increases, the driving current I flowing through the OLED also increases, thereby extending the service life of the OLED and improving the display quality of the display device having the OLED.

[0112] Because the pixel circuit 101 provided in the embodiments of the present disclosure utilizes the circuit structure of the pixel circuit 101 itself to compensate the current of the light-emitting element L from within the sub-pixel, the compensation method using this pixel circuit 101 can be referred to as an internal compensation method. Compared to the external compensation method used in the aforementioned related art, when using the pixel circuit 101 provided in the embodiments of the present disclosure to compensate the current of the light-emitting element L, there is no need to add an IC to the display device, resulting in lower compensation costs. Furthermore, the light-emitting element L coupled to each pixel circuit 101 can be independently compensated, resulting in higher compensation accuracy.

[0113] In addition, the light-emitting materials in OLED are usually made by evaporation process. Due to the limited precision of evaporation process, the threshold voltage V oled_th The evaporation process may affect the unevenness. The pixel circuit 101 provided by the embodiment of the present disclosure has the following characteristics: the driving current I that flows through the OLED and its threshold voltage V oled_th Positive correlation can make the driving current I flowing through the OLED and the threshold voltage V oled_th changes synchronously, thereby improving the threshold voltage V oled_th Uneven luminescence caused by unevenness.

[0114] Moreover, since the driving current I finally flowing through the OLED is equal to the first voltage V DD The threshold voltage Vth of the driving sub-circuit 20 is not related to the driving current I of the OLED, so that the driving current I is not affected by the transmission of the first voltage V DDThe first power line L V1 The voltage drop (ie, the potential difference across the resistor, IR drop) and the threshold voltage Vth of the driving sub-circuit 20 are reduced. Thus, the pixel circuit 101 can also improve the uniformity of the driving current flowing through the OLED, thereby achieving uniform luminous brightness.

[0115] Since in the compensation phase U2, the second compensation sub-circuit 42 converts the first voltage V from the first voltage terminal V1 into DD and the threshold voltage Vth of the driving sub-circuit 20 are transmitted to the second node N2 to compensate the threshold voltage Vth of the driving sub-circuit 20; and the first compensation sub-circuit 41 converts the second voltage V SS and the threshold voltage V of the light-emitting element L oled_th Transmitted to the first node N1 to compensate the threshold voltage V oled_th Since both compensation sub-circuits operate in the compensation phase U2 of the image frame, the threshold voltage V oled_th The compensation time of can be set to be the same as the compensation time of the second compensation sub-circuit 42 for the threshold voltage Vth of the driving sub-circuit 20, so as to simplify the timing control process of the signal.

[0116] For example, Figure 6 As shown, the first control signal terminal Q1 and the second control signal terminal Q2 can be the same control signal terminal Q, and the control signal terminal Q is coupled to a control signal line L Q That is, the first compensation sub-circuit 41 and the second compensation sub-circuit 42 are turned on simultaneously and for the same duration. This can also simplify the number of signal lines in the display substrate 100, leaving the display substrate 100 with more space for wiring, thereby enabling the display device 200 to have a higher resolution.

[0117] Figure 7 FIG. 1 is a circuit diagram of a pixel circuit according to some other embodiments. Figure 7 As shown, the pixel circuit 101 includes: a data writing sub-circuit 10, a driving sub-circuit 20, a storage sub-circuit 30, a first compensation sub-circuit 41, a second compensation sub-circuit 42, a light emitting control sub-circuit 50, and a potential holding sub-circuit 60. The potential holding sub-circuit 60 is coupled between the first voltage terminal V1 and the first node N1. The potential holding sub-circuit 60 is configured to hold the potential of the first node N1.

[0118] The functions and mutual coupling methods of the data writing subcircuit 10, the driving subcircuit 20, the storage subcircuit 30, the first compensation subcircuit 41, the second compensation subcircuit 42 and the light emitting control subcircuit 50 are the same as those in the previous embodiment and are not repeated here.

[0119] Since the potential holding sub-circuit 60 is coupled to the first voltage terminal V1 and the first node N1, on the one hand, the voltage of the first node N1 can be kept stable at V during the light emitting phase U4. data , preventing it from being in a floating state, thereby avoiding affecting the compensation of the driving current I of the light emitting element L; on the other hand, the first voltage V DD When a drop or fluctuation occurs, the voltages of the first node N1 and the second node N2 can be equal to the first voltage V DD The same jump makes the Vgs of the driving sub-circuit 20 unchanged, thereby keeping the luminous brightness of the light-emitting element L unchanged.

[0120] Figures 8A to 8D FIG. 1 is a circuit diagram of a pixel circuit according to some further embodiments. Figures 8A to 8D As shown, the pixel circuit 101 includes: a data writing sub-circuit 10, a driving sub-circuit 20, a storage sub-circuit 30, a first compensation sub-circuit 41, a second compensation sub-circuit 42, a light emitting control sub-circuit 50, and at least one of a first initialization sub-circuit 71, a second initialization sub-circuit 72 and a third initialization sub-circuit 73.

[0121] 9A to 9D FIG. 1 is a circuit diagram of a pixel circuit according to some further embodiments. 9A to 9D As shown, the pixel circuit 101 includes: a data writing sub-circuit 10, a driving sub-circuit 20, a storage sub-circuit 30, a first compensation sub-circuit 41, a second compensation sub-circuit 42, a light emitting control sub-circuit 50, a potential holding sub-circuit 60, and at least one of a first initialization sub-circuit 71, a second initialization sub-circuit 72 and a third initialization sub-circuit 73.

[0122] The functions of the data writing sub-circuit 10, the driving sub-circuit 20, the storage sub-circuit 30, the first compensation sub-circuit 41, the second compensation sub-circuit 42, the light emitting control sub-circuit 50 and the potential holding sub-circuit 60 and the coupling method therebetween are the same as those in the aforementioned embodiment and will not be repeated here.

[0123] like Figure 8A 、 Figure 8D 、 Figure 9A and Figure 9D As shown, the first initialization sub-circuit 71 is coupled to the first reset signal terminal Rst1, the first initialization signal terminal Init1, and the first node N1. The first initialization sub-circuit 71 is configured to, in response to the first reset signal received at the first reset signal terminal Rst1, transmit the first initialization signal received at the first initialization signal terminal Init1 to the first node N1 to initialize the potential of the first node N1, that is, to pull the potential of the first node N1 low.

[0124] The first initialization sub-circuit 71 operates in the reset phase U1 before the compensation phase U2 of the image frame F, and resets the first node N1.

[0125] In the reset phase U1, the data voltage V of the first node N1 in the previous image frame is cleared by the first initialization signal. data , so that the potential of the first node N1 is initialized to avoid signal interference. The voltage of the first initialization signal can be selected according to actual conditions and is not limited here. For example, the first initialization signal is a low-level signal. For example, the first initialization signal is -3V.

[0126] like Figure 8B 、 Figure 8D 、 Figure 9B and Figure 9D As shown, the second initialization sub-circuit 72 is coupled to the second reset signal terminal Rst2, the second initialization signal terminal Init2, and the second node N2. The second initialization sub-circuit 72 is configured to, in response to the second reset signal received at the second reset signal terminal Rst2, transmit the second initialization signal received at the second initialization signal terminal Init2 to the second node N2 to initialize the potential of the second node N2, that is, to pull the potential of the second node N2 low.

[0127] The second initialization sub-circuit 72 operates in the reset phase U1 before the compensation phase U2 of the image frame F, and resets the second node N2.

[0128] In the reset phase U1, the voltage (V data +V DD +Vth-V SS -V oled_th ), so that the potential of the second node N2 is initialized to avoid signal interference. The voltage of the second initialization signal can be selected according to actual conditions and is not limited here. For example, the second initialization signal is a low-level signal. For example, the second initialization signal is -3V.

[0129] like Figure 8C 、 Figure 8D 、 Figure 9C and Figure 9D As shown, the third initialization sub-circuit 73 is coupled to the third reset signal terminal Rst3, the third initialization signal terminal Init3, and the first electrode of the light-emitting element L. The third initialization sub-circuit 73 is configured to, in response to the third reset signal received at the third reset signal terminal Rst3, transmit the third initialization signal received at the third initialization signal terminal Init3 to the first electrode of the light-emitting element L to initialize the potential of the first electrode of the light-emitting element L, that is, to pull the potential of the first electrode of the light-emitting element L down.

[0130] The third initialization sub-circuit 73 operates in the reset phase U1 before the compensation phase U2 of the image frame F, and resets the first electrode of the light-emitting element L.

[0131] In the reset stage U1, the voltage of the first electrode of the light-emitting element L is cleared by the third initialization sub-circuit 73, so that the potential of the first electrode of the light-emitting element L is initialized, thereby preventing the light-emitting element L from emitting light in a dark state due to the influence of the leakage current of the light-emitting control sub-circuit 50, thereby improving the display quality of the display device having the pixel circuit 101.

[0132] It should be noted that, in the compensation phase U2 after the reset phase U1, the second compensation sub-circuit 42 is turned on in response to the second control signal received at the second control signal terminal Q2, so that the line between the second node N2 and the third node N3 is also turned on. In this way, the first voltage V DD The charge at the first node N1 can be transferred to the second node N2 through the second compensation sub-circuit 42 and the driving sub-circuit 20, thereby increasing the potential of the second node N2. Due to the bootstrap effect of the storage sub-circuit 30, the potential of the first node N1 will be driven, that is, the potential of the first node N1 will be synchronously increased. Subsequently, the charge at the first node N1 will flow into the first electrode of the light-emitting element L through the first compensation sub-circuit 41, thereby compensating the threshold voltage V of the light-emitting element L. oled_th Finally, the voltage V N2 V DD +Vth, this voltage is not related to the potential of the second node N2 in the reset phase U1; the voltage V selected by the first node N1 in the stable state N1 V SS +V oled_th , which voltage is unrelated to the potential of the first node N1 during the reset phase U1.

[0133] That is to say, in the compensation phase U2, the charge of the first node N1 has been transferred to the first electrode of the light emitting element L before the stable state (that is, the threshold voltage V of the light emitting element L is compensated). oled_th ), therefore, in the compensation phase U2, the potential difference between the two ends of the storage sub-circuit 30 will not be maintained at the potential difference in the previous reset phase U1.

[0134] Based on the above analysis, it can be seen that whether the initialization signals from the various initialization signal terminals are identical or not does not affect the compensation phase U2. In other words, the initialization signals from the various initialization signal terminals can be identical. In this case, during the reset phase U1, the potentials of the first node N1 and the second node N2 are identical, and the potential difference across the storage sub-circuit 30 is zero. Alternatively, the initialization signals from the various initialization signal terminals can be different. In this case, during the reset phase U1, the potentials of the first node N1 and the second node N2 are different, and the potential difference across the storage sub-circuit 30 is non-zero. Neither of these two situations affects the compensation phase U2.

[0135] Furthermore, in some embodiments, Figure 8D and Figure 9D As shown, the pixel circuit 101 includes the first initialization sub-circuit 71, the second initialization sub-circuit 72, and the third initialization sub-circuit 73. These three initialization sub-circuits all operate during the reset phase of the image frame F. Therefore, the first initialization sub-circuit 71, the second initialization sub-circuit 72, and the third initialization sub-circuit 73 can be set to have the same conduction time to simplify the signal timing control process.

[0136] For example, the first reset signal terminal Rst1, the second reset signal terminal Rst2 and the third reset signal terminal Rst3 can be the same reset signal terminal RST, so that the first initialization sub-circuit 71, the second initialization sub-circuit 72 and the third initialization sub-circuit 73 can be turned on at the same time and have the same turn-on time. The reset signal terminal RST is coupled to a reset signal line L RST In this way, the number of signal lines in the display substrate 100 can be simplified, so that the display substrate 100 has a looser wiring space, so as to realize a higher resolution of the display device 200.

[0137] Furthermore, in some embodiments, when the pixel circuit 101 includes the first initialization sub-circuit 71, the second initialization sub-circuit 72, and the third initialization sub-circuit 73, the first initialization signal terminal Init1, the second initialization signal terminal Init2, and the third initialization signal terminal Init3 may be the same initialization signal terminal INIT, thereby eliminating the reference voltage terminal (Vref) in the pixel circuit provided by the related art, thereby simplifying the signal timing control process. The initialization signal terminal INIT is coupled to an initialization signal line L INIT In this way, the number of signal lines in the display substrate 100 can be simplified, so that the display substrate 100 has a looser wiring space, so as to realize a higher resolution of the display device 200.

[0138] In the pixel circuit 101 provided in the embodiment of the present disclosure, the specific implementation method of each sub-circuit is not limited to the method described above, and it can be any implementation method used, such as a conventional connection method well known to those skilled in the art. It is only necessary to ensure that each sub-circuit can realize the corresponding function. Circuits that can realize the functions of the above-mentioned pixel circuit 101, such as a circuit that can provide a driving current I to the light-emitting element L, are all within the protection scope of the present disclosure. Moreover, the above examples or embodiments cannot limit the protection scope of the present disclosure. In actual applications, technicians can choose to use or not use one or more of the above-mentioned sub-circuits according to the circumstances. Various combination variations based on the above-mentioned sub-circuits do not deviate from the principles of the present disclosure and will not be described in detail.

[0139] Figure 10 FIG. 1 is a circuit diagram of a pixel circuit according to some further embodiments. Figure 10 As shown, the specific structure of the pixel circuit 101 is as follows:

[0140] The driving sub-circuit 20 includes a driving transistor DT, a control electrode of the driving transistor DT coupled to the second node N2, a first electrode of the driving transistor DT coupled to the first voltage terminal V1, and a second electrode of the driving transistor DT coupled to the third node N3.

[0141] The first compensation subcircuit 41 includes a first transistor M1 , a control electrode of which is coupled to the first control signal terminal Q1 , a first electrode of which is coupled to the first node N1 , and a second electrode of which is coupled to the first electrode of the light emitting element L.

[0142] The second compensation sub-circuit 42 includes a second transistor M2 , a control electrode of the second transistor M2 coupled to the second control signal terminal Q2 , a first electrode of the second transistor M2 coupled to the third node N3 , and a second electrode of the second transistor M2 coupled to the second node N2 .

[0143] The first initialization sub-circuit 71 includes a third transistor M3 , a control electrode of which is coupled to the first reset signal terminal Rst1 , a first electrode of which is coupled to the first initialization signal terminal Init1 , and a second electrode of which is coupled to the first node N1 .

[0144] The second initialization sub-circuit 72 includes a fourth transistor M4 , a control electrode of which is coupled to the second reset signal terminal Rst2 , a first electrode of which is coupled to the second initialization signal terminal Init2 , and a second electrode of which is coupled to the second node N2 .

[0145] The third initialization subcircuit 73 includes a fifth transistor M5 , a control electrode of which is coupled to the third reset signal terminal Rst3 , a first electrode of which is coupled to the third initialization signal terminal Init3 , and a second electrode of which is coupled to the first electrode of the light emitting element L.

[0146] The data writing sub-circuit 10 includes a sixth transistor M6 , a control electrode of which is coupled to the scan signal terminal Scan, a first electrode of which is coupled to the data signal terminal Data, and a second electrode of which is coupled to the first node N1 .

[0147] The light emitting control subcircuit 50 includes a seventh transistor M7 , a control electrode of which is coupled to the enable signal terminal EM, a first electrode of which is coupled to the third node N3 , and a second electrode of which is coupled to the first electrode of the light emitting element L.

[0148] The potential holding sub-circuit 60 includes a first capacitor C1 , a first terminal of the first capacitor C1 is coupled to the first node N1 , and a second terminal of the first capacitor C1 is coupled to the first voltage terminal V1 .

[0149] The storage sub-circuit 30 includes a second capacitor C2 , a first terminal of the second capacitor C2 is coupled to the first node N1 , and a second terminal of the second capacitor C2 is coupled to the second node N2 .

[0150] Since the first capacitor C1 only needs to maintain the potential of the first node N1 and does not need to have a large capacitance, in some examples, the capacitance of the first capacitor C1 may be smaller than the capacitance of the second capacitor C2 .

[0151] Thus, the pixel circuit 101 provided in some embodiments has an "8T2C" structure. Here, "T" represents a transistor, and the number preceding it represents the number of transistors in the pixel circuit 101; "C" represents a capacitor, and the number preceding it represents the number of capacitors in the pixel circuit 101. Except for the driving transistor DT, the remaining transistors are switching transistors.

[0152] Figure 11 FIG. 1 is a circuit diagram of a pixel circuit according to some further embodiments. Figure 11 As shown, in the pixel circuit 101, the first control signal terminal Q1 coupled to the first compensation sub-circuit 41 and the second control signal terminal Q2 coupled to the second compensation sub-circuit 42 can be the same control signal terminal Q. In this way, the first control signal received at the first control signal terminal Q1 and the second control signal received at the second control signal terminal Q2 are the same control signal V Q .

[0153] Similarly, the first reset signal terminal Rst1 coupled to the first initialization sub-circuit 71, the second reset signal terminal Rst2 coupled to the second initialization sub-circuit 72, and the third reset signal terminal Rst3 coupled to the third initialization sub-circuit 73 can be the same reset signal terminal RST. In this way, the first reset signal received at the first reset signal terminal Rst1, the second reset signal received at the second reset signal terminal Rst2, and the third reset signal received at the third reset signal terminal Rst3 are the same reset signal Rst.

[0154] Similarly, the first initialization signal terminal Init1 coupled to the first initialization sub-circuit 71, the second initialization signal terminal Init2 coupled to the second initialization sub-circuit 72, and the third initialization signal terminal Init3 coupled to the third initialization sub-circuit 73 can be the same initialization signal terminal INIT. In this way, the first initialization signal received at the first initialization signal terminal Init1, the second initialization signal received at the second initialization signal terminal Init2, and the third initialization signal received at the third initialization sub-circuit 73 are the same initialization signal Vint.

[0155] In this way, the number of signal lines in the display substrate 100 can be significantly reduced, so that the display substrate 100 has a looser wiring space, so as to realize a higher resolution of the display device 200.

[0156] Figure 11 The specific structure and mutual connection relationship of each sub-circuit in the pixel circuit 101 shown in FIG. Figure 10 The description of the pixel circuit 101 is not repeated here.

[0157] In the pixel circuit 101 provided in the above embodiment, each transistor may be a thin film transistor (TFT), a field effect transistor (FET) or other switching devices with the same characteristics, which is not limited in the embodiment of the present disclosure.

[0158] In some embodiments, the control electrode of each transistor in the pixel circuit 101 is the gate of the transistor, the first electrode is one of the source and drain of the transistor, and the second electrode is the other of the source and drain of the transistor. Since the source and drain of the same transistor can be symmetrical in structure, the source and drain can be structurally the same. In other words, the first electrode and the second electrode of the transistor in the embodiments of the present disclosure can be structurally the same.

[0159] Exemplarily, when the transistor is a P-type transistor, such as a Positive channel Metal Oxide Semiconductor (PMOS), the first electrode of the transistor is a source electrode, and the second electrode is a drain electrode. Exemplarily, when the transistor is an N-type transistor, such as a Negative channel Metal Oxide Semiconductor (NMOS), the first electrode of the transistor is a drain electrode, and the second electrode is a source electrode.

[0160] In some embodiments, as Figure 10 and Figure 11 As shown, the transistors in the above pixel circuit 101 are all P-type transistors, for example, all are PMOS, that is, each transistor is turned on in response to a low-level signal received on its control electrode, that is, the condition for turning on each transistor is that the effective level signal is a low-level signal.

[0161] Figure 12 for Figure 11 The following uses the example of each transistor in the pixel circuit 101 being a P-type transistor to illustrate the working conditions of a pixel circuit 101 at different stages within an image frame F.

[0162] Table 1 shows the voltage V of the first node N1 in different stages. N1 and the voltage V at the second node N2 N2 , and the working states of the pixel circuit 101 at different stages.

[0163] Table 1

[0164]

[0165] Figure 13A for Figure 11 The working state diagram of the pixel circuit in the reset phase is shown in FIG. Figure 12 and Figure 13A As shown, in the reset phase U1 of the image frame F, the reset signal Rst provided by the reset signal terminal RST is a low-level signal, and the third transistor M3, the fourth transistor M4 and the fifth transistor M5 are turned on at the same time.

[0166] The initialization signal Vint provided by the initialization signal terminal INIT is a low level signal. The third transistor M3 transmits the initialization signal Vint to the first node N1 (the transmission path is as shown in FIG. 1 ). Figure 13AThe first transistor M2 transmits the initialization signal Vint to the second node N2 (the transmission path is shown in FIG. 1 ). Figure 13A The fifth transistor M5 transmits the initialization signal Vint to the first electrode of the light emitting element L (the transmission path is shown in FIG. Figure 13A (as indicated by the dotted arrow c) to initialize the first electrode of the light-emitting element L.

[0167] Thus, in the reset phase U1 , the first node N1 , the second node N2 , the first electrode of the light emitting element L, the first capacitor C1 , and the second capacitor C2 are all reset.

[0168] Figure 13B for Figure 11 The working state diagram of the pixel circuit in the compensation stage is shown in FIG. Figure 12 and Figure 13B As shown, when entering the compensation phase U2 of the image frame F, due to the voltage V N2 The Vint state is still maintained, so that the driving transistor DT is turned on. In the compensation stage U2, the control signal V provided by the control signal terminal Q Q = is a low level signal, the first transistor M1 and the second transistor M2 are turned on at the same time. Since the second transistor M2 is turned on, the line between the second node N2 and the third node N3 is connected, that is, the line between the control electrode and the second electrode of the driving transistor DT is connected, so that the driving transistor DT is transformed into a diode connection state in the compensation phase U2. In this way, the first voltage V from the first voltage terminal V1 is DD The signal is transmitted to the second node N2 through the turned-on driving transistor DT and the second transistor M2 (the transmission path is as shown in FIG. Figure 13B As shown by the dotted arrow d in the middle, the potential of the second node N2 increases. Due to the bootstrap effect of the second capacitor C2 coupled between the second node N2 and the first node N1, the potential of the first node N1 is driven and increases accordingly (as shown in the dotted arrow d in the middle). Figure 13B Then, the charge of the first node N1 flows into the first electrode of the light emitting element L through the first transistor M1 (the transmission path is shown as Figure 13B As shown by the dotted arrow f), the threshold voltage V oled_th .

[0169] Finally, the voltage V of the second node N2 in the stable state N2 V DD +Vth, the voltage V of the first node N1 in the stable state N1 V SS+V oled_th .

[0170] Figure 13C for Figure 11 The working state diagram of the pixel circuit in the writing phase is shown in FIG. Figure 12 and Figure 13C As shown, in the writing phase U3 of the image frame F, the scanning signal S provided by the scanning signal terminal Scan is a low level signal, the sixth transistor M6 is turned on, and the data signal V received at the data signal terminal Data is turned on. data Write to the first node N1 (transmission path as Figure 13C As shown by the dotted arrow g), the voltage V N1 Directly changes to V data Due to the bootstrap effect of the second capacitor C2, the potential of the second node N2 also changes accordingly (eg Figure 13C As shown by the dotted arrow h), eventually, the voltage V N2 Stable to V data +V DD +Vth-V SS -V oled_th .

[0171] Figure 13D for Figure 11 The working state diagram of the pixel circuit in the light-emitting stage is shown in FIG. Figure 12 and Figure 13D As shown, in the light emitting stage U4 of the image frame F, the voltages of the first node N1 and the second node N2 are the same as those in the compensation stage U2. The enable signal Em provided by the enable signal terminal EM is a low level signal, and the seventh transistor M7 is turned on. In this way, the first voltage V DD After the transmission of the driving transistor DT, the driving current generated by the driving transistor DT is I=1 / 2·μ·C ox ·W / L·(V SS +V oled_th -V data ) 2 , the driving current I is transmitted to the light emitting element L through the seventh transistor M7 (the transmission path is as follows Figure 13D The light emitting element L is driven to emit light (as indicated by the dotted arrow i).

[0172] As the use time of the light emitting element L increases, the threshold voltage V oled_th The Vgs of the driving transistor DT is increased, that is, the absolute value of the Vgs of the driving transistor DT is increased (since the Vgs of the P-type transistor is a negative voltage, usually -5V to -10V, it can also be understood as a decrease in Vgs, that is, Vgs is more negative), thereby driving the driving current I flowing through the light-emitting element L to increase accordingly.

[0173] Figure 14 The following is a feedback principle diagram of two pixel circuits provided by a technical solution. Figure 14 As shown, the data signal terminal Data is coupled to the positive terminal of an amplifier (AMP) formed by the transistors in the pixel circuit, the power supply voltage terminal VDD and the first terminal of the light-emitting element L are coupled to the two negative terminals of the amplifier AMP. The second terminal of the light-emitting element L is coupled to the reference voltage terminal VSS.

[0174] like Figure 14 As shown in (a), in a feedback mode of a pixel circuit, in order to feed back the voltage on the surface of the first electrode (usually the anode) of the light-emitting element L to the pixel circuit for compensation, the method adopted is to feed back the voltage to the data signal V provided by the data signal terminal Data. data superior.

[0175] like Figure 14 As shown in (b), in another feedback mode of the pixel circuit, in order to feed back the voltage on the surface of the first electrode (usually the anode) of the light-emitting element L to the pixel circuit for compensation, the method adopted is to feed back the voltage to the voltage V provided by the power supply voltage terminal VDD. DD superior.

[0176] Since the voltage V provided by the power supply voltage terminal VDD DD As a DC voltage, it cannot form feedback. Figure 14 The feedback principle shown in (a) of FIG. 1 is that the compensation principle adopted by the pixel circuit 101 provided in the embodiment of the present disclosure is to feed back the voltage on the first surface of the light-emitting element L to the data signal V data superior.

[0177] Figure 15 The figure is a comparison diagram of the feedback principle of the pixel circuit provided according to some embodiments and the feedback principle of the pixel circuit provided by a technical solution. Figure 15 As shown, the data signal terminal Data is coupled to the positive electrode of an amplifier (AMP) formed by the transistors in the pixel circuit, and the power supply voltage terminal VDD (i.e., the first voltage terminal V1 in the embodiment of the present disclosure) and the first electrode of the light-emitting element L are coupled to the two negative electrodes of the amplifier AMP. The second electrode of the light-emitting element L is coupled to the reference voltage terminal VSS (i.e., the second voltage terminal V2 in the embodiment of the present disclosure).

[0178] Feedback can be divided into the following ways: Figure 15 The first feedback shown in (a) and Figure 15 The second feedback is shown in (b).

[0179] In the first feedback mode, the capacitor C for storing voltage is coupled between the data signal terminal Data and the first electrode of the light-emitting element L. The voltage on the surface of the first electrode of the light-emitting element L is fed back to the data signal V provided by the data signal terminal Data during the light-emitting phase. data The feedback path is as follows Figure 15 As shown by the dotted arrow in (a) of FIG. When the transistors in the pixel circuit are primarily P-type transistors (e.g., PMOS), the amplifier AMP formed by these transistors is an inverting amplifier circuit. When the voltage on the first electrode surface of the light-emitting element L is a positive voltage, negative feedback will eventually occur. That is, the voltage of the amplifier AMP decreases, resulting in a decrease in the current flowing through the light-emitting element L. This fails to improve the low brightness of the light-emitting element L due to aging.

[0180] The pixel circuit 101 provided in the embodiment of the present disclosure adopts the second feedback mode, namely: Figure 15 As shown by the dotted arrow ① in (b), the voltage on the first surface of the light-emitting element L is first written to the second capacitor C2; Figure 15 As shown by the dotted arrow ② in (b), the voltage on the first surface of the light-emitting element L is connected to the V data The voltage is written to the control electrode of the driving transistor DT.

[0181] In this way, the pixel circuit 101 provided by the embodiment of the present disclosure first feeds back the voltage on the first surface of the light emitting element L to the second capacitor C2, and then uses the bootstrap effect of the capacitor to feed back the voltage on the first surface of the light emitting element L to the second capacitor C2. data and V oled_th At the same time, the control electrode of the driving transistor DT is written, and a positive feedback circuit is finally formed, thereby increasing the current flowing through the light-emitting element L and achieving a compensation effect on the service life of the light-emitting element L.

[0182] Figure 16 for Figure 11 Schematic diagram of the simulation model of the pixel circuit shown. Figure 17 for Figure 11 Schematic diagram of simulation signals of the pixel circuit shown.

[0183] exist Figure 16 The first voltage terminal V1 provides a first voltage V DD is 4.6V, and the second voltage V provided by the second voltage terminal V2 SS The data signal V provided by the data signal terminal Data is -3V. dataThe initialization signal Vint provided by the initialization signal terminal INIT is -4V, the capacitance of the first capacitor C1 is 0.05 pF, the capacitance of the second capacitor C2 is 0.1 pF, each transistor is PMOS, the threshold voltage Vth of the driving transistor DT is set to -2V, and the threshold voltage V oled_th It is set to 0.4V at the beginning of use.

[0184] like Figure 17 As shown, during the simulation, in the reset phase U1, the potentials of the first node N1 and the second node N2 are both -3V (i.e., equal to the voltage of the initialization signal Vint). In the compensation phase U2, the voltage V N2 is 2.6V, which is equal to V DD +Vth (ie 4.6V+(-2V)), the voltage of the first node N1 V N is -2.6V, which is equal to V SS +V oled_th (ie, -3V+0.4V). In the writing phase U3, the voltages of the first node N1 and the second node N2 drop simultaneously.

[0185] Obviously, through the above simulation process, the respective potentials of the first node N1 and the second node N2 in the reset stage U1, the compensation stage U2 and the writing stage U3 are verified, which fully demonstrates that the above pixel circuit 101 provided by the embodiment of the present disclosure realizes compensation for the driving current I flowing through the light-emitting element L, thereby extending the service life of the light-emitting element L.

[0186] Figure 18 FIG is a structural diagram of a display substrate according to some other embodiments. Figure 18 As shown, the display substrate 100 includes a plurality of sub-pixels P disposed in the AA area, and each sub-pixel P includes a pixel circuit 101. When the plurality of sub-pixels P are arranged in an array, the pixel circuits 101 arranged in a row along the X direction are referred to as pixel circuits 101 in the same row, and the pixel circuits 101 arranged in a row along the Y direction are referred to as pixel circuits 101 in the same column.

[0187] In this case, the initialization signal terminals INIT of the pixel circuits 101 in the same row may be coupled to the same initialization signal line L extending along the X direction (or substantially extending along the X direction). INIT The reset signal terminals RST of the pixel circuits 101 in the same row can be coupled to the same reset signal line L extending along the X direction (or substantially extending along the X direction). RST The control signal terminals Q of the pixel circuits 101 in the same row can be coupled to the same control signal line L extending along the X direction (or substantially extending along the X direction). QThe scan signal terminals Scan of the pixel circuits 101 in the same row can be coupled to the same scan signal line SL extending along the X direction (or substantially extending along the X direction), and the enable signal terminals EM of the pixel circuits 101 in the same row can be coupled to the same enable signal line L extending along the X direction (or substantially extending along the X direction). EM .

[0188] Similarly, the data signal terminal Data of the pixel circuits 101 in the same column can be coupled to the same data signal line DL extending along the Y direction (or substantially extending along the Y direction), and the first voltage terminal V1 of the pixel circuits 101 in the same column can be coupled to the same first power line L extending along the Y direction (or substantially extending along the Y direction). V1 The second voltage terminal V2 of the pixel circuits 101 in the same column can be coupled to the same second power line L extending along the Y direction (or substantially extending along the Y direction). V2 .

[0189] In this way, when the plurality of pixel circuits 101 are arranged in an array, the display substrate 100 can have a relatively loose wiring space, so as to realize a display device 200 with a higher resolution.

[0190] In some examples, the display substrate 100 further includes a scan driving circuit located in the peripheral area W. The scan driving circuit can be connected to the initialization signal line L INIT , reset signal line L RST , control signal line L Q , scan signal line SL and enable signal line L EM The initialization signal Vint, the reset signal Rst, and the control signal V are respectively transmitted to the pixel circuit 101 through these signal lines. Q , scan signal S and enable signal Em.

[0191] Exemplarily, the scan driving circuit is a GOA (Gate Driver on Array) driving circuit.

[0192] In some other examples, the display substrate 100 further includes a plurality of scan driving circuits located in the peripheral area W. A portion of the plurality of scan driving circuits is located at one of the two opposite sides of the display area AA, and another portion is located at the other of the two opposite sides of the display area AA. The plurality of scan driving circuits may be connected to the initialization signal line L. INIT , reset signal line L RST , control signal line L Q , scan signal line SL and enable signal line L EM The initialization signal Vint, the reset signal Rst, and the control signal V are respectively transmitted to the pixel circuit 101 through these signal lines.Q , scan signal S and enable signal Em.

[0193] Exemplarily, each scan driving circuit is a GOA (Gate Driver on Array, array substrate row driving) driving circuit.

[0194] The embodiments of the present disclosure do not limit the specific structure of the scan driving circuit (eg, GOA), as long as it can transmit corresponding signals to the pixel circuit 101 .

[0195] Figure 19 FIG. 1 is a schematic diagram of a layout of a display substrate according to some embodiments. 20A to 20D for Figure 19 Schematic diagram of the layout of each layer.

[0196] Figure 19 The display substrate 100 shown schematically has the following Figure 11 The pixel circuit 101 is shown.

[0197] It should be noted that for the sake of illustration, Figure 19 Only one pixel circuit 101 located on the substrate 100 a and the portion of each signal line passing through the area where the pixel circuit 101 is located (ie, the sub-pixel area) are illustrated, and the remaining pixel circuits 101 and the complete signal lines are not illustrated.

[0198] like Figure 20A As shown, a semiconductor layer Act is formed on a substrate 100a. For example, a polycrystalline silicon (p-Si) film can be formed by a chemical vapor deposition (CVD) process, and the polycrystalline silicon film is subjected to a first patterning process to form a semiconductor layer Act located in each sub-pixel region.

[0199] A gate insulating layer is formed on the substrate 100a to cover the semiconductor layer Act. Exemplarily, the gate insulating layer is made of at least one insulating material selected from silicon nitride, silicon oxide, and silicon oxynitride by a CVD process.

[0200] like Figure 20B As shown, in the gate insulating layer ( Figure 20B For example, a metal film made of copper (Cu) and aluminum (Al) may be formed by sputtering, and the metal film may be subjected to a second patterning process to form the first conductor layer G1 in each sub-pixel region.

[0201] In the same sub-pixel region, the overlapping portion of the orthographic projection of the first conductive layer G1 on the substrate 100 a and the orthographic projection of the semiconductor layer Act on the substrate 100 a forms the control electrode of each transistor.

[0202] That is, the first conductive layer G1 includes: a control electrode DTg of the driving transistor DT, a control electrode M1g of the first transistor M1, a control electrode M2g of the second transistor M2, a control electrode M3g of the third transistor M3, a control electrode M4g of the fourth transistor M4, a control electrode M5g of the fifth transistor M5, a control electrode M6g of the sixth transistor M6, and a control electrode M7g of the seventh transistor M7.

[0203] Since the second end of the second capacitor C2 and the control electrode DTg of the driving transistor DT are both coupled to the second node N2, that is, the second end of the second capacitor C2 and the control electrode DTg of the driving transistor DT are coupled together, therefore, the control electrode DTg of the driving transistor DT can be reused as a second conductor pattern R2 as the second end of the second capacitor C2 (that is, the lower electrode plate of the second capacitor C2) to simplify the layout of the pixel circuit 101.

[0204] The first conductor layer G1 further includes a first conductor pattern R1 that is not connected to the second conductor pattern R2 . The first conductor pattern R1 is the second end of the first capacitor C1 (ie, the lower electrode plate of the first capacitor C1 ).

[0205] The first conductor layer G1 further includes: a reset signal line L RST The portion passing through the sub-pixel region, the control signal line L Q The portion passing through the sub-pixel area, the portion of the scan signal line SL passing through the sub-pixel area, and the portion of the enable signal line L EM The portion passing through the sub-pixel area.

[0206] Reset signal line L RST It is connected to the control electrode M3g of the third transistor M3, the control electrode M4g of the fourth transistor M4, and the control electrode M5g of the fifth transistor M5 to form an integrated structure.

[0207] Control signal line L Q It is connected to the control electrode M1g of the first transistor M1 and the control electrode M2g of the second transistor M2 to form an integrated structure.

[0208] The scan signal line SL and the control electrode M6g of the sixth transistor M6 are connected to form an integrated structure.

[0209] Enable signal line L EM It is connected to the control electrode M7g of the seventh transistor M7 to form an integrated structure.

[0210] The overlapping portion of the orthographic projection of the semiconductor layer Act on the substrate 100 a and the orthographic projection of the control electrode of each transistor on the substrate 100 a forms the active layer of the corresponding transistor (ie, the channel region when the transistor is turned on).

[0211] Using the first conductive layer G1 as a mask, ion implantation is performed on the regions of the semiconductor layer Act excluding the active layers (i.e., the regions of the semiconductor layer Act not covered by the first conductive layer G1), thereby converting these regions into conductors. This converted region Act-a can serve as the first or second electrode of each transistor, or as part of the first or second electrode of each transistor. The first and second electrodes of each transistor will be described in detail later.

[0212] It should be noted that although a gate insulating layer is provided between the semiconductor layer Act and the first conductive layer G1, by controlling the parameters of ion injection (such as the speed of ion injection), ions can still pass through the gate insulating layer and enter the area of ​​the semiconductor layer Act that is not covered by the first conductive layer G1, thereby conducting the area.

[0213] A first interlayer insulating layer covering the above structures is formed on the substrate 100a. Exemplarily, the first interlayer insulating layer is made of at least one insulating material selected from silicon nitride, silicon oxide, and silicon oxynitride by a CVD process.

[0214] like Figure 20C As shown, in the first interlayer insulating layer ( Figure 20C For example, a metal film made of copper (Cu) and aluminum (Al) may be formed by sputtering, and the metal film may be subjected to a third patterning process to form the second conductor layer G2 in each sub-pixel region.

[0215] The second conductor layer G2 includes a third conductor pattern R3. The orthographic projection of the third conductor pattern R3 on the substrate 100a overlaps with the orthographic projection of the first conductor pattern R1 in the first conductor layer G1 on the substrate 100a, thereby forming a first capacitor C1. The orthographic projection of the third conductor pattern R3 on the substrate 100a overlaps with the orthographic projection of the second conductor pattern R2 on the substrate 100a, thereby forming a second capacitor C2.

[0216] Since the first end of the first capacitor C1 and the first end of the second capacitor C2 are both coupled to the first node N1, that is, the first end of the first capacitor C1 and the first end of the second capacitor C2 are coupled together, the first end of the first capacitor C1 (that is, the upper electrode plate of the first capacitor C1) and the first end of the second capacitor C2 (that is, the upper electrode plate of the second capacitor C2) can be connected into an integrated structure to simplify the layout of the pixel circuit 101.

[0217] In other examples, the first end of the first capacitor C1 and the first end of the second capacitor C2 may be two independent electrode plates, which is not limited in the embodiments of the present disclosure.

[0218] The third conductor pattern R3 has an opening O, and the orthographic projection of the opening O on the substrate 100a has an overlapping area with the orthographic projection of the second conductor pattern R2 below on the substrate 100a, so as to facilitate the coupling of the second electrode of the subsequently formed fourth transistor M4 and the second end of the second capacitor C2. The specific coupling method will be described in detail in the subsequent description.

[0219] The second conductor layer G2 further includes an initialization signal line L which is not connected to the third conductor pattern R3. INIT .

[0220] A second interlayer insulating layer covering the above structures is formed on the substrate 100a. Exemplarily, the second interlayer insulating layer is made of at least one insulating material selected from silicon nitride, silicon oxide, and silicon oxynitride by a CVD process.

[0221] like Figure 20D As shown, in the second interlayer insulating layer ( Figure 20D A third conductive layer SD is formed on the substrate (not shown). For example, a metal thin film made of copper (Cu) and aluminum (Al) can be formed by sputtering, and the metal thin film is subjected to a fourth patterning process to form the third conductive layer SD located in each sub-pixel region.

[0222] The third conductor layer SD includes a first connection pattern SD-1, a second connection pattern SD-2, a third connection pattern SD-3, a fourth connection pattern SD-4, a fifth connection pattern SD-5, a sixth connection pattern SD-6, a seventh connection pattern SD-7, an eighth connection pattern SD-8, a ninth connection pattern SD-9, a data signal line DL, and a first power line L. V1 and the second power line L V2 ( Figure 20D not shown).

[0223] like Figure 19 and Figure 20D As shown, the above-mentioned connection patterns and the coupling relationship between each connection pattern and the corresponding circuit structure will be specifically described below.

[0224] The first electrode DT- 1 and the second electrode DT- 2 of the driving transistor DT are portions of the conductive region Act-a located on both sides of the control electrode DTg of the driving transistor.

[0225] First power line L V1 The first electrode DT-1 of the driving transistor DT is connected to the first electrode DT-1 through the via H15 penetrating the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer. In this way, the coupling between the first electrode DT-1 of the driving transistor DT and the first voltage terminal V1 is achieved (the first voltage terminal V1 is coupled to the first power line LV1). In addition, the first power line L V1 The first conductor pattern R1 (i.e., the second end of the first capacitor C1) is also connected to the first conductor pattern R1 (i.e., the second end of the first capacitor C1) through the via H16 that penetrates the first interlayer insulating layer and the second interlayer insulating layer. In this way, the coupling between the second end of the first capacitor C1 and the first voltage terminal V1 (the first voltage terminal V1 is coupled to the first power line L1) is achieved. V1 ).

[0226] The first electrode M6 - 1 and the second electrode M6 - 2 of the sixth transistor M6 are portions located on both sides of the control electrode M6 g of the sixth transistor M6 in the conductive region Act-a.

[0227] The first connection pattern SD-1 is connected to the data signal line DL as an integral structure. Furthermore, the first connection pattern SD-1 is connected to the first electrode M6-1 of the sixth transistor M6 via a via H13 that penetrates the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer. In this way, coupling is achieved between the first electrode M6-1 of the sixth transistor M6 and the data signal terminal Data (the data signal terminal Data is coupled to the data signal line DL).

[0228] The second connection pattern SD-2 is connected to the second electrode M6-2 of the sixth transistor M6 via a via H12 that penetrates the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer. Furthermore, the second connection pattern SD-2 is connected to the third conductor pattern R3 (i.e., the first end of the first capacitor C1 and the first end of the second capacitor C2) via a via H11 that penetrates the second interlayer insulating layer. In this way, coupling is achieved between the second electrode M6-2 of the sixth transistor M6 and the first end of the first capacitor C1 and the first end of the second capacitor C2.

[0229] The first electrode M7 - 1 and the second electrode M7 - 2 of the seventh transistor M7 are portions located on both sides of the control electrode M7 g of the seventh transistor M7 in the conductive region Act-a.

[0230] The first electrode M1 - 1 and the second electrode M1 - 2 of the first transistor M1 are portions of the conductive region Act-a located on both sides of the control electrode M1 g of the first transistor M1 .

[0231] The third connection pattern SD-3 is connected to the second electrode M7-2 of the seventh transistor M7 through a via hole H14 that penetrates the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer. Furthermore, the third connection pattern SD-3 is connected to the second electrode M1-2 of the first transistor M1 through a via hole H19 that penetrates the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer. In this way, coupling is achieved between the second electrode M7-2 of the seventh transistor M7 and the second electrode M1-2 of the first transistor M1.

[0232] The first electrode M5 - 1 and the second electrode M5 - 2 of the fifth transistor M5 are portions located on both sides of the control electrode M5 g of the fifth transistor M5 in the conductive region Act-a.

[0233] The fourth connection pattern SD-4 is connected to the initialization signal line L through the via hole H17 penetrating the second interlayer insulating layer. INIT Furthermore, the fourth connection pattern SD-4 is further connected to the first electrode M5-1 of the fifth transistor M5 through a via H18 penetrating the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer. In this way, the coupling between the first electrode M5-1 of the fifth transistor M5 and the initialization signal terminal INIT is achieved (the initialization signal terminal INIT is coupled to the initialization signal line L INIT ).

[0234] The first electrode M3 - 1 and the second electrode M3 - 2 of the third transistor M3 are portions located on both sides of the control electrode M3 g of the third transistor M3 in the conductive region Act-a.

[0235] The fifth connection pattern SD-5 is connected to the initialization signal line L through the via hole H7 penetrating the second interlayer insulating layer. INIT Furthermore, the fifth connection pattern SD-5 is further connected to the first electrode M3-1 of the third transistor M3 through a via H8 penetrating the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer. In this way, the coupling between the first electrode M3-1 of the third transistor M3 and the initialization signal terminal INIT is achieved (the initialization signal terminal INIT is coupled to the initialization signal line L INIT ).

[0236] The first electrode M4 - 1 and the second electrode M4 - 2 of the fourth transistor M4 are portions located on both sides of the control electrode M4 g of the fourth transistor M4 in the conductive region Act-a.

[0237] The sixth connection pattern SD-6 is connected to the initialization signal line L through the via hole H1 penetrating the second interlayer insulating layer. INITFurthermore, the sixth connection pattern SD-6 is further connected to the first electrode M4-1 of the fourth transistor M4 through a via H2 penetrating the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer. In this way, the coupling between the first electrode M4-1 of the fourth transistor M4 and the initialization signal terminal INIT is achieved (the initialization signal terminal INIT is coupled to the initialization signal line L INIT ).

[0238] The seventh connection pattern SD-7 is connected to the second electrode M4-2 of the fourth transistor M4 via a via H3 that penetrates the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer. Furthermore, the seventh connection pattern SD-7 is connected to the second conductor pattern R2 (the second end of the second capacitor C2) via a via H4 that penetrates the first interlayer insulating layer and the second interlayer insulating layer. This achieves coupling between the second electrode M4-2 of the fourth transistor M4 and the second end of the second capacitor C2. The orthographic projection of the via H4 on the substrate 100a is within the orthographic projection of the opening O of the third conductor pattern R3 on the substrate 100a, preventing the seventh connection pattern SD-7 from contacting the third conductor pattern R3 and causing signal confusion.

[0239] The first electrode M2 ​​- 1 and the second electrode M2 ​​- 2 of the second transistor M2 are portions of the conductive region Act-a located on both sides of the control electrode M2 ​​g of the second transistor M2 .

[0240] The eighth connection pattern SD-8 is connected to the second electrode M3-2 of the third transistor M3 via a via H9 that penetrates the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer. The eighth connection pattern SD-8 is also connected to the first electrode M1-1 of the first transistor M1 via a via H20 that penetrates the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer. Furthermore, the eighth connection pattern SD-8 is also connected to the third conductor pattern R3 (i.e., the first end of the second capacitor C2 and the first end of the first capacitor C1) via a via H10 that penetrates the second interlayer insulating layer. In this way, coupling is achieved between the second electrode M3-2 of the third transistor M3, the first electrode M1-1 of the first transistor M1, the first end of the second capacitor C2, and the first end of the first capacitor C1.

[0241] Furthermore, to avoid forming a control electrode outside the required "8T2C" structure in the pixel circuit 101, the orthographic projection of the scan signal line SL on the substrate 100a does not overlap with the orthographic projection of the semiconductor layer Act on the substrate 100a. Therefore, when forming the scan signal line SL, disconnected portions of the scan signal line SL may exist. Therefore, the third conductor layer SD further includes a ninth connection pattern SD-9. The ninth connection pattern SD-9 is connected to the scan signal line SL via a via H5 penetrating the first and second interlayer insulating layers, and a via H6 penetrating the first and second interlayer insulating layers. This couples the disconnected portions of the scan signal line SL together, enabling the scan signal line SL to transmit scan signals.

[0242] exist Figure 19 A flat layer (usually made of an organic insulating material, Figure 19 (not shown in the figure), the light emitting element L coupled to the above-mentioned pixel circuit 101 can be formed on the flat layer.

[0243] The light-emitting element L is, for example, a top-emitting OLED, that is, it emits light upward relative to the substrate 100a, and the emitted light does not pass through the substrate 100a. The first electrode (e.g., the anode) of the OLED is connected to the second electrode M7-2 of the seventh transistor M7 via a via hole penetrating the planar layer. The position of the via hole in the planar layer corresponds to the aforementioned via hole H14, that is, in a direction away from the substrate 100a, the via hole H14 is located below, and the via hole in the planar layer for connecting the first electrode of the OLED to the second electrode M7-2 of the seventh transistor M7 is located above the via hole H14.

[0244] An OLED includes a light-emitting layer and a second electrode positioned sequentially away from a first electrode. When the first electrode is an anode, the second electrode is a cathode. In this case, in some examples, the OLED may further include a hole transport layer and / or a hole injection layer between the light-emitting layer and the first electrode; in some examples, the OLED may further include an electron transport layer and / or an electron injection layer between the light-emitting layer and the second electrode.

[0245] In some examples, the display substrate 100 includes multiple pixel circuits 101 , and the second electrodes of the light-emitting elements L coupled to the multiple pixel circuits 101 can be connected into an integrated structure, that is, forming an electrode layer, to simplify the structure of the display substrate 100 .

[0246] It should be noted that due to limited space, Figure 19 The light emitting element L is not shown.

[0247] It should be understood that when describing the coupling relationship between the above structures, the description of "a certain structure is connected to another structure through a via penetrating one or more insulating layers" is used. In this description, the orthographic projection of the one structure on the substrate 100a must have an overlapping area with the orthographic projection of the other structure on the substrate 100a, so as to achieve direct contact, i.e., connection, between the one structure located above and the other structure through the via.

[0248] It should be noted that the "composition process" mentioned in the above embodiments can be a process of processing a film layer (a thin film or a multi-layer thin film) to form a process having one or more specific patterns. A typical composition process is to use a mask (Mask) to expose part of the photoresist covering the film layer, develop the exposed part of the photoresist, etch the part of the film layer exposed by the photoresist, remove the remaining photoresist, and finally obtain the desired pattern.

[0249] In some embodiments, as Figure 3 As shown, the display device 200 provided in an embodiment of the present disclosure further includes a driver chip 210. The driver chip 210 is coupled to the display substrate 100. The driver chip 210 is configured to provide the pixel circuit 101 in the display substrate 100 with a signal required to drive the pixel circuit 101. For example, the driver chip 210 is a driver integrated circuit (Driver IC).

[0250] For example, the driver chip 210 may provide an initialization signal Vint, a reset signal Rst, a control signal V Q , scan signal S, enable signal Em, data signal Vdata, first voltage V DD and the second voltage V SS etc. are signals required to drive the pixel circuit 101. In addition, the embodiment of the present disclosure does not limit the number of driving chips in the display device 200, as long as they can provide the signals required to drive the pixel circuit 101.

[0251] In some examples, the display device 200 further includes a thin film encapsulation layer or an encapsulation substrate disposed on the display substrate 100 to isolate the light-emitting element L in the display substrate 100 from water vapor and oxygen in the external environment.

[0252] In some examples, the light emitted by the light-emitting element L in the display substrate 100 is white light. In this case, the display device 200 further includes a color filter substrate disposed on the light-emitting side of the display substrate 100 to enable the display device to display a color image. The light conversion layer in the color filter substrate can be a color filter layer and / or a quantum dot light-emitting layer, which is not limited in the embodiments of the present disclosure.

[0253] Figure 21 FIG. 1 is a flow chart of a driving method for a pixel circuit according to some embodiments. The driving method is applied to the aforementioned pixel circuit 101, and the specific structure of the pixel circuit 101 is not described here in detail. Figure 21 As shown, the driving method includes steps S2-S4.

[0254] S2, in the compensation phase U2 of an image frame F, the second compensation sub-circuit 42 responds to the second control signal received at the second control signal terminal Q2 to reduce the first voltage V from the first voltage terminal V1 to DD The threshold voltage Vth of the driving sub-circuit 20 is transmitted to the second node N2; the first compensation sub-circuit 41 receives the first control signal at the first control signal terminal Q1 and converts the second voltage V from the second voltage terminal V2 into SS and the threshold voltage V of the light-emitting element L oled_th Transmitted to the first node N1.

[0255] Thus, in the compensation phase U2, the voltage V N2 =V DD +Vth, the voltage of the first node N1 V N1 =V SS +V oled_th .

[0256] S3, in the writing phase U3 of the image frame F, the data writing sub-circuit 10 responds to the scanning signal received at the scanning signal terminal Scan and writes the data signal V received at the data signal terminal Data to the data signal terminal Data. data Write to the first node N1.

[0257] S4. In the light-emitting stage U4 of the image frame F, the driving sub-circuit 20 is turned on in response to the voltage of the second node N2, generating a driving current I; the light-emitting control sub-circuit 50 responds to the enable signal received at the enable signal terminal EM, and outputs the driving current I transmitted to the third node N3 to the light-emitting element L, so as to drive the light-emitting element L to emit light.

[0258] The driving current I=1 / 2·μ·C ox ·W / L·(V SS +V oled_th -V data ) 2 .

[0259] The driving current I that finally flows through the light emitting element L is not related to the threshold voltage Vth of the driving sub-circuit 20, but is related to the threshold voltage V oled_thAs the light emitting element L is used for a longer time, the light emitting efficiency of the light emitting element L decreases due to material aging, and the threshold voltage V oled_th will increase, and the threshold voltage V oled_th The increase of the data signal V data In other words, the current of the light-emitting element L is compensated.

[0260] In some embodiments, the pixel circuit 101 further includes at least one of a first initialization sub-circuit 71, a second initialization sub-circuit 72, and a third initialization sub-circuit 73. The first initialization sub-circuit 71 is coupled to the first reset signal terminal Rst1, the first initialization signal terminal Init1, and the first node N1. The second initialization sub-circuit 72 is coupled to the second reset signal terminal Rst2, the second initialization signal terminal Init2, and the second node N2. The third initialization sub-circuit 73 is coupled to the third reset signal terminal Rst3, the third initialization signal terminal Init3, and the first electrode of the light-emitting element L.

[0261] Figure 22 FIG. 1 is a flow chart of a driving method for a pixel circuit according to some other embodiments. Before the compensation phase U2 of the image frame F, as shown in FIG. Figure 22 As shown, the driving method further includes at least one of the following steps S11-S13:

[0262] S11. In the reset phase U1 of the image frame F, the first initialization sub-circuit 71 transmits the first initialization signal received at the first initialization signal terminal Init1 to the first node N1 in response to the first reset signal received at the first reset signal terminal Rst1 to initialize the potential of the first node N1.

[0263] Thus, in the reset phase U1, the data voltage V of the first node N1 in the previous image frame is cleared by the first initialization signal. data , so that the potential of the first node N1 is initialized to avoid signal interference.

[0264] S12. In the reset phase U1 of the image frame F, the second initialization sub-circuit 72 transmits the second initialization signal received at the second initialization signal terminal Init2 to the second node in response to the second reset signal received at the second reset signal terminal Rst2 to initialize the potential of the second node N2.

[0265] Thus, in the reset phase U1, the voltage (V data +V DD +Vth-V SS -V oled_th), so that the potential of the second node N2 is initialized to avoid signal interference.

[0266] S13. In the reset phase U1 of the image frame F, the third initialization sub-circuit 73 transmits the third initialization signal received at the third initialization signal terminal Init3 to the first electrode of the light-emitting element L in response to the third reset signal received at the third reset signal terminal Rst3, so as to initialize the potential of the first electrode of the light-emitting element L.

[0267] In this way, in the reset stage U1, the voltage of the first electrode of the light-emitting element L is cleared by the third initialization sub-circuit 73, so that the potential of the first electrode of the light-emitting element L is initialized, thereby preventing the light-emitting element L from emitting light in a dark state due to the influence of the leakage current of the light-emitting control sub-circuit 50, thereby improving the display quality of the display device having the pixel circuit 101.

[0268] The driving method of the above-mentioned pixel circuit has the same beneficial effects as the above-mentioned pixel circuit, and the specific driving principle will not be described in detail here.

[0269] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display substrate, characterized in that: include: substrate; A pixel circuit stack is provided on the substrate, and the pixel circuit stack is configured to form a pixel circuit; wherein the pixel circuit stack includes a semiconductor layer, a gate insulating layer, a first conductor layer, a first interlayer insulating layer, a second conductor layer, a second interlayer insulating layer and a third conductive layer arranged in sequence in a direction away from the substrate; the semiconductor layer includes a first pattern, and the first pattern is configured to form an active layer, a first electrode and a second electrode of a sixth transistor; the first conductor layer includes a first conductor pattern and a second conductor pattern that are not connected to each other; the second conductor layer is provided on a side of the first conductor layer away from the substrate and is insulated from the first conductor layer; the second conductor layer includes a third conductor pattern; an orthographic projection of the third conductor pattern on the substrate is aligned with an orthographic projection of the first conductor pattern on the substrate The projections of the third conductor pattern on the substrate have an overlapping area to form a first capacitor; the orthographic projection of the third conductor pattern on the substrate has an overlapping area with the orthographic projection of the second conductor pattern on the substrate to form a second capacitor; the third conductive layer includes a first power line, a data signal line, and a first connection pattern, the first connection pattern and the data signal line are connected to form an integral structure, and the first connection pattern is connected to the first electrode of the sixth transistor through a via hole penetrating the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer; the orthographic projections of the data signal line and the first pattern on the substrate do not overlap, and the orthographic projection of the first power line on the substrate does not overlap with the orthographic projections of the first pattern, the data signal line, and the first connection pattern on the substrate; a light-emitting element disposed on the substrate, the light-emitting element being coupled to the pixel circuit; The pixel circuit includes a data writing subcircuit, a driving subcircuit, a storage subcircuit, a second compensation subcircuit, a light emitting control subcircuit and a potential holding subcircuit; The data writing sub-circuit is coupled to the data signal terminal, the scan signal terminal and the first node; the data writing sub-circuit includes the sixth transistor, the control electrode of the sixth transistor is coupled to the scan signal terminal, the first electrode of the sixth transistor is coupled to the data signal terminal, and the second electrode of the sixth transistor is coupled to the first node; The driving sub-circuit is coupled to the first voltage terminal, the second node and the third node; the driving sub-circuit is configured to generate a driving current in response to a voltage of the second node; The storage sub-circuit is coupled between the first node and the second node; the storage sub-circuit is configured to store a voltage; the storage sub-circuit includes a second capacitor, a first terminal of the second capacitor is coupled to the first node; the second compensation sub-circuit is coupled to the second control signal terminal, the second node, and the third node; the second compensation sub-circuit is configured to transmit the first voltage from the first voltage terminal and the threshold voltage of the driving sub-circuit to the second node in response to a second control signal received at the second control signal terminal; The light emitting control subcircuit is coupled to the enable signal terminal, the third node, and the first electrode of the light emitting element; the light emitting control subcircuit is configured to output the driving current transmitted to the third node to the light emitting element in response to an enable signal received at the enable signal terminal; The potential maintaining subcircuit is coupled between the first voltage terminal and the first node; the potential maintaining subcircuit is configured to maintain the potential of the first node; the potential maintaining subcircuit includes the first capacitor, and the first end of the first capacitor is coupled to the first node.

2. The display substrate according to claim 1, wherein: The second conductor layer further includes an initialization signal line that is not connected to the third conductor pattern.

3. The display substrate according to claim 1, wherein The second terminal of the first capacitor is coupled to the first voltage terminal.

4. The display substrate according to claim 1, wherein: The second compensation sub-circuit includes a second transistor; a control electrode of the second transistor is coupled to the second control signal terminal, a first electrode of the second transistor is coupled to the third node, and a second electrode of the second transistor is coupled to the second node.

5. The display substrate according to claim 1, wherein The pixel circuit further includes: A first initialization sub-circuit is coupled to the first reset signal terminal, the first initialization signal terminal and the first node; the first initialization sub-circuit is configured to respond to the first reset signal received at the first reset signal terminal, transmit the first initialization signal received at the first initialization signal terminal to the first node, so as to initialize the potential of the first node.

6. The display substrate according to claim 1, wherein: The pixel circuit further includes: A second initialization sub-circuit is coupled to the second reset signal terminal, the second initialization signal terminal and the second node; the second initialization sub-circuit is configured to respond to the second reset signal received at the second reset signal terminal, transmit the second initialization signal received at the second initialization signal terminal to the second node, so as to initialize the potential of the second node.

7. The display substrate according to claim 1, wherein: The pixel circuit further includes: A third initialization subcircuit is coupled to a third reset signal terminal, a third initialization signal terminal, and the first electrode of the light-emitting element; the third initialization subcircuit is configured to respond to a third reset signal received at the third reset signal terminal by transmitting the third initialization signal received at the third initialization signal terminal to the first electrode of the light-emitting element to initialize the potential of the first electrode of the light-emitting element.

8. The display substrate according to any one of claims 5 to 7, wherein: When the pixel circuit includes a first initialization sub-circuit, a second initialization sub-circuit and a third initialization sub-circuit, The first reset signal terminal, the second reset signal terminal and the third reset signal terminal are the same reset signal terminal, and / or the first initialization signal terminal, the second initialization signal terminal and the third initialization signal terminal are the same initialization signal terminal.

9. The display substrate according to claim 5, wherein: The first initialization sub-circuit includes a third transistor; a control electrode of the third transistor is coupled to the first reset signal terminal, a first electrode of the third transistor is coupled to the first initialization signal terminal, and a second electrode of the third transistor is coupled to the first node.

10. The display substrate according to claim 6, wherein: The second initialization sub-circuit includes a fourth transistor; a control electrode of the fourth transistor is coupled to the second reset signal terminal, a first electrode of the fourth transistor is coupled to the second initialization signal terminal, and a second electrode of the fourth transistor is coupled to the second node.

11. The display substrate according to claim 7, wherein: The third initialization subcircuit includes a fifth transistor; the control electrode of the fifth transistor is coupled to the third reset signal terminal, the first electrode of the fifth transistor is coupled to the third initialization signal terminal, and the second electrode of the fifth transistor is coupled to the first electrode of the light-emitting element.

12. The display substrate according to claim 1, wherein The second terminal of the second capacitor is coupled to the second node.

13. The display substrate according to claim 1, wherein The driving sub-circuit includes a driving transistor; a control electrode of the driving transistor is coupled to the second node, a first electrode of the driving transistor is coupled to the first voltage terminal, and a second electrode of the driving transistor is coupled to the third node.

14. The display substrate according to claim 1, wherein The light emitting control subcircuit includes a seventh transistor; the control electrode of the seventh transistor is coupled to the enable signal terminal, the first electrode of the seventh transistor is coupled to the third node, and the second electrode of the seventh transistor is coupled to the first electrode of the light emitting element.

15. A display device, characterized in that: include: The display substrate according to any one of claims 1 to 14; as well as, a driving chip coupled to the display substrate; The driving chip is configured to provide the pixel circuits in the display substrate with signals required to drive the pixel circuits.

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