A twin 8T SRAM storage and computing unit and computing system

Abstract

The present invention discloses a twin 8T SRAM storage and calculation unit and a computing system. The twin 8T SRAM storage and calculation unit includes a computing unit and a storage unit. The storage unit is a twin 8T SRAM unit, including a high-weight storage unit M8T and a low-weight storage unit L8T. When operating in storage mode, the high-weight storage unit M8T and the low-weight storage unit L8T are used to separate read and write paths. When operating in calculation mode, the computing unit is used to implement multiplication of 2 bits of input data and 2 bits of weight. The present invention improves computing efficiency while reducing power consumption and avoiding the problem of read interference write.

Description

Technical Field

[0001] The present invention belongs to the field of computer technology, and in particular relates to a twin 8T SRAM storage and computing unit and a computing system. Background Art

[0002] In the existing technology, many designs only support multiplication calculations of single-bit input and single-bit weight, which fundamentally limits efficiency improvements. In many designs that study multi-bit calculations, the local calculation units are designed to be relatively complex, which is not conducive to saving area and reducing power consumption. In order to reduce area, some designs use 6T SRAM storage cells as basic storage cells, but this introduces read interference and write problems to the circuit. Summary of the Invention

[0003] To address the deficiencies in the prior art, the present invention provides a twin 8T SRAM storage and computing unit and computing system, which improves computing efficiency while reducing power consumption and avoids the problem of read-interference-write.

[0004] In order to achieve the above object, the technical solution adopted by the present invention is:

[0005] In a first aspect, a twin 8T SRAM storage and computing unit is provided, including: a computing unit and a storage unit, wherein the storage unit is a twin 8T SRAM unit, including a high-weight storage unit M8T and a low-weight storage unit L8T; when working in storage mode, the high-weight storage unit M8T and the low-weight storage unit L8T are used to realize the separation of read and write paths; when working in computing mode, the computing unit is used to realize the multiplication operation of 2 bits of input data and 2 bits of weight.

[0006] Furthermore, the low-bit weight storage unit L8T includes: NMOS transistors N1 to N6 and PMOS transistors P1 to P2; wherein the source terminals of the NMOS transistors N1, N2, and N5 are grounded; the drain terminal of the NMOS transistor N1 is connected to the gate terminal of the NMOS transistor N2, the gate terminal of the PMOS transistor P2, the drain terminal of the PMOS transistor P1, and the source terminal of the NMOS transistor N3; the gate terminal of the NMOS transistor N1 is connected to the gate terminal of the PMOS transistor P1, the drain terminal of the NMOS transistor N2, the drain terminal of the PMOS transistor P1, and the source terminal of the NMOS transistor N3; The drain terminal of P2, the source terminal of NMOS transistor N4 and the gate terminal of NMOS transistor N5 are connected; the source terminals of PMOS transistors P1 and P2 are connected to the power supply potential; the gate terminals of NMOS transistors N3 and N4 are connected to word line WL, and the drain terminal of NMOS transistor N3 is connected to bit line BL1; the drain terminal of NMOS transistor N4 is connected to bit line BL1B; the drain terminal of NMOS transistor N5 is connected to the source terminal of NMOS transistor N6, the drain terminal of NMOS transistor N6 is connected to read bit line RBL, and the gate terminal of NMOS transistor N6 is connected to read word line RWL.

[0007] Furthermore, the high-weight storage unit M8T includes: NMOS transistors N7 to N12 and PMOS transistors P3 to P4; wherein the source terminals of the NMOS transistors N8, N9, and N10 are grounded; the source terminals of the PMOS transistors P3 and P4 are connected to the power supply potential; the drain terminal of the NMOS transistor N7 is connected to the read bit line RBL; the gate terminal of the NMOS transistor N7 is connected to the read word line RWL; the source terminal of the NMOS transistor N7 is connected to the drain terminal of the NMOS transistor N8; the gate terminal of the NMOS transistor N8 is connected to the drain terminal of the NMOS transistor N9 , the drain terminal of the PMOS transistor P3, the source terminal of the NMOS transistor N11, the gate terminal of the PMOS transistor P4 and the gate terminal of the NMOS transistor N10 are connected; the gate terminal of the NMOS transistor N9 is connected to the gate terminal of the PMOS transistor P3, the drain terminal of the PMOS transistor P4, the drain terminal of the NMOS transistor N10 and the source terminal of the NMOS transistor N12; the drain terminal of the NMOS transistor N11 is connected to the bit line BL2B, the drain terminal of the NMOS transistor N12 is connected to the bit line BL2; the gate terminals of the NMOS transistors N11 and N12 are connected to the word line WL.

[0008] Furthermore, the change in charge on the read bit line RBL causes a different voltage value on the read bit line RBL, namely:

[0009]

[0010] Where ΔV represents the voltage change on the read bit line RBL, and ΔQ represents the capacitance C connected to the read bit line RBL. C The charge change Cc represents the capacitance connected to the read bit line RBL; by detecting the voltage on the read bit line RBL, the size of the stored 2-bit weight data can be determined.

[0011] Furthermore, the calculation unit includes PMOS transistors P5 to P8, transmission gates T1 to T2, capacitors C1 to C2 and capacitor CC; wherein the drain terminals of the PMOS transistors P7 and P8 are grounded; the lower plates of the capacitors C1, C2 and CC are grounded; the input terminal of the transmission gate T1 is connected to the bit line BL1 and the gate terminal of the PMOS transistor P7; the input terminal of the transmission gate T2 is connected to the bit line BL2 and the gate terminal of the PMOS transistor P8; the high-level control ports of the transmission gates T1 and T2 are both connected to the NMOS input HTS, and the low-level control ports are connected to the NMOS input HTS. The ports are all connected to the PMOS input LTS; the output end of the transmission gate T1 is connected to the upper plate of the capacitor C1 and the source end of the PMOS transistor P5; the output end of the transmission gate T2 is connected to the upper plate of the capacitor C2 and the source end of the PMOS transistor P6; the gate ends of the PMOS transistors P5 and P6 are connected to the read bit line RBL; the upper plate of the capacitor CC is connected to the read bit line RBL; the drain end of the PMOS transistor P5 is connected to the source end of the PMOS transistor P7; and the drain end of the PMOS transistor P6 is connected to the source end of the PMOS transistor P8.

[0012] Furthermore, the amount of charge discharged from the read bit line RBL to the ground is different, so that the read bit line RBL is stabilized at potentials of different magnitudes, which are used to represent the stored weight data.

[0013] In a second aspect, a computing system is provided, wherein the computing system is configured with the twin 8T SRAM storage and computing units described in the first aspect.

[0014] Compared with the prior art, the present invention has the following beneficial effects:

[0015] (1) The present invention sets the storage unit as a twin 8T SRAM unit, including a high-weight storage unit M8T and a low-weight storage unit L8T. When working in the storage mode, the high-weight storage unit M8T and the low-weight storage unit L8T are used to realize the separation of the read and write paths; when working in the calculation mode, the calculation unit is used to realize the multiplication operation of 2 bits of input data and 2 bits of weight, thereby improving the calculation efficiency while reducing power consumption, separating the read and write paths, and solving the read interference write problem existing in the traditional 6T SRAM;

[0016] (2) The present invention has high computational efficiency and can simultaneously perform multiplication operations on 2-bit input data and 2-bit weights, which is more efficient than an SRAM array with a single-bit weight.

[0017] (3) The present invention has a larger signal margin, and the voltage swing of the read bit line RBL is larger, so the corresponding signal margin is improved;

[0018] (4) The local computing unit circuit is simple, saving area consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 This is a schematic diagram of the circuit principle of a twin 8T SRAM storage and computing unit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0020] The present invention will be further described below in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solutions of the present invention and are not intended to limit the scope of protection of the present invention.

[0021] Example 1:

[0022] like Figure 1 As shown, a twin 8T SRAM storage and computing unit mainly includes a twin 8T SRAM storage unit composed of NMOS transistors N1 to N12 and PMOS transistors P1 to P4, and a computing unit composed of PMOS transistors P5 to P8, transmission gates T1 to T2, capacitors C1 to C2 and capacitor CC. Among them, BL1 is the bit line of the low-order 8T SRAM cell, which is used to transmit low-order input data and weight data; BL1B is the bit line NOT of the low-order 8T SRAM cell, which is used to transmit low-order input data and weight data; BL2 is the bit line of the high-order 8T SRAM cell, which is used to transmit high-order input data and weight data; BL2B is the bit line NOT of the high-order 8TSRAM cell, which is used to transmit high-order input data and weight data; RBL is the read bit line of the twin 8T SRAM cell, and also acts on the gate terminals of the P5 and P6 transistors in the local computing unit to control their conduction; RWL is the read word line of the twin 8T SRAM cell, which is used to control the weight data reading of the twin 8T SRAM cell; WL is the word line used to control the twin 8T The weight data of the SRAM unit is written; HTS is the NMOS input of the transmission gates T1 and T2 (high potential is valid); LTS is the PMOS input of the transmission gates T1 and T2 (low potential is valid); HM is the high-order calculation result of the local calculation unit; LM is the low-order calculation result of the local calculation unit; M8T is the high-order weight storage unit in the twin 8T SRAM; L8T is the low-order weight storage unit in the twin 8T SRAM; VDD is the highest potential of the circuit, the power supply potential; VSS is the lowest potential of the circuit, the ground potential; N1~N12 are NMOS transistors; P1~P8 are PMOS transistors; T1 and T2 are transmission gates; C1, C2, CC are capacitors.

[0023] The source terminals of the NMOS transistors N1, N2, N5, N8, N9, and N10, the drain terminals of the PMOS transistors P7 and P8, the lower plate of the capacitor C1, the lower plate of the capacitor C2, and the lower plate of the capacitor CC are all grounded; the drain terminal of the NMOS transistor N1 is connected to the gate terminal of the NMOS transistor N2, the gate terminal of the PMOS transistor P2, the drain terminal of the PMOS transistor P1, and the source terminal of the NMOS transistor N3; the gate terminal of the NMOS transistor N1 is connected to the gate terminal of the PMOS transistor P1, the drain terminal of the NMOS transistor N2, the drain terminal of the PMOS transistor P2, the source terminal of the NMOS transistor N4, and the NMOS transistors The gate terminal of N5 is connected; the source terminals of PMOS transistors P1, P2, P3 and P4 are all connected to the power supply potential; the gate terminals of NMOS transistors N3, N4, N11 and N12 are all connected to word line WL, the drain terminal of NMOS transistor N3 is connected to bit line BL1, the input terminal of transmission gate T1 and the gate terminal of PMOS transistor P7; the drain terminal of NMOS transistor N4 is connected to bit line BL1B; the drain terminal of NMOS transistor N5 is connected to the source terminal of NMOS transistor N6; the drain terminals of NMOS transistors N6 and N7, the gate terminals of PMOS transistors P5 and P6, and the upper plate of capacitor CC are all on the read bit line RBL; the NMOS transistors The gate terminals of transistors N6 and N7 are both connected to the read word line RWL; the source terminal of NMOS transistor N7 is connected to the drain terminal of NMOS transistor N8; the gate terminal of NMOS transistor N8 is connected to the drain terminal of NMOS transistor N9, the drain terminal of PMOS transistor P3, the source terminal of NMOS transistor N11, the gate terminal of PMOS transistor P4 and the gate terminal of NMOS transistor N10; the gate terminal of NMOS transistor N9 is connected to the gate terminal of PMOS transistor P3, the drain terminal of PMOS transistor P4, the drain terminal of NMOS transistor N10 and the source terminal of NMOS transistor N12; the drain terminal of NMOS transistor N11 is connected to On the bit line BL2B; the drain terminal of the NMOS transistor N12, the input terminal of the transmission gate T2 and the gate terminal of the PMOS transistor P8 are all connected to the bit line BL2; the high-level control ports of the transmission gates T1 and T2 are both connected to HTS, and the low-level control ports are both connected to LTS; the output terminal of the transmission gate T1 is connected to the upper plate of the capacitor C1 and the source terminal of the PMOS transistor P5; the output terminal of the transmission gate T2 is connected to the upper plate of the capacitor C2 and the source terminal of the PMOS transistor P6; the drain terminal of the PMOS transistor P5 is connected to the source terminal of the PMOS transistor P7; the drain terminal of the PMOS transistor P6 is connected to the source terminal of the PMOS transistor P8;

[0024] In this embodiment, the twin 8T SRAM storage and computing units have two working modes: storage mode and computing mode. In any working mode, the size of NMOS transistors N7 and N8 is twice that of NMOS transistors N5 and N6, so as to achieve 2-bit weight. Table 1 is a 2-bit weight truth table, where ILC The current generated on the RBL by the low-order 8T SRAM cell, i.e., L8T, is RBL Current; the current generated on the RBL by the high-order 8T SRAM cell, i.e., M8T, is 2×I LC .

[0025] Table 1 2-bit weight truth table

[0026]

[0027] When working in storage mode, the circuit mainly performs writing and reading operations. The write operation takes the high-bit 8T SRAM writing "0" and the low-bit 8T SRAM writing "1" as an example: first precharge the bit lines BL1 and BL2B to the high potential "1" and the bit lines BL1B and BL2 to the low potential "0", then turn on the word line WL, and turn on the NMOS transistors N3, N4, N11 and N12 to write the nodes Q1, Q1B, Q2 and QB2 to the high potential "1", low potential "0", low potential "0" and high potential "1" respectively. After the potentials of the four nodes are stable, disconnect the word line WL to store data; the read operation takes the high-bit 8T SRAM reading "1" and the low-bit 8T SRAM reading "0" as an example: turn on the read word line RWL, then the NMOS transistors N6 and N7 are turned on. The weight Q2 stored in the SRAM is "1", then Q2B is "0", so the NMOS transistor N8 is not turned on, and the NMOS transistors N7 and N8 do not form a conductive path from the read bit line RBL to the ground; and because the low bit 8T If the weight Q1 stored in the SRAM is "0", then Q1B is "1", so the NMOS transistor N5 is turned on, and the read bit line RBL is discharged to the ground through the conductive path formed by the NMOS transistors N5 and N6. This is because: 1) the NMOS transistors N5, N6, N7, and N8 do not form a conductive path; 2) the NMOS transistors N5 and N6 form a conductive path, but the NMOS transistors N7 and N8 do not form a conductive path; 3) the NMOS transistors N5 and N6 do not form a conductive path, but the NMOS transistors N7 and N8 do; 4) the NMOS transistors N5, N6, N7, and N8 all form a conductive path. Because the capacitance of the read bit line RBL does not change, within a certain period of time, the four different conductive path scenarios formed by the NMOS transistors N5, N6, N7, and N8 have different effects on the charge change on the read bit line RBL, resulting in different voltage values ​​on the read bit line RBL, namely:

[0028]

[0029] Where ΔV represents the voltage change on the read bit line RBL, and ΔQ represents the capacitance C connected to the read bit line RBL. CCc represents the capacitance connected to the read bit line RBL.

[0030] By detecting the voltage on the read bit line RBL, the size of the stored 2-bit weight data is determined.

[0031] When working in the calculation mode, similar to the storage mode, the read word line RWL is turned on, and the weight data stored in the twin 8T SRAM is Q1 and Q2, where Q2 is the high weight and Q1 is the low weight. According to the values ​​of Q1 and Q2, the NMOS transistors N5, N6 and N7, N8 will form different conductive path combinations: 1) When the weight Q1 is "0" and Q2 is "0", the read word line RWL is turned on, and the NMOS transistors N5, N6 and N7, N8 respectively form a conductive path to the read bit line RBL to the ground, so the potential on the read bit line RBL changes greatly; 2) When the weight Q1 is "1" and Q2 is "0", the read word line RWL is turned on, and the NMOS transistors N5 and N6 do not form a conductive path to the read bit line RBL to the ground, but the NMOS transistors N7 and N8 form a conductive path to the ground, so the potential on the read bit line RBL changes greatly. The change is large; 3) When the weight Q1 is "0" and Q2 is "1", the read word line RWL is turned on, and the NMOS transistors N5 and N6 form a conductive path to the read bit line RBL to the ground, but the NMOS transistors N7 and N8 do not form a conductive path to the read bit line RBL to the ground, so the potential on the read bit line RBL changes little; 4) When the weight Q1 is "1" and Q2 is "1", the read word line RWL is turned on, and the NMOS transistors N5, N6 and N7, N8 do not form a conductive path to the read bit line RBL to the ground, so the potential on the read bit line RBL does not change; within a certain period of time, the above four different weight storage conditions will cause the read bit line RBL to discharge different amounts of charge to the ground, thereby stabilizing the read bit line RBL at potentials of different sizes, thereby representing the stored weight data.

[0032] The 2-bit input data is added to BL1 and BL2 respectively, where BL2 is the high-bit input data and BL1 is the low-bit input data. The multiplication operation of the input data and the weight is generated by controlling the on and off of transistors P7 and P8 by BL1 and BL2 and the conduction degree of transistors P5 and P6 controlled by the read bit line RBL. The multiplication result of the high bit of the 2-bit input data and the weight will be displayed at HM in the form of a voltage change, and the multiplication result of the low bit and the weight will be displayed at LM in the form of a voltage change. The multiplication result of the 2-bit input data and the 2-bit weight can be obtained by combining the results of HM and LM.

[0033] The present invention has the following features: 1) Separating read and write paths to solve the read interference and write problem existing in traditional 6T SRAM; 2) High efficiency: the circuit unit can simultaneously perform multiplication operations on 2-bit input data and 2-bit weight, which is higher than SRAM arrays with single-bit weight; 3) Greater signal tolerance: the voltage swing of the read bit line RBL is larger, so the corresponding signal tolerance is improved; 4) The local calculation unit circuit is simple, saving area consumption. Features 1), 2), and 3) are primarily derived from the twin 8T SRAM cells. The 8T design allows for different read and write paths in the storage mode, preventing the simultaneous activation of multiple word lines (WL) from potentially causing the bit line potential to drop below the write tolerance, potentially causing a cell originally storing a "1" to be mistakenly written as a "0." Furthermore, the twin 8T design enables the circuit to perform multi-bit storage and operations, which not only improves efficiency but also increases the voltage swing on the read bit line (RBL), thereby increasing the signal tolerance and reducing the probability of false flips in the circuit. Features 2) and 4) also benefit from the local computation unit, which is relatively small, with only four transistors and two data input terminals. This allows for a small area while supporting 2-bit data input.

[0034] This embodiment verifies the functions of a twin 8T SRAM storage and computing unit through simulation, and the verification results show that all functions meet the design requirements.

[0035] Example 2:

[0036] Based on the twin 8T SRAM storage and computing unit described in the first embodiment, this embodiment provides a computing system, which is configured with the twin 8T SRAM storage and computing unit described in the first embodiment.

[0037] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A twin 8T SRAM storage and computing unit, characterized in that: include: Computing unit and storage unit, the storage unit is a twin 8T SRAM unit, including a high-weight storage unit M8T and a low-weight storage unit L8T; When working in storage mode, the high-weight storage unit M8T and the low-weight storage unit L8T are used to separate the read and write paths; When working in calculation mode, the calculation unit is used to implement the multiplication operation of 2 bits of input data and 2 bits of weight; The calculation unit includes PMOS transistors P5-P8, transmission gates T1-T2, capacitors C1-C2 and capacitor CC; wherein the drain terminals of the PMOS transistors P7 and P8 are grounded; the lower plates of the capacitors C1, C2 and CC are grounded; The input terminal of the transmission gate T1 is connected to the bit line BL1 and the gate terminal of the PMOS transistor P7; the input terminal of the transmission gate T2 is connected to the bit line BL2 and the gate terminal of the PMOS transistor P8; the high-level control ports of the transmission gates T1 and T2 are both connected to the NMOS input HTS, and the low-level control ports are both connected to the PMOS input LTS; the output terminal of the transmission gate T1 is connected to the upper plate of the capacitor C1 and the source terminal of the PMOS transistor P5; the output terminal of the transmission gate T2 is connected to the upper plate of the capacitor C2 and the source terminal of the PMOS transistor P6; The gate terminals of PMOS transistors P5 and P6 are connected to the read bit line RBL; the upper plate of capacitor CC is connected to the read bit line RBL; the drain terminal of PMOS transistor P5 is connected to the source terminal of PMOS transistor P7; the drain terminal of PMOS transistor P6 is connected to the source terminal of PMOS transistor P8.

2. The twin 8T SRAM storage and computing unit according to claim 1, characterized in that: The low-bit weight storage unit L8T includes: NMOS transistors N1 to N6 and PMOS transistors P1 to P2; wherein the source terminals of the NMOS transistors N1, N2, and N5 are grounded; The drain terminal of the NMOS transistor N1 is connected to the gate terminal of the NMOS transistor N2, the gate terminal of the PMOS transistor P2, the drain terminal of the PMOS transistor P1 and the source terminal of the NMOS transistor N3; The gate terminal of the NMOS transistor N1 is connected to the gate terminal of the PMOS transistor P1, the drain terminal of the NMOS transistor N2, the drain terminal of the PMOS transistor P2, the source terminal of the NMOS transistor N4, and the gate terminal of the NMOS transistor N5; The source terminals of the PMOS transistors P1 and P2 are connected to the power supply potential; The gate terminals of the NMOS transistors N3 and N4 are connected to the word line WL, and the drain terminal of the NMOS transistor N3 is connected to the bit line BL1; The drain terminal of the NMOS transistor N4 is connected to the bit line BL1B; The drain terminal of the NMOS transistor N5 is connected to the source terminal of the NMOS transistor N6 . The drain terminal of the NMOS transistor N6 is connected to the read bit line RBL. The gate terminal of the NMOS transistor N6 is connected to the read word line RWL.

3. The twin 8T SRAM storage and computing unit according to claim 2, characterized in that: The high-weight storage unit M8T includes: NMOS transistors N7 to N12 and PMOS transistors P3 to P4; wherein the source terminals of the NMOS transistors N8, N9, and N10 are grounded; and the source terminals of the PMOS transistors P3 and P4 are connected to the power supply potential; The drain terminal of the NMOS transistor N7 is connected to the read bit line RBL; the gate terminal of the NMOS transistor N7 is connected to the read word line RWL; the source terminal of the NMOS transistor N7 is connected to the drain terminal of the NMOS transistor N8; The gate terminal of the NMOS transistor N8 is connected to the drain terminal of the NMOS transistor N9, the drain terminal of the PMOS transistor P3, the source terminal of the NMOS transistor N11, the gate terminal of the PMOS transistor P4, and the gate terminal of the NMOS transistor N10; The gate terminal of the NMOS transistor N9 is connected to the gate terminal of the PMOS transistor P3, the drain terminal of the PMOS transistor P4, the drain terminal of the NMOS transistor N10, and the source terminal of the NMOS transistor N12; A drain terminal of the NMOS transistor N11 is connected to the bit line BL2B, and a drain terminal of the NMOS transistor N12 is connected to the bit line BL2; gate terminals of the NMOS transistors N11 and N12 are connected to the word line WL.

4. The twin 8T SRAM storage and computing unit according to claim 3, characterized in that: The change in charge on the read bit line RBL causes the voltage value on the read bit line RBL to be different, that is: ， in, Represents the voltage change on the read bit line RBL, Represents the capacitance connected to the read bit line RBL The change in charge, Represents the capacitance connected to the read bit line RBL; By detecting the voltage on the read bit line RBL, the size of the stored 2-bit weight data can be determined.

5. The twin 8T SRAM storage and computing unit according to claim 4, characterized in that: The amount of charge discharged from the read bit line RBL to the ground is different, so that the read bit line RBL is stabilized at potentials of different magnitudes, which are used to represent the stored weight data.

6. A computing system, characterized in that The computing system is configured with a twin 8TSRAM storage and computing unit as described in any one of claims 1 to 5.

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