Three-dimensional memory device

Abstract

The present disclosure provides a three-dimensional memory device, such as a three-dimensional AND flash memory device. The three-dimensional memory device includes a plurality of memory cell arrays, a plurality of bit line switches, and a plurality of source line switches. The memory cell arrays have a plurality of memory cell rows coupled to a plurality of source lines and a plurality of bit lines, respectively. The bit line switches and the source line switches are formed by a plurality of first transistors and a plurality of second transistors, respectively. The first transistors are coupled to a common bit line and a bit line. The second transistors are coupled to a common source line and a source line. The first transistors are P-type transistors or N-type transistors having a triple-well region base, and the second transistors are P-type transistors or N-type transistors having a triple-well region base.

Description

Technical Field

[0001] This disclosure relates to a three-dimensional memory device, and more particularly to a three-dimensional memory device that can provide a negative source line voltage or bit line voltage. Background Technology

[0002] With the advancement of semiconductor process technology and the refinement of electronic product functions, the installation of high-density flash memory in electronic products has become a trend.

[0003] In existing three-dimensional AND-gate flash memory devices, bit line switches and source line switches are often constructed using N-type transistors. In this case, the bit line switches and source line switches can only provide positive word line voltages and source line voltages to the memory cells, enabling them to perform programming or erasing operations. However, since memory cells can be selected or unselected during programming or erasing, ensuring that selected memory cells can effectively perform programming or erasing operations while suppressing unselected memory cells from interference presents a challenging problem due to process limitations: how to provide a suitable bias voltage for each memory cell.

[0004] Public content

[0005] This disclosure provides a three-dimensional memory device that can provide suitable bit line voltages and source line voltages to each memory cell.

[0006] The three-dimensional memory device disclosed herein includes multiple memory cell arrays, multiple bit line switches, and multiple source line switches. The memory cell arrays have corresponding multiple memory cell rows, each coupled to multiple source lines and multiple bit lines. The bit line switches are each composed of multiple first transistors. A first terminal of each first transistor is coupled to a common bit line, and a second terminal of each first transistor is coupled to a bit line. The source line switches are each composed of multiple second transistors. A second terminal of each second transistor is coupled to a common source line, and a second terminal of each second transistor is coupled to a source line. The first transistors are either P-type transistors or N-type transistors with a triple-well substrate, and the second transistors are either P-type transistors or N-type transistors with a triple-well substrate.

[0007] Based on the above, the three-dimensional memory device of this disclosure constructs source line switches and bit line switches using P-type transistors or N-type transistors with a triple-well substrate. In this three-dimensional memory device, the source or drain can be supplied with positive or negative voltages by controlling the voltage on the well regions of the P-type and / or N-type transistors. In this way, the source line switches and bit line switches can provide appropriate voltages to the selected and unselected memory cells, enabling each memory cell to perform read, program, and erase operations. Attached Figure Description

[0008] Figure 1 This is a schematic diagram of a three-dimensional memory device according to an embodiment of the present disclosure.

[0009] Figure 2 This is a schematic diagram illustrating an embodiment of an N-type transistor with a triple-well substrate in a three-dimensional memory device according to an embodiment of the present disclosure.

[0010] Figures 3A to 3D This is a schematic diagram illustrating the access operation of a three-dimensional memory device according to an embodiment of the present disclosure.

[0011] Figures 4A to 4D This is a schematic diagram illustrating the access operation of a three-dimensional memory device according to another embodiment of the present disclosure.

[0012] Figures 5A to 5D This is a schematic diagram illustrating the access operation of a three-dimensional memory device according to another embodiment of the present disclosure.

[0013] Figures 6A to 6D This is a schematic diagram illustrating the access operation of a three-dimensional memory device according to another embodiment of the present disclosure.

[0014] Explanation of reference numerals in the attached figures

[0015] 100, 300, 400, 500, 600: Three-dimensional memory devices

[0016] 111, 112: Storage cell array

[0017] 120, 130, 320, 330, 420, 430, 520, 530, 620, 630: Base

[0018] 200: N-type transistor

[0019] 210: N-type deep well region

[0020] 220: P-type well region

[0021] 230: N-type well region

[0022] 231, 232: N-type heavily doped regions

[0023] 233: P-type heavily doped region

[0024] 245: Insulation Structure

[0025] 250: Gate structure

[0026] BLT0~BLT3: Bit line switches

[0027] CSL: Common Source Line

[0028] CT: Connectivity Structure

[0029] GBL: Common Line

[0030] LBL0~LBL3: Bit lines

[0031] LSL0~LSL3: Source Line

[0032] M11~M24: Transistors

[0033] MC1, MC2: Storage units

[0034] SLT0~SLT3: Source line switches

[0035] SMB: Selected storage cell block

[0036] SMC: Selected storage unit

[0037] WL0_0~WL1_1: Word lines Detailed Implementation

[0038] Please refer to Figure 1 , Figure 1 This is a schematic diagram of a three-dimensional memory device according to an embodiment of the present disclosure. The three-dimensional memory device 100 includes memory cell arrays 111 and 112, bit line switches BLT0 to BLT3, and source line switches SLT0 to SLT3. Memory cell array 111 includes a plurality of memory cells MC1. Memory cell array 112 includes a plurality of memory cells MC2. In memory cell array 111, the memory cells MC1 are arranged in a plurality of memory cell rows and columns. In memory cell array 112, the memory cells MC2 are also arranged in a plurality of memory cell rows and columns. The plurality of memory cell columns in memory cell array 111 are respectively coupled to word lines WL1_0 to WL1_1, and the plurality of memory cell columns in memory cell array 112 are respectively coupled to word lines WL00 to WL01. In addition, the plurality of memory cell rows in memory cell arrays 111 and 112 correspond to each other and are respectively coupled to bit lines LBL0 to LBL3 and source lines LSL0 to LSL3.

[0039] Bit line switches BLT0 to BLT3 are disposed in substrate 120. Bit line switches BLT0 to BLT3 are each composed of multiple transistors M11 to M14. Source line switches SLT0 to SLT3 are disposed in substrate 130. Source line switches SLT0 to SLT3 are each composed of multiple transistors M21 to M24. Transistors M11 to M14 are controlled by selection signals SEL_BLT0 to SEL_BLT3 to be turned on or off, respectively. Transistors M21 to M24 are controlled by selection signals SEL_SLT0 to SEL_SLT3 to be turned on or off, respectively.

[0040] In this embodiment, transistors M11 to M14 can be P-type transistors or N-type transistors with a triple-well substrate. Transistors M21 to M24 can be P-type transistors or N-type transistors with a triple-well substrate.

[0041] Incidentally, the memory cell arrays 111 and 112 in this embodiment are AND-type flash memory cell arrays. Furthermore, in this embodiment, a single source line is coupled to a common source line CSL only through a corresponding single source line switch. A single bit line is coupled to a common bit line GBL only through a corresponding single bit line switch.

[0042] Please refer to the following: Figure 2 , Figure 2 This is a schematic diagram illustrating an embodiment of an N-type transistor with a triple-well substrate in a three-dimensional memory device according to an embodiment of the present disclosure. The N-type transistor 200 includes an N-type deep well region (DNW) 210, a P-type well region (PWI) 220, an N-type well region 230, N-type heavily doped regions (n+) 231 and 232, a P-type heavily doped region (p+) 233, and a gate structure 250. The N-type deep well region 210 may be formed in a P-type substrate. The P-type well region (PWI) 220 is formed on the N-type deep well region 210 and surrounded by the N-type well region 230. The N-type heavily doped regions (n+) 231 and 232 and the P-type heavily doped region (p+) 233 are arranged sequentially on the P-type well region (PWI) 220. The N-type heavily doped regions (n+) 232 and the P-type heavily doped regions (p+) 233 can be isolated from each other by an insulating structure 245. The N-type heavily doped regions (n+) 231 and 232 can be used to form a channel, and the gate structure 250 covers the channel and partially covers the N-type heavily doped regions (n+) 231 and 232.

[0043] In this embodiment, the bias voltage VPW can be transmitted to the heavily doped P-type region (p+) 233 via the connection structure CT and applied to the P-type well region (PWI) 220. By controlling the bias voltage VPW and the voltage on the N-type deep well region 210, the heavily doped N-type regions (n+) 231 and 232, which serve as the source and drain (or drain and source) of the transistor 200, can be used to transmit negative or positive voltages.

[0044] Please refer to the following: Figures 3A to 3D , Figures 3A to 3D This is a schematic diagram illustrating the access operation of a three-dimensional memory device according to an embodiment of the present disclosure. Figure 3A In the three-dimensional memory device 300, transistors M21 to M24, which serve as source line switches SLT0 to SLT3, and transistors M11 to M14, which serve as bit line switches BLT0 to BLT3, are all N-type transistors with a triple-well substrate.

[0045] During the read operation, a bias voltage of 0 volts is applied to the substrate (P-type well region) 320 of transistors M11-M14, and a bias voltage of 0 volts is also applied to the substrate (P-type well region) 330 of transistors M21-M24. Corresponding to the selected memory cell SMC, bit line LBL2 and source line LSL2 are the selected bit line and source line, respectively. Bit line switch BLT2 and source line switch SLT2 are the selected bit line switch and source line switch, respectively, and are turned on. The remaining bit line switches BLT0, BLT1, and BLT3, and the remaining source line switches SLT0, SLT1, and SLT3 are turned off. At this time, the voltage on the common bit line GBL can be equal to the first voltage, and the turned-on bit line switch BLT2 can provide the first voltage to the bit line LBL2 of the selected memory cell SMC. Additionally, at this time, the voltage on the common source line CSL is equal to the second voltage, and the turned-on source line switch SLT2 can provide the second voltage to the source line LSL2 corresponding to the selected memory cell SMC. In this embodiment, the first voltage can be a positive value and is greater than the second voltage. For example, the first voltage can be 1 volt, and the second voltage can be 0 volts.

[0046] On the other hand, the word line electrical signal on word line WL0_0 corresponding to the selected memory cell SMC can be equal to the read voltage (e.g., 5-7 volts). The word line electrical signals on the remaining word lines WL0_1, WL1_0, and WL1_1 that are not corresponding to the selected memory cell SMC can be equal to 0 volts.

[0047] In addition, since bit line switches BLT0, BLT1, BLT3 and source line switches SLT0, SLT1, SLT3 are all in the open state, bit lines LBL0, LBL1, LBL3 and source lines LSL0, LSL1, LSL3 are all floating to the ground voltage.

[0048] The selected memory cell SMC can transmit current based on the stored data, and this current is transmitted to the sense amplifier (not shown) via bit line LBL2. The sense amplifier can convert the current supplied by the selected memory cell SMC into a voltage signal and compare the voltage signal with a reference voltage to sense the data stored in the selected memory cell SMC.

[0049] exist Figure 3B In this process, the three-dimensional memory device 300 performs a programming operation. It adjusts the threshold voltage of the selected memory cell's SMC using FN tunneling (Fowler-Nordheim tunneling) and then performs the programming operation.

[0050] During the programming process, the substrates (P-type well regions) 320 of transistors M11-M14 and the substrates (P-type well regions) 330 of transistors M21-M24 are all subjected to a negative bias voltage (e.g., -7.5 volts). Furthermore, the bit line switch BLT2 corresponding to the selected memory cell SMC is activated and turned on. The remaining bit line switches BLT0, BLT1, and BLT3 are turned off. Bit line switch BLT2 provides a negative first voltage to the bit line LBL2 corresponding to the selected memory cell SMC. This first voltage is, for example, -7.5 volts. Additionally, the source line switch SLT2 corresponding to the selected memory cell SMC is set to activate and turned off. The remaining source line switches SLT0, SLT1, and SLT3 are turned on. Here, the voltage on the common source line CSL is, for example, equal to 6.5 volts. Based on the body effect, the activated source line switches SLT0, SLT1, and SLT3 can provide a positive second voltage (e.g., equal to 3.5 volts) to the source lines LSL0, LSL1, and LSL3 corresponding to the unselected memory cells. This second voltage serves as an inhibit voltage. Here, source line LSL2 is in a floating state.

[0051] Furthermore, the word line voltage on word line WL0_0 corresponding to the selected memory cell SMC can be set to 12.5 volts, while the word line voltages on the remaining word lines WL1_0, WL1_1, and WL0_1 can be set to -1.5 volts. In this way, the selected memory cell SMC can withstand a programming bias voltage of up to 20 volts (the voltage difference between the word line and bit line (or source line) corresponding to the memory cell during programming), effectively executing the programming operation.

[0052] Regarding other unselected memory cells, the programming bias voltage for memory cells corresponding to unselected bit lines, unselected source lines, and unselected word lines can be -5 volts; the programming bias voltage for memory cells corresponding to unselected bit lines, unselected source lines, and selected word lines can be 9 volts; and the programming bias voltage for memory cells corresponding to selected bit lines, selected source lines, and unselected word lines can be 6 volts. All of the above unselected memory cells can be effectively suppressed without being affected by programming operations.

[0053] exist Figure 3C In the process, the three-dimensional memory device 300 performs a byte erase operation. The selected memory cell (SMC) is selected to perform the erase operation in a FN tunneling-based manner.

[0054] During the byte erase operation, the substrates (P-type well regions) 320 of transistors M11-M14 and the substrates (P-type well regions) 330 of transistors M21-M24 are all subjected to a negative bias voltage (e.g., -3.5 volts). Furthermore, the bit line switch BLT2 corresponding to the selected memory cell SMC is activated and turned on. The remaining bit line switches BLT0, BLT1, and BLT3 are turned off. Bit line switch BLT2 provides a positive first voltage to the bit line LBL2 corresponding to the selected memory cell SMC based on the voltage on the shared bit line GBL. For example, if the voltage on the shared bit line GBL is equal to 10.5 volts, based on the volume effect, bit line switch BLT2 can provide a first voltage of, for example, 7.5 volts to bit line LBL2.

[0055] Furthermore, the source line switch SLT2 corresponding to the selected memory cell SMC is set to the selected source line switch and is turned off. The remaining source line switches SLT0, SLT1, and SLT3 are turned on. Here, the voltage on the common source line CSL is, for example, equal to -3.5 volts. The turned-on source line switches SLT0, SLT1, and SLT3 can each provide a negative second voltage (for example, equal to -3.5 volts) to the source lines LSL0, LSL1, and LSL3. Here, the source line LSL2 is in a floating state.

[0056] Furthermore, the word line voltage on word line WL0_0 corresponding to the selected memory cell SMC can be set to -12.5 volts, and the word line voltages on the remaining word lines WL1_0, WL1_1, and WL0_1 can be set to 1.5 volts. In this way, the selected memory cell SMC can withstand an erase bias voltage of up to -20 volts (the voltage difference between the word line and bit line (or source line) corresponding to the memory cell during the erase operation), effectively performing the erase operation.

[0057] For other unselected memory cells, the erase bias voltage for memory cells corresponding to unselected bit lines, unselected source lines, and unselected word lines can be 5 volts; the erase bias voltage for memory cells corresponding to unselected bit lines, unselected source lines, and selected word lines can be -9 volts; and the erase bias voltage for memory cells corresponding to selected bit lines, selected source lines, and unselected word lines can be -6 volts. All of the above unselected memory cells can be effectively suppressed without being affected by the erase operation.

[0058] exist Figure 3D In this process, the three-dimensional memory device 300 performs a block erasure operation. Multiple memory cells in the selected memory cell block (SMB) are simultaneously selected to perform the erasure operation.

[0059] During the block erasure operation, the substrate (P-type well region) 320 of transistors M11-M14 and the substrate (P-type well region) 330 of transistors M21-M24 are both subjected to a 0-volt bias voltage. The voltage on the common bit line GBL and the common source line CSL can be approximately 13 volts.

[0060] In addition, source line switches SLT0-SLT3 and bit line switches BLT0-BLT3 are all turned on. Due to the floor effect, the voltages on source lines LSL0-LSL3 and bit lines LBL0-LBL3 are all positive 10 volts.

[0061] Furthermore, the word line voltages on word lines WL0_0 and WL0_1 of the selected memory cell block SMB can be set to -10 volts, while the word line voltages on the remaining word lines WL1_0 and WL1_1 can be set to 4 volts. This allows the memory cells in the selected memory cell block SMB to withstand erase bias voltages up to -20 volts and effectively perform the erase operation. The remaining memory cells that are not erased can withstand erase bias voltages of -6 volts and can be suppressed without being affected by the erase operation.

[0062] Please refer to the following: Figures 4A to 4D , Figures 4A to 4D This is a schematic diagram illustrating the access operation of a three-dimensional memory device according to another embodiment of the present disclosure. Figure 4A In the three-dimensional memory device 400, transistors M21 to M24, which serve as source line switches SLT0 to SLT3, are P-type transistors, while transistors M11 to M14, which serve as bit line switches BLT0 to BLT3, are N-type transistors with a triple-well substrate.

[0063] During the read operation, a bias voltage of 0 volts is applied to the substrate (P-type well region) 420 of transistors M11-M14, and a bias voltage of, for example, 1.8 volts is applied to the substrate (N-type well region) 430 of transistors M21-M24. Corresponding to the selected memory cell SMC, bit line LBL2 and source line LSL2 are the selected bit line and source line, respectively, and bit line switch BLT2 and source line switch SLT2 are the selected bit line switch and source line switch, respectively, and are turned on. Bit line switches BLT0, BLT1, BLT3 and source line switches SLT0, SLT1, SLT3 are turned off. At this time, the voltage on the common bit line GBL can be equal to a first voltage, and the turned-on bit line switch BLT2 can provide the first voltage to the bit line LBL2 of the selected memory cell SMC. Additionally, at this time, the voltage on the common source line CSL is equal to a second voltage, and the turned-on source line switch SLT2 can provide the second voltage to the source line LSL2 corresponding to the selected memory cell SMC. In this embodiment, the first voltage can be a positive value and is greater than the second voltage. For example, the first voltage can be 1 volt, and the second voltage can be 0 volts.

[0064] On the other hand, the word line electrical signal on word line WL0_0 corresponding to the selected memory cell SMC can be equal to the read voltage (e.g., 5-7 volts). The word line electrical signals on the remaining word lines WL0_1, WL1_0, and WL1_1 that are not corresponding to the selected memory cell SMC can be equal to 0 volts.

[0065] In addition, since bit line switches BLT0, BLT1, BLT3 and source line switches SLT0, SLT1, SLT3 are all in the open state, bit lines LBL0, LBL1, LBL3 and source lines LSL0, LSL1, LSL3 are all floating to the ground voltage.

[0066] The selected memory cell SMC can transmit current based on the stored data, and this current is transmitted to the sense amplifier (not shown) via bit line LBL2. The sense amplifier can convert the current supplied by the selected memory cell SMC into a voltage signal and compare the voltage signal with a reference voltage to sense the data stored in the selected memory cell SMC.

[0067] exist Figure 4B In this process, the three-dimensional memory device 400 performs a programming operation. It adjusts the threshold voltage of the selected memory cell's SMC using FN tunneling (Fowler-Nordheim tunneling) and then performs the programming operation.

[0068] During the programming process, a negative bias voltage (e.g., -10.5 volts) is applied to the substrate (P-type well region) 420 of transistors M11-M14, while a positive bias voltage (e.g., 3.5 volts) is applied to the substrate (N-type well region) 430 of transistors M21-M24. Furthermore, bit line switch BLT2 corresponding to the selected memory cell SMC is activated and turned on. The remaining bit line switches BLT0, BLT1, and BLT3 are turned off. Bit line switch BLT2 provides a negative first voltage to the bit line LBL2 corresponding to the selected memory cell SMC. This first voltage is, for example, -10.5 volts. Additionally, source line switch SLT2 corresponding to the selected memory cell SMC is set to be activated and turned off. The remaining source line switches SLT0, SLT1, and SLT3 are turned on. The activated source line switches SLT0, SLT1, and SLT3 provide a positive second voltage of approximately 3.5 volts to the source lines LSL0, LSL1, and LSL3. This second voltage serves as an inhibit voltage. Here, source line LSL2 is in a floating state.

[0069] Furthermore, the word line voltage on word line WL0_0 corresponding to the selected memory cell SMC can be set to 12.5 volts, while the word line voltages on the remaining word lines WL1_0, WL1_1, and WL0_1 can be set to -1.5 volts. In this way, the selected memory cell SMC can withstand a programming bias voltage of up to 23 volts (the voltage difference between the word line and bit line (or source line) corresponding to the memory cell during programming), effectively executing the programming operation.

[0070] Regarding other unselected memory cells, the programming bias voltage for memory cells corresponding to unselected bit lines, unselected source lines, and unselected word lines can be -5 volts; the programming bias voltage for memory cells corresponding to unselected bit lines, unselected source lines, and selected word lines can be 9 volts; and the programming bias voltage for memory cells corresponding to selected bit lines, selected source lines, and unselected word lines can be 9 volts. All of the above unselected memory cells can be effectively suppressed without being affected by programming operations.

[0071] exist Figure 4C In the process, the three-dimensional memory device 400 performs a byte erase operation. The selected memory cell (SMC) is selected to perform the erase operation in a FN tunneling-based manner.

[0072] During the byte erase operation, a negative bias voltage (e.g., -6.5 volts) is applied to the substrate (P-type well region) 420 of transistors M11-M14, and a positive bias voltage (e.g., 7.5 volts) is applied to the substrate (N-type well region) 430 of transistors M21-M24. Furthermore, bit line switch BLT2 corresponding to the selected memory cell SMC is turned off. The remaining bit line switches BLT0, BLT1, and BLT3 are turned on. Bit line switches BLT0, BLT1, and BLT3 provide a positive first voltage to the bit lines LBL0, LBL1, and LBL3 corresponding to the unselected memory cells based on the voltage on the shared bit line GBL. The voltage on the shared bit line GBL is, for example, equal to -6.5 volts. Bit line switches BLT0, BLT1, and BLT3 can provide a negative first voltage, for example, equal to -6.5 volts, to the bit lines LBL0, LBL1, and LBL3. Bit line LBL2 is in a floating state.

[0073] Furthermore, the source line switch SLT2 corresponding to the selected memory cell SMC is set to the selected source line switch and is turned on. The remaining source line switches SLT0, SLT1, and SLT3 are turned off. Here, the voltage on the common source line CSL is, for example, equal to 7.5 volts. The turned-on source line switch SLT2 can provide a second voltage (equal to 7.5 volts) to the source line LSL2. Here, source lines LSL0, LSL1, and LSL3 are in a floating state.

[0074] Furthermore, the word line voltage on word line WL0_0 corresponding to the selected memory cell SMC can be set to -12.5 volts, and the word line voltages on the remaining word lines WL1_0, WL1_1, and WL0_1 can be set to 1.5 volts. In this way, the selected memory cell SMC can withstand an erase bias voltage of up to -20 volts (the voltage difference between the word line and bit line (or source line) corresponding to the memory cell during the erase operation), effectively performing the erase operation.

[0075] Regarding other unselected memory cells, the erase bias voltage for memory cells corresponding to unselected bit lines, unselected source lines, and unselected word lines can be 8 volts; the erase bias voltage for memory cells corresponding to unselected bit lines, unselected source lines, and selected word lines can be -6 volts; and the erase bias voltage for memory cells corresponding to selected bit lines, selected source lines, and unselected word lines can be -6 volts. All of the above unselected memory cells can be effectively suppressed without being affected by the erase operation.

[0076] exist Figure 4D In this process, the three-dimensional memory device 400 performs a block erasure operation. Multiple memory cells in the selected memory cell block (SMB) are simultaneously selected to perform the erasure operation.

[0077] During the block erase operation, the substrate (P-type well region) 420 of transistors M11-M14 can be biased with a voltage of 0 volts. The substrate (N-type well region) 430 of transistors M21-M24 can be biased with a voltage of 10 volts. The voltage on the common bit line GBL can be approximately 13 volts, and the voltage on the common source line CSL can be 10 volts.

[0078] Furthermore, source line switches SLT0-SLT3 and bit line switches BLT0-BLT3 are all turned on. The voltage across source lines LSL0-LSL3 is a positive 10 volt. Also, due to the floor effect, the voltage across bit lines LBL0-LBL3 can also be a positive 10 volt.

[0079] Furthermore, the word line voltages on word lines WL0_0 and WL0_1 of the selected memory cell block SMB can be set to -10 volts, while the word line voltages on the remaining word lines WL1_0 and WL1_1 can be set to 4 volts. This allows the memory cells in the selected memory cell block SMB to withstand erase bias voltages up to -20 volts and effectively perform the erase operation. The remaining memory cells that are not erased can withstand erase bias voltages of -6 volts and can be suppressed without being affected by the erase operation.

[0080] Please refer to the following: Figures 5A to 5D , Figures 5A to 5D This is a schematic diagram illustrating the access operation of a three-dimensional memory device according to another embodiment of the present disclosure. Figure 5A In the three-dimensional memory device 500, transistors M21 to M24, which serve as source line switches SLT0 to SLT3, are N-type transistors with a triple-well substrate, while transistors M11 to M14, which serve as bit line switches BLT0 to BLT3, are P-type transistors.

[0081] During the read operation, a bias voltage of 1.8 volts is applied to the substrate (N-type well region) 420 of transistors M11-M14, and a bias voltage of, for example, 0 volts is applied to the substrate (P-type well region) 430 of transistors M21-M24. Corresponding to the selected memory cell SMC, bit line LBL2 and source line LSL2 are the selected bit line and source line, respectively, and bit line switch BLT2 and source line switch SLT2 are the selected bit line switch and source line switch, respectively, and are turned on. Bit line switches BLT0, BLT1, BLT3 and source line switches SLT0, SLT1, SLT3 are turned off. At this time, the voltage on the common bit line GBL can be equal to a first voltage, and the turned-on bit line switch BLT2 can provide the first voltage to the bit line LBL2 of the selected memory cell SMC. Additionally, at this time, the voltage on the common source line CSL is equal to a second voltage, and the turned-on source line switch SLT2 can provide the second voltage to the source line LSL2 corresponding to the selected memory cell SMC. In this embodiment, the first voltage can be a positive value and is greater than the second voltage. For example, the first voltage can be 1 volt, and the second voltage can be 0 volts.

[0082] On the other hand, the word line electrical signal on word line WL0_0 corresponding to the selected memory cell SMC can be equal to the read voltage (e.g., 5-7 volts). The word line electrical signals on the remaining word lines WL0_1, WL1_0, and WL1_1 that are not corresponding to the selected memory cell SMC can be equal to 0 volts.

[0083] In addition, since bit line switches BLT0, BLT1, BLT3 and source line switches SLT0, SLT1, SLT3 are all in the open state, bit lines LBL0, LBL1, LBL3 and source lines LSL0, LSL1, LSL3 are all floating to the ground voltage.

[0084] The selected memory cell SMC can transmit current based on the stored data, and this current is transmitted to the sense amplifier (not shown) via bit line LBL2. The sense amplifier can convert the current supplied by the selected memory cell SMC into a voltage signal and compare the voltage signal with a reference voltage to sense the data stored in the selected memory cell SMC.

[0085] exist Figure 5B In this process, the three-dimensional memory device 500 performs a programming operation. It adjusts the threshold voltage of the selected memory cell's SMC using FN tunneling (Fowler-Nordheim tunneling) and then performs the programming operation.

[0086] During the programming process, a positive bias voltage (e.g., 3.5 volts) is applied to the substrate (N-type well region) 420 of transistors M11-M14, and a negative bias voltage (e.g., -10.5 volts) is applied to the substrate (P-type well region) 430 of transistors M21-M24. Furthermore, bit line switch BLT2 corresponding to the selected memory cell SMC is selected and turned off. The remaining bit line switches BLT0, BLT1, and BLT3 are turned on. Bit line switches BLT0, BLT1, and BLT3 provide a positive first voltage to the bit lines LBL0, LBL1, and LBL3 corresponding to the unselected memory cells. This first voltage is, for example, 3.5 volts. Additionally, source line switch SLT2 corresponding to the selected memory cell SMC is set to selected and turned on. The remaining source line switches SLT0, SLT1, and SLT3 are turned off. The activated source line switch SLT2 can provide a second voltage (e.g., -10.5 volts) to the source line LSL2, which is approximately equal to a negative value. The aforementioned first voltage serves as an inhibit voltage. Here, the bit line LBL2 is in a floating state.

[0087] Furthermore, the word line voltage on word line WL0_0 corresponding to the selected memory cell SMC can be set to 12.5 volts, while the word line voltages on the remaining word lines WL1_0, WL1_1, and WL0_1 can be set to -1.5 volts. In this way, the selected memory cell SMC can withstand a programming bias voltage of up to 23 volts (the voltage difference between the word line and bit line (or source line) corresponding to the memory cell during programming), effectively executing the programming operation.

[0088] Regarding other unselected memory cells, the programming bias voltage for memory cells corresponding to unselected bit lines, unselected source lines, and unselected word lines can be -5 volts; the programming bias voltage for memory cells corresponding to unselected bit lines, unselected source lines, and selected word lines can be 9 volts; and the programming bias voltage for memory cells corresponding to selected bit lines, selected source lines, and unselected word lines can be 9 volts. All of the above unselected memory cells can be effectively suppressed without being affected by programming operations.

[0089] exist Figure 5C In the process, the three-dimensional memory device 500 performs a byte erase operation. The selected memory cell (SMC) is selected to perform the erase operation in a FN tunneling-based manner.

[0090] During the byte erase operation, a positive bias voltage (e.g., 7.5 volts) is applied to the substrates (N-type well regions) 420 of transistors M11-M14, while a negative bias voltage (e.g., -4.5 volts) is applied to the substrates (P-type well regions) 430 of transistors M21-M24. Furthermore, the bit line switch BLT2 corresponding to the selected memory cell SMC is activated and turned on. The remaining bit line switches BLT0, BLT1, and BLT3 are deactivated. Bit line switch BLT2 provides a positive first voltage to the bit line LBL2 corresponding to the selected memory cell SMC based on the voltage on the shared bit line GBL. The voltage on the shared bit line GBL is, for example, equal to 7.5 volts. Bit line switch BLT2 can provide a positive first voltage (e.g., equal to 7.5 volts) to bit line LBL2. Bit lines LBL0, LBL1, and LBL3 are in a floating state.

[0091] Furthermore, the source line switch SLT2 corresponding to the selected memory cell SMC is set to the selected source line switch and is turned off. The remaining source line switches SLT0, SLT1, and SLT3 are turned on. Here, the voltage on the common source line CSL is, for example, equal to -4.5 volts. The turned-on source line switches SLT0, SLT1, and SLT3 can provide a negative second voltage (for example, equal to -4.5 volts) to the source lines LSL0, LSL1, and LSL3 corresponding to the unselected memory cells. Here, source line LSL2 is in a floating state.

[0092] Furthermore, the word line voltage on word line WL0_0 corresponding to the selected memory cell SMC can be set to -12.5 volts, and the word line voltages on the remaining word lines WL1_0, WL1_1, and WL0_1 can be set to 1.5 volts. In this way, the selected memory cell SMC can withstand an erase bias voltage of up to -20 volts (the voltage difference between the word line and bit line (or source line) corresponding to the memory cell during the erase operation), effectively performing the erase operation.

[0093] Regarding other unselected memory cells, the erase bias voltage for memory cells corresponding to unselected bit lines, unselected source lines, and unselected word lines can be 6 volts; the erase bias voltage for memory cells corresponding to unselected bit lines, unselected source lines, and selected word lines can be -8 volts; and the erase bias voltage for memory cells corresponding to selected bit lines, selected source lines, and unselected word lines can be -6 volts. All of the above unselected memory cells can be effectively suppressed without being affected by the erase operation.

[0094] exist Figure 5D In this process, the three-dimensional memory device 500 performs a block erasure operation. Multiple memory cells in the selected memory cell block (SMB) are simultaneously selected to perform the erasure operation.

[0095] During the block erase operation, the substrate (N-type well region) 420 of transistors M11-M14 can be biased with a voltage of 10 volts. The substrate (P-type well region) 430 of transistors M21-M24 can be biased with a voltage of 0 volts. The voltage on the common bit line GBL can be approximately 10 volts, and the voltage on the common source line CSL can be 13 volts.

[0096] Furthermore, source line switches SLT0-SLT3 and bit line switches BLT0-BLT3 are all turned on. The voltage across source lines LSL0-LSL3 is a positive 10 volt. Also, due to the floor effect, the voltage across bit lines LBL0-LBL3 can also be a positive 10 volt.

[0097] Furthermore, the word line voltages on word lines WL0_0 and WL0_1 of the selected memory cell block SMB can be set to -10 volts, while the word line voltages on the remaining word lines WL1_0 and WL1_1 can be set to 4 volts. This allows the memory cells in the selected memory cell block SMB to withstand erase bias voltages up to -20 volts and effectively perform the erase operation. The remaining memory cells that are not erased can withstand erase bias voltages of -6 volts and can be suppressed without being affected by the erase operation.

[0098] Please refer to the following: Figures 6A to 6D , Figures 6A to 6D This is a schematic diagram illustrating the access operation of a three-dimensional memory device according to another embodiment of the present disclosure. Figure 6A In the three-dimensional memory device 600, transistors M21 to M24, which serve as source line switches SLT0 to SLT3, and transistors M11 to M14, which serve as bit line switches BLT0 to BLT3, are all P-type transistors.

[0099] During the read operation, a bias voltage of 1.8 volts is applied to the substrate (N-type well region) 420 of transistors M11-M14, and a bias voltage of 1.8 volts can also be applied to the substrate (N-type well region) 430 of transistors M21-M24. Corresponding to the selected memory cell SMC, bit line LBL2 and source line LSL2 are the selected bit line and source line, respectively, and bit line switch BLT2 and source line switch SLT2 are the selected bit line switch and source line switch, respectively, and are turned on. Bit line switches BLT0, BLT1, BLT3 and source line switches SLT0, SLT1, SLT3 are turned off. At this time, the voltage on the common bit line GBL can be equal to a first voltage, and the turned-on bit line switch BLT2 can provide the first voltage to the bit line LBL2 of the selected memory cell SMC. Additionally, at this time, the voltage on the common source line CSL is equal to the second voltage, and the turned-on source line switch SLT2 can provide the second voltage to the source line LSL2 corresponding to the selected memory cell SMC. In this embodiment, the first voltage can be a positive value and is greater than the second voltage. For example, the first voltage can be 1 volt, and the second voltage can be 0 volts.

[0100] On the other hand, the word line electrical signal on word line WL0_0 corresponding to the selected memory cell SMC can be equal to the read voltage (e.g., 5-7 volts). The word line electrical signals on the remaining word lines WL0_1, WL1_0, and WL1_1 that are not corresponding to the selected memory cell SMC can be equal to 0 volts.

[0101] In addition, since bit line switches BLT0, BLT1, BLT3 and source line switches SLT0, SLT1, SLT3 are all in the open state, bit lines LBL0, LBL1, LBL3 and source lines LSL0, LSL1, LSL3 are all floating to the ground voltage.

[0102] The selected memory cell SMC can transmit current based on the stored data, and this current is transmitted to the sense amplifier (not shown) via bit line LBL2. The sense amplifier can convert the current supplied by the selected memory cell SMC into a voltage signal and compare the voltage signal with a reference voltage to sense the data stored in the selected memory cell SMC.

[0103] exist Figure 6B In this process, the three-dimensional memory device 600 performs a programming operation. It adjusts the threshold voltage of the selected memory cell's SMC using FN tunneling (Fowler-Nordheim tunneling) and then performs the programming operation.

[0104] During programming, the substrates (N-type well regions) 420 of transistors M11-M14 and transistors M21-M24 can be subjected to a positive bias voltage (e.g., 3.5 volts). Furthermore, bit line switch BLT2 corresponding to the selected memory cell SMC is activated and turned on. The remaining bit line switches BLT0, BLT1, and BLT3 are turned off. Bit line switch BLT2 provides a positive first voltage to the bit line LBL2 corresponding to the selected memory cell SMC. This first voltage is, for example, -7.5 volts. Additionally, source line switch SLT2 corresponding to the selected memory cell SMC is set to activate and turned off. The remaining source line switches SLT0, SLT1, and SLT3 are turned on. The turned-on source line switches SLT0, SLT1, and SLT3 provide a second voltage (e.g., equal to 3.5 volts) of approximately equal positive value to the source lines LSL0, LSL1, and LSL3. The second voltage mentioned above is used as an inhibit voltage. Here, the source line LSL2 is in a floating state.

[0105] Furthermore, the word line voltage on word line WL0_0 corresponding to the selected memory cell SMC can be set to 12.5 volts, while the word line voltages on the remaining word lines WL1_0, WL1_1, and WL0_1 can be set to -1.5 volts. In this way, the selected memory cell SMC can withstand a programming bias voltage of up to 20 volts (the voltage difference between the word line and bit line (or source line) corresponding to the memory cell during programming), effectively executing the programming operation.

[0106] Regarding other unselected memory cells, the programming bias voltage for memory cells corresponding to unselected bit lines, unselected source lines, and unselected word lines can be -5 volts; the programming bias voltage for memory cells corresponding to unselected bit lines, unselected source lines, and selected word lines can be 9 volts; and the programming bias voltage for memory cells corresponding to selected bit lines, selected source lines, and unselected word lines can be 6 volts. All of the above unselected memory cells can be effectively suppressed without being affected by programming operations.

[0107] exist Figure 6C In the process, the three-dimensional memory device 600 performs a byte erase operation. The selected memory cell (SMC) is selected to perform the erase operation in a FN tunneling-based manner.

[0108] During the byte erase operation, a positive bias voltage (e.g., 7.5 volts) is applied to the substrates (N-type well regions) 420 and 430 of transistors M11-M14 and M21-M24. Furthermore, the bit line switch BLT2 corresponding to the selected memory cell SMC is activated and turned on. The remaining bit line switches BLT0, BLT1, and BLT3 are deactivated. Bit line switch BLT2 provides a positive first voltage to the bit line LBL2 corresponding to the selected memory cell SMC based on the voltage on the shared bit line GBL. The voltage on the shared bit line GBL is, for example, equal to 7.5 volts. Bit line switch BLT2 can provide a positive first voltage (e.g., equal to 7.5 volts) to bit line LBL2. Bit lines LBL0, LBL1, and LBL3 are in a floating state.

[0109] Furthermore, the source line switch SLT2 corresponding to the selected memory cell SMC is set as the selected source line switch and is turned off. The remaining source line switches SLT0, SLT1, and SLT3 are turned on. Here, the voltage on the common source line CSL is, for example, equal to -6.5 volts. Due to the floor effect, the turned-on source line switches SLT0, SLT1, and SLT3 can provide a negative second voltage (for example, equal to -3.5 volts) to the source lines LSL0, LSL1, and LSL3 corresponding to the unselected memory cells. Here, source line LSL2 is in a floating state.

[0110] Furthermore, the word line voltage on word line WL0_0 corresponding to the selected memory cell SMC can be set to -12.5 volts, and the word line voltages on the remaining word lines WL1_0, WL1_1, and WL0_1 can be set to 1.5 volts. In this way, the selected memory cell SMC can withstand an erase bias voltage of up to -20 volts (the voltage difference between the word line and bit line (or source line) corresponding to the memory cell during the erase operation), effectively performing the erase operation.

[0111] For other unselected memory cells, the erase bias voltage for memory cells corresponding to unselected bit lines, unselected source lines, and unselected word lines can be 5 volts; the erase bias voltage for memory cells corresponding to unselected bit lines, unselected source lines, and selected word lines can be -9 volts; and the erase bias voltage for memory cells corresponding to selected bit lines, selected source lines, and unselected word lines can be -6 volts. All of the above unselected memory cells can be effectively suppressed without being affected by the erase operation.

[0112] exist Figure 6D In this process, the three-dimensional memory device 600 performs a block erasure operation. Multiple memory cells in the selected memory cell block (SMB) are simultaneously selected to perform the erasure operation.

[0113] During the block erasure operation, the substrates (N-type well regions) 420 and 430 of transistors M11-M14 and M21-M24 can all be biased with a voltage of 10 volts. The voltages on the common bit line GBL and the common source line CSL can both be approximately 10 volts.

[0114] In addition, source line switches SLT0-SLT3 and bit line switches BLT0-BLT3 are all turned on. The voltage on source lines LSL0-LSL3 is a positive 10 volt. The voltage on bit lines LBL0-LBL3 can also be a positive 10 volt.

[0115] Furthermore, the word line voltages on word lines WL0_0 and WL0_1 of the selected memory cell block SMB can be set to -10 volts, while the word line voltages on the remaining word lines WL1_0 and WL1_1 can be set to 4 volts. This allows the memory cells in the selected memory cell block SMB to withstand erase bias voltages up to -20 volts and effectively perform the erase operation. The remaining memory cells that are not erased can withstand erase bias voltages of -6 volts and can be suppressed without being affected by the erase operation.

[0116] It should be noted that the various voltage values ​​mentioned in the foregoing embodiments are merely for illustrative purposes and are not intended to limit the scope of this disclosure. Those skilled in the art can set the relevant voltage values ​​based on the process parameters of the integrated circuit and the voltage range of the operating power supply of the three-dimensional memory device; there are no particular limitations.

[0117] In summary, in the three-dimensional memory device of this disclosure, the bit line switches and word line switches can be constructed using P-type transistors or N-type transistors with a triple-well substrate. By applying appropriate substrate voltages, the bit line switches and word line switches can utilize positive or negative bit line voltages and source line voltages. In this way, during memory cell access operations, appropriate voltages can be effectively applied to selected and unselected memory cells, ensuring that access operations are performed correctly.

Claims

1. A three-dimensional memory device, comprising: Multiple memory cell arrays, each having a corresponding multiple rows of memory cells, are coupled to multiple source lines and multiple bit lines, respectively. Multiple bit line switches are each composed of multiple first transistors. The first terminals of these first transistors are coupled to a common bit line, and the second terminals of these first transistors are respectively coupled to these bit lines. as well as Multiple source-line switches are each composed of multiple second transistors. The first terminal of each of these second transistors is coupled to a common source line, and the second terminal of each of these second transistors is coupled to the respective source lines. Among them, the first transistors are P-type transistors or N-type transistors with a triple-well substrate, and the second transistors are P-type transistors or N-type transistors with a triple-well substrate. When these second transistors are N-type transistors with a triple-well substrate, each of the second transistors includes: A type N deep well region; A P-type well region is formed on the N-type deep well region; An N-type well region is formed on the side of the P-type well region; A first N-type heavily doped region, a second N-type heavily doped region, and a P-type heavily doped region are formed on the P-type well region. The first N-type heavily doped region and the second N-type heavily doped region form a channel, and the P-type heavily doped region is used to receive a bias voltage. The first N-type heavily doped region, the second N-type heavily doped region, and the P-type heavily doped region are isolated by an insulating structure. A gate structure is formed on the first N-type heavily doped region, the second N-type heavily doped region, and the channel.

2. The three-dimensional memory device of claim 1, wherein the first transistors are controlled by a plurality of first selection signals to be turned on or off, and the second transistors are controlled by a plurality of second selection signals to be turned on or off.

3. The three-dimensional memory device according to claim 1, wherein the on / off states of each bit line switch and each source line switch corresponding to the same memory cell row are the same.

4. The three-dimensional memory device according to claim 1, wherein the memory cell array is divided into multiple memory cell columns, each of which receives multiple word line signals.

5. The three-dimensional memory device according to claim 4, wherein during the read operation, a selection bit line switch corresponding to a selected memory cell is turned on and provides a first voltage to the selected memory cell, and a selection source line switch corresponding to the selected memory cell is turned on and provides a second voltage to the selected memory cell, wherein the first voltage is greater than the second voltage.

6. The three-dimensional memory device according to claim 4, wherein each of the first transistors and each of the second transistors are N-type transistors having a triple-well substrate, and during programming, a selected bit line switch corresponding to a selected memory cell is turned on and provides a negative first voltage to the selected memory cell, a selected source line switch corresponding to the selected memory cell is turned off, and the remaining plurality of unselected source line switches are turned on and provide a positive second voltage to the plurality of unselected memory cells, wherein among these word line signals, the selected character signal corresponding to the selected memory cell is a positive third voltage, and the remaining plurality of unselected character signals are a negative fourth voltage.

7. The three-dimensional memory device of claim 4, wherein each of the first transistors and each of the second transistors are N-type transistors having a triple-well substrate, and during the byte erase operation, a selected bit line switch corresponding to a selected memory cell is turned on and a first voltage of a positive value is provided to the selected memory cell, a selected source line switch corresponding to the selected memory cell is turned off, and a plurality of unselected source line switches are turned on and a second voltage of a negative value is provided to the plurality of unselected memory cells, wherein among these word line signals, the selected character signal corresponding to the selected memory cell is a third voltage of a negative value, and the plurality of unselected character signals are a fourth voltage of a positive value.

8. The three-dimensional memory device of claim 4, wherein each of the first transistors and each of the second transistors are N-type transistors having a triple-well substrate, and during block erasure, the bit line switches and the source line switches are turned on and respectively provide a positive first voltage to the memory cells, a negative second voltage corresponding to multiple selected character signals of a selected memory cell block, and a positive third voltage corresponding to multiple selected character signals of at least one unselected memory cell block.

9. The three-dimensional memory device of claim 4, wherein each of the first transistors is an N-type transistor having a triple-well substrate, each of the second transistors is a P-type transistor, and during programming, a selected bit line switch corresponding to a selected memory cell is turned on and provides a negative first voltage to the selected memory cell, a selected source line switch corresponding to the selected memory cell is turned off, and a plurality of unselected source line switches are turned on and provide a positive second voltage to the plurality of unselected memory cells, wherein among these word line signals, the selected character signal corresponding to the selected memory cell is a positive third voltage, and the plurality of unselected character signals are negative fourth voltages.

10. The three-dimensional memory device of claim 4, wherein each of the first transistors is an N-type transistor having a triple-well substrate, each of the second transistors is a P-type transistor, and during the byte erase operation, a selected bit line switch corresponding to a selected memory cell is turned off, a plurality of unselected bit line switches are turned on and provide a negative first voltage to the plurality of unselected memory cells, a selected source line switch corresponding to the selected memory cell is turned on and provides a positive second voltage to the selected memory cell, wherein among these word line signals, the selected character signal corresponding to the selected memory cell is a negative third voltage, and the plurality of unselected character signals are a positive fourth voltage.

11. The three-dimensional memory device of claim 4, wherein each of the first transistors is an N-type transistor having a triple-well substrate, each of the second transistors is a P-type transistor, and during block erasure, the bit line switches and the source line switches are all turned on, providing a positive first voltage to the memory cells, a negative second voltage corresponding to multiple selected character signals of a selected memory cell block, and a positive third voltage corresponding to multiple selected character signals of at least one unselected memory cell block.

12. The three-dimensional memory device of claim 4, wherein each of the first transistors is a P-type transistor, each of the second transistors is an N-type transistor having a triple-well substrate, and during programming, a selected bit line switch corresponding to a selected memory cell is turned on and provides a positive first voltage to the selected memory cell, a selected source line switch corresponding to the selected memory cell is turned on and provides a negative second voltage to the selected memory cell, wherein among these word line signals, the selected character signal corresponding to the selected memory cell is a positive third voltage, and a plurality of unselected character signals are negative fourth voltages.

13. The three-dimensional memory device of claim 4, wherein each of the first transistors is a P-type transistor, each of the second transistors is an N-type transistor having a triple-well substrate, and during the byte erase operation, a selected bit line switch corresponding to a selected memory cell is turned on and a first voltage of a positive value is provided to the selected memory cell, a selected source line switch corresponding to the selected memory cell is turned off, and a plurality of unselected source line switches are turned on and a second voltage of a negative value is provided to a plurality of unselected memory cells, wherein among these word line signals, the selected character signal corresponding to the selected memory cell is a third voltage of a negative value, and the plurality of unselected character signals are a fourth voltage of a positive value.

14. The three-dimensional memory device of claim 4, wherein each of the first transistors is a P-type transistor, each of the second transistors is an N-type transistor having a triple-well substrate, and during block erasure, the bit line switches and the source line switches are all turned on, and respectively provide a positive first voltage to the memory cells, a negative second voltage corresponding to multiple selected character signals of a selected memory cell block, and a positive third voltage corresponding to multiple selected character signals of at least one unselected memory cell block.

15. The three-dimensional memory device of claim 4, wherein the first transistors and the second transistors are all P-type transistors, and during programming, a selected bit line switch corresponding to a selected memory cell is turned on and provides a negative first voltage to the selected memory cell, a selected source line switch corresponding to the selected memory cell is turned off, and a plurality of unselected source line switches are turned on and provide a positive second voltage to the plurality of unselected memory cells, wherein among these word line signals, the selected character signal corresponding to the selected memory cell is a positive third voltage, and the plurality of unselected character signals are a negative fourth voltage.

16. The three-dimensional memory device of claim 4, wherein the first transistors and the second transistors are all P-type transistors, and during the byte erase operation, a selected bit line switch corresponding to a selected memory cell is turned on and a first voltage of positive value is provided to the selected memory cell, a selected source line switch corresponding to the selected memory cell is turned off, and a plurality of unselected source line switches are turned on and a second voltage of negative value is provided to a plurality of unselected memory cells, wherein among these word line signals, the selected character signal corresponding to the selected memory cell is a third voltage of negative value, and the plurality of unselected character signals are a fourth voltage of positive value.

17. The three-dimensional memory device of claim 4, wherein the first transistors and the second transistors are all P-type transistors, and during block erasure, the bit line switches and the source line switches are all turned on and respectively provide a positive first voltage to the memory cells, a negative second voltage corresponding to multiple selected character signals of a selected memory cell block, and a positive third voltage corresponding to multiple selected character signals of at least one unselected memory cell block.

18. The three-dimensional memory device of claim 1, wherein the memory cell array is an AND gate flash memory cell array.

19. The three-dimensional memory device of claim 1, wherein each of the source lines is coupled to the common source line only through a corresponding source line switch, and each of the bit lines is coupled to the common bit line only through a corresponding bit line switch.

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