Three-dimensional memory devices

Abstract

The present invention provides a three-dimensional memory device, such as a three-dimensional AND flash memory device. The three-dimensional memory device includes a plurality of word lines, a plurality of first switches, a plurality of second switches, and N conductive layers, where N is a positive integer greater than 1. The word lines are divided into a plurality of word line groups. The first switches receive a common word line voltage. The second switches receive a reference ground voltage. The first word line group connects to the first conductive layer via the second conductive layer. The i-th word line group, in turn, connects to the first conductive layer via the i+1-th conductive layer to the second conductive layer, where N>i>1.

Description

Technical Field

[0001] The present invention relates to a three-dimensional memory device, and more particularly to a layout structure of word lines of the three-dimensional memory device. Background Art

[0002] In three-dimensional memory devices, as circuit dimensions increase, the layout of memory circuits becomes increasingly complex. In particular, the length of the wordline signal transmission path is a crucial factor in memory device access performance. Especially with the demand for high-speed access, reducing the capacitance and resistance loads along the wordline signal transmission path is also a crucial factor in improving signal transmission quality.

[0003] Public content

[0004] The present invention provides a three-dimensional memory device which can simplify the complexity of word line layout.

[0005] The three-dimensional memory device of the present invention includes a plurality of word lines, a plurality of first switches, a plurality of second switches, and N conductive layers, where N is a positive integer greater than 1. The word lines are divided into a plurality of word line groups. The first switches receive a common word line voltage. The second switches receive a reference ground voltage. The transmission wires of the first conductive layer are connected to the transmission wires of the second conductive layer. The transmission wires of the first conductive layer are coupled to the first switches and the second switches, respectively. The first word line group is connected to the first conductive layer via the second conductive layer, and the i-th word line group is sequentially connected to the first conductive layer via the i+1-th conductive layer to the second conductive layer, where N>i>1.

[0006] Based on the above, the three-dimensional memory device of the present invention divides word lines into multiple word line groups. Each word line group is connected to a corresponding switch via transmission conductors in two or more conductor layers, which are then coupled to a common word line. This grouping effectively simplifies the word line layout, thereby improving the electrical characteristics of the three-dimensional memory device and reducing the required circuit layout area. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 A schematic diagram of a three-dimensional memory device according to an embodiment of the present invention is shown.

[0008] Figure 2 FIG. 1 is a circuit diagram illustrating an implementation of a driver for driving word lines in a three-dimensional memory device according to an embodiment of the present invention.

[0009] Figure 3 FIG. 1 is a circuit diagram illustrating another implementation of a word line driver according to an embodiment of the present invention.

[0010] Figure 4FIG. 1 is a schematic diagram illustrating the layout structure of a three-dimensional memory device according to an embodiment of the present invention.

[0011] Figure 5 FIG. 1 is a top view illustrating a layout structure of a word line driver in a three-dimensional memory device according to an embodiment of the present invention.

[0012] Figure 6 A partial three-dimensional diagram of a transmission line of a three-dimensional memory device according to an embodiment of the present invention is shown.

[0013] Figure 7 FIG. 1 is a schematic diagram illustrating a driving mechanism of a word line in a three-dimensional memory device according to an embodiment of the present invention.

[0014] Figure 8 FIG. 1 is a schematic diagram illustrating a layout path of word lines of a three-dimensional memory device according to an embodiment of the present invention.

[0015] Figure 9 FIG. 4 is a schematic diagram of a memory cell array of a three-dimensional memory device according to an embodiment of the present invention.

[0016] Description of Reference Numerals

[0017] 100, 400, 900: Three-dimensional memory devices

[0018] 200, 311-323, DV1A-DV32A, DV1B-DV32B, 710: Drivers

[0019] 421, 422, 720: Voltage shifter

[0020] 430: Control Logic Circuit

[0021] 510: Well region

[0022] 520: Base

[0023] BLn, BLn+1: bit lines

[0024] BM1~BM4: conductor layer

[0025] CT1, CT2: contact windows

[0026] CW21, CW41, WBM1, WBM2, WBM3-1, WBM3-2, 610, 620: Transmission conductors

[0027] DIR1, DIR2: direction

[0028] GN, GP: Gate structure

[0029] GWL, GWL_[n], GWL_[n+1]: common word line voltage

[0030] HT: line height

[0031] IN: Input signal

[0032] IV: Inverter

[0033] L1~L12, L1A~L32A, L1B~L32B, WL1~WL4: word lines

[0034] M1~M4:Transistors

[0035] M11-1 to M22-1, M11-2 to M22-2: Storage units

[0036] MA1, MA2, 410, 701: memory cell array

[0037] PATH1, PATH2: transmission path

[0038] PG[1], PG[2], PG[3]: control signals

[0039] PGB[1], PGB[2], PGB[3]: reverse control signals

[0040] SLn, SLn+1: Source lines

[0041] SW11~SW112, SW21~SW212: switches

[0042] BV1~BV3, BVE1, BVE2: conductive through-hole structure

[0043] TAV: Through-array conductive structure

[0044] Vss: reference ground voltage

[0045] WGWL: Common word voltage transmission wire

[0046] WH: Line width

[0047] WLG1~WLG3: word line group

[0048] WLs: word line signal

[0049] WVSS: Reference ground voltage transmission conductor DETAILED DESCRIPTION

[0050] Please refer to Figure 1 , Figure 1A schematic diagram illustrates a three-dimensional memory device according to an embodiment of the present invention. The three-dimensional memory device 100 includes a plurality of word lines L1-L12, a plurality of first switches SW11-SW112, a plurality of second switches SW21-SW212, and a plurality of conductive layers BM1-BM4. In this embodiment, the word lines L1-L12 are divided into three word line groups WLG1-WLG3. Word lines L1-L4 belong to word line group WLG1, word lines L2-L8 belong to word line group WLG2, and word lines L9-L12 belong to word line group WLG3. One end of the first switches SW11-SW112 can receive a common word line voltage GWL, and the other end of each of the first switches SW11-SW112 is respectively coupled to a plurality of transmission lines in the first conductive layer BM1. One end of the second switches SW21-SW212 can receive a common reference ground voltage Vss, and the other end of each of the second switches SW21-SW212 is respectively coupled to a plurality of transmission lines in the first conductive layer BM1. Conductive layers BM1-BM4 are sequentially disposed between the first switches SW11-SW112, the second switches SW21-SW212, and the word lines L1-L12. In this embodiment, conductive layers BM1-BM4 may be the bottom metal layer of the integrated circuit. Word lines L1-L12 may be coupled to the memory cell array of the three-dimensional memory device 100 via through array via (TAV) structures.

[0051] Each of the wire layers BM1 to BM4 has a plurality of transmission wires. In this embodiment, the transmission wires in the first wire layer BM1 can extend along the first direction DIR1, and the transmission wires in the remaining wire layers BM2 to BM4 other than the first wire layer BM1 can extend along the second direction DIR2. The first direction DIR1 and the second direction DIR2 are different. The first direction DIR1 and the second direction can be orthogonal to each other. It is worth mentioning that in Figure 1 In the embodiment, the transmission conductors of conductor layers BM2-BM4 can be L-shaped or elongated. For example, transmission conductor CW41 is an elongated transmission conductor, while transmission conductor CW21 is an L-shaped transmission conductor. Regardless of the type of transmission conductor, its rear end extends along the second direction DIR2.

[0052] On the other hand, in this embodiment, the transmission conductors between two adjacent conductor layers can be interconnected via conductive via structures (vias). Specifically, the transmission conductors of conductor layer BM4 and conductor layer BM3 are interconnected via conductive via structure BV1; the transmission conductors of conductor layer BM3 and conductor layer BM2 are interconnected via conductive via structure BV2; and the transmission conductors of conductor layer BM2 and conductor layer BM1 can be interconnected via conductive via structure BV3.

[0053] Please note that in this embodiment, the word lines L1-L12 of different word line groups WLG1-WLG3 have different routing schemes. Specifically, the word lines L1-L4 of the first word line group WLG1 can be directly connected to the second conductive layer BM2 via conductive via structures BV3 and BV2, and then connected to the first conductive layer BM1 via transmission lines and conductive via structures BV1 of the second conductive layer BM2. Specifically, the word lines L1-L4 of the first word line group WLG1 can be directly connected to the conductive via structures BV3 and BV2 through contacts CT1 and CT2, respectively, while passing through the fourth conductive layer BM4 and the third conductive layer BM3. In addition, word lines L5-L8 of the second word line group WLG2 are first directly connected to the transmission wires of the third conductive layer BM3 through contact window CT1 and conductive via structure BV3; then connected to the transmission wires of the second conductive layer BM2 through the transmission wires of the third conductive layer BM3 and conductive via structure BV2; then connected to the transmission wires of the first conductive layer BM1 through the transmission wires of the second conductive layer BM2 and conductive via structure BV1. Word lines L9-L12 of the third word line group WLG3 are directly connected to the transmission wires of the fourth conductive layer BM3; then connected to the transmission wires of the third conductive layer BM3 through conductive via structure BV3; then connected to the transmission wires of the second conductive layer BM2 through the transmission wires of the third conductive layer BM3 and conductive via structure BV2; then connected to the transmission wires of the first conductive layer BM1 through the transmission wires of the second conductive layer BM2 and conductive via structure BV1.

[0054] Of course, in other embodiments of the present invention, the number of word lines, the number of word line groups, and the number of conductive line layers can be different. Figure 1 In terms of configuration details, assuming the number of wiring layers is equal to N (N is a positive integer greater than 1), multiple transmission wires in a first wiring layer are connected to multiple transmission wires in a second wiring layer. The transmission wires in the first wiring layer are respectively coupled to a first switch and a second switch. The first word line group can be connected to the first wiring layer via the second wiring layer. The i-th word line group can sequentially pass through the i+1-th wiring layer to the second wiring layer, and then pass through the second wiring layer to connect to the first wiring layer, where N>i>1.

[0055] In another aspect, the three-dimensional memory device 100 of this embodiment further includes a common word voltage transmission conductor WGWL and a reference ground voltage transmission conductor WVSS. The common word voltage transmission conductor WGWL and the reference ground voltage transmission conductor WVSS may be arranged along a second direction DIR2. The common word voltage transmission conductor WGWL may be coupled to the first switches SW11-SW112 via a conductive via structure BVE1, while the reference ground voltage transmission conductor WVSS may be coupled to the second switches SW21-SW212 via a conductive via structure BVE2. The common word voltage transmission conductor WGWL is used to provide a common word line voltage GWL, while the reference ground voltage transmission conductor WVSS is used to provide a reference ground voltage Vss.

[0056] The first switches SW11-SW112 can each form a plurality of drivers with the second switches SW21-SW212. In this embodiment, the first switches SW11-SW112 are P-type transistors, while the second switches SW21-SW212 are N-type transistors. Each of the first switches SW11-SW112 and the corresponding second switches SW21-SW212 form a complementary metal-oxide-semiconductor (CMOS) architecture, and are used to set the corresponding word lines L1-L12 to a reference ground voltage Vss or a common word line voltage GWL.

[0057] You can refer to this Figure 2 The circuit diagram of one embodiment of a driver for driving a word line in a three-dimensional memory device according to an embodiment of the present invention is shown. The driver 200 includes transistors M1 and M2. Transistor M1 corresponds to Figure 1 One of the first switches SW11 to S112, the transistor M2 corresponds to Figure 1 The first terminal of transistor M1 receives a common wordline voltage GWL. The second terminal of transistor M1 is coupled to the first terminal of transistor M2 and generates a wordline signal WLs. The second terminal of transistor M2 receives a reference ground voltage Vss. The control terminals of transistors M1 and M2 are coupled to each other and receive a control signal PG.

[0058] Re-reference Figure 1 In this embodiment, the first switches SW11-SW112 can be divided into multiple groups (for example, M) for layout, and the second switches SW21-SW212 can be divided into multiple groups (for example, P) for layout. Figure 1 In the example, M = 2 and P = 3. In other embodiments of the present invention, M and P may be other positive integers, and M may be equal to P, without any specific limitation.

[0059] Depend on Figure 1 It can be seen that the embodiments of the present invention divide word lines L1-L12 into word line groups WLG1-WLG3 and sequentially couple each word line group WLG1-WLG3 to a driver via transmission lines spanning from a few to multiple layers. This allows for a neat and simple layout of word lines L1-L12, effectively reducing layout complexity. Furthermore, this grouping approach reduces the number of transmission lines required in the same area and improves the pitch between them, minimizing parasitic effects between signals.

[0060] Please refer to the following Figure 3 , Figure 3 A circuit diagram illustrating another embodiment of a word line driver according to an embodiment of the present invention is shown. Drivers 311-313 are coupled to memory cell array MA1, while drivers 321-323 are coupled to memory cell array MA2. Drivers 311-313 are used to drive word lines L1-L3 of memory cell array MA1, while drivers 321-323 are used to drive word lines L4-L6 of memory cell array MA2.

[0061] Taking the driver 311 as an example, the driver 311 includes three switches formed by three transistors M1 to M3. Among them, the first terminal of the transistor M1 receives the common word line voltage GWL[n+1], the second terminal of the transistor M1 and the first terminal of the transistor M2 are commonly coupled to the word line L1, the control terminals of the transistors M1 and M2 receive the control signal PG[1], and the second terminal of the transistor M2 receives the reference ground voltage Vss. In addition, Figure 2 In a different embodiment, the driver 311 further includes a transistor M3. A first terminal of the transistor M3 receives the common word line voltage GWL[n+1]. A second terminal of the transistor M3 is coupled to the word line L1. A control terminal of the transistor M3 receives a reverse control signal PGB[1]. The reverse control signal PGB[1] is reverse to the control signal PG[1].

[0062] It is worth noting that transistor M1 can be a P-type transistor, while transistors M2 and M3 can both be N-type transistors. When the control signal PG[1] is logic 0, transistor M1 can be turned on and transistor M2 can be turned off, and the voltage on word line L1 is equal to the common word line voltage GWL[n+1]. When the control signal PG[1] is logic 1, transistor M1 can be turned off and transistor M2 can be turned on, and the voltage on word line L1 is equal to the reference ground voltage.

[0063] exist Figure 3In the embodiment, since multiple memory cell arrays MA1 and MA2 can be sequentially selected for access, the common word line voltages GWL_[n] and GWL_[n+1] can be sequentially activated according to the scan order. In the driver 311, if the memory cell array MA1 is not selected, the common word line voltage GWL_[n+1] can be 0 volts. When the control signal PG[1] is logic 0, the word line L1 can be higher than 0 volts due to the body effect of the transistor M1. Therefore, in this embodiment, the transistor M3 is simultaneously turned on according to the reverse control signal PGB[1], so that the word line L1 can be pulled down to 0 volts, and the unselected memory cell array MA1 will not generate read / write interference.

[0064] In this embodiment, drivers 311 and 321 can share the same control signal PG[1] and reverse control signal PGB[1]; drivers 312 and 322 can share the same control signal PG[2] and reverse control signal PGB[2]; and drivers 313 and 323 can share the same control signal PG[3] and reverse control signal PGB[3].

[0065] Incidentally, in this embodiment, the substrate of the transistor M1 may be an N-type well region (Nwell), and the substrates of the transistors M2 and M3 may be P-type deep well regions (PWI).

[0066] Furthermore, in memory devices, the common word line voltages GWL_[n] and GWL_[n+1] typically require a relatively high voltage when enabled. Therefore, voltage shifters (not shown) are often required before drivers 311-323 to generate sufficient common word line voltages GWL_[n] and GWL_[n+1].

[0067] Please refer to the following Figure 4 , Figure 4A schematic diagram illustrates the layout structure of a three-dimensional memory device according to an embodiment of the present invention. In a three-dimensional memory device 400, a memory cell array 410 is coupled to a plurality of word lines L1A-L32A and L1B-L32B. The three-dimensional memory device 400 also includes drivers DV1A-DV32A and DV1B-DV32B, voltage shifters 421 and 422, and a control logic circuit 430. Word lines L1A-L32A and L1B-L32B are disposed on two sides of the three-dimensional memory device 400, respectively. Drivers DV1A-DV32A and DV1B-DV32B are disposed on two sides of the three-dimensional memory device 400, corresponding to the positions of word lines L1A-L32A and L1B-L32B. Drivers DV1A-DV16A and DV17A-DV32A are used to drive word lines L1A-L16A and L17A-L32A, respectively. Drivers DV1B-DV16B and DV17B-DV32B are used to drive word lines L1B-L16B and L17B-L32B respectively.

[0068] The connection between word lines L1A~L32A and L1B~L32B and drivers DV1A~DV32A, DV1B~DV32B is the same as Figure 1 The layout described in the embodiment will not be described in detail here.

[0069] The control logic circuit 430 generates a first control signal and a second control signal based on the accessed address of the memory cell array 410. Voltage shifters 421 and 422 are disposed on either side of the control logic circuit 430. The voltage shifters 421 and 422 are used to increase the voltage of the common word line and provide the common word line voltage to drivers DV1A-DV32A and drivers DV1B-DV32B, respectively.

[0070] Incidentally, the memory cell array 410 in this embodiment is an AND gate (AND) flash memory cell array.

[0071] Please refer to the following Figure 5 , Figure 5A top view of the layout structure of the word line driver in the three-dimensional memory device of an embodiment of the present invention is shown. A plurality of gate structures GN are provided on both sides of a substrate 520, forming a plurality of N-type transistors. A well region 510 is provided in the central portion of the substrate 520. A plurality of gate structures GP are provided on the well region 510, forming a plurality of P-type transistors. A contact window CT1 having a channel structure may be provided on the source and drain of each N-type transistor, and a contact window CT2 having a channel structure may be provided on the source and drain of each P-type transistor. Through the contact windows CT1 and CT2, each N-type transistor and each P-type transistor can be connected to a transmission wire WBM2 on the second conductive layer via a transmission wire WBM1 on the first conductive layer. The transmission wire WBM2 on the second conductive layer is then connected to a through-array conductive structure TAV, and is coupled to the corresponding plurality of word lines via the through-array conductive structure TAV.

[0072] In addition, the transmission wire WBM2 on the second wire layer can be used to provide the common word line voltage WGWL and the reference ground voltage WVSS to each P-type transistor and each N-type transistor.

[0073] Each of the gate structures GN and GP can receive control signals PG[1], PG[2], PG[3], PG[4] and inverse control signals PGB[1], PGB[2], PGB[3], PGB[4]. The control signals PG[1], PG[2], PG[3], PG[4] and inverse control signals PGB[1], PGB[2], PGB[3], PGB[4] are used to control the on / off state of the corresponding transistor.

[0074] Please refer to Figure 6 , Figure 6 A partial stereoscopic view of the transmission wires of a three-dimensional memory device according to an embodiment of the present invention is shown. Transmission wires 610 and 620 are two adjacent transmission wires in the same wire layer. Based on the present invention, word lines are grouped, and word lines in different word line groups are connected to word line drivers through different mechanisms. In this way, the density of transmission wires in the same area can be effectively reduced. In other words, the spacing between transmission wires 610 and 620 can be enlarged, and the line width WH of transmission wire 610 can be increased. Furthermore, the embodiment of the present invention can also increase the line height HT of transmission wire 610. In this way, the equivalent resistance of transmission wire 610 can be effectively reduced, thereby improving the transmission efficiency of word line signals.

[0075] Please refer to the following Figure 7 , Figure 7A schematic diagram illustrates a word line driving mechanism in a three-dimensional memory device according to an embodiment of the present invention. In this embodiment, the three-dimensional memory device provides a word line signal WLs to a selected word line of a memory cell array 701 via a voltage shifter 720 and a driver 710. Driver 710 includes transistors M1 and M2. Transistors M1 and M2 are coupled in series. Transistor M1 receives a common word line voltage GWL provided by voltage shifter 720 and, when turned on by a control signal PG, sets word line signal WLs to the common word line voltage GWL, thereby enabling access to the corresponding memory cell.

[0076] The voltage shifter 720 in this embodiment includes transistors M3-M6 and an inverter IV. The first terminals of transistors M3 and M4 receive voltage V1, and the control terminals of transistors M3 and M4 are coupled to the second terminals of transistors M4 and M3, respectively. Transistor M5 is connected in series between transistor M3 and a reference ground voltage Vss, while transistor M6 is connected in series between transistor M4 and the reference ground voltage Vss. Inverter IV is connected in series between the control terminals of transistors M5 and M6. Inverter IV receives an input signal IN and provides an output signal to the control terminal of transistor M5.

[0077] In terms of operational details, when the input signal is a logic 1, transistor M6 is turned on and transistor M5 is turned off. The turned-on transistor M6 pulls down the voltage on the control terminal of transistor M3 to the reference ground voltage Vss, turning on transistor M3 and turning off transistor M4. The turned-on transistor M3 then raises the common word line voltage GWL to equal voltage V1. When the input signal is a logic 0, transistor M6 is turned off, but transistor M5 is turned on based on the output signal of inverter IV. The turned-on transistor M5 provides the reference ground voltage Vss to the control terminal of transistor M4, turning on transistor M4. The turned-on transistor M4 causes the control terminal of transistor M3 to receive voltage V1, turning off transistor M3. Therefore, due to the turned-off transistor M3 and the turned-on transistor M5, the common word line voltage GWL is pulled down to equal the reference ground voltage Vss.

[0078] The circuit details of the voltage shifter 720 are merely examples for illustration purposes. Other types of voltage shifters known to those skilled in the art may also be applied to the present invention without particular limitation.

[0079] Incidentally, the memory cell array 701 of this embodiment is a three-dimensionally arranged AND gate flash memory cell array.

[0080] Please refer to the following Figure 8 , Figure 8A schematic diagram illustrating the layout path of word lines of a three-dimensional memory device according to an embodiment of the present invention is shown. Figure 8 In the embodiment, word line L1 can be connected to switch SW11 via transmission path PATH1, and then to the source of common word line voltage GWL via switch SW11. Word line L2 can be connected to switch SW12 via transmission path PATH2, and then to the source of common word line voltage GWL via switch SW12. Transmission path PATH1 has a relatively short transmission distance on transmission conductor WBM3-1, but can have a relatively long transmission distance between switch SW11 and the source of common word line voltage GWL. Conversely, transmission path PATH2 has a relatively long transmission distance on transmission conductor WBM3-2, but can have a relatively short transmission distance between switch SW12 and the source of common word line voltage GWL. Therefore, it can be seen that the lengths of transmission path PATH1 and transmission path PATH2 can be substantially equal. In other words, in embodiments of the present invention, word lines L1 and L2 can have substantially the same capacitive and resistive loads, which can ensure a certain degree of uniformity in the signal quality of word line signals.

[0081] Please refer to Figure 9 , Figure 9 A schematic diagram of a memory cell array of a three-dimensional memory device according to an embodiment of the present invention. The three-dimensional memory device 900 includes memory cell arrays MA1 and MA2. Memory cell array MA1 includes memory cells M11-1 through M22-1, while memory cell array MA2 includes memory cells M11-2 through M22-2. In memory cell array MA1, memory cells MC11-1 and MC12-1 in the same row are coupled to the same source line SLn and bit line BLn, but to different word lines WL1 and WL2, respectively. Memory cells MC21-1 and MC22-1 in the same row are coupled to the same source line SLn+1 and bit line BLn+1, but to different word lines WL1 and WL2, respectively. In addition, the memory cells MC11-1 and MC21-1 in the same column are coupled to the same word line WL1, but are respectively coupled to different source lines SLn and SLn+1 and different bit lines BLn and BLn+1; the memory cells MC12-1 and MC22-1 in the same column are coupled to the same word line WL2, but are respectively coupled to different source lines SLn and SLn+1 and different bit lines BLn and BLn+1.

[0082] In this embodiment, the memory cell array MA2 and the memory cell array MA1 have the same memory cell arrangement, and will not be further described here. It is worth noting that the memory cell array MA2 and the memory cell array MA1 may share source lines SLn, SLn+1 and bit lines BLn, BLn+1, but are coupled to independent word lines WL1, WL2 and WL3, WL4.

[0083] In this embodiment, the memory cells M11-1 to M22-1 and M11-2 to M22-2 are flash memory cells. According to the arrangement of the memory cells M11-1 to M22-1 and M11-2 to M22-2, the memory cell arrays MA1 and MA2 are arranged as AND-type flash memory cell arrays.

[0084] In summary, the three-dimensional memory device of the present invention divides word lines into multiple word line groups, and each word line group is routed through different stair-stepping methods to facilitate the layout of transmission lines within multiple wiring layers. This simplifies word line layout. When a large number of word lines are required, not only can the layout be completed quickly and easily, but the density of transmission lines per unit area can also be reduced, improving the electrical characteristics of the transmission lines and boosting the access efficiency of the three-dimensional memory device.

Claims

1. A three-dimensional memory device, characterized in that: include: A plurality of word lines are divided into a plurality of word line groups; A plurality of first switches receiving a common word line voltage; A plurality of second switches receiving a reference ground voltage; as well as N conductor layers, where N is a positive integer greater than 1, Among these wire layers: The plurality of transmission wires of the first wire layer are connected to the plurality of transmission wires of the second wire layer, and the transmission wires of the first wire layer are coupled to the first switches and the second switches respectively. Among these wordline groups: The first word line group passes through the second conductive layer to connect to the first conductive layer, and the i-th word line group sequentially passes through the i+1-th conductive layer to the second conductive layer to connect to the first conductive layer, wherein N>i>1.

2. The three-dimensional memory device according to claim 1, wherein The transmission wires of the first wire layer are respectively connected to the transmission wires of the second wire layer through a plurality of through array conductive structures.

3. The three-dimensional memory device according to claim 2, wherein: The transmission wires of the first wire layer extend along a first direction to be connected to the first switches and the second switches respectively. The transmission wires of the second wire layer extend along a second direction to be connected to the through-array conductive structures respectively. The first direction is different from the second direction.

4. The three-dimensional memory device according to claim 1, wherein: The transmission wires from the Nth wire layer to the second wire layer extend in the same direction.

5. The three-dimensional memory device according to claim 1, wherein: The first word line group is connected to the second conductive line layer through a plurality of contact windows corresponding to the Nth conductive line layer to the third conductive line layer.

6. The three-dimensional memory device according to claim 1, wherein: Also includes: a common word voltage transmission conductor, coupled to the plurality of common word lines respectively through the plurality of first conductive via structures; as well as a reference ground voltage transmission conductor, coupled to the plurality of reference ground lines respectively through the plurality of second conductive through-hole structures; The common word lines respectively provide the common word line voltage to the first switches, and the reference ground lines respectively provide the reference ground voltage to the second switches.

7. The three-dimensional memory device according to claim 6, wherein: The extending direction of the common word voltage transmission wire and the reference ground voltage transmission wire is the same as the extending direction of the transmission wires of the second wire layer.

8. The three-dimensional memory device according to claim 1, wherein: The first switches are respectively connected in series with the second switches to form a plurality of drivers, and the drivers are respectively controlled by a plurality of control signals.

9. The three-dimensional memory device according to claim 8, wherein: Also includes: A plurality of third switches are respectively coupled to the output terminals of the drivers and commonly coupled to the common word line. The third switches are respectively controlled by a plurality of reverse control signals.

10. The three-dimensional memory device according to claim 9, wherein: Each of the first switches is a first transistor, and each of the second switches is a second transistor. The first end of the first transistor receives the common word line voltage, the second end of the first transistor is coupled to the first end of the second transistor, and the second end of the second transistor receives the reference ground voltage. The control ends of the first transistor and the second transistor jointly receive the corresponding control signals.

11. The three-dimensional memory device according to claim 10, wherein: Each of the third switches is a third transistor, a first terminal of the third transistor receives the common word line voltage, a second terminal of the third transistor is coupled to the first terminal of the second transistor, and a control terminal of the third transistor receives the corresponding reverse control signal.

12. The three-dimensional memory device according to claim 11, wherein: The first transistor is a P-type transistor, and the second transistor and the third transistor are N-type transistors.

13. The three-dimensional memory device according to claim 11, wherein: Contact windows with channel structures are provided on the sources and drains of the first transistor, the second transistor and the third transistor.

14. The three-dimensional memory device according to claim 8, wherein Also includes: A plurality of voltage shifters are coupled to the driver and used for generating the control signals.

15. The three-dimensional memory device according to claim 14, wherein: The drivers are divided into a first driver group and a second driver group. The first driver group and the second driver group are respectively arranged at two opposite sides of the layout area of ​​the voltage shifters.

16. The three-dimensional memory device according to claim 1, wherein: The lengths of the signal transmission paths from the word lines to the first switches are the same.

17. The three-dimensional memory device according to claim 1, wherein: The first switches are divided into M first switch groups, and the second switches are divided into P second switch groups. The first switch groups are alternately arranged with the second switch groups, and M and P are positive integers.

18. The three-dimensional memory device according to claim 17, wherein: P is greater than or equal to M.

19. The three-dimensional memory device according to claim 1, wherein The transmission wires from the second wire layer to the Nth wire layer are in a strip shape or an L shape.

20. The three-dimensional memory device according to claim 1, wherein Also includes: A memory cell array is coupled to the word lines, wherein the memory cell array is an AND gate flash memory cell array.

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