Efficient sensing of soft bit data for non-volatile memory

Abstract

A non-volatile memory improves read time efficiency by combining hard and soft reads into a single effective soft read sequence using two senses per state level. Instead of a standard hard read, which performs two soft reads offset above and below the hard read value, the hard reads are shifted so that they reliably sense one state but less reliably sense the other, and soft data is determined only for the less reliably sensed state. This reduces the amount of soft data. The effective soft-sensing sequence can be used as the default read mode, providing soft-sensing information for ECC correction without triggering read error handling. Combining soft and hard sensing into a single sequence avoids the additional overhead for read sequence operations.

Description

[0001] Priority Statement

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 244,951, filed September 16, 2021, entitled “Plane Level Vertical Compression Scheme” by Hsu et al. Background Technology

[0003] This disclosure relates to non-volatile storage devices.

[0004] Semiconductor memories are widely used in a variety of electronic devices, such as cellular phones, digital cameras, personal digital assistants, medical electronics, mobile computing devices, servers, solid-state drives, non-mobile computing devices, and other devices. Semiconductor memories can include non-volatile or volatile memories. Non-volatile memories allow information to be stored and retained even when not connected to a power source (e.g., a battery). An example of a non-volatile memory is flash memory (e.g., NAND flash memory and NOR flash memory).

[0005] Users of non-volatile memory can program (e.g., write) data into the non-volatile memory and then read that data back. For example, a digital camera can take a photo and store it in non-volatile memory. The user of the digital camera can then view the photo by having the camera read it from the non-volatile memory. Because users often rely on the data they store, it is important for users of non-volatile memory to be able to reliably store data so that it can be successfully read back. Attached Figure Description

[0006] Components with similar numbers refer to common parts in different drawings.

[0007] Figure 1 It is a block diagram depicting one implementation of a storage system.

[0008] Figure 2A This is a block diagram of one implementation scheme for a memory die.

[0009] Figure 2B This is a block diagram of one implementation scheme for an integrated memory component.

[0010] Figure 2C and Figure 2D Different implementation schemes for the integrated memory component are described.

[0011] Figure 3 A circuit system for sensing data from a non-volatile memory is described.

[0012] Figure 4 This is a perspective view of one implementation of a monolithic three-dimensional memory architecture.

[0013] Figure 4A This is a block diagram of one implementation of a memory structure with two planes.

[0014] Figure 4B A top view depicting a portion of an embodiment of a block of memory cells.

[0015] Figure 4C A cross-sectional view depicting a portion of one embodiment of a block of memory cells.

[0016] Figure 4D A cross-sectional view depicting a portion of one embodiment of a block of memory cells.

[0017] Figure 4E A cross-sectional view depicting a portion of one embodiment of a block of memory cells.

[0018] Figure 4F This is a cross-sectional view of one embodiment of a vertical column of memory cells.

[0019] Figure 4G A cross-section of the memory hole that implements a vertical NAND string is depicted.

[0020] Figure 4H A cross-section of the memory hole that implements a vertical NAND string is depicted.

[0021] Figure 4I A cross-section of the memory hole that implements a vertical NAND string is depicted.

[0022] Figure 4J A schematic diagram of multiple NAND strings in multiple sub-blocks of the same block.

[0023] Figure 5A The threshold voltage distribution was depicted.

[0024] Figure 5B The threshold voltage distribution was depicted.

[0025] Figure 5C The threshold voltage distribution was depicted.

[0026] Figure 5D The threshold voltage distribution was depicted.

[0027] Figure 5E The threshold voltage distribution was depicted.

[0028] Figure 5F The threshold voltage distribution was depicted.

[0029] Figure 6 This is a flowchart describing one implementation of the process for programming non-volatile memory.

[0030] Figure 7 The diagram shows the overlap of the distributions of two adjacent data states and a set of reads that can be used to determine the data state of a cell and the reliability of such reads.

[0031] Figure 8 The concepts of hard bits and soft bits are shown.

[0032] Figure 9A and Figure 9B The read levels for calculating the hard and soft bit values ​​of the next page data are shown in the three-bit data implementation per memory cell.

[0033] Figure 10 The assignment of hard and soft bit values ​​and readout levels used in an implementation for effective soft sensing is shown.

[0034] Figure 11 The diagram illustrates how the coding in Table 2 is used in a three-bit data implementation per memory cell to apply an effective soft-sensing mode to the next page of data.

[0035] Figure 12 It shows the corresponding Figure 11 The implementation scheme shown is a sensing operation for the next page data reading operation in an effective soft sensing reading operation of the reading point.

[0036] Figure 13 An implementation scheme of a sensing amplifier circuit that can be used to determine the hard and soft bit values ​​of a memory cell is shown.

[0037] Figure 14 This is a flowchart of an implementation scheme for effective soft sensing operation. Detailed Implementation

[0038] In some memory systems, error correction methods sometimes employ "soft bit" data. Soft bit data provides information about the reliability of a standard or "hard bit" data value used to distinguish between data states. For example, when a data value is based on a threshold voltage of a memory cell, a hard bit read will determine whether the threshold voltage of the memory cell is higher or lower than the data read value in order to distinguish between stored data states. For memory cells with threshold voltages slightly higher or lower than this reference value, such a hard bit may be incorrect because the memory cell actually implies a different data state. To determine memory cells with threshold voltages close to the hard bit read level, and therefore with hard bit values ​​of lower reliability, a pair of additional reads offset slightly above and slightly below the hard bit read level can be performed to generate soft bit values ​​for the hard bit values. The use of soft bits can be a powerful tool for extracting the data contents of memory cells, but because it requires additional reads to obtain the soft bit data that then needs to be passed to the error correction circuitry system, it is generally only used when the data cannot be accurately determined from the hard bit values ​​alone.

[0039] The following proposes an efficient soft-sensing readout mode that requires fewer reads to generate soft-bit data and generates less soft-bit data, thereby reducing the performance and power consumption losses typically associated with using soft-bit data. This allows the efficient soft-sensing mode to be used as the default readout mode. Compared to a typical hard-bit / soft-bit arrangement, the hard-bit readout point offset ensures that the hard bit value of one data state of the memory cell is reliable, but the hard bits of the other data state include a larger number of unreliable hard bit values. Performing a single soft-bit read for the less reliable hard bit value, but without providing reliability information for the more reliable hard bit value, reduces the number of reads and the amount of data obtained. To further improve performance, both hard-bit sensing and soft-bit sensing can be combined into a single sensing, such as by pre-charging the node of the sensing amplifier and performing a single discharge through the selected memory cell, but sensing the level twice for the single discharge at the node, once for the hard bit value and once for the soft bit value.

[0040] Figure 1This is a block diagram illustrating one embodiment of the storage system 100 implementing the technology of the present invention described herein. In one embodiment, the storage system 100 is a solid-state drive (“SSD”). The storage system 100 may also be a memory card, a USB drive, or other type of storage system. The technology of the present invention is not limited to any type of memory system. The storage system 100 is connected to a host 102, which may be a computer, server, electronic device (e.g., a smartphone, tablet, or other mobile device), appliance, or another device that uses memory and has data processing capabilities. In some embodiments, the host 102 is separate from the storage system 100 but connected to the storage system. In other embodiments, the storage system 100 is embedded in the host 102.

[0041] Figure 1 The components of the storage system 100 depicted are electronic circuits. The storage system 100 includes a memory controller 120 connected to a non-volatile memory 130 and a local high-speed volatile memory 140 (e.g., DRAM). The memory controller 120 uses the local high-speed volatile memory 140 to perform certain functions. For example, the local high-speed volatile memory 140 stores logic in a physical address translation table (“L2P table”).

[0042] The memory controller 120 includes a host interface 152 that connects to and communicates with the host 102. In one embodiment, the host interface 152 implements NVM Express (NVMe) via PCI Express (PCIe). Other interfaces, such as SCSI, SATA, etc., may also be used. The host interface 152 is also connected to a network on-chip (NOC) 154. The NOC is a communication subsystem on an integrated circuit. The NOC can span synchronous and asynchronous clock domains, or use non-clocked asynchronous logic. NOC technology applies network theory and methods to on-chip communication and provides significant improvements compared to conventional bus and crossbar interconnects. Compared to other designs, the NOC improves the scalability of the system-on-chip (SoC) and the power efficiency of complex SoCs. The wires and links of the NOC are shared by many signals. Because all links in the NOC can operate simultaneously on different data packets, a high degree of parallelism is achieved. Therefore, as the complexity of integrated subsystems increases, the NOC provides enhanced performance (such as throughput) and scalability compared to previous communication architectures (e.g., dedicated point-to-point signal lines, shared buses, or segmented buses with bridges). In other embodiments, NOC 154 may be replaced by a bus. Processor 156, ECC engine 158, memory interface 160, and DRAM controller 164 are connected to and communicate with NOC 154. DRAM controller 164 is used to operate and communicate with local high-speed volatile memory 140 (e.g., DRAM). In other embodiments, local high-speed volatile memory 140 may be SRAM or another type of volatile memory.

[0043] ECC engine 158 performs error correction services. For example, ECC engine 158 performs data encoding and decoding according to implemented ECC technology. In one embodiment, ECC engine 158 is a software-programmable electronic circuit. For example, ECC engine 158 may be a programmable processor. In other embodiments, ECC engine 158 is a custom-designed dedicated hardware circuit without any software. In yet another embodiment, the functionality of ECC engine 158 is implemented by processor 156.

[0044] Processor 156 performs various controller memory operations, such as programming, erasing, reading, and memory management processes. In one embodiment, processor 156 is programmed by firmware. In other embodiments, processor 156 is a custom-designed dedicated hardware circuit without any software. Processor 156 also implements a translation module, either as a software / firmware process or as dedicated hardware circuitry. In many systems, non-volatile memory is addressed inward to the memory system using physical addresses associated with one or more memory dies. However, the host system will use logical addresses to address various memory locations. This allows the host to assign data to consecutive logical addresses while the memory system is idle to store data between the locations of one or more memory dies as desired. To implement such a system, memory controller 120 (e.g., a translation module) performs address translation between logical addresses used by the host and physical addresses used by the memory dies. An exemplary embodiment maintains a table that identifies the current translation between logical and physical addresses (i.e., the L2P table described above). Entries in the L2P table may include a logical address and an identifier of the corresponding physical address. Although logical address to physical address tables (or L2P tables) include the word "table," they do not have to be tables in the literal sense. Instead, logical address to physical address tables (or L2P tables) can be any type of data structure. In some examples, the memory space of the storage system is so large that local memory 140 cannot hold all the L2P tables. In this case, the entire set of L2P tables is stored in memory die 130, and a subset of the L2P tables is cached (the L2P cache) in local high-speed volatile memory 140.

[0045] Memory interface 160 communicates with non-volatile memory 130. In one embodiment, the memory interface provides a switching mode interface. Other interfaces may also be used. In some exemplary embodiments, memory interface 160 (or another part of controller 120) implements a scheduler and buffer for transferring data to and receiving data from one or more memory dies.

[0046] In one embodiment, the non-volatile memory 130 includes one or more memory dies. Figure 2A This is a functional block diagram of one embodiment of a memory die 200 including non-volatile memory 130. Each of one or more memory dies of non-volatile memory 130 can be implemented as Figure 2A The memory die 200. Figure 2AThe components depicted are circuits. Memory die 200 includes a memory array 202, which may include non-volatile memory cells, as described in more detail below. The array terminal lines of memory array 202 include various word line layers organized in rows and various bit line layers organized in columns. However, other orientations may also be implemented. Memory die 200 includes a row control circuitry system 220, the output of which is 208 connected to a corresponding word line of memory array 202. Row control circuitry system 220 receives a set of M row address signals and one or more various control signals from system control logic circuitry 260, and typically includes circuitry such as a row decoder 222, an array terminal driver 224, and a block select circuitry system 226 for both read and write (programming) operations. Row control circuitry system 220 may also include a read / write circuitry system. Memory die 200 also includes a column control circuitry system 210, which includes a sense amplifier 230, the input / output of which is 206 connected to a corresponding bit line of memory array 202. Although only a single block is shown for array 202, the memory die may include multiple arrays that can be accessed individually. The column control circuitry 210 receives a set of N column address signals and one or more various control signals from the system control logic unit 260, and typically includes circuitry such as a column decoder 212, array terminal receiver or driver circuitry 214, block selection circuitry 216, read / write circuitry, and I / O multiplexers.

[0047] System control logic unit 260 receives data and commands from memory controller 120 and provides output data and status to the host. In some embodiments, system control logic unit 260 (which includes one or more circuits) includes a state machine 262 that provides die-level control for memory operations. In one embodiment, state machine 262 is programmable by software. In other embodiments, state machine 262 does not use software and is implemented entirely in hardware (e.g., circuitry). In yet another embodiment, state machine 262 is replaced by a microcontroller or microprocessor located on or outside the memory chip. System control logic unit 260 may also include a power control module 264 that controls the power and voltage supplied to rows and columns of memory structure 202 during memory operations and may include charge pump and regulator circuitry for generating regulated voltages. System control logic unit 260 includes a storage device 266 (e.g., RAM, registers, latches, etc.) that can be used to store parameters for operating memory array 202.

[0048] Commands and data are transmitted between memory controller 120 and memory die 200 via memory controller interface 268 (also referred to as the "communication interface"). Memory controller interface 268 is an electrical interface used for communicating with memory controller 120. Examples of memory controller interface 268 include a switching mode interface and an Open NAND Flash Interface (ONFI). Other I / O interfaces may also be used.

[0049] In some embodiments, all components of memory die 200 (including system control logic 360) may be formed as part of a single die. In other embodiments, some or all of the system control logic 260 may be formed on different dies.

[0050] In one embodiment, memory structure 202 includes a three-dimensional memory array of non-volatile memory cells, wherein multiple memory stages are formed over a single substrate such as a wafer. The memory structure may include any type of non-volatile memory, which is integrally formed in one or more physical stages of memory cells having active regions disposed over a silicon (or other type of) substrate. In one example, the non-volatile memory cells include vertical NAND strings with charge trapping layers.

[0051] In another embodiment, memory structure 202 includes a two-dimensional memory array of non-volatile memory cells. In one example, the non-volatile memory cells are NAND flash memory cells utilizing floating gates. Other types of memory cells (e.g., NOR flash memory) may also be used.

[0052] The exact type of memory array architecture or memory cell included in memory structure 202 is not limited to the examples described above. Many different types of memory array architectures or memory technologies can be used to form memory structure 202. Implementing the novel embodiments claimed herein does not require a specific non-volatile memory technology. Other examples of suitable technologies for memory cells of memory structure 202 include ReRAM (Resistive Random Access Memory), magnetoresistive memory (e.g., MRAM, spin-torque MRAM, spin-orbit torque MRAM), FeRAM, phase-change memory (e.g., PCM), etc. Examples of suitable technologies for memory cell architectures of memory structure 202 include two-dimensional arrays, three-dimensional arrays, cross-point arrays, stacked two-dimensional arrays, vertical bitline arrays, etc.

[0053] One example of a ReRAM crosspoint memory includes reversible resistive switching elements arranged in a crosspoint array accessed by X-rays and Y-rays (e.g., word lines and bit lines). In another embodiment, the memory cell may include a conductive bridge memory element. A conductive bridge memory element may also be referred to as a programmable metallized cell. Based on the physical repositioning of ions within a solid electrolyte, the conductive bridge memory element can be used as a state-changing element. In some cases, the conductive bridge memory element may include two solid metal electrodes, one relatively inert (e.g., tungsten) and the other electrochemically active (e.g., silver or copper), with a thin film of solid electrolyte between the two electrodes. As temperature increases, ion mobility also increases, leading to a decrease in the programming threshold of the conductive bridge memory cell. Therefore, the conductive bridge memory element can have a wide range of programming thresholds across the entire temperature range.

[0054] Another example is magnetoresistive random access memory (MRAM), which stores data using magnetic storage elements. These elements are formed from two ferromagnetic layers separated by a thin insulating layer, each of which can remain magnetized. One of these layers is a permanent magnet set to a specific polarity; the magnetization of the other layer can be changed to match the magnetization of the memory by an external magnetic field. The memory device is constructed from a grid of such memory cells. In one implementation for programming, each memory cell is located between a pair of write lines arranged at right angles to each other, parallel to the cell, one above and one below. When current passes through them, an induced magnetic field is generated. MRAM-based memory implementations will be discussed in more detail below.

[0055] Phase-change memories (PCMs) utilize the unique properties of chalcogenide glasses. One embodiment uses a GeTe-Sb₂Te₃ superlattice to achieve a non-thermal phase transition by changing the coordination state of germanium atoms using only a laser pulse (or a light pulse from another source). Therefore, the programming dose is the laser pulse. Memory cells can be suppressed by preventing them from receiving light. In other PCM embodiments, memory cells are programmed by current pulses. It should be noted that the use of "pulse" in this document does not require a rectangular pulse, but includes (continuous or discontinuous) vibrations or pulse trains of sound, current, voltage, light, or other waves. These memory elements within the individual selectable memory cells or bits may include additional series elements as selectors, such as bidirectional threshold switches or metallic insulator substrates.

[0056] Those skilled in the art will recognize that the techniques described herein are not limited to a single particular memory structure, memory configuration, or material composition, but encompass many related memory structures within the technical essence and scope as described herein and as understood by those skilled in the art.

[0057] Figure 2A The components can be grouped into two parts: (1) memory structure 202 and (2) peripheral circuit system, which includes Figure 2A The diagram depicts all components except for memory structure 202. A key characteristic of memory circuitry is its capacity, which can be increased by increasing the area of ​​the memory die reserved for the memory structure 202 within the memory system 100; however, this reduces the area of ​​the memory die available for peripheral circuitry. This can impose significant limitations on these peripheral circuitry components. For example, the need to mount sense amplifier circuitry within the available area can be a major constraint on sense amplifier design architecture. The reduced available area relative to system control logic components 260 may limit the available functionality that can be implemented on the chip. Therefore, a fundamental trade-off must be made between the amount of dedicated area for memory structure 202 and the amount of dedicated area for peripheral circuitry in the design of the memory die for memory system 100.

[0058] Another area where memory structure 202 often conflicts with peripheral circuitry lies in the processing involved in forming these areas, as these areas typically involve different processing techniques and trade-offs when implementing different techniques on a single die. For example, when memory structure 202 is NAND flash memory, it is an NMOS structure, while peripheral circuitry is typically CMOS-based. For instance, components of other peripheral circuitry such as sense amplifier circuitry, charge pumps, logic elements in state machines, and system control logic unit 260 typically employ PMOS devices. The processing operations used to manufacture CMOS dies will differ in many ways from those optimized for NMOS flash NAND memory or other memory cell technologies.

[0059] To mitigate these limitations, the implementation scheme described below can... Figure 2AThe components are separated onto individually formed dies, and then these dies are bonded together. More specifically, the memory structure 202 can be formed on a single die (referred to as the memory die), and some or all of the peripheral circuitry components (including one or more control circuits) can be formed on separate dies (referred to as the control die). For example, the memory die can be formed solely of memory elements, such as flash NAND memory, MRAM memory, PCM memory, ReRAM memory, or other memory cell arrays of other memory types. Some or all of the peripheral circuitry (even including components such as decoders and sense amplifiers) can then be moved to separate control dies. This allows each die in the memory die to be optimized individually according to its technology. For example, a NAND memory die can be optimized for an NMOS-based memory array structure without worrying about CMOS elements now moved to a control die that can be optimized for CMOS processing. This provides more space for peripheral components, and additional capabilities that might not be easily combined can now be incorporated if peripheral components were confined to the edges of the same die housing the memory cell array. Two dies can then be bonded together in a bonded multi-die memory circuit, with an array on one die connected to peripheral components on the other die. For example, while the following will focus on a bonded memory circuit with one memory die and one control die, other implementations may use more dies, such as two memory dies and one control die.

[0060] Figure 2B It shows Figure 2A An alternative arrangement of the arrangement can be implemented using wafer-to-wafer bonding to provide bonded die pairs. Figure 2B A functional block diagram of one embodiment of integrated memory component 207 is depicted. One or more integrated memory components 207 may be used to implement the non-volatile memory 130 of memory system 100. Integrated memory component 207 includes two types of semiconductor dies (or more simply, "dies"). Memory die 201 includes memory structure 202. Memory structure 202 includes non-volatile memory cells. Control die 211 includes control circuitry systems 260, 210, and 220 (as described above). In some embodiments, control die 211 is configured to be connected to memory structure 202 within memory die 201. In some embodiments, memory die 201 and control die 211 are coupled together.

[0061] Figure 2B An example of a peripheral circuit system is shown, including control circuitry formed in the peripheral circuitry or control die 311, which is coupled to a memory structure 202 formed in the memory die 201. General components are similar to... Figure 2AThe system control logic unit 260, row control circuitry system 220, and column control circuitry system 210 are located in control die 211. In some embodiments, all or part of the column control circuitry system 210 and all or part of the row control circuitry system 220 are located on memory die 201. In some embodiments, some circuitry in the system control logic unit 260 is located on memory die 201.

[0062] System control logic unit 260, row control circuit system 220, and column control circuit system 210 can be formed using conventional processes (e.g., CMOS processes), making it possible to add elements and functions more commonly found on memory controller 120, such as ECC, with few or no additional process steps (i.e., the same process steps used to manufacture controller 120 can also be used to manufacture system control logic unit 260, row control circuit system 220, and column control circuit system 210). Therefore, while removing such circuitry from a die (e.g., memory 2 die 201) reduces the number of steps required to manufacture such a die, adding such circuitry to a die (e.g., control die 311) may not require many additional process steps. Because some or all of the control circuit systems 260, 210, and 220 are implemented using CMOS technology, control die 211 may also be referred to as a CMOS die.

[0063] Figure 2B A column control circuitry system 210, including a sense amplifier 230, is shown on a control die 211. This column control circuitry is coupled to a memory structure 202 on a memory die 201 via an electrical path 206. For example, electrical path 206 can provide electrical connections between the column decoder 212, the driver circuitry system 214, the block selector 216, and the bit lines of the memory structure 202. The electrical path can extend from the column control circuitry system 210 in the control die 211 through pads on the control die 211 that bond to corresponding pads on the memory die 201 that connect to the bit lines of the memory structure 202. Each bit line of the memory structure 202 can have a corresponding electrical path in electrical path 206, including a pair of bonded pads connected to the column control circuitry system 210. Similarly, a row control circuitry system 220 (including a row decoder 222, an array driver 224, and a block selector 226) is coupled to the memory structure 202 via an electrical path 208. Each electrical path in electrical path 208 may correspond to a word line, a dummy word line, or a select gate line. Additional electrical paths may also be provided between the control die 211 and the memory die 201.

[0064] For the purposes of this document, the phrase "control circuitry" or "one or more control circuits" may include all or a portion of memory controller 120, state machine 262, system control logic 260, all or a portion of row control circuitry system 220, all or a portion of column control circuitry system 210, microcontroller, microprocessor, and / or other similar functional circuitry, or any combination thereof. Control circuitry may consist of hardware only or a combination of hardware and software (including firmware). For example, a controller programmed by firmware to perform the functions described herein is an example of control circuitry. Control circuitry may include processors, FGAs, ASICs, integrated circuits, or other types of circuitry.

[0065] In some embodiments, the integrated memory component 207 contains more than one control die 211 and more than one memory die 201. In some embodiments, the integrated memory component 207 includes a stack of multiple control dies 211 and multiple memory dies 201. Figure 2C A side view of one embodiment of an integrated memory assembly 207 (e.g., a stack including control dies 211 and memory dies 201) stacked on a substrate 271 is depicted. The integrated memory assembly 207 has three control dies 211 and three memory dies 201. In some embodiments, there are more than three memory dies 201 and more than three control dies 211.

[0066] Each control die 211 is attached (e.g., bonded) to at least one memory die in memory die 201. Some of the bonding pads 282 / 284 are depicted. There may be more bonding pads. The space between the two dies 201, 211 bonded together is filled with a solid layer 280, which may be formed of epoxy resin or other resins or polymers. The solid layer 280 protects the electrical connection between the dies 201, 211 and further secures the dies together. Various materials can be used as the solid layer 280, but in this embodiment, the material may be Hysol epoxy resin from Henkel Corporation, which has offices in California, USA.

[0067] The integrated memory component 207 can be stacked, for example, in a stepped offset manner, such that the bonding pads at each level are not covered and can be reached from above. Wire bonds 270 connected to the bonding pads connect the control die 211 to the substrate 271. Multiple such wire bonds can be formed across the width of each control die 211 (i.e., formed to...). Figure 2C (on the page).

[0068] A through-silicon via (TSV) 276 for memory die 201 can be used to route signals through memory die 201. A through-silicon via (TSV) 278 for control die 211 can be used to route signals through control die 211. TSVs 276 and 278 can be formed before, during, or after the formation of integrated circuits in semiconductor dies 201 and 211. TSVs can be formed by etching through holes in the wafer. These holes can then be lined with a barrier to prevent metal diffusion. The barrier layer can in turn be lined with a seed layer, and the seed layer can be plated with an electrical conductor, such as copper, although other suitable materials such as aluminum, tin, nickel, gold, doped polysilicon, and alloys or combinations thereof can be used.

[0069] Solder balls 272 may optionally be attached to contact pads 274 on the lower surface of substrate 271. Solder balls 272 may be used to electrically and mechanically couple integrated memory assembly 207 to host devices such as printed circuit boards. Solder balls 272 may be omitted if integrated memory assembly 207 will be used as an LGA package. Solder balls 272 may form part of the interface between integrated memory assembly 207 and memory controller 120.

[0070] Figure 2D A side view of another embodiment of an integrated memory assembly 207 stacked on a substrate 271 is depicted. Figure 2D The integrated memory component 207 has three control dies 211 and three memory dies 201. In some embodiments, there are more than three memory dies 201 and more than three control dies 211. In this example, each control die 211 is coupled to at least one memory die 201. Optionally, the control die 211 may be coupled to two or more memory dies 201.

[0071] Some of the bonding pads 282 and 284 are depicted. There may be more bonding pads. The space between the two joined dies 201 and 211 is filled with a solid layer 280, which may be formed of epoxy resin or other resins or polymers. Figure 2C Compared to the examples in, Figure 2D The integrated memory component 207 in the memory die 201 does not have a stepped offset. A through-silicon via (TSV) 276 can be used to route signals through the memory die 201. A through-silicon via (TSV) 278 can be used to route signals through the control die 211.

[0072] Solder balls 272 may optionally be attached to contact pads 274 on the lower surface of substrate 271. Solder balls 272 may be used to electrically and mechanically couple integrated memory assembly 207 to host devices such as printed circuit boards. Solder balls 272 may be omitted if integrated memory assembly 207 will be used as an LGA package.

[0073] As briefly discussed above, the control die 211 and the memory die 201 can be bonded together. Bonding pads on each die 201, 211 can be used to bond the two dies together. In some embodiments, in a so-called Cu-Cu bonding process, the bonding pads are bonded directly to each other without solder or other additional material. In the Cu-Cu bonding process, the bonding pads are controlled to be highly flat and formed in a highly controlled environment that is essentially free of environmental particles that would otherwise deposit on the bonding pads and prevent a tight bond. Under these properly controlled conditions, the bonding pads are aligned and pressed against each other to form a bond based on surface tension. This bond can be formed at room temperature, although heat can also be applied. In embodiments using Cu-Cu bonding, the bonding pads can be approximately 5 μm square and spaced apart from each other at a pitch of 5 μm to 5 μm. Although this process is referred to herein as Cu-Cu bonding, the term can also be applied to situations where the bonding pads are formed from materials other than copper.

[0074] When the area of ​​the bonding pads is small, it can be difficult to bond semiconductor dies together. The size and spacing of the bonding pads can be further reduced by providing a film layer on the surface of the semiconductor die, including the bonding pads. The film layer is disposed around the bonding pads. When the dies are placed together, the bonding pads can bond to each other, and the film layers on the individual dies can bond to each other. This bonding technique can be called hybrid bonding. In embodiments using hybrid bonding, the bonding pads can be approximately 5 μm square and spaced apart from each other with a pitch of 1 μm to 5 μm. Bonding techniques can be used to provide bonding pads with even smaller sizes and pitches.

[0075] Some embodiments may include a membrane on the surfaces of dies 201, 211. If such a membrane is not initially provided, the space between the dies may be underfilled with epoxy resin or other resins or polymers. The underfill material may be applied as a liquid and then allowed to harden into a solid layer. This underfilling step protects the electrical connection between dies 201, 211 and further secures the dies together. Various materials may be used as underfill materials, but in this embodiment, the underfill material may be Hysol epoxy resin from Henkel, a company with offices in California, USA.

[0076] Figure 3This is a block diagram depicting one embodiment of a column control circuitry system 210, which is divided into a plurality of sense amplifiers 230 and a common section referred to as management circuitry 302. In one embodiment, each sense amplifier 230 is connected to a corresponding bit line, which in turn is connected to one or more NAND strings. In one exemplary embodiment, each bit line is connected to six NAND strings, with one NAND string per sub-block. Management circuitry 302 is connected to a group of a plurality (e.g., four, eight, etc.) of sense amplifiers 230. Each of the sense amplifiers 230 in the group communicates with the associated management circuitry via a data bus 304.

[0077] Each sense amplifier 230 operates to provide voltage to bit lines (see BL0, BL1, BL2, BL3) during programming, verification, erasing, and read operations. The sense amplifiers are also used to sense the conditions (e.g., data state) of memory cells in a NAND string connected to the respective sense amplifier.

[0078] Each sense amplifier 230 includes a selector 306 or switch connected to a transistor 308 (e.g., an NMOS). Based on the voltage at the control gate 310 and drain 312 of transistor 308, the transistor can operate as a pass-through gate or bit-line clamp. When the voltage at the control gate is sufficiently higher than the voltage at the drain, the transistor operates as a pass-through gate to pass the voltage at the drain to the bit line (BL) at the source 314 of the transistor. For example, a programming disable voltage (such as 1V-2V) can be passed through when pre-charging and disabling an unselected NAND string. Alternatively, a programming enable voltage (such as 0V) can be passed through to allow programming in a selected NAND string. The selector 306 can pass a supply voltage Vdd (e.g., 3V-4V) to the control gate of transistor 308 to make it operate as a pass-through gate.

[0079] When the voltage at the control gate is lower than the voltage at the drain, transistor 308 operates as a source follower to set or clamp the bit line voltage at Vcg - Vth, where Vcg is the voltage at the control gate 310 and Vth (e.g., 0.7V) is the threshold voltage of transistor 308. This assumes the source line is at 0V. If Vcelsrc is non-zero, the bit line voltage is clamped at Vcg - Vcelsrc - Vth. Therefore, the transistor is sometimes referred to as a bit line clamp (BLC) transistor, and the voltage Vcg at the control gate 310 is called the bit line clamp voltage Vblc. This mode can be used during sensing operations, such as read and verification operations. Thus, the bit line voltage is set by transistor 308 based on the voltage output by selector 306. For example, selector 306 can pass Vsense + Vth (e.g., 1.5V) to the control gate of transistor 308 to provide Vsense (e.g., 0.8V) on the bit line. Vbl selector 316 can pass a relatively high voltage, such as Vdd, to drain 312, which is higher than the control gate voltage on transistor 308 to provide source follower mode in sensing operation. Vbl refers to the bit line voltage.

[0080] Vbl selector 316 can transmit one of a plurality of voltage signals. For example, the Vbl selector can transmit a programming disable voltage signal that increases from an initial voltage (e.g., 0V) to a programming disable voltage (e.g., Vbl_inh) for the corresponding bit line of an unselected NAND string during a programming cycle. Vbl selector 316 can also transmit a programming enable voltage signal (such as 0V) for the corresponding bit line of a selected NAND string during a programming cycle.

[0081] In one approach, the selector 306 for each sensing circuit can be controlled separately from the selectors of other sensing circuits. The Vbl selector 316 for each sensing circuit can also be controlled separately from the Vbl selectors of other sensing circuits.

[0082] During sensing, the sensing node 318 is charged up to an initial voltage Vsense_init (such as 3V). The sensing node is then passed to a bitline via transistor 308, and the amount of decay of the sensing node is used to determine whether the memory cell is in a conductive or non-conductive state. The amount of decay of the sensing node also indicates whether the current Icell in the memory cell exceeds a reference current Iref. A larger decay corresponds to a larger current. If Icell ≤ Iref, the memory cell is in a non-conductive state, and if Icell > Iref, the memory cell is in a conductive state.

[0083] Specifically, the comparator circuit 320 determines the attenuation amount by comparing the sense node voltage with the trip voltage during sensing. If the sense node voltage attenuates below the trip voltage Vtrip, the memory cell is in a conductive state and its Vth is equal to or lower than the verification voltage. If the sense node voltage does not attenuate below Vtrip, the memory cell is in a non-conductive state and its Vth is higher than the verification voltage. For example, the comparator circuit 320 sets the sense node latch 322 to 0 or 1 based on whether the memory cell is in a conductive or non-conductive state. For example, in a program-verify test, 0 can indicate failure, and 1 can indicate success. The bits in the sense node latch can be read during a status bit scan operation of a scan operation or toggled from 0 to 1 during a fill operation. The bits in the sense node latch 322 can also be used in a lock scan to determine whether the bit line voltage is set to an inhibit level or a programming level in the next programming cycle.

[0084] The management circuitry 302 includes a processor 330, four sets of exemplary data latches 340, 342, 344 and 346, and an I / O interface 332 coupled between the sets of data latches and the data bus 334. Figure 3 Four exemplary sets of data latches 340, 342, 344, and 346 are shown; however, in other embodiments, more or fewer than four sets may be implemented. In one embodiment, each sense amplifier 230 has one set of latches. A set of three data latches may be provided for each sense circuit, for example, including individual latches ADL, BDL, CDL, and XDL. In some cases, different numbers of data latches may be used. In a three-bit per memory cell embodiment, ADL stores bits for next page data, BDL stores bits for intermediate page data, CDL stores bits for previous page data, and XDL acts as an interface latch for storing / latching data from the memory controller.

[0085] Processor 330 performs calculations, such as determining data stored in sensed memory cells and storing the determined data in the set of data latches. Each set of data latches 340-346 is used to store data bits determined by processor 330 during a read operation and data bits imported from data bus 334 during a programming operation, these data bits representing write data to be programmed into memory. I / O interface 332 provides an interface between data latches 340-346 and data bus 334.

[0086] During a read operation, the system operates under the control of state machine 262, which controls the supply of different control gate voltages to the addressed memory cell. As it progresses through various predefined control gate voltages corresponding to different memory states supported by the memory, a sensing circuit can trip at one of these voltages, and the corresponding output is provided to the processor 330 from the sensing amplifier via data bus 304. The processor 330 then determines the resulting memory state by considering the tripping event of the sensing circuit and information about the control gate voltages applied via input line 348 from the state machine. It then calculates the binary code of the memory state and stores the resulting data bits in data latches 340-346.

[0087] Some specific implementations may include multiple processors 330. In one implementation, each processor 330 will include output lines (not depicted) such that each output line is connected by a line or connection. A line or connection or line can be provided by connecting multiple lines together at a node, where each line carries a high or low input signal from the corresponding processor, and the node's output is high if any of the input signals is high. In some implementations, the output lines are inverted before being connected to the line or line. This configuration allows for rapid determination of when the programming process is complete during programming verification testing, as the state machine receiving the line or line can determine when all programmed bits have reached the desired level. For example, when each bit reaches its desired level, a logic zero for that bit is sent to the line or line (or data one is inverted). When all bits output data 0 (or data one is inverted), the state machine knows to terminate the programming process. Because each processor communicates with eight sensing circuits, the state machine needs to read the line or line eight times, or logic can be added to the processor 330 to accumulate the results of the relevant bit lines, so that the state machine only needs to read the line or line once. Similarly, by correctly selecting the logic level, the global state machine can detect when the first bit changes its state and adjust the algorithm accordingly.

[0088] During the programming or verification operation of a memory cell, the data to be programmed (written data) is stored in data latch groups 340-346 from the data bus 334. During reprogramming, the corresponding set of data latches for the memory cell can store data indicating when the memory cell can be reprogrammed based on the programming pulse magnitude value.

[0089] Under the control of state machine 262, the programming operation applies a series of programming voltage pulses to the control gate of the addressed memory cell. The amplitude of each voltage pulse can be incrementally increased by one step from the previous programming pulse during the process, a process known as incremental step pulse programming. Each programming voltage is followed by a verification operation to determine whether the memory cell has been programmed to the desired memory state. In some cases, processor 330 monitors the read-back memory state relative to the desired memory state. When both are consistent, processor 330 sets the bit line to a programming-inhibited mode, such as by updating its latch. This prevents further programming of the memory cell coupled to the bit line, even if additional programming pulses are applied to its control gate.

[0090] Figure 4 This is a perspective view as part of an exemplary embodiment of a monolithic three-dimensional memory array / structure that may include memory structure 202, which includes a plurality of non-volatile memory cells arranged as vertical NAND strings. For example, Figure 4 A portion 400 of a memory block is shown. The depicted structure includes a set of bit lines BL, which lie above a stack 401 of alternating dielectric and conductive layers. For illustrative purposes, one of the dielectric layers is labeled D, and one of the conductive layers (also referred to as a word line layer) is labeled W. The number of alternating dielectric and conductive layers can vary based on specific implementation requirements. As will be explained below, in one embodiment, the alternating dielectric and conductive layers are divided into six (or a different number of) regions (e.g., sub-blocks) by isolation regions IR. Figure 4 An isolation region IR separating two sub-blocks is shown. The source line layer SL lies beneath alternating dielectric and word line layers. Memory vias are formed within the stack of alternating dielectric and conductive layers. For example, a memory via is labeled MH. Note that in... Figure 4 In the diagram, the dielectric layers are depicted as a perspective view, allowing the reader to see the memory holes located within the stack of alternating dielectric and conductive layers. In one embodiment, NAND strings are formed by filling the memory holes with a material including a charge-trapping material to form vertical columns of memory cells. Each memory cell can store one or more data bits. Further details of a three-dimensional monolithic memory array including memory structure 202 are provided below.

[0091] Figure 4AThis is a block diagram illustrating an exemplary organization of a memory structure 202, which is divided into two planes 402 and 404. Each plane is then divided into M blocks. In one example, each plane has approximately 2000 blocks. However, different numbers of blocks and planes can also be used. In one embodiment, a block of memory cells is an erase unit. That is, all memory cells in a block are erased together. In other embodiments, blocks can be divided into sub-blocks, and sub-blocks can be erase units. Memory cells can also be grouped into blocks for other reasons, such as to organize the memory structure to enable signaling and selection circuitry. In some embodiments, a block represents a group of connected memory cells because the memory cells in a block share a common set of word lines. For example, all word lines of a block are connected to all vertical NAND strings in that block. Although Figure 4A Two planes 402 / 404 are shown, but more or fewer planes can be implemented. In some embodiments, the memory structure 202 includes eight planes.

[0092] Figures 4B to 4J An exemplary three-dimensional (“3D”) NAND structure is depicted, which corresponds to Figure 4 The structure and can be used to implement Figure 2A and Figure 2B The memory structure 202. Figure 4B This is a top-view block diagram depicting a portion 406 of block 2, which is part of plane 402. (See diagram from...) Figure 4B As can be seen, Figure 4B The block depicted extends along the direction 432. In one embodiment, the memory array has multiple layers; however, Figure 4B Only the top layer is shown.

[0093] Figure 4B Multiple circles are depicted representing vertical columns corresponding to memory holes. Each vertical column includes multiple selection transistors (also called select gates or select cells) and multiple memory cells. In one implementation, each vertical column implements a NAND string. For example, Figure 4B The subsets of the vertical columns / NAND strings 426, 432, 436, 446, 456, 462, 466, 472, 474, and 476 are marked.

[0094] Figure 4B A set of bit lines 415 is also depicted, including bit lines 411, 412, 413, 414, ..., 419. Figure 4B Twenty-four bit lines are shown because only a portion of the block is shown. It is conceivable that more than twenty-four bit lines could be connected to the vertical columns of the block. Each circle representing a vertical column has an "x" to indicate that it is connected to a bit line. For example, bit line 411 is connected to vertical columns 426, 436, 446, 456, 466, and 476.

[0095] Figure 4B The block depicted includes a set of isolation regions 480, 482, 484, 486, and 488, formed of SiO2; however, other dielectric materials may also be used. Isolation regions 480, 482, 484, 486, and 488 are used to divide the top layer of the block into six regions; for example, Figure 4B The top layer depicted is divided into regions 420, 430, 440, 450, 460, and 470, all of which are referred to as sub-blocks. In one implementation, the isolation region is divided only into layers for implementing the select gate, allowing NAND strings in different sub-blocks to be selected independently. In one exemplary embodiment, bit lines are connected to only one vertical column / NAND string in each of the regions (word blocks) 420, 430, 440, 450, 460, and 470. In this embodiment, each block has twenty-four active columns, and each bit line is connected to six rows in each block. In one embodiment, all six vertical columns / NAND strings connected to a common bit line are connected to the same word line (or word line group). Therefore, the system uses a drain-side select line to select one (or a subset of another) of the six for memory operations (programming, verification, reading, and / or erasing).

[0096] although Figure 4B The diagram shows that each region 420, 430, 440, 450, 460, and 470 in a block has four vertical columns, resulting in twenty-four vertical columns for six regions. However, these exact numbers are exemplary implementations. Other implementations may include more or fewer regions per block, more or fewer vertical columns per region, and more or fewer vertical columns per block. Figure 4B It is also shown that the vertical columns are staggered. In other embodiments, different staggering patterns may be used. In some embodiments, the vertical columns are not staggered.

[0097] Figure 4C A portion of one embodiment of the three-dimensional memory structure 202 is depicted, showing along... Figure 4B The cross-sectional view of line AA. This cross-sectional view cuts through the vertical columns (NAND strings) 472 and 474 of region 470 (see...). Figure 4B ). Figure 4C The structure includes: three drain-side select layers SGD0, SGD1, and SGD2; three source-side select layers SGS0, SGS1, and SGS2; three dummy word line layers DD0, DD1, and DDS; two hundred and forty word line layers WL0-WL239 for connecting to data memory cells; and two hundred and five dielectric layers Dl0-DL249. Other embodiments may implement more or fewer of the above-mentioned features. Figure 4CThe numbers mentioned above. In one embodiment, SGD0, SGD1, and SGD2 are connected together, and SGDS0, SGS1, and SGS2 are connected together.

[0098] Vertical columns 472 and 474 are depicted protruding through the drain-side select layer, source-side select layer, dummy word line layer, and word line layer. In one embodiment, each vertical column includes a vertical NAND string. Below the vertical columns and layers are a substrate 453, an insulating film 454 on the substrate, and a source line SL. The NAND string of vertical column 442 has a source terminal at the bottom of the stack and a drain terminal at the top of the stack. Figure 4B middle, Figure 4C A vertical column 472 is shown connected to bit line 414 via connector 417.

[0099] For ease of reference, the drain-side select layer, source-side select layer, dummy word line layer, and data word line layer are collectively referred to as conductive layers. In one embodiment, the conductive layers are made of a combination of TiN and tungsten. In other embodiments, other materials may be used to form the conductive layers, such as doped polysilicon, metals (such as tungsten), or metal silicides. In some embodiments, the different conductive layers may be formed of different materials. Between the conductive layers are dielectric layers DL0-DL249. For example, dielectric layer DL240 is above word line layer WL235 and below word line layer WL236. In one embodiment, the dielectric layers are made of SiO2. In other embodiments, other dielectric materials may be used to form the dielectric layers.

[0100] Non-volatile memory cells are formed along vertical columns that extend through alternating conductive and dielectric layers in the stack. In one embodiment, the memory cells are arranged within a NAND string. Word line layers WL0-W239 are connected to the memory cells (also referred to as data memory cells). Dummy word line layers DD0, DD1, and DS are connected to dummy memory cells. Dummy memory cells do not store host data and are not eligible to store host data (data provided from a host or entity outside the storage system 100, such as data from a host user), while data memory cells are eligible to store host data. Host data can be compared with system data generated by the memory system 100 (e.g., an L2P table). In some embodiments, data memory cells and dummy memory cells may have the same structure. Drain-side select layers SGD0, SGD1, and SGD2 are used to electrically connect and disconnect the NAND string from the bit lines. Source-side select layers SGS0, SGS1, and SGS2 are used to electrically connect and disconnect the NAND string from the source line SL.

[0101] It should be noted that the stacking of word lines WL0-WL239 includes two edge word lines at the edges of the stack, namely the top edge word line WL239 and the bottom edge word line WL0. Word lines WL1-WL238 are non-edge word lines.

[0102] Figure 4D A portion of one embodiment of the three-dimensional memory structure 202 is depicted, showing along... Figure 4B A cross-sectional view of line BB. This cross-sectional view cuts through the vertical columns (NAND strings) 432 and 434 of region 430 (see...). Figure 4B ). Figure 4D It shows the relationship with Figure 4C The same alternating conductive and dielectric layers. Figure 4D Isolation region 482 is also shown. Isolation regions 480, 482, 484, 486, and 488 occupy space already used for a portion of memory vias / vertical columns / NAND strings. For example, isolation region 482 occupies space already used for a portion of vertical column 434. More specifically, a portion of vertical column 434 (e.g., half its diameter) has been removed from layers SDG0, SGD1, SGD2, and DD0 to accommodate isolation region 482. Thus, while most of vertical column 434 is cylindrical (with a circular cross-section), portions of vertical column 434 in layers SDG0, SGD1, SGD2, and DD0 have a semi-circular cross-section. In one embodiment, after forming a stack of alternating conductive and dielectric layers, the stack is etched to create the space for the isolation region, and this space is subsequently filled with SiO2.

[0103] Figure 4E A portion of one embodiment of the three-dimensional memory structure 202 is depicted, showing along... Figure 4B A cross-sectional view of line CC. This cross-sectional view cuts through vertical columns (NAND strings) 452 and 462 (see...). Figure 4B ). Figure 4E It shows the relationship with Figure 4C The same alternating conductive and dielectric layers. Figure 4E The isolation zone 486, cut into vertical columns (NAND strings) 452, is also shown.

[0104] Figure 4F It depicts a portion including vertical column 472. Figure 4CA cross-sectional view of region 429. In one embodiment, the vertical column is circular; however, other shapes may be used in other embodiments. In one embodiment, the vertical column 472 includes an inner core layer 490 made of a dielectric such as SiO2. Other materials may also be used. Surrounding the inner core 490 is a polysilicon channel 491. Materials other than polysilicon may also be used. Note that the channel 491 connects to the bit line and the source line. Surrounding the channel 491 is a tunneling dielectric 492. In one embodiment, the tunneling dielectric 492 has an ONO structure. Surrounding the tunneling dielectric 492 is a charge trapping layer 493, such as, for example, silicon nitride. Other memory materials and structures may also be used. The techniques described herein are not limited to any particular material or structure.

[0105] Figure 4D Dielectric layers DLL239, DLL240, DLL241, DLL242, and DLL243, and word line layers WLL234, WLL235, WLL236, WLL237, and WLL238 are depicted. Each word line layer includes a word line region 496 surrounded by an aluminum oxide layer 497, which is surrounded by a barrier oxide layer 498. In other embodiments, the barrier oxide layer may be a vertical layer parallel to and adjacent to the charge trapping layer 493. The physical interaction of the word line layers with the vertical columns forms a memory cell. Thus, in one embodiment, the memory cell includes a channel 491, a tunneling dielectric 492, a charge trapping layer 493, a barrier oxide layer 498, an aluminum oxide layer 497, and a word line region 496. For example, word line layer WLL238 and a portion of vertical column 472 constitute memory cell MC1. Word line layer WLL237 and a portion of vertical column 472 constitute memory cell MC2. Word line layer WLL236 and a portion of vertical column 472 constitute memory cell MC3. Word line layer WLL235 and a portion of vertical column 472 constitute memory cell MC4. Word line layer WLL234 and a portion of vertical column 472 constitute memory cell MC5. In other architectures, memory cells may have different structures; however, a memory cell will still be a storage cell.

[0106] When a memory cell is programmed, electrons are stored in a portion of the charge trapping layer 493 associated with the memory cell (e.g., within the memory cell). In response to an appropriate voltage on the word line region 496, these electrons are attracted from the channel 491 into the charge trapping layer 493 via tunneling dielectric 492. The threshold voltage (Vth) of the memory cell increases proportionally to the amount of charge stored. In one embodiment, programming is achieved by electrons tunneling into the charge trapping layer via Fowler-Nordheim tunneling. During an erase operation, electrons return to the channel or holes are injected into the charge trapping layer to recombine with electrons. In one embodiment, erasure is achieved using hole injection into the charge trapping layer via a physical mechanism such as GIDL.

[0107] Figure 4G It shows Figure 4F The cross-section of vertical column 472 cuts through MC5. Therefore, Figure 4G The text line layer WL234, inner core 490, channel 491, tunneling dielectric 492, charge trapping layer 493, alumina layer 497, and barrier oxide layer 498 are depicted.

[0108] Figure 4H It shows Figure 4F The cross-section of the vertical column 472 cuts through SGD1 (the select gate layer implementing the select gate). Therefore, Figure 4H The drain-side selector layer SGD1, inner core 490, channel 491, tunneling dielectric 492, charge trapping layer 493, alumina layer 497, and barrier oxide layer 498 are depicted.

[0109] Figure 4I It shows Figure 4D The cross-section of vertical column 434 cuts through SGD1. Therefore, Figure 4I The drain-side selector layer SGD1, inner core 490, channel 491, tunneling dielectric 492, charge trapping layer 493, alumina layer 497, and barrier oxide layer 498 are depicted. Figure 4I A portion of quarantine zone 482 is also shown. (For example...) Figure 4I As can be seen, since the vertical column (NAND string) 434 intersects with the isolation region 482, the select gate (select gate layer and select line layer) of the vertical column 434 is semi-circular (or partially circular).

[0110] Figure 4J yes Figures 4 to 4I A schematic diagram of a portion of the memory array 202 depicted in the figure. Figure 4J The physical data word lines WL0-WL239, which extend across the entire block, are shown. Figure 4J The structure corresponds to Figure 4ASection 306 of block 2 includes bit lines 411. Within this block, in one embodiment, each bit line is connected to six NAND strings. Therefore, Figure 4J The diagram shows bit lines connected to NAND string NS0 (corresponding to column 426), NAND string NS1 (corresponding to column 436), NAND string NS2 (corresponding to column 446), NAND string NS3 (corresponding to column 456), NAND string NS4 (corresponding to column 466), and NAND string NS5 (corresponding to column 476). As described above, in one embodiment, SGD0, SGD1, and SGD2 are connected together to operate as a single logic select gate for each sub-block separated by isolation regions (480, 482, 484, 486, and 486), forming SGD-s0, SGD-s1, SGD-s2, SGD-s3, SGD-s4, and SGD-s5. SGD0, SG1, and SGD2 are also connected together as... Figure 4E The SGS is operated by a single logic select gate. Although the select gates SGD-s0, SGD-s1, SGD-s2, SGD-s3, SGD-s4 and SGD-s5 are isolated from each other due to the isolation region, the data word lines WL0-WL239 of each sub-block are connected together.

[0111] The isolation zones (480, 482, 484, 486, and 486) are used to allow individual control of sub-blocks. The first sub-block corresponds to the vertical NAND strings controlled by SGD-s0. The second sub-block corresponds to the vertical NAND strings controlled by SGD-s1. The third sub-block corresponds to the vertical NAND strings controlled by SGD-s2. The fourth sub-block corresponds to the vertical NAND strings controlled by SGD-s3. The fifth sub-block corresponds to the vertical NAND strings controlled by SGD-s4. The sixth sub-block corresponds to the vertical NAND strings controlled by SGD-s5.

[0112] Figure 4J Only the NAND strings connected to bit line 411 are shown. However, a full schematic of the block would show each bit line and the six vertical NAND strings connected to each bit line.

[0113] Although Figures 4 to 4J An exemplary memory is a three-dimensional memory structure comprising vertical NAND strings with charge trapping material, but other (2D and 3D) memory structures may also be used with the techniques described herein.

[0114] The memory system discussed above can be erased, programmed, and read. At the end of a successful programming process, the threshold voltage of the memory cell should, where appropriate, be within one or more distributions of the threshold voltages of the memory cells used for programming or within the distribution of the threshold voltages of the erased memory cells. Figure 5A This is a graph of threshold voltage versus the number of memory cells, illustrating an exemplary threshold voltage distribution of the memory array when each memory cell stores one bit of data per memory cell. A memory cell that stores one bit of data per memory cell is called a single-level cell (“SLC”). The data stored in an SLC memory cell is called SLC data; therefore, SLC data comprises one bit per memory cell. Data stored as one bit per memory cell is SLC data. Figure 5A Two threshold voltage distributions are shown: E and P. Threshold voltage distribution E corresponds to the erase data state. Threshold voltage distribution P corresponds to the program data state. Therefore, memory cells with a threshold voltage in threshold voltage distribution E are in the erase data state (e.g., they are erased). Therefore, memory cells with a threshold voltage in threshold voltage distribution P are in the program data state (e.g., they are programmed). In one embodiment, erased memory cells store data "1", and programmed memory cells store data "0". Figure 5A The reference voltage Vr is described. By testing (e.g., performing one or more sensing operations) whether the threshold voltage of a given memory cell is higher or lower than Vr, the system can determine whether the memory cell is erased (state E) or programmed (state P). Figure 5A The verification reference voltage Vv is also described. In some implementations, when memory cells are programmed to data state P, the system will test whether these memory cells have a threshold voltage greater than or equal to Vv.

[0115] Figures 5B to 5F An exemplary threshold voltage distribution for a memory array is shown when each memory cell stores multiple bits of data per memory cell. A memory cell that stores multiple bits of data per memory cell is called a multi-level cell (“MLC”). The data stored in an MLC memory cell is called MLC data; therefore, MLC data comprises multiple bits per memory cell. Data stored as multiple bits per memory cell data is MLC data. Figure 5B In one exemplary implementation, each memory cell stores two bits of data. Other implementations may use other data capacities per memory cell (e.g., three, four, five, or six bits of data per memory cell).

[0116] Figure 5BA first threshold voltage distribution E for erasing memory cells is shown. Three threshold voltage distributions A, B, and C for programming memory cells are also depicted. In one embodiment, the threshold voltage in distribution E is negative, and the threshold voltages in distributions A, B, and C are positive. Figure 5B Each distinct threshold voltage distribution corresponds to a predetermined set of values ​​for a set of data bits. In one implementation, each of the two data bits stored in the memory cell resides in a different logical page, referred to as the next page (LP) and the previous page (UP). In other implementations, all data bits stored in the memory cell reside in a common logical page. The specific relationship between the data programmed into the memory cell and the threshold voltage level of that cell depends on the data encoding scheme adopted by the cell. Table 1 provides exemplary encoding schemes.

[0117] Table 1

[0118] E A B C LP 1 0 0 1 UP 1 1 0 0

[0119] In one implementation known as full-sequence programming, it is possible to use Figure 6 The process directly programs memory cells from an erased data state E to any of a programmed data state A, B, or C (discussed below). For example, a group of memory cells to be programmed can be erased first, leaving all memory cells in the group in an erased data state E. The programming process then directly programs the memory cells to data states A, B, and / or C. For example, while some memory cells are being programmed from data state E to data state A, other memory cells are being programmed from data state E to data state B and / or from data state E to data state C. Figure 5B The arrow indicates full-sequence programming. In some implementations, data states AC can overlap, where the memory controller 120 (or memory die 211) relies on error correction to identify the correct data being stored.

[0120] Figure 5C An exemplary threshold voltage distribution for memory cells is depicted, where each memory cell stores three bits of data per memory cell (another example of MLC data). Figure 5CEight threshold voltage distributions corresponding to eight data states are shown. The first threshold voltage distribution (data state) Er represents an erased memory cell. The other seven threshold voltage distributions (data states) AG represent programmed memory cells and are therefore also referred to as programmed states. Each threshold voltage distribution (data state) corresponds to a predetermined set of data bits. The specific relationship between the data programmed into the memory cell and the threshold voltage level of that cell depends on the data encoding scheme adopted by that cell. In one implementation, Gray code allocation is used to assign data values ​​to a range of threshold voltages such that if the memory's threshold voltage is erroneously shifted to its adjacent physical state, only one bit will be affected. Table 2 provides examples of encoding schemes for implementations where each of the three bits of data stored in the memory cell is in a different logical page, referred to as the next page (LP), middle page (MP), and previous page (UP).

[0121] Table 2

[0122] Er A B C D E F G UP 1 1 1 0 0 0 0 1 MP 1 1 0 0 1 1 0 0 LP 1 0 0 0 0 1 1 1

[0123] Figure 5C Seven read reference voltages, VrA, VrB, VrC, VrD, VrE, VrF, and VrG, are shown for reading data from memory cells. By testing (e.g., performing a sensing operation) whether the threshold voltage of a given memory cell is higher or lower than the seven read reference voltages, the system can determine the data state of the memory cell (i.e., A, B, C, D, ...).

[0124] Figure 5C Seven verification reference voltages, VvA, VvB, VvC, VvD, VvE, VvF, and VvG, are also shown. In some embodiments, when memory cells are programmed to data state A, the system tests whether these memory cells have a threshold voltage greater than or equal to VvA. When memory cells are programmed to data state B, the system tests whether these memory cells have a threshold voltage greater than or equal to VvB. When memory cells are programmed to data state C, the system determines whether these memory cells have a threshold voltage greater than or equal to VvC. When memory cells are programmed to data state D, the system tests whether these memory cells have a threshold voltage greater than or equal to VvD. When memory cells are programmed to data state E, the system tests whether these memory cells have a threshold voltage greater than or equal to VvE. When memory cells are programmed to data state F, the system tests whether these memory cells have a threshold voltage greater than or equal to VvF. When memory cells are programmed to data state G, the system tests whether these memory cells have a threshold voltage greater than or equal to VvG. Figure 5CIt also shows Vev, which is the voltage level used to test whether a memory cell has been correctly erased.

[0125] In implementations utilizing full sequence programming, the following can be used: Figure 6 The process involves directly programming memory cells from an erased data state Er to any of the programmed data states AG (discussed below). For example, the group of memory cells to be programmed can be erased first, leaving all memory cells in the group in an erased data state Er. Then, the programming process is used to directly program the memory cells to data states A, B, C, D, E, F, and / or G. For example, while some memory cells are being programmed from data state ER to data state A, other memory cells are being programmed from data state ER to data state B and / or from data state ER to data state C, and so on. Figure 5C The arrow indicates full-sequence programming. In some embodiments, the data state AG may overlap, where the control die 211 and / or memory controller 120 rely on error correction to identify the correct data being stored. It should be noted that in some embodiments, the system may use a multi-pass programming process known in the art instead of full-sequence programming.

[0126] Generally, during verification and read operations, the selected word line is connected to a voltage (an example of a reference signal), the level of which is specific to each read operation (see, for example, [reference]). Figure 5C The read comparison levels VrA, VrB, VrC, VrD, VrE, VrF, and VrG) or verification operations (e.g., see [link to relevant documentation]). Figure 5C The verification target levels (VvA, VvB, VvC, VvD, VvE, VvF, and VvG) are specified to determine whether the threshold voltage of the relevant memory cell has been reached. After the word line voltage is applied, the conduction current of the memory cell is measured to determine whether the memory cell is turned on (conducted current) in response to the voltage applied to the word line. If the conduction current is measured to be greater than a certain value, then it is assumed that the memory cell is turned on and the voltage applied to the word line is greater than the threshold voltage of the memory cell. If the conduction current is not measured to be greater than a certain value, then it is assumed that the memory cell is not turned on and the voltage applied to the word line is not greater than the threshold voltage of the memory cell. During the read or verification process, unselected memory cells are provided with one or more read pass voltages (also known as bypass voltages) at their control gate, causing these memory cells to conduct current as if they were being operated through the gate (e.g., conducting current regardless of whether these memory cells are being programmed or erased).

[0127] There are many methods to measure the conduction current of a memory cell during a read or verification operation. In one example, the conduction current of the memory cell is measured as the rate at which the memory cell discharges or charges a dedicated capacitor in a sense amplifier. In another example, the conduction current of a selected memory cell allows (or does not allow) the NAND string of the memory cell to discharge to the corresponding bit line. The voltage on the bit line is measured after a certain period of time to see if it has discharged. It should be noted that the techniques described herein can be used in conjunction with various methods known in the art for verification / reading. Other read and verification techniques known in the art can also be used.

[0128] Figure 5D The threshold voltage distribution is depicted when each memory cell stores four bits of data (another example of MLC data). Figure 5D The diagram illustrates that some overlap may exist between the threshold voltage distributions (data states) S0-S15. This overlap can occur due to factors such as memory cell charge loss (and thus a drop in threshold voltage). Programming interference can unintentionally increase the threshold voltage of a memory cell. Similarly, read interference can unintentionally increase the threshold voltage of a memory cell. Over time, the position of the threshold voltage distribution can change. Such changes can increase the bit error rate, thereby increasing decoding time or even making decoding impossible. Changing the read reference voltage can help mitigate such effects. Using ECC during the read process can correct errors and ambiguities. Note that in some implementations, the threshold voltage distributions of a group of memory cells storing four bits of data per memory cell do not overlap and are separated from each other; for example, as... Figure 5E What is depicted. Figure 5D The threshold voltage distribution will include reading the reference voltage and verifying the reference voltage, as discussed above.

[0129] When each memory cell uses four bits, the memory can be programmed using the full-sequence programming discussed above or the multi-pass programming process known in the art. Figure 5D Each threshold voltage distribution (data state) corresponds to a predetermined set of values ​​for a set of data bits. The specific relationship between the data programmed into the memory cell and the threshold voltage level of that cell depends on the data encoding scheme adopted by that cell. Table 3 provides examples of encoding schemes in which each of the four bits of data stored in the memory cell resides in different logical pages, referred to as the next page (LP), middle page (MP), previous page (UP), and top page (TP).

[0130] Table 3

[0131] S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 TP 1 1 1 1 1 0 0 0 0 0 1 1 0 0 0 1 UP 1 1 0 0 0 0 0 0 1 1 1 1 1 1 0 0 MP 1 1 1 0 0 0 0 1 1 0 0 0 0 1 1 1 LP 1 0 0 0 1 1 0 0 0 0 0 1 1 1 1 1

[0132] Figure 5FThe threshold voltage distribution is depicted when each memory cell stores five bits of data (another example of MLC data). In one exemplary implementation, when the memory cell stores five bits of data, the data is stored in any of thirty-two data states (e.g., S0-S31).

[0133] Figure 6 This is a flowchart describing one implementation of the process for programming memory cells. For the purposes of this document, the terms program and programming are synonymous with write and writing. In one exemplary implementation, the memory array 202 is executed using one or more control circuits discussed above (e.g., system control logic 260, column control circuit system 210, row control circuit system 220). Figure 6 The process. In one exemplary implementation, Figure 6 The process is performed by integrated memory component 207 using one or more control circuits of control die 211 (e.g., system control logic 260, column control circuitry system 210, row control circuitry system 220) to program memory cells on memory die 201. This process includes multiple loops, each including a programming phase and a verification phase. Figure 6 The process is to achieve full-sequence programming as well as other programming schemes including multi-pass programming. When implementing multi-pass programming, Figure 6 The process is used to implement any / every pass of the multi-pass programming process.

[0134] Typically, during programming operations (via selected data word lines), the programming voltage applied to the control gate is applied as a series of programming pulses (e.g., voltage pulses). Between the programming pulses is a set of verification pulses (e.g., voltage pulses) to perform verification. In many implementations, the amplitude of the programming pulses increases by a predetermined step size with each successive pulse. Figure 6In step 602, the programming voltage signal (Vpgm) is initialized to an initial amplitude (e.g., approximately 12V to 16V or another suitable level), and the programming counter PC maintained by state machine 262 is initialized to 1. In one embodiment, a set of memory cells selected for programming (referred to herein as the selected memory cells) are programmed simultaneously and all connected to the same word line (the selected word line). There may be other memory cells not selected for programming (unselected memory cells) also connected to the selected word line. That is, the selected word line will also be connected to memory cells that should be disabled for programming. Furthermore, when the memory cells reach their expected target data state, they will be disabled for further programming. These NAND strings (e.g., unselected NAND strings) boost their channels to disable programming; these strings include the memory cells to be disabled for programming connected to the selected word line. When the channel has a boosted voltage, the voltage difference between the channel and the word line is insufficient to induce programming. To assist in boosting, in step 604, the control die precharges the channel of the NAND string that includes the memory cells connected to the selected word line that will be disabled for programming. In step 606, a NAND string including a memory cell connected to the selected word line to be disabled for programming is boosted to disable programming. Such a NAND string is referred to herein as an "unselected NAND string". In one embodiment, the unselected word line receives one or more boost voltages (e.g., about 7 volts to 11 volts) (also referred to as pass voltages) to perform a boost scheme. A programming disable voltage is applied to the bit line coupled to the unselected NAND string.

[0135] In step 608, a programming voltage pulse of the programming voltage signal Vpgm is applied to the selected word line (the word line selected for programming). If a memory cell on the NAND string should be programmed, the corresponding bit line is biased at the programming enable voltage. In step 608, programming pulses are simultaneously applied to all memory cells connected to the selected word line, such that all memory cells connected to the selected word line are programmed simultaneously (unless they are disabled for programming). That is, they are programmed at the same time or during an overlap period (both are considered simultaneous). In this way, all memory cells connected to the selected word line will have their threshold voltage changes simultaneously, unless they are disabled for programming.

[0136] In step 610, the memory cell that has undergone programming verification and reached its target state is locked and cannot be further programmed by the control die. Step 610 includes performing programming verification by sensing at one or more verification reference levels. In one embodiment, the verification process is performed by testing whether the threshold voltage of the selected memory cell for programming has reached the appropriate verification reference voltage. In step 610, after the memory cell has been verified (by the test of Vt) that the memory cell has reached its target state, the memory cell can be locked.

[0137] If, in step 612, it is determined that all memory cells have reached their target threshold voltage (pass), the programming process is complete and successful because all selected memory cells have been programmed and verified to their target state. In step 614, a "pass" status is reported. Otherwise, if it is determined in 612 that not all memory cells have reached their target threshold voltage (failure), the programming process continues to step 616.

[0138] In step 616, the number of memory cells that have not yet reached their respective target threshold voltage distributions is counted. That is, the number of memory cells that have failed to reach their target state so far is counted. This counting can be performed by state machine 262, memory controller 120, or another circuit. In one embodiment, there is a total count that reflects the total number of currently programmed memory cells for which the last verification step failed. In another embodiment, a separate count is maintained for each data state.

[0139] In step 618, it is determined whether the count from step 616 is less than or equal to a predetermined limit. In one embodiment, the predetermined limit is the number of bits that can be corrected by error correction codes (ECC) during the page read process of a memory cell. If the number of failed cells is less than or equal to the predetermined limit, the programming process can stop and a "pass" status is reported in step 614. In this case, enough memory cells have been correctly programmed so that ECC can be used during the read process to correct any remaining memory cells that have not yet been fully programmed. In some embodiments, the predetermined limit used in step 618 is lower than the number of bits that can be corrected by error correction codes (ECC) during the read process to allow for future / additional errors. The predetermined limit can be a fraction (proportional or non-proportional) of the number of bits that can be corrected by ECC during the page read process of a memory cell when programming fewer than all memory cells of a page, or when comparing counts of only one data state (or fewer than all states). In some embodiments, the limit is not predetermined. Instead, it varies based on the number of errors already counted for the page, the number of program erase cycles performed, or other criteria.

[0140] If the number of failed memory cells is not less than a predetermined limit, the programming process continues at step 620 and the programming counter PC is checked against the programming limit value (PL). Examples of programming limit values ​​include 6, 12, 16, 19, 20, and 30; however, other values ​​can be used. If the programming counter PC is not less than the programming limit value PL, the programming process is considered to have failed and a "failure" status is reported in step 624. If the programming counter PC is less than the programming limit value PL, the process continues at step 626, during which the programming counter PC is incremented by 1, and the programming voltage signal Vpgm is stepped to the next amplitude. For example, the next pulse will have an amplitude ΔVpgm larger than the previous pulse (e.g., a step size of 0.1 volts to 1.0 volts). After step 626, the process loops back to step 604, and another programming pulse is applied (to the selected word line) to cause execution... Figure 6 Another iteration of the programming process (steps 604-626).

[0141] In one implementation, memory cells are erased before programming, and erasure is the process of changing the threshold voltage of one or more memory cells from a programming data state to an erase data state. For example, changing the threshold voltage of one or more memory cells from... Figure 5A The state changes from P to E. Figure 5B The state changes from A / B / C to E. Figure 5C The state AG changes to state Er or from Figure 5DThe states S1-S15 change to state S0.

[0142] One technique for erasing memory cells in some memory devices is to bias a p-well (or other type) substrate to a high voltage to charge the NAND channel. When the NAND channel is at a high voltage, an erase enable voltage (e.g., a low voltage) is applied to the control gate of the memory cell to erase the non-volatile memory element (memory cell). In this document, this is referred to as p-well erasure.

[0143] Another method for erasing memory cells is to generate a gate-induced drain leakage (GIDL) current to charge the NAND string channel. An erase enable voltage is applied to the control gate of the memory cell while maintaining the NAND string channel potential to erase the memory cell. In this paper, this is referred to as GIDL erase. Both p-well erase and GIDL erase can be used to reduce the threshold voltage (Vt) of the memory cell.

[0144] In one embodiment, a GIDL current is generated by inducing a drain-to-gate voltage at a select transistor (e.g., SGD and / or SGS). The drain-to-gate voltage of the transistor that generates the GIDL current is referred to herein as the GIDL voltage. A GIDL current is generated when the drain voltage of the select transistor is significantly higher than the control gate voltage of the select transistor. The GIDL current is a result of carrier generation, i.e., electron-hole pair generation due to band-band tunneling and / or trap-assisted generation. In one embodiment, the GIDL current can cause one type of carrier (e.g., holes) to move predominantly into the NAND channel, thereby raising the channel potential. Another type of carrier (e.g., electrons) is extracted from the channel by an electric field along the direction of the bit line or along the direction of the source line. During erasure, holes can tunnel from the channel to the charge storage region of the memory cell and recombine with electrons therein to lower the threshold voltage of the memory cell.

[0145] A GIDL current can be generated at either end of the NAND string. A first GIDL voltage can be generated between the two terminals of a select transistor (e.g., a drain-side select transistor) connected to or near the bit line to generate a first GIDL current. A second GIDL voltage can be generated between the two terminals of a select transistor (e.g., a source-side select transistor) connected to or near the source line to generate a second GIDL current. An erase based on the GIDL current at only one end of the NAND string is called a single-sided GIDL erase. An erase based on the GIDL current at both ends of the NAND string is called a double-sided GIDL erase.

[0146] In some implementations, the control die or memory die performs the ECC decoding process (see ECC engine). Error correction is used to help correct errors that may occur when storing data. During the programming process, the ECC engine encodes the data to add ECC information. For example, the ECC engine is used to create codewords. In one implementation, data is programmed on a page-by-page basis. Error correction is used in conjunction with the programming of data pages because errors can occur during programming or reading, and errors can occur when storing data (e.g., due to electronic drift, data retention problems, or other phenomena). Many error correction coding schemes are well known in the art. These conventional error correction codes (ECCs) are particularly useful in high-capacity memories, including flash memory (and other non-volatile) memories, because such coding schemes can have a significant impact on manufacturing yield and device reliability, making devices with a small number of unprogrammable or defective cells usable. Of course, there is a trade-off between yield savings and the cost of providing additional memory cells to store code bits (i.e., encoding "rate"). Therefore, some ECC codes are better suited to flash memory devices than others. Generally, ECC codes for flash memory devices tend to have a higher encoding rate (i.e., a lower code bit / data bit ratio) than codes used in data communication applications (which can have encoding rates as low as half). Well-known examples of ECC codes commonly used with flash memory storage devices include Reed-Solomon codes, other BCH codes, Hamming codes, etc. Sometimes, error correction codes used with flash memory storage devices are "systematic" because the data portion of the final codeword does not change from the actual data being encoded, with code or parity bits appended to the data bits to form the complete codeword. In other implementations, the actual data is altered.

[0147] Specific parameters for a given error-correcting code include the type of code, the size of the block from which the actual data from which the codeword is derived, and the total length of the encoded codeword. For example, a typical BCH code applied to 512 bytes (4096 bits) of data can correct up to four error bits if at least 60 ECC or parity bits are used. Reed-Solomon codes are a subset of BCH codes and are also commonly used for error correction. For example, a typical Reed-Solomon code can correct up to four errors in a 512-byte data sector using approximately 72 ECC bits. In the case of flash memory, error-correcting codes provide significant improvements in manufacturing yield and the reliability of flash memory over time.

[0148] In some implementations, the controller receives host data, also known as information bits, which will be stored in a memory structure. Information bits are represented by a matrix i = [1 0] (note that two bits are used for illustrative purposes only, and many implementations have codewords longer than two bits). An error-correcting coding process (such as any process mentioned above or below) is implemented where parity bits are added to the information bits to provide the data, represented by a matrix or codeword ν = [1 0 1 0], indicating that two parity bits have been appended to the data bits. Other techniques can be used to map input data to output data in a more complex manner. For example, low-density parity-check (LDPC) codes, also known as Gallager codes, can be used. Further details on LDPC codes can be found in RG Gallager's "Low-density parity-check codes", IRE Trans. Inform. Theory, vol. IT-8, pp. 21-28, Jan. 1962; and D. MacKay's Information Theory, Inference and Learning Algorithms, Cambridge University Press, 2003, chapter 47. In practice, such LDPC codes are typically applied to multiple pages encoded across multiple memory elements, but they do not necessarily need to be applied across multiple pages. Data bits can be mapped to logical pages and stored in memory structure 326 by programming one or more memory cells to one or more programming states corresponding to a matrix or codeword ν.

[0149] In one possible implementation, an iterative probabilistic decoding process is used, which corresponds to the error-correcting decoding of the encoding implemented in controller 120. Further details regarding iterative probabilistic decoding can be found in the aforementioned D. MacKay text. Iterative probabilistic decoding attempts to decode the codeword by assigning an initial probability metric to each bit in the codeword. The probability metric indicates the reliability of each bit, that is, the probability that the bit is not erroneous. In one approach, the probability metric is the log-likelihood ratio (LLR) obtained from an LLR table. The LLR value is a measure of the known reliability of the values ​​of the various binary bits read from the storage element.

[0150] The LLR of 1 bit is given by the following formula:

[0151]

[0152] Where P(v = 0 | Y) is the probability that a bit is 0 given a read state of Y, and P(v = 1 | Y) is the probability that a bit is 1 given a read state of Y. Therefore, an LLR > 0 indicates that a bit is more likely to be 0 than 1, and an LLR < 0 indicates that a bit is more likely to be 1 than 0, to satisfy one or more parity checks of the error correction code. Furthermore, a larger magnitude indicates a greater probability or reliability. Therefore, a bit with LLR = 63 is more likely to be 0 than a bit with LLR = 5, and a bit with LLR = -63 is more likely to be 1 than a bit with LLR = -5. An LLR = 0 indicates that a bit can also be either 0 or 1.

[0153] An LLR value can be provided for each bit position in a codeword. Furthermore, the LLR table can specify multiple reads, allowing a larger LLR value to be used when bit values ​​are consistent across different codewords.

[0154] The controller receives codeword Y1 and LLR and iterates in successive iterations, where the controller determines whether the parity (equation) of the error encoding process has been satisfied. If all parity checks have been satisfied, the decoding process has converged and the codeword has been corrected. If one or more parity checks have not been satisfied, the decoder adjusts the LLR of one or more bits that are inconsistent with the parity check, and then reapplies the parity check or the next check in the process to determine whether it has been satisfied. For example, the magnitude and / or polarity of the LLR can be adjusted. If the parity check in question is still not satisfied, the LLR can be adjusted again in another iteration. In some, but not all, adjusting the LLR may result in bit flipping (e.g., from 0 to 1 or from 1 to 0). In one implementation, once the parity check in question is satisfied, another parity check is applied to the codeword, if applicable. In other cases, the process moves to the next parity check and later loops back to the failed check. The process continues to attempt to satisfy all parity checks. Thus, the decoding process of Y1 is completed to obtain decoding information including parity bit v and decoding information bit i.

[0155] Figure 7 The standard read flow combining ECC correction and read error handling is illustrated. Step 701 involves reading data stored in a memory cell to determine a "hard bit" (HB), where the hard bit value corresponds to the value used. Figures 5A to 5C The standard reading of the value Vri is used to distinguish different states (if they are as follows). Figures 5A to 5C(A well-defined, separated distribution as in the example). Step 703 uses ECC technology to determine whether the read data is correctable, and if so, the read process is completed at step 705. When the hard bit data becomes uncorrectable by ECC in step 703, a read error handling flow can be invoked at step 707, which may involve various read types to recover the read data. According to the implementation, some examples of read types that can be used to recover data content are: "CFh read" 711, which is a hard bit reread that allows an unselected word line of the NAND string to reach the bias voltage for a longer time, or other alternative read bias timing, such as allowing the bias level (such as the voltage of the selected word line) to settle for a longer time; "soft bit" read 713, which provides information about the reliability of the hard bit value; "BES read" 715, which attempts to offset the hard bit read level in order to extract the data; and "DLA read" 717, which takes into account the influence of adjacent word lines on the read selected word line. One or more of these can be combined in various sequences or combinations to attempt and extract data content in the event of a failure of the basic ECC process. For any implementation scheme, performance is typically severely degraded once the read error handling flow 707 is invoked as step 703. The following considers techniques for using soft-bit data while mitigating its impact on memory performance. Figure 8 Consider the uses of soft positions in more detail.

[0156] Figure 8 It can be used to illustrate the concepts of hard bits and soft bits. Figure 8 The diagram illustrates the overlap of distributions of two adjacent data states and a set of read values ​​that can be used to determine the data state of a cell and the reliability of such reads. The corresponding hard and soft bits for a specific encoding of the value are shown in the table below. The read value VH is the initial data state value or hard read value used to determine the hard bit (HB) value, and corresponds to... Figure 5A , Figure 5B or Figure 5C The value Vri is used to distinguish different states (if they are as follows). Figures 5A to 5C (A well-defined, separated distribution like that in [the original text]). Additional read levels, VS+ with a margin slightly above VH and VS- with a margin slightly below VH, are "soft read" values ​​and can be used to provide "soft bit" (SB) values. Soft bit values ​​give information about the quality or reliability of the initial data state or hard bit data, as soft bit data provides information about the extent to which the distribution has been expanded. Some implementations of ECC codes (such as Low-Density Parity-Check (LDPC) codes) can use both hard and soft bit data to increase their capabilities. Although... Figure 8Only one pair of soft-bit readouts is shown, but other implementations can use additional readouts with margin to generate more soft-bit values ​​for a given hard bit if higher resolution is desired. More generally, a hard bit corresponds to a hypothetical data value based on sensing operations, and soft information (which can be a single binary soft bit, multiple soft bits, or a decimal / minute value) indicates the reliability or confidence level of the hard-bit value. When used in ECC methods that utilize soft information, the soft information can be considered as the probability that the corresponding hard-bit value is correct.

[0157] During a read operation, if VH is below the memory cell threshold, the memory cell will be non-conductive, and the read data value (HB) will be read as "0". If the memory cell is below the threshold, the read data value will be non-conductive. Figure 8 If the data is within the central region of either distribution, then reads of VS+ and VS- will provide the same result; if these reads differ, the threshold voltage of the memory cell lies between these values ​​and may originate from the tail region of either the upper or lower distribution, making the HB data unreliable. If the data is considered reliable, reading at both levels and performing an XOR NOT operation on the result gives an SB value of "1"; if unreliable, an SB value of "0" is given.

[0158] For example, when both SB+ and SB- read "0", then:

[0159] SB = (SB+) × NOR (SB-)

[0160] = "0" x NOR "0"

[0161] =1,

[0162] SB=1 and the HB read value will be considered reliable. During soft bit decoding in ECC, this will result in memory cells in the upper distribution having HB="0" and SB="1" to indicate a reliable correct bit (RCB), while memory cells with a threshold voltage between SB+ and SB- will result in SB="0" to indicate that the HB value is unreliable.

[0163] Figure 9A and Figure 9B The read levels for calculating the hard and soft bit values ​​of the next page data in a three-bit data implementation per memory cell using the encoding in Table 2 above are shown respectively, wherein the soft bit values ​​1 and 0 indicate that the hard bit value is reliable and unreliable, respectively. Figure 9A This shows the threshold voltage distribution of memory cells in each 3-bit unit, similar to... Figure 5CAs shown, the distribution is not well-defined and exhibits some overlap. This overlap can arise from several causes, such as charge leakage or interference, where an operation on one word line or bit line affects the data state stored in nearby memory cells. Furthermore, in actual write operations, the distribution typically does not behave as expected. Figure 5C The definition is not ideal because writing to memory cells with such accuracy would be detrimental to performance, as a large number of fine-grained programming steps would make some cells difficult or overly fast to program. Therefore, programming algorithms typically allow for a degree of overlap, relying on ECC to accurately extract user data content.

[0164] The read points used to distinguish the data values ​​for the next page are represented by vertical dashed lines between Er and A states, and between D and E states, and the corresponding hard bits written below. Due to overlapping distributions, multiple memory cells storing Er or E data will be incorrectly read as HB = 0, and multiple memory cells storing A or D data will be incorrectly read as HB = 1. For example, the optimal read value can be determined as part of the device characterization and stored as the fuse value of the control circuitry system. In some implementations, the control circuitry can offset these values ​​to improve its accuracy as part of a standard read operation or as part of the read error handling flow 707 of the BES read 715.

[0165] To handle higher error rates, a more robust ECC can be used. However, this requires storing more parity bits, reducing the proportion of memory available for user data and thus effectively decreasing memory capacity. Furthermore, performance is impacted because more computation is involved in encoding / decoding codewords and writing and reading additional ECC data. Additionally, ECC data needs to be transferred to and from the ECC circuitry via a data bus structure.

[0166] Figure 9B It shows that it can be used to determine the corresponding Figure 9A The soft bit value and read point of the next page hard bit value. As shown, the soft bit value is determined to either side of the basic hard bit read value based on a pair of reads. For example, these soft bit read values ​​may be based on an offset from the hard bit read value, and may be symmetrical or asymmetrical, and are stored as fuse values ​​in a register that is determined as part of the device characterization. In other implementations, they may be determined or updated dynamically. Although using soft bits at step 713 may be quite efficient in retrieving data content that cannot be retrieved in step 703, it comes with a performance penalty because it requires being invoked in response to an ECC failure at step 703, uses two additional reads for each hard bit read, requires the soft bit data to be transmitted after the additional reads, and requires additional calculations.

[0167] To improve this situation, an implementation scheme of "Effective Soft Sensing Mode" is introduced below. In this sensing mode, hard and soft reads can be combined into a sequence using two sensing levels to sense time efficiency. By using Effective Soft Sensing Read as the default mode, additional soft bit information can be provided for ECC correction without triggering the read error handling process. Since only two sensing operations are used to generate hard and soft bit data, this technique avoids the threefold increase in sensing time caused by standard hard and soft reads. Furthermore, by merging hard and soft bit sensing into a single sequence, most of the additional overhead involved in read sequence operations (e.g., enabling charge pumps, ramping word lines, etc.) can be avoided. Figure 10 The use of the effective soft sensing mode is shown.

[0168] Figure 10 The assignment of hard and soft bit values, along with the read level, is shown in an implementation for effective soft sensing. Figure 10 Similar to Figure 8 The diagram illustrates a distribution of memory cells Vth that again overlaps with two data states in the central region. A hard read is performed again, but instead of attempting to place it at or near the center of the overlapping region at an optimized point to distinguish the two states, in this embodiment, the hard read is offset to the lower Vth side, such that any memory cell read at or below VH is reliably in the lower data state (shown here as "1", as in the exemplary diagram). Figure 8 (in Chinese). It also assigns a soft bit value of "0", which is related to... Figure 8 Compared to the previous implementation, the SB=0 value now indicates a reliable HB value. If a memory cell reads above VH, its hard bit value corresponds to a higher Vth data state with HB=0. Figure 10 In the implementation plan, different Figure 8 Of the two soft-bit reads, only a single soft-bit read is performed as a VS value offset to the high Vth side. If a memory cell's Vth is found to be higher than VS, it is assigned an HB value of HB=0 and is considered reliable (HS=0). For memory cells with a Vth found between VH and VS, the memory cell is assigned HB=0 but is considered unreliable (SB=1). Note that in Figure 10In this implementation, only one of the two states is checked for the soft bit data, such that only the HB=0 state can have any SB value, while the HB=1 memory cell will always have SB=0. In other words, the soft bit data is determined only on one side of the overlapping distribution (here, the lower side, for HB=0), and not on the other side (here, the higher side, for HB=1). In this implementation, a single VS read is performed on the left side of the VH read (higher Vth), but in other implementations, this arrangement can be reversed.

[0169] although Figure 10 The total amount of data generated in the implementation plan is less than Figure 8 The total amount of data, but Figure 10 An effective soft-sensing mode will generally be sufficient to extract user data content without excluding further read error handling. Because in Figure 10 The determination involves only two readings, so the sensing time is short, and can be further reduced by performing the two readings as a single sensing operation, such as relative to... Figure 12 The increased error tolerance provided by effective soft sensing also improves write performance because the data does not need to be precisely programmed, allowing for relaxed programming tolerances.

[0170] Figure 11 The diagram illustrates how the coding in Table 2 is used in a three-bit data implementation per memory cell to apply an effective soft-sensing mode to the next page of data. Figure 11 Similar to Figure 9A and Figure 9B However, the HB and SB values ​​are combined into a single graph, and a single SB read level is used for a given HB read level for effective soft sensing, instead of a pair of SB reads for a given HB. For example, observe the difference between Er and A states. For a left-hand read, the left memory cell is reliably "1" for the next page value, where (HB,SB) = (1,0). Note again that in this encoding, SB = 0 indicates a reliable HB value, and SB = 1 indicates an unreliable HB value. For a right-hand read of Er and A, the right memory cell indicates a memory cell with a reliable next page value of "0" or (HB,SB) = (0,0). Memory cells with Vth between the left and right read levels are assigned a next page hard value of 0 but are considered unreliable, such that (HB,SB) = (0,1). Similarly, for reads that distinguish between states D and E, the memory cell to the left of the left read is reliably "0" ((HB,SB)=(0,0)), the memory cell above the right read is a reliable next page "1" data ((HB,SB)=(1,0)), and the memory cell in between is assigned an unreliable next page value of "1" ((HB,SB)=(1,1)).

[0171] Figure 12 It shows the corresponding Figure 11 The illustration shows an implementation of a sensing operation for the next page data read operation in an effective soft-sensing read operation. At the top, Figure 12 This diagram illustrates the relationship between the control gate read voltage VCGRV waveform that can be applied to the word line of a selected memory cell and the effective soft sensing time of the 3 bits of next-page data per memory cell, where the vertical dashed line corresponds to... Figure 11 The four readings are also marked with dashed lines (but the determined order is different, as will be explained below). Below the waveform, it is shown how these readings using the waveform at the top correspond to the Vth values ​​of the D and E state distributions.

[0172] To improve read time performance Figure 12 The implementation uses a "reverse order" read mode, but other implementations can use a standard sequence. In a standard read sequence, the read voltage applied to the selected memory cell starts at a lower limit and gradually increases. In reverse order read mode, the control gate read voltage (VCGRV) applied to the selected word line initially ramps up to a high value and then the read is performed from a higher Vth state to a lower Vth state. In this example of a next-page read, reads distinguishing between D and E states are performed before reads distinguishing between A state and Er state. Therefore, after the initial ramp, the VCGRV voltage drops to the read level of E state (ER) and then drops to the read level of A state (AR). This sequence reduces the time required for the significant additional overhead involved in read sequence operations (e.g., enabling charge pumps, ramping up word lines, etc.).

[0173] For each read voltage level, two sensing operations are performed to generate a hard bit and a soft value, allowing for a faster sensing time than using a single read voltage. (Reference) Figure 12 The D and E state distributions at the bottom, the dashed lines for the HB and SB boundaries, both represent relatively close Vth values, but the SB boundary is offset to the right with a higher Vth value. Therefore, in embodiments where sensing is based on discharging voltage through selected memory cells, if a read voltage ER is chosen, the HB and SB Vth values ​​are conducted to some extent, but by different amounts. The HB boundary corresponds to a lower Vth value because the memory cell at the SB boundary will be more conductive, thus discharging faster, and can be determined using a shorter sensing interval. The slower-discharging SB boundary is sensed using the same control gate voltage, but with a longer sensing time.

[0174] Figure 13 An implementation scheme of a sensing amplifier circuit that can be used to determine the hard and soft bit values ​​of a memory cell is shown. Figure 13 The sensing amplifier circuit can correspond to Figure 2A Or a 2B sensing amplifier 230, and as included Figure 3 In the structure. In Figure 13 In one implementation, the state of the memory cell is determined by pre-charging the sensing line or node SEN 1305 to a predetermined level, connecting the sensing node to the bit line of the bias-selected memory cell, and determining the degree to which the node SEN 1305 discharges within the sensing interval. Many variations are possible depending on the implementation, however... Figure 13 The implementation scheme illustrates some typical components. Node SEN 1305 can be precharged to level VHLB via switch SPC 1323, where many MOSFET switches are notated here using the same names and corresponding control signals as transistors, where various control signals can be controlled by processor 330, state machine 262, and / or Figure 2A , Figure 2B and Figure 3 Other control elements are provided for the implementation scheme. Node SEN 1305 can be connected to the selected memory cell via switch XXL 1319 to node SCOM 1307 along bit line BL 1309, and then connected after possible intermediate elements to bit line selection switch BLS 1327 corresponding to the decoding and selection circuitry of the memory device. SEN node 1305 is connected to the local data bus LBUS 1301 via switch BLQ 1313, which can then be connected to data DBUS 1303 via switch DSW 1311. Switch LPC 1321 can be precharged to level VLPC, where the values ​​of VHLB and VLPC depend on the details of the implementation scheme and specific implementation.

[0175] In the sensing operation, the selected memory cell is biased by setting its corresponding selected word line to the read voltage level as described above. In a NAND array implementation, the selected gate of the NAND string of the selected word line and the unselected word line are also biased to ON. Once the array is biased, the selected memory cell conducts a level based on the relationship between the applied read voltage and the threshold voltage of the memory cell. Capacitor 1325 can be used to store charge on SEN node 1305, wherein during pre-charging, level CLK (and the lower plate of capacitor 1325) can be set to a low voltage (e.g., ground or VSS) such that the voltage on SEN node 1305 references this low voltage. The pre-charge SEN node 1305 of the selected memory is connected to the corresponding bit line 1309 via XXL 1319 and BLS 1327 to the selected bit line and is allowed to discharge to a level dependent on the threshold voltage of the memory cell within the sensing interval relative to the voltage level applied to the control gate of the selected memory cell. At the end of the sensing interval, XXL 1319 can be turned off to trap the resulting charge on SEN 1305. At this time, the CLK level can be slightly increased, similarly increasing the voltage on SEN 1305 to account for the voltage drop across intermediate components (such as XXL 1319) in the discharge path. Therefore, the voltage level on SEN 1305 that controls the degree to which transistor 1317 is turned on will reflect the data state of the selected memory cell relative to the applied read voltage. Local data LBUS 1301 is also pre-charged so that LBUS will discharge to the CLK node as determined by the voltage level on SEN 1305 during the continuous gating interval when turn-on transistor STB 1315 is on. At the end of the gating interval, STB 1315 is turned off to set the sensed value on LBUS, and the result can be latched into one of the latches, such as... Figure 3 As shown.

[0176] Now return to the reference. Figure 12 After biasing the selected memory cell to the ER voltage level and other array biases (select gate, unselected word line, etc.) as needed, the precharged SEN node 1305 is discharged against the interval ER between the dashed lines: if the level on SEN is high enough to discharge LBUS 1301 when STB1315 is selected, the Vth of the memory cell is lower than HB; otherwise, it is higher than HB. After discharging the additional interval ER+, STB 1315 is re-selected: if LBUS 1301 is now discharged, the Vth of the memory cell is between HB and SB; otherwise, it is higher than SB. This process is then repeated with the VCGRV value at the AR level to determine the HB and SB values ​​used to distinguish between the A state and the erase state.

[0177] Therefore, in relation to Figure 12 Under the illustrated implementation, for each VCGRV level, the left sensing result is used to generate HB data, and the right sensing result is combined with the left sensing result to generate SB data. To optimize the performance of the two senses (left / right), Figure 12 The implementation scheme uses "sensing time modulation" for Vth separation without word line voltage level changes.

[0178] In contrast to the effective soft-sensing read level control and parameters, similar to typical implementations of read parameters, these can be determined as part of the device characterization process and stored as register values ​​(such as control data parameters set to fuse values ​​in memory device 266), dynamically determined, or some combination thereof. In one set of implementations, the hard-bit and soft-bit read levels for effective soft sensing can be referenced to standard hard read values. Even when using the effective soft-sensing read process as the default read operation, memory devices typically have a standard read (i.e., hard-bit only) read mode option, making... Figures 5A to 5C The standard read value will be available as a read option. For example, return to see Figure 11 The read levels associated with distinguishing between the D and E state distributions can be referenced to the effective soft-sensing level relative to the normal HB read trim value, represented as a heavier dashed line at the apex of the D and E state distributions. The effective soft-sensing read levels for left reads (effective soft-sensing hard bit, decremented) and right reads (effective soft-sensing soft bit, incremented) can be specified relative to the normal HB read levels. This allows for the reuse of the group feature register to generate effective soft-sensing left / right offsets, and in one set of implementations, a common setting can be used across all planes, with separate settings for each state.

[0179] Figure 14 This is a high-level flowchart of an implementation scheme for effective soft sensing operations. (See the above section regarding...) Figures 1 to 4J The memory system and relative to Figure 12 The process is described within the context of the described embodiment. The process begins at step 1401 to perform a first sensing operation on a plurality of memory cells to determine a hard bit value that distinguishes between two data states in the data states of the memory cells. In an effective soft-sensing embodiment, both the hard bit read in step 1401 and the soft bit read in step 1403 can be responded to a single read command. For example, see [link to previous section] Figure 1 The host 102 and / or non-volatile memory controller 120 can issue valid soft-sensing commands to one or more of the memories 130. Then, system control logic 260 ( Figure 2A and Figure 2B Performing sensing operations, such as reading the next page data in the example above, to determine both the hard bit value and the soft bit value of the memory cell, such as... Figure 11 As shown.

[0180] To perform the hard bit determination in step 1401, in the above embodiment, the memory array is biased for read operations, and the sensing nodes of one or more corresponding sense amplifiers are pre-charged. More specifically, for the embodiment used as an example herein, the control gate of the selected memory cell is biased by the read voltage through its corresponding word line for distinguishing between data states, and other array elements (e.g., selected gates and unselected word lines of NAND strings) are biased as needed based on the memory architecture. When using, such as Figure 13 When using a sensing amplifier such as a sensing amplifier, in the case of determining the data state while discharging the sensing node SEN 1305, the sensing node SEN 1305 is pre-charged and connected to the bit line of the selected memory cell for the first sensing interval ( Figure 12 Discharge within the ER(HB) boundary region to determine the hard potential value.

[0181] As relative to Figure 11 As shown in the implementation, the hard bit determination is offset to a lower Vth value, so memory cells sensed below this value are reliably within that value, while memory cells sensed above this value include both reliable and unreliable hard bit values. In an implementation using more conventional sequential sensing, hard bit sensing for the hard bit is performed first, followed by soft bit sensing for differentiation between Er and A states, and then both hard and soft bit sensing for differentiation between D and E states, each of which involves different biases and sensing node pre-charges for each sensing operation. In relation to... Figure 12 In the reverse sequence sensing operation shown, hard and soft bit values ​​are first determined for the D and E states, and then hard and soft bit values ​​are determined for the Er and A states. Although Figure 14 The process typically involves hard bit determination (step 1401) preceding soft bit determination (step 1403), but in some implementations, the order can be reversed. Additionally, Figure 14 The process involves only a single hard bit and a single soft bit determination, which is insufficient in many cases (such as in...). Figure 12 (In the middle), multiple hard / soft bit pairs will be identified.

[0182] At step 1403, a second sensing operation is performed to determine soft bits. During effective soft sensing, this is reliability information determined only for memory cells that have a first hard bit value but not a second hard bit value. For example, in Figure 11 In the implementation scheme, when the hard bit boundary shifts downward, the soft bit value is used only for the higher of the hard bit values. In relation to... Figure 12In the described implementation, the second sensing operation is based on the longer discharge time of the pre-charged sensing node SEN 1305. If the read involves distinguishing between a pair of states (as in the binary memory cell implementation), only one hard-bit / soft-bit pair is determined. In the case of a multilevel memory cell, as described above... Figure 11 and Figure 12 In the example, additional hard and soft bit pairs are determined, where the next page sensing operation is similar to steps 1401 and 1403 used for Er / A state determination in determining the hard and soft bit pairs. Once the hard and soft bit data values ​​are determined, they can be used to perform ECC operations at step 1405. This can be done on the non-volatile memory controller 120 in ECC engine 158, on control die 211, or some combination thereof.

[0183] According to the first aspect, the non-volatile memory device includes control circuitry configured to be connected to one or more non-volatile memory cells. The control circuitry is configured to: perform a first hard bit read operation at a read level, the read level being configured to determine a first hard bit value for each of one or more selected non-volatile memory cells, the first hard bit value indicating whether the memory cell is reliably in a first data state or unreliably in a second data state; perform a first soft bit read operation, the first soft bit read operation being configured to generate a first soft bit value, the first soft bit value indicating a reliability value for each of the memory cells determined to be in the second data state, but not for the memory cells determined to be in the first data state; and provide the first hard bit value and the first soft bit value to an error correction code engine, the error correction code engine being configured to determine the data content of the selected memory cells from the first hard bit value and the first soft bit value.

[0184] In another aspect, a method includes performing a first sensing operation on a plurality of non-volatile memory cells to distinguish between a first data state and a second data state of the non-volatile memory cells. A second sensing operation is then performed on the memory cells via the first sensing operation to determine the reliability of the first sensing operation for memory cells determined to be in the second data state, but not for memory cells determined to be in the first data state. The result of the first sensing operation and the reliability of the first sensing operation are used to perform an error correction code operation for memory cells determined to be in the second data state, but not for memory cells determined to be in the first data state, to determine the data content stored in the plurality of non-volatile memory cells.

[0185] Other aspects include a non-volatile memory device comprising: a plurality of non-volatile memory cells, each configured to hold a plurality of data bits; a sense amplifier circuit including a sense node configured to be connected to a first selected memory cell; and one or more control circuits connected to the plurality of non-volatile memory cells and the sense amplifier. The one or more control circuits are configured to receive a read command and, in response to the read command,: bias the selected memory cell at a read voltage level; precharge the sense node; discharge the precharged sense node through the biased selected memory cell during a first sensing interval; determine a hard bit value of the selected memory cell based on the amount of discharge of the sense node during the first sensing interval; after discharging the sense node during the first sensing interval, continue discharging the precharged sense node through the biased selected memory cell during an additional sensing interval; and determine a first soft bit value of the first selected memory cell based on the amount of discharge of the sense node during the combined first and additional sensing intervals.

[0186] For the purposes of this document, the terms “implementation scheme,” “one implementation scheme,” “some implementation schemes,” or “another implementation scheme” used in the specification may be used to describe different implementation schemes or the same implementation scheme.

[0187] For the purposes of this document, a connection may be a direct connection or an indirect connection (e.g., via one or more other components). In some cases, when a component is referred to as being connected or coupled to another component, the component may be directly connected to the other component or indirectly connected to the other component via an intermediary component. When a component is referred to as being directly connected to another component, there is no intermediary component between the two components. If two devices are directly or indirectly connected, the two devices are “communicating”, enabling them to exchange electronic signals with each other.

[0188] For the purposes of this document, the term “based on” may be understood as “at least partially based on”.

[0189] For the purposes of this document, the use of numerical terms such as “first” object, “second” object, and “third” object without additional context may not imply an ordering of objects, but may be used for identification purposes to distinguish different objects.

[0190] For the purposes of this document, the term "group" of objects may refer to a "group" of one or more objects.

[0191] The detailed description above has been provided for purposes of illustration and description. It is not intended to be exhaustive or to limit the precise forms disclosed in the invention. Many modifications and variations are possible based on the teachings above. The described embodiments were chosen to best explain the principles of the proposed technology and its practical application, thereby enabling others skilled in the art to best utilize it in various embodiments and various modifications suitable for the specific intended use. The scope of the invention is intended to be defined by the appended claims.

Claims

1. A non-volatile memory device, comprising: A control circuit, configured to be connected to one or more non-volatile memory cells, is configured to: In the first read mode, a read operation is performed, and the control circuit is configured as follows: A first hard bit read operation is performed at a read level, the read level being configured to determine a first hard bit value for each of one or more selected non-volatile memory cells, the first hard bit value indicating whether the memory cell is reliably in a first data state or unreliably in a second data state. A first soft bit read operation is performed, the first soft bit read operation being configured to generate a first soft bit value, the first soft bit value indicating a reliability value for each of the memory cells determined to be in the second data state, but not for the memory cells determined to be in the first data state; as well as The first hard bit value and the first soft bit value are provided to the error correction code engine, which is configured to determine the data content of the selected memory cell from the first hard bit value and the first soft bit value. In the second read mode, the read operation is performed, and the control circuit is configured as follows: Perform a read operation to distinguish between the first data state and the second data state based solely on the second hard bit read value; as well as The parameter values ​​for performing the first hard bit read operation and for performing the first soft bit read operation are stored as offsets relative to the parameter values ​​configured to perform the read operation for distinguishing between the first data state and the second data state based solely on the second hard bit read value.

2. The non-volatile memory device according to claim 1, wherein the control circuit is formed on a control die, and the non-volatile memory device further comprises: A memory die, the memory die including the non-volatile memory cell, the memory die being separately formed from and coupled to the control die.

3. The non-volatile memory device according to claim 1, wherein the first data state and the second data state correspond to different threshold voltage ranges, and the first data state corresponds to a lower threshold voltage.

4. The non-volatile memory device according to claim 1, wherein the control circuit comprises: A sensing amplifier circuit, the sensing amplifier circuit including a sensing node configured to be connected to a first selected memory cell, wherein, in order to perform the first hard bit read operation and the first soft bit read operation on the first selected memory cell, the control circuit is configured to: The first selected memory cell is biased at a first voltage level; Precharge the sensing node to a first level; During the first sensing interval, the sensing node, pre-charged to the first level, is discharged through the first selected memory cell biased at the first voltage level. The first hard bit value of the first selected memory cell is determined based on the amount of discharge of the sensing node during the first sensing interval. After discharging the sensing node within the first sensing interval, the sensing node, pre-charged to the first level, is further discharged within the first additional sensing interval via the first selected memory cell biased at the first voltage level; and The first soft bit value of the first selected memory cell is determined based on the amount of discharge of the sensing node during the combined first sensing interval and first additional sensing interval.

5. The non-volatile memory device of claim 4, wherein the non-volatile memory cell is a multi-level memory cell, and the control circuit is further configured to perform the read operation in the first read mode as follows: A third hard bit read operation is performed at a read level, the read level being configured to determine a third hard bit value for each of one or more selected non-volatile memory cells, the third hard bit value indicating whether the memory cell is reliably in a third data state or unreliably in a fourth data state. A second soft bit read operation is performed, which is configured to generate a second soft bit value for each of the memory cells determined to be in the fourth data state, but not for the memory cells determined to be in the third data state; as well as The third hard bit value and the second soft bit value are provided to the error correction code engine, which is further configured to determine the data content of the selected memory cell from the third hard bit value and the second soft bit value.

6. The non-volatile memory device according to claim 5, wherein, In order to perform the third hard bit read operation on the first selected memory cell and perform the second soft bit read operation, the control circuit is configured to: The first selected memory cell is biased at the second voltage level; Precharge the sensing node to the second level; During the second sensing interval, the sensing node, which is precharged to the second level, is discharged through the first selected memory cell biased at the second voltage level. The third hard bit value of the first selected memory cell is determined based on the amount of discharge of the sensing node during the second sensing interval; After discharging the sensing node within the second sensing interval, the sensing node, pre-charged to the second level, is discharged again within the second additional sensing interval by the first selected memory cell biased at the second voltage level. as well as The second soft bit value of the first selected memory cell is determined based on the amount of discharge of the sensing node during the combined second sensing interval and the second additional sensing interval.

7. The non-volatile memory device of claim 6, wherein the second voltage level is lower than the first voltage level, and the control circuit is configured to determine the first hard bit value and the first soft bit value before calculating the third hard bit value and the second soft bit value.

8. The non-volatile memory device of claim 1, wherein the non-volatile memory cell is a multi-level memory cell, and the control circuit is further configured to perform the read operation in the first read mode as follows: A third hard bit read operation is performed at a read level, the read level being configured to determine a third hard bit value for each of one or more selected non-volatile memory cells, the third hard bit value indicating whether the memory cell is reliably in a third data state or unreliably in a fourth data state. A second soft bit read operation is performed, which is configured to generate a second soft bit value for each of the memory cells determined to be in the fourth data state, but not for the memory cells determined to be in the third data state; as well as The third hard bit value and the second soft bit value are provided to the error correction code engine, which is further configured to determine the data content of the selected memory cell from the third hard bit value and the second soft bit value.

9. The non-volatile memory device of claim 6, wherein the multilevel memory cell stores data values ​​as a plurality of data pages, and wherein the first hard bit value and the third hard bit value correspond to the value of the first data page in the data pages.

10. The non-volatile memory device of claim 1, wherein at least a portion of the error correction code engine is formed on the control circuit, and the non-volatile memory device is further configured to: The error correction engine receives the first hard bit value and the first soft bit value; and The data content of the selected memory cell is determined from the first hard bit value and the first soft bit value.

11. The non-volatile memory device according to claim 1, further comprising: A non-volatile memory controller, the non-volatile memory controller including the error correction code engine; as well as A bus structure, wherein the control circuitry is configured to provide the first hard bit value and the first soft bit value to the error correction code engine via the bus structure.

12. The non-volatile memory device according to claim 1, further comprising: NAND memory array, the NAND memory array comprising one or more non-volatile memory cells formed according to a three-dimensional architecture.

13. A method comprising: Receive read command; In response to the read command, the read command is executed in either a first mode or a second mode. Executing the read command in the first mode includes: A first sensing operation is performed on a plurality of non-volatile memory cells to distinguish between a first data state and a second data state of the non-volatile memory cells; Perform a second sensing operation on the memory cells to determine the reliability of the first sensing operation for memory cells that were determined to be in the second data state by the first sensing operation, but not for memory cells that were determined to be in the first data state by the first sensing operation; and Using the result of the first sensing operation and the reliability of the first sensing operation, error correction code operations are performed on memory cells determined to be in the second data state, but not on memory cells determined to be in the first data state, to determine the data content stored in the plurality of non-volatile memory cells. Executing the read command in the second mode includes: Perform a third sensing operation to distinguish between the first data state and the second data state based solely on the second hard bit read value; and Parameter values ​​for performing the first sensing operation and for performing the second sensing operation are stored as offsets relative to parameter values ​​configured to perform the third sensing operation for distinguishing between the first data state and the second data state based solely on the second hard bit read value.

14. The method of claim 13, further comprising: Before performing the first sensing operation, the non-volatile memory cells are biased at a first voltage level, and the corresponding sensing node is pre-charged to the first level for each non-volatile memory cell, wherein performing the first sensing operation for each non-volatile memory cell includes: During the first sensing interval, the corresponding sensing node, pre-charged to the first voltage level, is discharged through the memory cell biased at the first voltage level; and The distinction between the first data state and the second data state is made based on the amount of discharge by the sensing node during the first sensing interval. The second sensing operation is performed for each of the non-volatile memory cells determined to be in the second data state, including: During the first additional sensing interval, the corresponding sensing node, pre-charged to the first voltage level, is discharged through the memory cell biased at the first voltage level; and The reliability of the first sensing is determined based on the amount of discharge of the sensing node during the combined first sensing interval and first additional sensing interval.

15. The method of claim 14, further comprising: A fourth sensing operation is performed on the plurality of non-volatile memory cells to distinguish between the third data state and the fourth data state of the non-volatile memory cells. as well as After performing the fourth sensing operation, a fifth sensing operation is performed on the memory cells to determine the reliability of the fourth sensing operation for memory cells that were determined to be in the fourth data state by the fourth sensing operation, but not for memory cells that were determined to be in the third data state by the fourth sensing operation. The results of the fourth sensing operation and the reliability of the fourth sensing operation are also used to perform error correction code operations on memory cells determined to be in the fourth data state, but not on memory cells determined to be in the third data state, to determine the data content stored in the plurality of non-volatile memory cells.

16. The method of claim 15, further comprising: Before performing the fourth sensing operation, the non-volatile memory cells are biased at a second voltage level, and the corresponding sensing node is pre-charged to the second level for each non-volatile memory cell. Performing the fourth sensing operation for each non-volatile memory cell includes: During the second sensing interval, the corresponding sensing node, pre-charged to the second voltage level, is discharged through the memory cell biased at the second voltage level; and The distinction between the third data state and the fourth data state is based on the amount of discharge of the sensing node during the second sensing interval, and The fifth sensing operation is performed for each of the non-volatile memory cells determined to be in the fourth data state, including: During the second additional sensing interval, the corresponding sensing node, pre-charged to the second voltage level, is discharged through the memory cell biased at the second voltage level; and The reliability of the third sensing is determined based on the amount of discharge of the sensing node during the combined second sensing interval and second additional sensing interval.

17. The method of claim 16, wherein the second voltage level is lower than the first voltage level, and the method further comprises distinguishing the first data state from the second data state before distinguishing the third data state from the fourth data state.

18. A non-volatile memory device, comprising: Multiple non-volatile memory cells, each configured to hold multiple data bits; A sensing amplifier, the sensing amplifier including a sensing node configured to be connected to a first selected memory cell; as well as One or more control circuits, connected to the plurality of non-volatile memory cells and the sensing amplifier, are configured to: Receive read command; In response to the read command, the read command is executed in either a first mode or a second mode. To execute the read command in the first mode, the one or more control circuits are configured to: The selected memory cell is biased at the read voltage level; The sensing nodes are pre-charged; During the first sensing interval, the precharged sensing node is discharged through the biased selected memory cell; A first hard bit value for the selected memory cell is determined based on the amount of discharge of the sensing node during the first sensing interval. The first hard bit value indicates whether the memory cell is reliably in a first data state or unreliably in a second data state. After discharging the sensing node within the first sensing interval, the precharged sensing node continues to be discharged through the biased selected memory cell within an additional sensing interval. as well as The soft bit value of the first selected memory cell is determined based on the amount of discharge of the sensing node during the combined first sensing interval and additional sensing interval. In order to execute the read command in the second mode, the one or more control circuits are configured to: Perform a read operation to distinguish between the first data state and the second data state based solely on the second hard bit read value; as well as Parameter values ​​for determining the first hard bit value and the soft bit value are stored as offsets relative to parameter values ​​configured to perform the read operation for distinguishing between the first data state and the second data state based solely on the second hard bit read value.

19. The non-volatile memory device of claim 18, wherein, in order to execute the read command in the first mode, the one or more control circuits are further configured to: The first hard bit value and the soft bit value are provided to the error correction code engine, which is configured to determine the data content of the selected memory cell from the first hard bit value and the soft bit value.

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