Method for forming a gate stack, semiconductor device and method of forming the same

Abstract

Disclosed herein are gate fabrication techniques for providing gate stacks and / or gate structures (e.g., high-k / metal gates) with improved profiles (e.g., minimal to no warpage, bow, arch, and necking and / or substantially vertical sidewalls), which can be implemented in various device types. For example, the gate fabrication techniques disclosed herein provide gate stacks with stress-treated glue layers having a residual stress of less than about 1.0 gigapascal (GPa) (e.g., about -2.5 GPa to about 0.8 GPa). In some embodiments, the stress-treated glue layers are provided by depositing a glue layer over a work function layer and performing a stress reduction treatment (such as an ion implantation process and / or an anneal process in a gas environment) on the glue layer. In some embodiments, the stress-treated glue layers are provided by forming at least one glue sublayer / metal layer pair over a work function layer, performing a poisoning process, and forming a glue sublayer over the pair. Embodiments of the present application also relate to methods for forming gate stacks, semiconductor devices, and methods of forming the same.

Description

Technical Field

[0001] Embodiments of this application relate to methods for forming gate stacks, semiconductor devices, and methods for forming the same. Background Technology

[0002] The integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have yielded multiple generations of ICs, each featuring smaller and more complex circuitry than the previous generation. Throughout IC development, functional density (i.e., the number of interconnect devices per chip area) has generally increased, while geometry (i.e., the smallest component (or line) that can be created using manufacturing processes) has decreased. This scaling down of processes typically provides benefits through increased production efficiency and reduced associated costs.

[0003] Such scaling down also increases the complexity of handling and manufacturing ICs, and similar developments are needed in IC handling and manufacturing to achieve these advancements. For example, gate replacement processes have been implemented to improve device performance, typically involving replacing polysilicon gate electrodes with metal gate electrodes. During the gate replacement process, the work function of the metal gate electrode is adjusted to provide devices with different threshold (operating) voltages. While existing gate fabrication techniques and / or gate replacement processes are generally sufficient for their intended purposes, they are not entirely satisfactory in all aspects as IC technology and / or IC component sizes shrink. Summary of the Invention

[0004] Some embodiments of this application provide a method for forming a gate stack, the method comprising: depositing a gate dielectric layer on a channel region; depositing a work function layer on the gate dielectric layer; forming a stress-treated adhesive layer on the work function layer; and depositing a metal filler layer on the stress-treated adhesive layer.

[0005] Other embodiments of this application provide a method for forming a semiconductor device, comprising: forming a gate opening to expose a channel region; forming a gate dielectric layer in the gate opening; forming a functional layer in the gate opening above the gate dielectric layer; forming a metal adhesive layer in the gate opening above the functional layer; performing a stress reduction treatment on the metal adhesive layer; and after the stress reduction treatment, forming a metal filler layer in the gate opening above the metal adhesive layer, wherein the gate dielectric layer, the functional layer, the metal adhesive layer, and the metal filler layer form a gate stack that fills the gate opening with a gate structure.

[0006] Some embodiments of this application provide a semiconductor device including: a channel region disposed between an epitaxial source and drain; and a gate stack disposed above the channel region, wherein the gate stack includes: a gate dielectric layer, a work function layer disposed above the gate dielectric layer, a metal adhesive layer disposed above the work function layer, wherein the metal adhesive layer has a residual stress of about -2.5 gigapascals (GPa) to about 0.8 gigapascals, and a metal filler layer disposed above the metal adhesive layer. Attached Figure Description

[0007] The invention is best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industry practice, the various components are not drawn to scale and are for illustrative purposes only. In practice, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 This is a partial or complete perspective view of an exemplary multi-gate device according to various aspects of the present invention.

[0009] Figure 2 This is a flowchart of a method for manufacturing a gate stack having a stress-treated adhesive layer according to various aspects of the present invention.

[0010] Figures 3A to 3I This is a partial or complete cross-sectional view of a device at various stages of the manufacturing process of the gate stacks of a device when the adhesive layer of the gate stacks of the device is being stressed.

[0011] Figure 4A and Figure 4B This is a partial or complete cross-sectional view of a device at various stages of the manufacturing process of each gate stack when the adhesive layer of the gate stack of the device is not under stress processing, according to various aspects of the present invention.

[0012] Figure 6A and Figure 6B This is a partial or complete cross-sectional view of a device at various stages of the manufacturing process of each gate stack when the adhesive layer of the gate stack of the device is not under stress processing, according to various aspects of the present invention.

[0013] Figure 5 It is according to various aspects of the present invention Figure 4B A partial or complete top view of the device, and Figure 7 It is according to various aspects of the present invention Figure 6B A top view of part or all of the device.

[0014] Figures 8A to 8GThis is a partial or complete cross-sectional view of another device at a stage of manufacturing of each gate stack when the adhesive layer of the gate stack of the stress-treated device is being applied.

[0015] Figure 9A Experimental data are provided for wafers on which devices including gate stacks with adhesive layers are fabricated, according to various aspects of the present invention.

[0016] Figure 9B Experimental data are provided for wafers on which devices including gate stacks with adhesive layers are fabricated, according to various aspects of the present invention.

[0017] Figure 10 It is a use of various aspects of the present invention Figures 3A to 3I or Figures 8A to 8G A partial or complete cross-sectional view of another device of a gate stack manufactured during the gate stack manufacturing stage. Detailed Implementation

[0018] The present invention generally relates to gate stacks of electronic devices, and more specifically, to gate stacks (e.g., high-k / metal gates) having improved profiles (e.g., minimal to no bowing and / or necking) and methods of manufacturing such gate stacks.

[0019] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the invention. These are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, spatially relative terms such as “lower,” “upper,” “horizontal,” “vertical,” “above,” “under,” “below,” “upward,” “downward,” “top,” “bottom,” and their derivatives (e.g., “horizontally,” “downward,” “upward,” etc.) are used to facilitate understanding of the relationship between one component and another in the invention. Spatially relative terms are intended to cover different orientations of the device including the components. Reference numerals and / or characters may be repeated in various instances of the invention. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0020] Furthermore, when using terms such as "about," "approximately," etc., to describe numerical values ​​or ranges, as understood by those skilled in the art, the term is intended to encompass values ​​within a reasonable range that takes into account inherent variations during manufacturing. For example, based on known manufacturing tolerances associated with manufacturing a part having characteristics related to a numerical value, a numerical value or range encompasses a reasonable range including the described value, such as within + / - 10% of the described value. For example, a material layer with a thickness of "about 5 nm" could encompass a size range from 4.25 nm to 5.75 nm, where the manufacturing tolerance associated with the deposited material layer is + / - 10%, as known to those skilled in the art. Additionally, given the inherent variations in any manufacturing process, when device components are described as having "fundamental" properties and / or characteristics, such terms are intended to capture properties and / or characteristics within the tolerances of the manufacturing process. For example, a component that is "substantially vertical" or "substantially horizontal" is intended to capture a component that is approximately vertical and horizontal within a given tolerance of the manufacturing process used to manufacture such a component—but not a component that is mathematically or perfectly vertical and horizontal.

[0021] For advanced IC technology nodes, non-planar transistors, such as FinFETs and gate-all-around (GAA) transistors (collectively known as multi-gate devices), have become popular and promising candidates for high-performance and low-leakage applications. Figure 1 This is a partial perspective view of part or all of an exemplary multi-gate device 10 according to various aspects of the present invention. The multi-gate device 10 is a FinFET including a fin 15 extending from a substrate 20. The fin 15 has a length in the y-direction and a width (W) in the x-direction. fin ) and the height along the z-direction. In Figure 1 In the FinFET, fin 15 has non-recessed portions disposed between recessed portions, and the FinFET further includes a gate stack 25 that surrounds and engages the non-recessed portions of fin 15 (e.g., the gate stack 25 is disposed on the top and opposite sidewalls of the non-recessed portions of fin 15) and an epitaxial source / drain 30 disposed above the recessed portions of fin 15 (e.g., the epitaxial source / drain 30 is disposed on the top of the recessed portions of fin 15). The FinFET has a channel region (C) disposed between source / drain regions (S / D), wherein the channel region is provided by the non-recessed portions of fin 15, and the source / drain region is provided by the epitaxial source / drain 30 and the recessed portions below fin 15. During operation of the FinFET, current can flow between the channel region (e.g., the non-recessed portions of fin 15) and the source / drain region (e.g., the epitaxial source / drain 30). The gate stack 25 has a gate length (LG) along the y-direction, and in the depicted embodiment, the gate stack 25 includes a gate dielectric 25A and a gate electrode 25B. Gate spacers ( Figure 1(Not shown) is disposed along the sidewalls of the gate stack 25, and the gate spacer also surrounds the non-recessed portion of the fin 15. A substrate isolation member 40, such as a shallow trench isolation (STI) structure, electrically isolates the FinFET from other devices and / or regions of the multi-gate device 10. The substrate isolation member 40 is disposed above the substrate 20, along the sidewalls of the recessed portion of the fin 15 and along the sidewalls of the lower portion of the non-recessed portion of the fin 15. The gate stack 25 extends above the top of the substrate isolation member 40. In some embodiments, the substrate isolation member 40 surrounds the lower portion of the fin 15. In some embodiments, the fin 15 is not recessed in the source / drain region of the FinFET, and an epitaxial source / drain 30 surrounds the fin 15 (e.g., the epitaxial source / drain 30 is disposed on the top and opposite sidewalls of the fin 15). For clarity, simplified diagrams have been provided. Figure 1 To better understand the inventive concept of the present invention. Additional components may be added to the multi-gate device 10, and some of the components described below may be replaced, modified, or eliminated in other embodiments of the multi-gate device 10.

[0022] The gate stack 25 can be formed via a gate replacement process, which typically involves removing the dummy gate (e.g., a polysilicon gate) of the gate structure to form a gate opening (having sidewalls, for example, formed by gate spacers of the gate structure) and forming the gate stack 25 within the gate opening. As IC component sizes continue to shrink with advanced IC technology nodes, the dimensions of FinFETs (such as fin width W) are also decreasing. fin and gate length LG The corresponding reduction in size results in a significantly smaller gate opening during the gate replacement process. A gate replacement process with a smaller gate opening is more likely to form voids and / or seams in the gate stack 25. In particular, the gate replacement process has been observed to be particularly sensitive to residual stress in the individual layers of the gate stack 25 due to the reduced FinFET size and therefore the smaller gate opening size. For example, residual stress in the adhesive layer of the gate stack 25 has been observed to deform and / or warp the gate stack 25 during the gate replacement process and prevent complete filling of the gate opening, resulting in the formation of undesirable voids and / or seams in the gate stack 25. Such voids and / or seams provide pathways for chemicals and / or other impurities to reach and damage the channel region C during subsequent processing, thereby significantly reducing the performance and / or reliability of the FinFET.

[0023] This invention addresses this challenge by providing a gate stack with a stress-treated adhesive layer formed between the work function layer and the metal filler layer of the gate stack. The stress reduction process is configured to modify the properties and / or characteristics of the adhesive layer, such that the adhesive layer has compressive residual stress or negligible tensile residual stress (i.e., residual stress less than about 0.8 GPa). Various stress reduction processes disclosed herein have been observed to reduce residual stress and / or other characteristics (e.g., d-spacers) in the adhesive layer, reduce warpage of gate structures including the adhesive layer (e.g., gate stacks and / or gate spacers), and significantly reduce (and even eliminate) void and / or seam formation in gate stacks including the adhesive layer. Various characteristics of the gate structures and / or their adhesive layers resulting from implementing the proposed stress reduction processes and corresponding gate replacement processes are disclosed herein. Details of the proposed stress reduction techniques and / or gate fabrication techniques are described on the following pages.

[0024] Figure 2This is a flowchart of a method 50 for manufacturing a device with an improved profile (e.g., minimal warping, bending, bowing, and necking and / or substantially vertical sidewalls) according to various aspects of the present invention. In block 52, method 50 includes forming a gate dielectric layer over a channel region. In block 54, method 50 includes a square work function layer on the gate dielectric layer. In block 56, method 50 includes forming a stress-treated adhesive layer over the work function layer. In some embodiments, the stress-treated adhesive layer is formed by depositing an adhesive layer over the work function layer and performing a stress-reducing treatment (e.g., ion implantation and / or thermal processing) on ​​the adhesive layer. In some embodiments, the stress-treated adhesive layer is formed by depositing a gluon layer, depositing a metal layer between the gluon layers, and performing a hydrogen poisoning process (or other suitable poisoning process) on the gluon layer and / or the metal layer. In block 58, method 50 includes forming a metal fill layer over the stress-treated adhesive layer. In some embodiments, method 50 is implemented in a post-gate process (i.e., a gate replacement process). In such embodiments, a dummy gate (e.g., a polysilicon gate) is removed to form a gate opening defined between gate spacers of a gate structure, and a gate dielectric layer, a work function layer, a stress-treated adhesive layer, and a metal filler layer are formed in and fill the gate opening. A planarization process can be implemented to remove excess gate material from above the dielectric layer (e.g., an interlayer dielectric (ILD) layer), wherein the remaining portion of the gate material fills the gate opening and forms a gate stack of a gate structure comprising the gate dielectric layer, work function layer, stress-treated adhesive layer, and metal filler layer. In some embodiments, method 50 is implemented in a gate-first process. In such embodiments, the gate dielectric layer, work function layer, stress-treated adhesive layer, and metal filler layer are formed over a substrate including a channel region and then subsequently patterned to form a gate stack of a gate structure comprising the gate dielectric layer, work function layer, stress-treated adhesive layer, and metal filler layer. After the individual gate layers are patterned to form the gate stack, a dielectric layer (e.g., an ILD layer) can be formed. In some embodiments, method 50 is implemented in a hybrid gate-first-gate-later process. Additional steps may be provided before, during, and after method 50, and for additional embodiments of method 50, some of the described steps may be moved, replaced, or eliminated.

[0025] Figures 3A to 3I It is according to various aspects of the invention at various manufacturing stages (such as with) Figure 2 Partial or complete partial cross-sectional view of device 100 (related to method 50 in the text). Figures 3A to 3I The cross-sectional view is obtained by following along Figure 1 The device is obtained by "cutting" it in the y-direction as shown, and therefore, Figures 3A to 3IThe cross-sectional view in the diagram can be referred to as a y-cut view. It should be noted that the y-cut view is taken through the portion of the device including the channel region disposed between the source / drain regions and the gate structure disposed above the top of the channel region, rather than the portion of the device whose gate structure encloses the channel region (i.e., the y-cut view passes through the YZ plane, not the XZ plane of a multi-gate device). Device 100 may be included in a microprocessor, memory, and / or IC. Device 100 may be part of an IC chip, a system-on-a-chip (SoC), or a portion thereof, which includes various passive and active microelectronic devices such as transistors, resistors, capacitors, inductors, diodes, p-type FETs (PFETs), n-type FETs (NFETs), metal-oxide-semiconductor FETs (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS transistors (LDMOS), high-voltage transistors, high-frequency transistors, other suitable components and / or devices, or combinations thereof. For clarity, simplified diagrams have been provided. Figures 3A to 3I To better understand the inventive concept of the present invention. Additional components may be added to device 100, and some of the components described below may be replaced, modified, or eliminated in other embodiments of device 100.

[0026] Transfer to Figure 3A Device 100 includes a substrate (wafer) 105. Substrate 105 includes: elemental semiconductors, such as silicon and / or germanium; compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or combinations thereof; alloy semiconductors, such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or combinations thereof; or combinations thereof. In the depicted embodiments, substrate 105 is a silicon substrate. In some embodiments, substrate 105 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. Substrate 105 may include various doped regions, such as p-type doped regions (e.g., p-wells), n-type doped regions (e.g., n-wells), or combinations thereof. n-type doped regions include n-type dopants, such as phosphorus, arsenic, other n-type dopants, or combinations thereof. p-type doped regions include p-type dopants, such as boron, indium, other p-type dopants, or combinations thereof. In some embodiments, the doped region comprises a combination of p-type and n-type dopants. The doped region may be formed directly on and / or in the substrate 105, for example, by providing a p-well structure, an n-well structure, a double-well structure, a bump structure, other suitable structures, or combinations thereof.

[0027] Device 100 includes a channel region 110 disposed between epitaxial source / drain 120 and a gate structure 125 disposed above the channel region 110. The channel region 110 (also referred to as a channel layer) extends longitudinally along the y-direction and has a length along the y-direction, a width along the x-direction, and a height along the z-direction. The channel region 110 includes: elemental semiconductors such as silicon and / or germanium; compound semiconductors such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or combinations thereof; alloy semiconductors such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or combinations thereof; or combinations thereof. In the depicted embodiments, the channel region 110 includes silicon, germanium, silicon-germanium, other suitable semiconductor materials, or combinations thereof. When device 100 is a FinFET, as in the depicted embodiments, the channel region 110 is a portion of a semiconductor fin extending from the substrate 105 and may be referred to as a fin or fin structure. In some embodiments, the channel region 110 is a portion of the substrate 105, such as a portion of a material layer of the substrate 105. For example, if the substrate 105 comprises silicon, the channel region 110 comprises silicon (i.e., the channel region 110 is a silicon fin). In some embodiments, the channel region 110 is a semiconductor layer extending from the substrate 105 (e.g., the channel region 110 is a silicon-germanium fin). When the device 100 is a GAA transistor, the channel region 110 may be a semiconductor layer stack (e.g., silicon nanowires, which will be at least partially surrounded by a gate) subsequently processed to form one or more semiconductor layers floating above the substrate 105 (e.g., silicon-germanium layers and silicon layers stacked in an alternating, staggered configuration along the z-direction).

[0028] The epitaxial source / drain 120 comprises a semiconductor material and may be doped with n-type and / or p-type dopants. In embodiments where device 100 is an n-type transistor, the epitaxial source / drain 120 may comprise silicon doped with carbon, phosphorus, arsenic, other n-type dopants, or combinations thereof (e.g., Si:C epitaxial source / drain, Si:P epitaxial source / drain, or Si:C:P epitaxial source / drain). In embodiments where device 100 is a p-type transistor, the epitaxial source / drain 120 may comprise silicon germanium or germanium doped with boron, other p-type dopants, or combinations thereof (e.g., Si:Ge:B epitaxial source / drain). In some embodiments, the epitaxial source / drain 120 comprises more than one epitaxial semiconductor layer, wherein the epitaxial semiconductor layers may comprise the same or different materials and / or the same or different dopant concentrations. In some embodiments, the epitaxial source / drain 120 comprises materials and / or dopants that achieve desired tensile and / or compressive stresses in the channel region 110. In some embodiments, doped regions, such as heavily doped source / drain (HDD) regions, lightly doped source / drain (LDD) regions, other doped regions, or combinations thereof, are disposed in the epitaxial source / drain 120. In such embodiments, the doped regions (e.g., LDD regions) may extend into the channel region 110. As used herein, source / drain regions and / or epitaxial source / drain can refer to the source of device 100, the drain of device 100, or the sources and / or drains of multiple devices (including device 100).

[0029] Gate structure 125 includes a dummy gate 130 disposed above a channel region (e.g., channel region 110) of device 100 and between source / drain regions (e.g., epitaxial source / drain 120) of device 100. The dummy gate 130 extends longitudinally in a direction different from (e.g., orthogonal to) the longitudinal direction of channel region 110. For example, the dummy gate 130 extends longitudinally along the x-direction, having a length along the x-direction, a width along the y-direction, and a height along the z-direction. In the YZ plane ( Figure 3A In the channel region 110, a dummy gate 130 is disposed on top of the channel region 110. The width of the dummy gate 130 along the y-direction defines the critical dimension (CD) of the gate structure 125, which is the desired gate length (L) of the gate stack of the gate structure 125. GIn some embodiments, the critical dimension CD is about 14 nm to about 20 nm. In the XZ plane, when the channel region 110 is formed in the portion of the semiconductor fin extending from the substrate 105, as depicted, a dummy gate 130 is disposed over the top and sidewalls of the channel region 110 such that the dummy gate 130 encloses the channel region 110. In some embodiments, the dummy gate 130 includes a dummy gate electrode and a hard mask located above the dummy gate electrode. The dummy gate electrode includes a suitable dummy gate material, and the hard mask includes a suitable hard mask material. For example, the dummy gate electrode includes a polysilicon layer, and the hard mask includes a silicon nitride layer. In such embodiments, the dummy gate 130 may be referred to as a polysilicon gate. The dummy gate 130 may include other layers, such as a capping layer, an interface layer, a diffusion layer, a shielding layer, or a combination thereof. In some embodiments, the dummy gate 130 includes a dielectric layer between the dummy gate electrode and the channel region 110, such as a dummy gate dielectric layer and / or an interface layer (including, for example, silicon oxide).

[0030] Gate structure 125 also includes gate spacers 135 disposed adjacent to (e.g., along its sidewalls) the dummy gate 130. Gate spacers 135 comprise a dielectric material, which may include silicon, oxygen, carbon, nitrogen, other suitable materials, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbonoxynitride, silicon carbonoxynitride, silicon carbonitride, or combinations thereof). In some embodiments, gate spacers 135 comprise a multilayer structure, such as a first dielectric layer (e.g., a silicon oxide layer) and a second dielectric layer (e.g., a silicon nitride layer). In some embodiments, gate spacers 135 include more than one set of spacers, such as sealing spacers, offset spacers, sacrificial spacers, dummy spacers, main spacers, or combinations thereof. In such embodiments, different spacers may comprise different materials with different etch rates.

[0031] A dielectric layer 140 is disposed over the substrate 105, the channel region 110, the epitaxial source / drain 120, and the gate structure 125. The dielectric layer 140 may be a portion of various devices (e.g., transistors, resistors, capacitors, and / or inductors) and / or components (e.g., gate stacks and / or source / drains) of the electrically coupled device 100 of a multilayer interconnect (MLI) component, thereby enabling the various devices and / or components to operate as needed. The dielectric layer 140 may have a multilayer structure, such as an interlayer dielectric (ILD) layer located above a contact etch stop layer (CESL). The ILD layer includes a dielectric material, including, for example, silicon oxide, carbon-doped silicon oxide, silicon nitride, silicon oxynitride, oxides formed from tetraethyl orthosilicate (TEOS), borosilicate glass (BSG), phosphosilicate glass (PSG), borosilicate phosphosilicate glass (BPSG), fluorosilicate glass (FSG), and black silicate glass. (Applied Materials, Santa Clara, California), degel, aerogel, amorphous fluorinated carbon, parylene, benzocyclobutene (BCB)-based dielectric materials, SiLK (Dow Chemical Company, Midland, Michigan), polyimide, other suitable dielectric materials, or combinations thereof. In some embodiments, the ILD layer comprises a dielectric material having a dielectric constant less than that of silicon dioxide (e.g., k < 3.9). In some embodiments, the ILD layer comprises a dielectric material having a dielectric constant less than about 2.5 (i.e., very low k (ELK) dielectric material), such as porous silica, silicon carbide (SiC), and / or carbon-doped oxides (e.g., SiCOH-based materials (having, for example, Si-CH3 bonds)), each tuned / configured to exhibit a dielectric constant less than about 2.5. CESL comprises a dielectric material different from the dielectric material of the ILD layer. For example, in cases where the ILD layer comprises a low-k dielectric material (e.g., porous silicon oxide), the CESL may comprise silicon and nitrogen, such as silicon nitride, silicon carbonitride, or silicon carbonitride.

[0032] Transfer to Figures 3B to 3I The process continues with a gate replacement process, for example, by removing the dummy gate 130 from the gate structure 125 to form a gate opening 145 that exposes the channel region 110. Figure 3B ) and filling the gate opening 145 with the gate stack 150 ( Figures 3C to 3I (That is, replacing the dummy gate 130 with the gate stack 150). In Figure 3BIn this embodiment, the gate opening 145 has sidewalls formed by gate spacers 135 and a bottom formed by channel region 110. The width of the gate opening 145 along the longitudinal direction of the channel (e.g., the y-direction) is approximately equal to the critical dimension CD. In the depicted embodiment, the gate spacers 135 have substantially vertical sidewalls extending along the z-direction, providing a gate opening 145 with a substantially uniform width from top to bottom. In other words, the critical dimension CD is substantially the same from the top of the gate opening 145 near the top surface of the dielectric layer 140 to the bottom of the gate opening 145 near the top surface of the channel region 110. In some embodiments, an etching process selectively removes the dummy gate 130 relative to the gate spacers 135 and / or the dielectric layer 140. For example, the etching process substantially removes the dummy gate 130 but does not remove or substantially does not remove the gate spacers 135 and / or the dielectric layer 140. In some embodiments, an etchant is selected for the etching process that etches the polysilicon (i.e., the dummy gate 130) at a higher rate than the dielectric material (i.e., the gate spacer 135 and / or the dielectric layer 140) (i.e., the etchant has high etch selectivity relative to the polysilicon). The etching process is dry etching, wet etching, other suitable etching processes, or combinations thereof. The etching process can also be tailored to remove the dummy gate 130 without (or at least) removing the channel region 110. In some embodiments, the etching process uses a patterned mask layer (i.e., an etch mask) that covers the dielectric layer 140 and / or the gate spacer 135 but exposes the dummy gate 130.

[0033] exist Figure 3C In this embodiment, a gate dielectric layer 152 is formed over a substrate 105. The gate dielectric layer 152 has a substantially uniform thickness and partially fills the gate opening 145. The gate dielectric layer 152 is disposed on a gate spacer 135 (which forms a sidewall of the gate opening 145), a channel region 110 (which forms the bottom of the gate opening 145), and a dielectric layer 140. In some embodiments, the gate dielectric layer 152 has approximately to approximately The thickness of the gate dielectric layer 152 is specified. The gate dielectric layer 152 comprises a high-k dielectric material, such as HfO2, HfSiO, HfSiO4, HfSiON, HfLaO, HfTaO, HfTiO, HfZrO, and HfAlO. xZrO, ZrO2, ZrSiO2, AlO, AlSiO, Al2O3, TiO, TiO2, LaO, LaSiO, LaO3, La2O3, Ta2O3, Ta2O5, Y2O3, SrTiO3, BaZrO, BaTiO3 (BTO), (Ba,Sr)TiO3 (BST), Si3N4, HfO2-Al2O3, other suitable high-k dielectric materials, or combinations thereof. High-k dielectric materials generally refer to dielectric materials with a high dielectric constant, such as greater than that of silicon dioxide (k≈3.9). In some embodiments, the gate dielectric layer 152 includes another suitable dielectric material, such as SiO2 or other suitable dielectric materials. The gate dielectric layer 152 may have a multilayer structure. The gate dielectric layer 152 is formed by atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), high-density plasma CVD (HDPCVD), metal-organic CVD (MOCVD), remote plasma CVD (RPCVD), plasma-enhanced CVD (PECVD), low-pressure CVD (LPCVD), atomic layer CVD (ALCVD), atmospheric pressure CVD (APCVD), thermal oxidation, chemical oxidation, other suitable methods, or combinations thereof.

[0034] An interface layer 152A may be formed between the channel region 110 and the gate dielectric layer 152. The interface layer 152A comprises a dielectric material, such as SiO2 or SiGeO. x The interface layer 152A is formed by thermal oxidation, chemical oxidation, ALD, CVD, other suitable processes (such as those described herein), or combinations thereof. The thickness of the interface layer 152A is less than the thickness of the gate dielectric layer 152. In some embodiments, the thickness of the interface layer 152A is approximately [missing information]. to approximately

[0035] exist Figure 3D In this embodiment, a metal gate layer 154 is formed above the substrate 105. The metal gate layer 154 has a substantially uniform thickness and partially fills the gate opening 145. The metal gate layer 154 is disposed on the gate dielectric layer 152. In some embodiments, the thickness of the metal gate layer 154 is approximately to approximately The metal gate layer 154 is formed by ALD, PVD, CVD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, plating, other suitable methods, or combinations thereof. In the depicted embodiments, the metal gate layer 154 has a multilayer structure, such as metal layers 154A, 154B, 154C, and 154D from bottom to top. Metal layer 154A physically contacts the gate dielectric layer 152, metal layer 154B physically contacts metal layer 154A, metal layer 154C physically contacts metal layer 154B, and metal layer 154D physically contacts metal layer 154C. The thickness of metal layer 154B may be greater than the thickness of each of metal layer 154A, metal layer 154B, and metal layer 154D. In some embodiments, the thickness of each of metal layer 154A, metal layer 154C, and metal layer 154D is approximately [missing information]. to approximately In some embodiments, the thickness of the metal layer 154B is approximately to approximately In some embodiments, the thickness of the metal layer 154D is approximately to approximately (For example, ).

[0036] In some embodiments, metal layer 154B is a power-function layer, and metal layers 154A, 154C, and 154D are capping layers, barrier layers, shielding layers, or combinations thereof. For example, each of metal layers 154A, 154C, and 154D includes a material that prevents or eliminates the diffusion and / or reaction of components between adjacent layers and / or promotes adhesion between adjacent layers, such as between gate dielectric layer 152 and metal layer 154B, or between metal layer 154B and a subsequently formed metal fill layer. In some embodiments, each of metal layers 154A, 154C, 154D, or combinations thereof includes a metal and nitrogen, such as titanium nitride, tantalum nitride, tungsten nitride (e.g., W₂N), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), other suitable metal nitrides, or combinations thereof. In some embodiments, metal layers 154A, 154C, 154D, or combinations thereof comprise amorphous materials, such as amorphous silicon, amorphous carbon, amorphous germanium, other amorphous materials, or combinations thereof. In the depicted embodiments, metal layers 154A and 154C are metal nitride layers (e.g., titanium nitride (TiN) layers, or tantalum nitride (TaN) layers), and metal layer 154D is an amorphous material layer (e.g., an amorphous silicon layer). The invention contemplates any suitable material for metal layers 154A, 154C, and 154D.

[0037] Metal layer 154B comprises a metallic material having a suitable work function. In the depicted embodiment, metal layer 154B comprises an n-type work function metal (nWFM), which generally refers to a metallic material or a metal-containing material having a work function value that is closer to the conduction band energy than the valence band energy of the material of channel region 110. In some embodiments, metal layer 154B is an nWFM layer comprising an aluminum-based material, such as aluminum titanium (TiAl), aluminum titanium carbide (TiAlC), aluminum silicon titanium carbide (TiSiAlC), aluminum tantalum (TaAl), aluminum tantalum carbide (TaAlC), Al-doped Ti, Al-doped TiN, Al-doped Ta, Al-doped TaN, other suitable aluminum-based nWFMs, or combinations thereof. For example, metal layer 154B is a TiAlC layer. In another example, metal layer 154B is a TiSiAlC layer. In yet another example, metal layer 154B is a TaAlC layer. In some embodiments, metal layer 154B comprises a p-type work function metal (pWFM), which generally refers to a metallic material or a metal-containing material having a work function value that is closer to the valence band energy than the conduction band energy of the material of channel region 110. In some embodiments, metal layer 154B is a substantially aluminum-free pWFM layer, such as titanium-based nitrides (e.g., TiN and / or TiSiN), tantalum-based nitrides (e.g., TaN and / or TaSiN), titanium-based alloys (including, for example, titanium and gold, copper, chromium, cobalt, molybdenum, nickel, other suitable components, or combinations thereof), tantalum-based alloys (including, for example, tantalum and gold, copper, tungsten, platinum, tungsten, molybdenum, other suitable components, or combinations thereof), other aluminum-free pWFMs, or combinations thereof. In some embodiments, nWFM has a work function value of less than about 4.5 electron volts (eV), and pWFM has a work function value greater than or equal to about 4.5 eV. For example, nWFM has a work function of about 3.5 eV to about 4.4 eV, wherein such a work function is closer to the conduction band energy of the semiconductor channel region (e.g., 4.1 eV for Si or 3.8 eV for SiGe) than the valence band energy of the semiconductor channel region (e.g., 5.2 eV for Si or 4.8 eV for SiGe), while pWFM has a work function of about 4.5 eV to about 5.5 eV, wherein such a work function is closer to the valence band energy of the semiconductor channel region than the conduction band energy of the semiconductor channel region. The present invention contemplates metal layer 154B comprising any material exhibiting the desired work function. In some embodiments, metal layer 154A and / or metal layer 154C comprises a material exhibiting the desired work function. For example, metal layer 154A and / or metal layer 154C comprises pWFM. In some embodiments, the materials of metal layers 154A, 154B, 154C, and 154D are configured to provide a metal layer 154 having a desired work function, and the metal layer 154 may be referred to as a work function layer.

[0038] exist Figure 3EIn this embodiment, an adhesive layer 156 is formed over a substrate 105. The adhesive layer 156 has a substantially uniform thickness, such as thickness T, and partially fills the gate opening 145. The adhesive layer 156 is disposed on the metal gate layer 154 and, in the depicted embodiment, physically contacts the metal layer 154D. In some embodiments, the thickness T is approximately... to approximately The adhesive layer 156 includes a material that promotes adhesion between the metal gate layer 154 (e.g., metal layer 154D) and the metal fill layer 158 of the gate stack 150 (which is subsequently formed and described below). In some embodiments, the material of the adhesive layer 156 includes metals (e.g., W, Al, Ta, Ti, Ni, Cu, Co, other suitable metals or combinations thereof), metal oxides, metal nitrides, metal alloys, or combinations thereof. The adhesive layer 156 is formed by ALD, PVD, CVD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, plating, other suitable methods, or combinations thereof. In one example, the adhesive layer 156 is a titanium nitride layer (e.g., a TiN layer) formed by ALD or CVD. In another example, the adhesive layer 156 is a tantalum nitride layer (e.g., a TaN layer) formed by ALD or CVD. In yet another example, the adhesive layer 156 is a cobalt layer (e.g., a Co layer) formed by ALD or CVD. In yet another example, the adhesive layer 156 is a titanium silicon nitride layer (e.g., a TSN layer) formed by ALD or CVD. In some embodiments, the TSN layer may comprise alternating deposited TiN layers and silicon nitride layers (e.g., SiN layers), wherein the TiN and SiN layers are so thin that they are indistinguishable and are therefore referred to as TSN layers.

[0039] The adhesive layer 156 has residual tensile stresses that cause it to warp, bend, neck, and / or bow, as depicted, which correspondingly warp the metal gate layer 154, the gate dielectric layer 152, the gate spacer 135, the other layers of the gate structure 125, or combinations thereof. For example, the adhesive layer 156 (when deposited) has residual stresses of about 1.0 gigapascals (GPa) to about 3.0 GPa (i.e., large residual tensile stresses), which alters the profile and critical dimensions of the gate structure 125. Figure 3EIn the diagram, lines A and A' represent the substantially vertical sidewalls of the gate stack 150 (which intersects with the gate spacer 135) prior to the formation of the adhesive layer 156 and have a defined critical dimension CD between them. Residual tensile stress in the adhesive layer 156 causes necking in the top portion of the gate structure 125, which reduces its critical dimension, and causes bowing in the middle and / or bottom portions of the gate structure 125, which increases its critical dimension. For example, the sidewalls of the top portion of the gate structure 125 bend inward and narrow the gate opening 145 (i.e., the distance between the sidewalls of the gate stack 150 decreases, thereby reducing the width of the gate opening 145), and the sidewalls of the middle and / or bottom portions of the gate structure 125 bend outward and widen the gate opening 145 (i.e., the distance between the sidewalls of the gate stack 150 increases, thereby increasing the width of the gate opening 145). In such an embodiment, in response to the residual tensile stress of the adhesive layer 156, the sidewalls of the gate stack 150 are curved and have outwardly bent portions (i.e., those bent / bent away from the gate opening 145) and inwardly bent portions (i.e., those bent / bent toward the gate opening 145). In some embodiments, the gate structure 125 has a convex cross-sectional profile (i.e., portions with a middle section and ends, wherein the width of the middle section is greater than the width of the ends).

[0040] In such an embodiment, the gate stack 150 has a non-uniform critical dimension. For example, the gate stack 150 has a necking critical dimension CD smaller than the critical dimension CD. N And the arc-shaped critical size CD is greater than the critical size CD. B During deposition, it has been observed that the adhesive layer 156 causes a necking of the critical size CD in the gate stack 150 that is approximately 85% to approximately 90% smaller than the critical size CD. N And in the gate stack 150, an arc-shaped critical size CD is caused by approximately 30% to approximately 35% of the critical size CD. B In some embodiments, the necking critical size CD N Approximately smaller than the critical size CD to approximately In some embodiments, the critical bow-shaped dimension CD B Approximately the critical size CD to approximately The necking portion of the gate stack 150 has a necking angle θ relative to line A or line A' (i.e., the axis along the z-direction, which represents the substantially perpendicular sidewalls of the gate stack 150 and / or gate structure 125 prior to the deposition of the adhesive layer 156), and the arcuate portion of the gate stack 150 has an arcuate angle φ relative to line A or line A'. During deposition, it has been observed that the adhesive layer 156 causes a necking angle θ greater than about 5° and an arcuate angle φ greater than about 5°. In some embodiments, each layer of the gate structure 125 (e.g., gate dielectric 152, metal gate layer 154, adhesive layer 156, gate spacer 135, or combinations thereof) may have a necking portion (segment) with a corresponding necking angle and / or an arcuate portion (segment) with a corresponding arcuate angle. As IC device scale and size shrink, the warpage of the gate structure 125 and / or gate stack 150 caused by the stress adhesive layer 156, and the resulting critical dimensional changes, can significantly narrow the gate opening 145 and prevent the subsequently formed metal filler layer 158 from completely filling the gate opening 145. This can lead to the formation of seams and / or voids in the gate stack 150, which can significantly degrade device performance and / or device integrity. For example, voids or seams in the gate stack 150 can result in a device 100 with performance characteristics different from those specified in the design specifications. In some embodiments, voids or seams in the gate stack 150 can result in a device 100 with unacceptable performance characteristics, which may lead to the rejection of the device 100.

[0041] Figure 4A , Figure 4B and Figure 5 This illustrates the seams and / or gaps that may occur when a narrower width of the gate opening 145, caused by warping, bending, necking, and / or bowing of the gate structure 125, creates a metal filler layer 158 that blocks the gate opening 145. Figure 4A This is a partial or complete cross-sectional view of device 100 after the deposition of the metal filler layer 158. Figure 4B It is a partial or complete cross-sectional view of device 100 after the planarization process, and Figure 5 It is according to various aspects of the present invention and Figure 4B Top view of the corresponding device 100. Figure 4B along Figure 5 BB cutoff. Figure 4A In this process, the metal filler layer 158 fills the top of the gate opening 145 before reaching and / or filling the middle and / or bottom of the gate opening 145, and forms a void 160A in the gate structure 125 between the adhesive layer 156 and the metal filler layer 158. Figure 4B and Figure 5In this process, a planarization process removes excess gate material from above the top surface of dielectric layer 140 to form gate stack 150. The planarization process also reduces the thickness of dielectric layer 140 and the height of gate structure 125 along the z-direction. In such an embodiment, the planarization process can remove metal filler layer 158 and reach voids 160A, thereby forming a seam 160A' in the gate stack 150 that exposes adhesive layer 156. Seam 160A' is the unfilled portion of gate opening 145 and forms a gap or opening in the gate stack 150. Seam 160A' has a width W along the y-direction. A In some embodiments, the width W A For the agreement to approximately

[0042] Figure 6A , Figure 6B and Figure 7 This illustrates the seams and / or gaps that may occur when the narrow width of the gate opening 145, caused by warping, bending, necking, and / or bowing of the gate structure 125, results in the pinching of the metal fill layer 158 within the gate opening 145. Figure 6A This is a partial or complete cross-sectional view of device 100 after the deposition of the metal filler layer 158. Figure 6B It is a partial or complete cross-sectional view of device 100 after the planarization process, and Figure 7 It is according to various aspects of the present invention and Figure 6B Top view of the corresponding device 100. Figure 6B along Figure 7 BB cutoff. Figure 6A In this configuration, the metal fill layer 158 fills or closes (pinches off) the top of the gate opening 145 before completely filling it, and forms a void 160B in the gate structure 125. The void 160B is the unfilled portion of the gate opening 145 located within the metal fill layer 158. Figure 6B and Figure 7 In this process, a planarization process removes excess gate material from above the top surface of dielectric layer 140 to form gate stack 150. The planarization process also reduces the thickness of dielectric layer 140 and the height of gate structure 125 along the z-direction. In such an embodiment, the planarization process can remove metal filler layer 158 and reach voids 160B, thereby forming seams 160B' in gate stack 150. Seams 160B' are unfilled portions of gate openings 145 and form gaps or openings in gate stack 150. Seams 160B' have a width W along the y-direction. B In some embodiments, the width W B For the agreement to approximately In the depicted embodiment, the width W of the seam 160B' B (Between the sidewall portions of the metal filler layer 158) less than the width W of the joint 160A' A (between the sidewall portions of adhesive layer 156).

[0043] As device 100 undergoes further processing, it has been observed that seams 160A' and / or seams 160B' provide pathways for chemicals and / or impurities to damage gate stack 150 and / or channel region 110. For example, chemicals and / or impurities entering seams 160A' and / or 160B' during subsequent processing can alter the physical and / or electrical properties of the metal filler layer 158, adhesive layer 156, metal gate layer 154, gate dielectric layer 152, interface layer 152A, or combinations thereof. In another instance, during a subsequent etching process, etchant can enter seams 160A' and / or 160B' and undesirably remove portions of gate stack 150 and, in some embodiments, expose channel region 110. In another instance, chemicals and / or impurities entering seams 160A' and / or 160B' during subsequent processing can alter the physical and / or electrical properties of channel region 110, particularly when channel region 110 is exposed due to the unintentional removal of portions of gate stack 150. In some embodiments, damage to gate stack 150 and / or channel region 110 caused by chemicals and / or impurities entering seams 160A' and / or 160B' may render device 100 inoperable.

[0044] The present invention addresses these challenges and eliminates or significantly reduces voids and / or seams in the gate stack 150 by reducing stress in the adhesive layer 156 and correspondingly eliminating or reducing warping of the gate structure 125 that may cause such voids and / or seams. For example, return Figures 3A to 3I ,exist Figure 3F and Figure 3G In the middle, for adhesive layer 156 ( Figure 3F ) Perform stress reduction treatment 170 to provide stress-treated adhesive layer 156' ( Figure 3GThe stress reduction treatment 170 alters the properties and / or characteristics of the adhesive layer 156 to reduce its residual stress, thereby causing the stress-treated adhesive layer 156' to have a residual stress less than that of the adhesive layer 156. For example, the stress reduction treatment 170 converts residual tensile stress (e.g., greater than 0 GPa) into residual compressive stress (e.g., less than 0 Pa), where a residual stress of 0 GPa represents neutralized stress or a stress-free metal layer. In some embodiments, the adhesive layer 156 has a residual stress of about 1.0 GPa to about 3 GPa (i.e., residual tensile stress), and the stress-treated adhesive layer 156' has a residual stress of about -2.5 GPa to about 0.8 GPa (i.e., residual compressive stress, neutralized stress, or negligible residual tensile stress). The stress-treated adhesive layer 156' with a residual stress of about -2.5 GPa to about 0.8 GPa exhibits minimal to no warping, bending, necking, and / or bowing, which correspondingly eliminates or significantly reduces warping of the gate structure 125 and the formation of voids and / or seams in the gate stack 150. Conversely, adhesive layers with residual stress greater than about 0.8 GPa or less than about -2.5 GPa can still exhibit undesirable warping, bending, necking, and / or bowing, which can cause warping of the gate structure 125, potentially leading to the formation of voids and / or seams in the gate stack 150.

[0045] The stress reduction process 170 reduces bowing, necking, and / or other profile variations in the gate structure 125 and / or gate stack 150. For example, the gate stack 150 and gate spacer 135 have substantially vertical sidewalls after the stress reduction process 170, and minimal (to no) bowing and / or necking is observed in the gate structure 125 and / or gate stack 150 after the stress reduction process 170. In embodiments where necking and / or bowing are observed in the gate structure 125 and / or gate stack 150 after the stress reduction process 170, the critical necking dimension CD is... N It is about 0% to about 15% smaller than the critical size CD, and the arc-shaped critical size CD B The critical size CD is approximately 0% to approximately 5%. In other words, the critical size CD and the necking critical size CD in the gate stack 150. N and / or the critical bow dimension CD B The difference between them is significantly smaller after the stress reduction treatment 170. In some embodiments, the necking critical dimension CD N Any observable difference between the critical size CD and the critical size CD is less than approximately In some embodiments, the critical bow-shaped dimension CD B Any observable difference between the critical size CD and the critical size CD is less than approximately Furthermore, any observed necking angle θ is less than about 5° and any observed bowing angle φ is less than about 5°. In some embodiments, the observed necking angle θ is about 2° to about 4° (e.g., 3.5°). In some embodiments, the observed bowing angle is about 2° to about 4° (e.g., 3.5°). Therefore, the gate stack 150 with stress-treated adhesive layer 156' has a substantially uniform critical dimension CD from top to bottom (i.e., a substantially uniform critical dimension). In such embodiments, the gate structure 125 and / or the gate stack 150 has a rectangular cross-sectional profile. In some embodiments, where the gate structure 125 and / or the gate stack 150 exhibits slight necking and / or bowing, the gate structure 125 and / or the gate stack 150 may have a concave cross-sectional profile (i.e., having a middle and an end portion, wherein the width of the middle portion is less than the width of the end portion). However, it should be noted that residual stress of less than approximately -2.5 GPa (i.e., large compressive residual stress) in the stress-treated adhesive layer 156' may cause necking, which narrows the gate opening 145 sufficiently to cause undesirable voids and / or seams. Furthermore, a necking critical size CD that is more than 15% smaller than the critical size CD is also present. N Gate structure and / or gate stack, bow-shaped critical size CD more than 5% larger than the critical size CD B Greater than Critical dimensional differences, necking angles greater than about 5° θ, bowing angles greater than about 5° φ, or combinations thereof may still result in undesirable warping, bending, necking, and / or bowing.

[0046] In some embodiments, the stress reduction process 170 reduces the d-space (i.e., the distance between parallel crystal planes in the material) in the adhesive layer 156 to reduce its residual stress. For example, the adhesive layer 156 has a d-space greater than approximately The d-space, stress-treated adhesive layer 156' has a d-spacing less than or equal to approximately The stress-reducing treatment 170 increases the titanium to nitrogen ratio (i.e., Ti / N ratio) in the adhesive layer 156 to reduce its residual stress. For example, the adhesive layer 156 has a Ti / N ratio of less than about 1.0 (e.g., about 0.8 to about 1.0), the stress-reducing adhesive layer 156' has a Ti / N ratio of greater than about 1.0 (e.g., about 1.3 to about 2.0), and the stress-reducing adhesive layer 156' has a residual stress of less than the residual stress of the adhesive layer 156. In some embodiments, the stress-reducing treatment 170 combines and / or increases the amount of non-metallic material in the adhesive layer 156 to reduce its residual stress. For example, adhesive layer 156 is substantially free of nonmetallic substances (e.g., argon (Ar), oxygen (O), fluorine (F), hydrogen (H), other suitable nonmetallic substances, or combinations thereof), stress-treated adhesive layer 156' includes nonmetallic substances (e.g., Ar, O, F, H, other nonmetallic substances, or combinations thereof), and stress-treated adhesive layer 156' has a residual stress less than that of adhesive layer 156 (i.e., increasing the amount of nonmetallic substance reduces the residual stress). In another example, adhesive layer 156 includes a first concentration of nonmetallic substance (e.g., a negligible amount), stress-treated adhesive layer 156' includes a second concentration of nonmetallic substance greater than the first concentration, and stress-treated adhesive layer 156' has a residual stress less than that of adhesive layer 156.

[0047] In some embodiments, the stress reduction treatment 170 is an ion implantation process that uses a dopant material (also referred to as implanted material and / or ions) to bombard the adhesive layer 156 to alter its stress characteristics. For example, an implantation energy of about 0.5 keV to about 5 keV and about 1 × 10⁻⁶ ions are used. 14 cm -3 To approximately 1×10 16 cm -3 The implantation dose is used to implant Ar, N, O, F, other suitable dopant materials, or combinations thereof into the adhesive layer 156. A tilt angle of approximately 5° to approximately 15° can be achieved to implant dopant materials into the adhesive layer 156, wherein the tilt angle is between the incident ion beam direction and the normal direction of the substrate 105. To ensure that the stress-treated adhesive layer 156' has sufficiently low residual stress (e.g., less than approximately 0.8 GPa) to eliminate (or significantly reduce) the bowing and / or necking of the gate structure 125 and / or gate stack 150, the ion implantation process is configured to provide a value greater than approximately 9 × 10⁻⁶. 16 cm -3The stress-treated adhesive layer 156' contains a concentration of non-metallic dopant material (e.g., Ar, N, O, F, other non-metallic dopant materials, or combinations thereof). The dopant material penetrates the stress-treated adhesive layer 156' to a depth D. Figure 3G The ion implantation process is configured to implant dopant material into the adhesive layer 156 to a sufficiently deep depth to substantially alter the properties and / or characteristics of the adhesive layer 156 and reduce its residual stress, while ensuring that the dopant material does not reach (or only a negligible amount of dopant material reaches) the underlying gate layer, such as the metal gate layer 154 and / or the gate dielectric layer 152. Therefore, the depth D is less than or equal to the thickness T. In some embodiments, the depth D is approximately... to approximately In some embodiments, the adhesive layer 156 is bombarded with a dopant material to disrupt and / or modify the lattice structure of the adhesive layer 156 in a manner that can reduce strain / stress. In such embodiments, the adhesive layer 156 and the stress-treated adhesive layer 156' have different lattice structures (e.g., the stress-treated adhesive layer 156' has a more relaxed lattice structure and / or smaller d-spaces) and different residual stress characteristics (e.g., the stress-treated adhesive layer 156' exhibits less residual stress).

[0048] In some embodiments, stress reduction treatment 170 is an argon ion implantation process that introduces argon into the adhesive layer 156. In such embodiments, during the ion implantation process, the flow rate of argon-containing gas (e.g., Ar) entering the process chamber is from about 1,000 standard cubic centimeters per minute (sccm) to about 5,000 sccm. In some embodiments, stress reduction treatment 170 is a nitrogen ion implantation process that introduces nitrogen into the adhesive layer 156. In such embodiments, during the ion implantation process, the flow rate of nitrogen-containing gas (e.g., N2) entering the process chamber is from about 1,000 sccm to about 2,000 sccm. In some embodiments, stress reduction treatment 170 is an oxygen ion implantation process that introduces oxygen into the adhesive layer 156. In such embodiments, during the ion implantation process, the flow rate of oxygen-containing gas (e.g., O2) entering the process chamber is from about 1,000 sccm to about 2,000 sccm. In some embodiments, stress reduction treatment 170 is a fluorine ion implantation process that introduces fluorine into the adhesive layer 156. In such an embodiment, during the ion implantation process, the flow rate of the fluorine-containing gas (e.g., F2) entering the process chamber is from about 500 sccm to about 1,500 sccm. Various ion implantation parameters can be adjusted to alter the stress characteristics of the adhesive layer 156 and provide a stress-treated adhesive layer 156' with desired stress characteristics (e.g., residual stress less than about 0.8 GPa), such as the implanted dopant material, implantation energy (e.g., ion beam energy), implantation dose, implantation angle (e.g., tilt angle), implantation gas composition (e.g., type of dopant source gas and / or type of carrier gas), dopant gas flow rate, carrier gas flow rate, implantation temperature, implantation time, other suitable ion implantation parameters, or combinations thereof. For example, implantation energy, implantation dose, tilt angle, and dopant gas flow rate greater than those at the upper end of the provided example may cause defects (e.g., physical defects such as pit defects and / or electrical defects) and / or undesirably alter the properties / characteristics (e.g., undesirable threshold voltage shift) in the stress-treated adhesive layer 156', metal gate layer 154, gate dielectric layer 152, interface layer 152A, or combinations thereof, while those less than those at the lower end of the provided example will not sufficiently reduce the residual stress in the adhesive layer 156 to eliminate or significantly reduce the warpage of the gate structure 125 (i.e., the stress-treated adhesive layer 156' may still have excessively high residual tensile stress (e.g., greater than 0.8 GPa)). In some embodiments, the values ​​of implantation energy, implantation dose, tilt angle, and dopant gas flow rate depend on the thickness of the adhesive layer 156.

[0049] In some embodiments, stress reduction treatment 170 is a thermal process, such as annealing, of heating adhesive layer 156 in a gaseous atmosphere to alter its stress characteristics. For example, adhesive layer 156 is annealed at a temperature of about 300°C to about 500°C in a process chamber containing an oxygen-containing gas (e.g., O2) and / or a hydrogen-containing gas (e.g., H2). In such embodiments, oxygen and / or hydrogen are introduced into adhesive layer 156 during stress reduction treatment 170, and stress-treated adhesive layer 156' comprises oxygen and / or hydrogen. In other words, adhesive layer 156 undergoes an oxidation process and / or a hydrogenation process. In some embodiments, after O2 annealing, the oxygen concentration in stress-treated adhesive layer 156' is greater than about 9 × 10⁻⁶. 16 cm -3 In some embodiments, after H2 annealing, the hydrogen concentration in the stress-treated adhesive layer 156' is greater than about 9 × 10⁻⁶. 16 cm -3 In some embodiments, the flow rate of the gas (e.g., O2 and / or H2) entering the process chamber during the annealing process is from about 100 sccm to about 200 sccm. In some embodiments, the annealing process is performed at a pressure of from about 3 Torr to about 50 Torr. In some embodiments, the annealing process is rapid thermal annealing (RTA). Various annealing parameters can be adjusted to change the stress characteristics of the adhesive layer 156 and provide a stress-treated adhesive layer 156' with desired stress characteristics (e.g., residual stress less than about 0.8 GPa), such as annealing temperature, annealing pressure, annealing time, annealing gas composition, annealing gas flow rate, other suitable annealing parameters, or combinations thereof. For example, annealing temperatures, annealing gas flow rates, and annealing pressures greater than those at the upper end of the provided example can alter the properties of the adhesive layer 156, the metal gate layer 154, the gate dielectric layer 152, the interface layer 152A, or combinations thereof, in a manner that causes undesirable threshold voltage shifts in device 100, while those less than those at the lower end of the provided example will not reduce residual stress sufficiently to eliminate or significantly reduce warpage of the gate structure 125. The invention also contemplates annealing the adhesive layer 156 in other gaseous environments, such that the stress-treated adhesive layer 156' may include components other than oxygen and / or hydrogen, depending on the annealing gas composition.

[0050] In embodiments where the adhesive layer 156 undergoes oxygen annealing (i.e., in a process chamber containing oxygen-containing gas), the device 100 may undergo a wet cleaning process prior to oxygen annealing. For example, an ozone-deionized water (DIO3) cleaning process may be performed on the adhesive layer 156 prior to oxygen annealing. In such embodiments, a DIO3 solution having an ozone concentration of about 30 ppm to about 100 ppm may be applied to the adhesive layer 156 while the wafer on which the device 100 is formed rotates at a speed of about 240 revolutions per minute (rpm) to about 500 rpm.

[0051] exist Figure 3H In this process, a metal filler (or bulk) layer 158 is formed above the substrate 105. The metal filler layer 158 is disposed on the stress-treated adhesive layer 156' and fills the remaining portion of the gate opening 145. In some embodiments, the metal filler layer 158 has approximately to approximately The thickness of the gate structure 125 is minimized or eliminated because the stress reduction treatment 170 provides a stress-treated adhesive layer 156'. The gate opening 145 has a substantially uniform width along its height, and the metal filler layer 158 can completely fill the remaining portion of the gate opening 145 without creating voids in the gate stack 150. For example, the substantially uniform width of the gate opening 145 reduces the likelihood that the metal filler layer 158 will block or pinch the gate opening 145 before filling. The metal filler layer 158 comprises a suitable conductive material, such as Al, W, Cu, other metals, metal oxides, metal nitrides, other suitable conductive materials, or combinations thereof. The metal filler layer 158 is formed by ALD, PVD, CVD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, plating, other suitable methods, or combinations thereof. In the depicted embodiment, the metal filler layer 158 is a tungsten layer formed by PVD or CVD.

[0052] Transfer to Figure 3IA planarization process is performed to remove excess gate material from device 100. For example, a CMP process is performed until the top surface of dielectric layer 140 is reached (exposed). In some embodiments, the CMP process continues and the thickness of dielectric layer 140 is reduced, and the height of gate structure 125 is correspondingly reduced. In the depicted embodiment, after the CMP process, the top of gate structure 125 is substantially coplanar with the top of dielectric layer 140, and the remaining portion of gate material filling gate opening 145 forms gate stack 150 of gate structure 125. Gate stack 150 includes gate dielectric (e.g., interface layer 152A and gate dielectric layer 152) and gate electrode (e.g., metal gate layer 154, stress-treated adhesive layer 156', and metal filler layer 158). In the case where gate dielectric layer 152 is a high-k dielectric layer, gate stack 150 may be referred to as a high-k / metal gate. Because a stress reduction process 170 is performed prior to the formation of the metal filler layer 158 to provide a stress-treated adhesive layer 156', the gate structure 125 has minimal to no warpage, and the metal filler layer 158 can completely fill the remaining portion of the gate opening 145 without forming voids in the gate stack 150. Therefore, the gate stack 150 does not have any seams, such as seams 160A' and / or seams 160B' (as described above, this occurs when voids are formed in the gate stack 150 because the metal filler layer 158 is insufficient to fill the remaining portion of the gate opening 145 due to the warpage profile of the gate structure 125 caused by the residual tensile stress of the adhesive layer 156). In some embodiments, negligible seams may be formed in the gate stack 150, such as those having less than approximately The width of the seam. Less than approximately The seams rarely cause damage to the gate stack 150 and / or the channel region 110, such as those described above with respect to seams 160A' and / or seams 160B'. Therefore, for the purposes of this invention, seams with negligible spacing (i.e., having less than approximately Gate stacks (such as gate stack 150) with seams of a certain width are considered to be seamless.

[0053] In some embodiments, device 100 is a transistor including a channel (e.g., channel region 110), source / drain electrodes (e.g., epitaxial source / drain 120), and a gate (e.g., a gate structure 125 having gate spacers 135 disposed along the sidewalls of a gate stack 150). The gate junction defines the channel between the source / drain electrodes, and current can flow between the source / drain electrodes (e.g., between the source and drain, and vice versa) during operation. In some embodiments, device 100 is a FinFET, channel region 110 is a portion of the semiconductor fin extending from substrate 105, gate stack 150 is located on top of the semiconductor fin (and therefore channel region 110) in the YZ plane, and gate stack 150 wraps around the semiconductor fin (and therefore channel region 110) in the XZ plane, such as in… Figure 1 In the middle (i.e., the gate stack 150 is disposed on the top and sidewalls of the semiconductor fin). In some embodiments, the device 100 is a GAA transistor, such as Figure 10 As depicted in [the text]. Figure 10In this embodiment, the channel region 110 is at least one semiconductor layer (i.e., the channel layer) floating above the substrate 105. The gate stack 150 is located on the top and bottom of the at least one semiconductor layer (and therefore the channel region 110) in the YZ plane (i.e., the gate stack 150 is also located between the channel region 110 and the substrate 105), and the gate stack 150 surrounds the at least one semiconductor layer (and therefore the channel region 110) in the XZ plane (i.e., the gate stack 150 is disposed on the top, bottom, and sidewalls of the at least one semiconductor layer). In such an embodiment, an internal spacer 180 is disposed between the gate stack 150 and the epitaxial source / drain 120. In such an embodiment, a channel release process is performed before the gate stack 150 is formed in the gate opening 145 to provide the channel region 110 having at least one semiconductor layer floating above the substrate 105 (i.e., after the channel release process, the semiconductor layer does not physically contact the substrate 105). For example, where a semiconductor layer stack having a first semiconductor layer (e.g., a silicon-germanium layer) and a second semiconductor layer (e.g., a silicon layer) is exposed at gate opening 145, the first semiconductor layer is selectively removed to form air gaps between the second semiconductor layers and between the second semiconductor layer and the substrate 105, thereby floating the second semiconductor layer above the substrate 105. The second semiconductor layers are stacked vertically along the z-direction and provide a channel region 110 having one or more channels through which current can flow between epitaxial source / drain 120. In some embodiments, an etching process is performed to selectively etch the first semiconductor layer while at least (or not at all) etching the second semiconductor layer, the substrate 105, the gate spacer 135, the dielectric layer 140, and / or the internal spacers. In some embodiments, an etchant is selected for the etching process that etches silicon-germanium (i.e., the first semiconductor layer) at a higher rate than silicon (i.e., the second semiconductor layer and the substrate 105) and the dielectric material (i.e., the gate spacer 135, the dielectric layer 140, and / or the internal spacers) (i.e., the etchant has high etch selectivity relative to silicon-germanium). The etching process is dry etching, wet etching, other suitable etching processes, or a combination thereof. In some embodiments, an oxidation process may be performed prior to the etching process to convert the first semiconductor layer into a silicon germanium oxide component, wherein the etching process then removes the silicon germanium oxide component. In some embodiments, during and / or after the removal of the first semiconductor layer, an etching process is performed to modify the profile of the second semiconductor layer to achieve a target size and / or target shape for the channel region 110.

[0054] In some embodiments, the fabrication of device 100 may continue to form various contacts to facilitate operation of device 100. For example, one or more dielectric layers similar to dielectric layer 140 may be formed over gate structure 125 (including gate stack 150) and dielectric layer 140. Contacts may then be formed in dielectric layer 140 and / or in dielectric layers disposed over dielectric layer 140. For example, contacts physically and / or electrically coupled to one or both of the epitaxial source / drain 120 of gate stack 150 and device 100 may be formed. Contacts include conductive materials, such as metals. Metals include aluminum, aluminum alloys (such as aluminum / silicon / copper alloys), copper, copper alloys, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, polysilicon, metal silicides, other suitable metals, or combinations thereof. Metal silicides may include nickel silicide, cobalt silicide, tungsten silicide, tantalum silicide, titanium silicide, platinum silicide, erbium silicide, palladium silicide, or combinations thereof. In some embodiments, the dielectric layer and contacts disposed above the dielectric layer 140 (e.g., gate contacts and source / drain contacts extending through and / or disposed therein) are portions of the MLI component disposed above the substrate 105, as described above. The MLI component may include a combination of metal and dielectric layers configured to form vertical interconnect components (such as contacts and / or vias) and / or horizontal interconnect components (such as lines). Each conductive component comprises a material similar to that of the contacts. In some embodiments, the MLI component is formed using a damascene process and / or a dual damascene process.

[0055] Figures 8A to 8G It is according to various aspects of the invention at various manufacturing stages (such as with) Figure 2 This is a partial schematic diagram of part or all of the device 200 (related to method 50 in the diagram). Device 200 may be included in a microprocessor, memory, and / or other integrated circuit device. Device 200 may be part of an IC chip, a SoC, or a portion thereof, which includes various passive and active microelectronic devices such as resistors, capacitors, inductors, diodes, PFETs, NFETs, MOSFETs, CMOS transistors, BJTs, LDMOS transistors, high-voltage transistors, high-frequency transistors, other suitable components, or combinations thereof. For clarity, simplified diagrams have been provided. Figures 8A to 8G To better understand the inventive concept of the present invention. Additional components may be added to device 200, and some of the components described below may be replaced, modified, or eliminated in other embodiments of device 200.

[0056] Figures 8A to 8G The fabrication of device 200 is similar in many ways to Figures 3A to 3IThe fabrication of device 200, except that the fabrication of device 200 forms a stress-treated multilayer adhesive layer 256' instead of stress-treated adhesive layer 156'. For example, fabrication begins with receiving, for example, a substrate 105, a channel region 110, an epitaxial source / drain 120, a gate structure 125 (including a dummy gate 130 and a gate spacer 135), and a dielectric layer 140 ( Figure 8A Its manufacturing process is similar to that of the reference. Figure 3A As described, the device precursor is used to remove the dummy gate 130 to form the gate opening 145. Figure 8B Its manufacturing process is similar to that of the reference. Figure 3B As described, a gate dielectric layer 152 is formed that partially fills the gate opening 145. Figure 8C Its manufacturing process is similar to that of the reference. Figure 3C As described above, and a metal gate layer 154 is formed above the gate dielectric layer 152. Figure 8D Its manufacturing process is similar to that of the reference. Figure 3D As described).

[0057] Then, turn to Figure 8E Instead of forming a single adhesive layer (such as adhesive layer 156) and implementing stress reduction treatment 170 to provide stress-treated adhesive layer 156', the fabrication of device 200 continues to form a stress-treated multilayer adhesive layer 256' having a thickness T. The stress-treated multilayer adhesive layer 256' partially fills the gate opening 145. Similar to stress-treated adhesive layer 156', the stress-treated multilayer adhesive layer 256' has a residual stress of about -2.5 GPa to about 0.8 GPa (i.e., residual compressive stress, neutralization stress, or negligible residual tensile stress) and therefore exhibits minimal to no warpage, bending, necking, and / or bowing, which correspondingly eliminates or significantly reduces the warpage of the gate structure 125, as shown from... Figure 8E As can be seen, the gate stack 150 with stress-treated multilayer adhesive layer 256' has a profile similar to that described above for the gate stack 150 with stress-treated adhesive layer 156', such as substantially uniform critical dimensions and / or necking critical dimensions CD. N Critical dimension CD of the bow shape B Critical dimensional differences, necking angle θ, bow angle φ, or combinations thereof, as described above.

[0058] The stress-treated multilayer adhesive layer 256' includes glue layers 256 separated by metal layers 260. In the depicted embodiment, the stress-treated multilayer adhesive layer 256' includes three glue layers 256 and two metal layers 260, wherein a first glue layer 256 physically contacts a metal gate layer 154, a first metal layer 260 is located between a first glue layer 256 and a second glue layer 256, and a second metal layer 260 is located between a second glue layer 256 and a third glue layer 256. The glue layers 256 have a thickness T1, and the metal layers 260 have a thickness T2. In some embodiments, the thickness T1 is approximately to approximately In some embodiments, the thickness T2 is approximately to approximately The stress-treated multilayer adhesive layer 256' includes a material that promotes adhesion between the metal gate layer 154 and the metal filler layer 158, such as a material comprising a metal (e.g., W, Al, Ta, Ti, Ni, Cu, Co, other suitable metals or combinations thereof), a metal oxide, a metal nitride, a metal alloy, or a combination thereof. For example, the adhesive layer 256 comprises a metal and nitrogen, and the metal layer 260 comprises a metal. In the depicted embodiment, the adhesive layer 256 is a titanium nitride layer (e.g., a TiN layer), and the metal layer 260 is a titanium layer (e.g., a Ti layer). In some embodiments, the adhesive layer 256 is a tantalum nitride layer (e.g., a TaN layer), and the metal layer 260 is a tantalum layer (e.g., a Ta layer). As further described below, a hydrogen poisoning process is performed when the stress-treated multilayer adhesive layer 256' is formed, such that the adhesive layer 256 and / or the metal layer 260 also comprise hydrogen. For example, the adhesive layer 256 comprises titanium, nitrogen, and hydrogen, and / or the metal layer 260 comprises titanium and hydrogen. The gluon layer 256 and the metal layer 260 are formed by ALD, PVD, CVD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, plating, other suitable methods, or combinations thereof.

[0059] In some embodiments, forming the stress-treated multilayer adhesive layer 256' includes loading a wafer on which the device 200 is fabricated into a process chamber; heating the wafer to a desired temperature (e.g., a temperature at which a chemical reaction is required to promote the formation of the adhesive layer 256 and the metal layer 260); performing a deposition cycle including at least one adhesive layer / metal layer pair (i.e., including depositing an adhesive layer (e.g., a titanium nitride layer), depositing a metal layer (e.g., a titanium layer) over the adhesive layer, and performing a hydrogen poisoning treatment (e.g., H2 immersion); and depositing a top adhesive layer over at least one adhesive layer / metal layer pair. The deposited adhesive layer 256 and metal layer 160 may include... This includes infusing one or more precursors and / or supports (e.g., H2, N2, Ar, other suitable carrier gases, or combinations thereof) into the process chamber, wherein the precursors react and / or decompose to form a gluon layer 256 or a metal layer 260. In some embodiments, depositing the gluon layer 256 includes introducing a titanium-containing precursor gas (e.g., titanium tetrachloride (TiCl4) gas), a nitrogen-containing precursor gas (e.g., ammonia (NH3) gas), and a carrier gas (e.g., H2 and / or Ar) into the process chamber to allow for a duration of deposition of TiN material having a thickness T1. In some embodiments, depositing the metal layer 260 includes infusing a titanium-containing precursor gas (e.g., H2, N2, Ar, other suitable carrier gases, or combinations thereof) into the process chamber. The introduction of TiCl4 and a carrier gas (e.g., H2 and / or Ar) into the process chamber allows for the deposition of Ti material with a thickness T2 for a duration (reaction time), such as from about 10 seconds to about 120 seconds. In some embodiments, performing hydrogen poisoning includes introducing a hydrogen-containing gas (e.g., H2) into the process chamber for a duration sufficient to bind hydrogen to the gel layer 256 and / or the metal layer 260, such as from about 10 seconds to about 30 seconds. In some embodiments, the hydrogen concentration in the stress-treated multilayer gel layer 256' is from about 0.5 atomic percent (at%) to about 1 at%. In some embodiments, when forming the stress-treated multilayer gel layer... During layer 256', the temperature maintained in the process chamber is approximately 400°C to approximately 500°C. Forming the stress-treated multilayer adhesive layer 256' may further include removing any remaining precursors (e.g., unreacted precursors), carriers, and / or byproducts from the process chamber. In some embodiments, the process chamber is purged after each adhesive layer is deposited, for example, to remove nitrogen-containing byproducts before depositing the metal layer. In some embodiments, the process chamber is purged after each metal sublayer is deposited. In some embodiments, the process chamber is purged after each hydrogen poisoning treatment. In some embodiments, the process chamber is purged after the final deposition cycle and before depositing the top adhesive layer.

[0060] Various deposition parameters and hydrogen poisoning parameters can be adjusted to change the stress characteristics of the stress-treated multilayer colloid 256', gluon layer 256, metal layer 260, or combinations thereof, and to provide the stress-treated multilayer colloid 256' with desired stress characteristics (e.g., residual stress less than about 0.8 GPa), such as deposition precursor type, deposition precursor flow rate, carrier gas type, carrier gas flow rate, deposition pressure, deposition temperature, deposition power, deposition time, hydrogen poisoning precursor type, hydrogen flow rate during hydrogen poisoning, hydrogen poisoning time, hydrogen poisoning temperature, other suitable deposition parameters, other hydrogen poisoning parameters, or combinations thereof. For example, deposition temperatures, deposition times, and hydrogen treatment times greater than those at the upper end of the provided example can alter the properties of the metal layer 260, gluon layer 256, metal gate layer 154, gate dielectric layer 152, interface layer 152A, or combinations thereof, in a manner that causes undesirable threshold voltage shifts in device 200, while those less than those at the lower end of the provided example will not reduce residual stress sufficiently to eliminate or significantly reduce warpage of the gate structure 125. The flow rate of the titanium-containing precursor when depositing the gluon layer 256 can be the same as or different from the flow rate of the titanium-containing precursor when depositing the metal layer 260. The hydrogen flow rate when depositing the metal layer 260 can be the same as or different from the hydrogen flow rate when performing hydrogen poisoning treatment. The titanium-containing precursor used when depositing the gluon layer 256 can be the same as or different from the titanium-containing precursor used when depositing the metal layer 260.

[0061] Then Figure 8F and Figure 8G The manufacturing of device 200 continues in a manner similar to that of other devices. Figure 3H and Figure 3I The fabrication of device 100. For example, fabrication includes forming a metal filler layer 158 over a stress-treated multilayer adhesive layer 256'. Figure 8F Its manufacturing process is similar to that of the reference. Figure 3H As described above) and performing a planarization process to remove excess gate material from device 200, thereby forming gate stack 150 ( Figure 8G Its manufacturing process is similar to that of the reference. Figure 3I As described). In Figure 8GIn this configuration, the gate stack 150 includes a gate dielectric (e.g., an interface layer 152A and a gate dielectric layer 152) and a gate electrode (e.g., a metal gate layer 154, a stress-treated multilayer adhesive layer 256', and a metal filler layer 158). Because the stress-treated multilayer adhesive layer 256' has sufficiently low residual stress (e.g., less than about 0.8 GPa and greater than about -2.5 GPa), the gate structure 125 has minimal to no warping, and the metal filler layer 158 can completely fill the remaining portion of the gate opening 145 without forming voids in the gate stack 150. Therefore, the gate stack 150 with the stress-treated multilayer adhesive layer 256' does not have any seams, such as seams 160A' and / or seams 160B' (as described above, this occurs when voids are formed in the gate stack 150 because the metal filler layer 158 is insufficient to fill the remaining portion of the gate opening 145 due to the warping profile of the gate structure 125 caused by the residual tensile stress of the adhesive layer). The present invention also considers, for example Figure 10 The device 200 is configured as depicted in the figure, which includes a gate stack 150 having a stress-treated multilayer adhesive layer 256'.

[0062] Figure 9A and Figure 9B Experimental data are provided for wafers on which devices including gate stacks with adhesive layers are fabricated, according to various aspects of the present invention. Figure 9A The defect count obtained through electron beam inspection (EBI) is used as the d-space of the adhesive layer (in terms of...). An exemplary graph 310 shows a function of (units). Defects detected by EBI may include voids and / or seams in the gate stack. Figure 9A In this study, the EBI and d-space of the adhesive layer were evaluated for four wafers:

[0063] A1, a wafer comprising a device having a gate stack with an unstress-reduced adhesive layer, such as the one referenced above. Figure 4A , Figure 4B , Figure 5 , Figure 6A , Figure 6B and Figure 7 As described;

[0064] A2, a wafer comprising a device having a gate stack with a stress-reducing adhesive layer, wherein the stress reduction treatment is an ion implantation process, as described in the reference above. Figures 3A to 3I As described;

[0065] A3 refers to a wafer containing a gate stack with a stress-reducing adhesive layer, wherein the stress reduction treatment is a thermal process, as described in the reference above. Figures 3A to 3I As described; and

[0066] A4, a wafer comprising a device having a gate stack with stress-treated multilayer adhesive layers, as shown in the reference above. Figures 8A to 8G As described.

[0067] Figure 9B Example curve 320 is an example of the defect count obtained through EBI as a function of the stress (in GPa) of the adhesive layer. Figure 9B In this study, the stress of EBI and the adhesive layer was evaluated on six wafers:

[0068] B1, a wafer comprising a device having a gate stack with an unstress-reduced adhesive layer, such as the one referenced above. Figure 4A , Figure 4B , Figure 5 , Figure 6A , Figure 6B and Figure 7 As described;

[0069] B2, refers to a wafer of a device comprising a gate stack with a stress-reducing adhesive layer, wherein the stress reduction treatment is an ion implantation process, as described in the reference above. Figures 3A to 3I As described;

[0070] B3 and B4 refer to wafers of devices comprising gate stacks with stress-reducing adhesive layers, wherein the stress reduction treatment is a thermal process, as described in the reference above. Figures 3A to 3I As described; and

[0071] B5 and B6 include devices with gate stacks having stress-treated multilayer adhesive layers.

[0072] wafers, such as those referenced above Figures 8A to 8G As described.

[0073] from Figure 9A and Figure 9B It can be seen that defects (such as voids and / or seams in the gate stack) are proportional to the d-space and / or residual stress of the adhesive layer of the gate stack. In other words, defects decrease as the d-space and / or residual stress of the adhesive layer of the gate stack decreases, and defects increase as the d-space and / or residual stress of the adhesive layer of the gate stack increases. For example, wafers including gate stacks with stress-reducing adhesive layers (e.g., A2-A4 and B2-B6) have fewer defects than wafers including gate stacks with untreated adhesive layers (e.g., A1 and B1), and wafers with stress-reducing adhesive layers (e.g., A2-A4 and B2-B6) have smaller d-space and less residual stress than wafers with untreated adhesive layers (e.g., A1 and B1). Figure 9AIn graph 310, line A, fitted to the experimental data for wafers A1-A4, indicates that defects decrease as the d-spacing of the adhesive layers in the gate stack decreases. Figure 9B In graph 320, line B, fitted to experimental data for wafers B1-B6, indicates that defects decrease as the residual stress of the adhesive layer in the gate stack decreases. Therefore, providing a gate stack with stress-treated adhesive layers, such as stress-treated adhesive layer 156' and stress-treated multilayer adhesive layer 256', can significantly reduce and / or eliminate gate stack warpage, which correspondingly reduces and / or eliminates voids and / or seams in the gate stack, and reduces and / or eliminates damage to the channel region (over which the gate stack is fabricated). Different embodiments may have different advantages, and no particular advantage is necessary for any embodiment.

[0074] This invention provides numerous different embodiments. Various methods are disclosed herein for forming gate stacks (e.g., high-k / metal gates) with improved profiles (e.g., minimal to no warping, bending, bowing, and necking and / or substantially vertical sidewalls) and associated gate structures, which can be implemented in a variety of device types. For example, the gate stacks described herein are suitable for planar field-effect transistors (FETs), multi-gate transistors such as FinFETs, gate all-around (GAA) transistors, omega-gate (Ω-gate) devices, π-gate (Π-gate) devices, or combinations thereof, as well as strained semiconductor devices, silicon-on-insulator (SOI) devices, partially depleted SOI devices, fully depleted SOI devices, other devices, or combinations thereof. This invention contemplates other IC devices that those skilled in the art will recognize can benefit from the gate stacks and / or gate formation techniques described herein.

[0075] An exemplary method for forming a gate stack includes: depositing a gate dielectric layer on a channel region; depositing a power function layer on the gate dielectric layer; forming a stress-treated adhesive layer on the power function layer; and depositing a metal filler layer on the stress-treated adhesive layer. In some embodiments, forming a stress-treated adhesive layer over the power function layer includes depositing a metal nitride layer over the power function layer and introducing a non-metallic substance into the metal nitride layer. The non-metallic substance is argon, nitrogen, fluorine, oxygen, hydrogen, or a combination thereof. In some embodiments, the non-metallic substance is introduced into the metal nitride layer by an ion implantation process. In some embodiments, the non-metallic substance is introduced into the metal nitride layer by a thermal process performed in a gas atmosphere. In some embodiments, forming a stress-treated adhesive layer over the power function layer includes: depositing a first gluon layer over the power function layer; depositing a metal layer over the first gluon layer; depositing a second gluon layer over the metal layer; and performing a hydrogen poisoning treatment.

[0076] In some embodiments, the gate stack has an arcuate critical size that is about 30% to about 35% of a predetermined critical size, and introducing a nonmetallic material into the metal nitride layer is configured to reduce the arcuate critical size such that the arcuate critical size is about 0% to about 5% of the predetermined critical size. In some embodiments, the metal nitride layer has a first d-spacer, and introducing a nonmetallic material into the metal nitride layer is configured to reduce the first d-spacer to a second d-spacer. In some embodiments, the metal nitride layer has a first nitrogen concentration, and introducing a nonmetallic material into the metal nitride layer is configured to increase the first nitrogen concentration to a second nitrogen concentration.

[0077] Another exemplary method includes: forming a gate opening that exposes a channel region; forming a gate dielectric layer in the gate opening; forming a functional layer in the gate opening above the gate dielectric layer; forming a metal adhesive layer in the gate opening above the functional layer; performing a stress reduction treatment on the metal adhesive layer; and after the stress reduction treatment, forming a metal filler layer in the gate opening above the metal adhesive layer. The gate dielectric layer, functional layer, metal adhesive layer, and metal filler layer form a gate stack of a gate structure that fills the gate opening. In some embodiments, the metal adhesive layer has residual tensile stress, and performing a stress reduction treatment on the metal adhesive layer includes changing the residual tensile stress into residual compressive stress. In some embodiments, the metal adhesive layer has a residual stress greater than about 1.0 GPa, and performing a stress reduction treatment on the metal adhesive layer includes reducing the residual stress to less than about 1.0 GPa. In some embodiments, the gate structure has a first gate spacer and a second gate spacer, a gate opening is located between the first gate spacer and the second gate spacer, a first distance exists between the first gate spacer and the second gate spacer before a metal adhesive layer is formed in the gate opening, a second distance exists between the first gate spacer and the second gate spacer after the metal adhesive layer is formed in the gate opening, and a stress reduction process is adjusted to reduce the second distance to the first distance. In some embodiments, performing a stress reduction process on the metal adhesive layer includes performing an ion implantation process on the metal adhesive layer. In some embodiments, performing a stress reduction process on the metal adhesive layer includes annealing the metal adhesive layer in a gaseous atmosphere, and in some embodiments, a wet cleaning process is performed before annealing the metal adhesive layer in a gaseous atmosphere.

[0078] An exemplary device includes a channel region disposed between an epitaxial source and drain, and a gate stack disposed above the channel region. The gate stack includes a gate dielectric layer, a work function layer above the gate dielectric layer, a metal paste layer above the work function layer, and a metal filler layer above the metal paste layer. The metal paste layer has a residual stress of about -2.5 gigapascals (GPa) to about 0.8 GPa. In some embodiments, the metal paste layer includes metal and non-metal dopants, and the concentration of the non-metal dopants is greater than about 9 × 10⁻⁶. 16cm -3 In some embodiments, the metal adhesive layer includes a metal layer disposed between a first gluon layer and a second gluon layer, the first and second gluon layers comprising metal and nitrogen, and the metal layer comprising metal. In some embodiments, the metal adhesive layer is a titanium nitride layer, and the ratio of nitrogen to titanium in the titanium nitride layer is about 1.3 to about 2.

[0079] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the invention.

Claims

1. A method for forming a gate stack, the method comprising: Deposit a gate dielectric layer on the channel region; A work function layer is deposited on the gate dielectric layer; A stress-treated adhesive layer is formed on the work function layer, wherein forming the stress-treated adhesive layer includes a deposition process and a stress-reduction process, wherein the deposition process includes: depositing a first gluon layer above the work function layer, depositing a metal layer above the first gluon layer, and depositing a second gluon layer above the metal layer; and the stress-reduction process includes performing hydrogen poisoning treatment; and A metal filler layer is deposited on the stress-treated adhesive layer.

2. The method according to claim 1, wherein, Depositing the first gluon layer includes depositing a first metal nitride layer.

3. The method according to claim 2, wherein, Depositing the second gluon layer includes depositing a second metal nitride layer.

4. The method according to claim 3, wherein, Depositing the first metal nitride layer and the second metal nitride layer includes depositing a titanium layer.

5. The method according to claim 1, wherein, The hydrogen poisoning treatment includes introducing hydrogen into the stress-treated adhesive layer.

6. The method according to claim 5, wherein, The hydrogen poisoning treatment involves exposing the stress-treated adhesive layer to hydrogen-containing gas for 10 to 30 seconds.

7. The method according to claim 1, wherein, The first gluon layer, the metal layer, and the second gluon layer each have a thickness of 2 Å to 5 Å.

8. The method according to claim 2, wherein: Depositing the first metal nitride layer includes depositing a first tantalum nitride layer and a second tantalum nitride layer.

9. The method according to claim 3, wherein, Depositing the first metal nitride layer and the second metal nitride layer includes depositing a tantalum layer.

10. A method of forming a semiconductor device, comprising: Forming a gate opening in the exposed channel region; A gate dielectric layer is formed in the gate opening; A functional layer is formed in the gate opening above the gate dielectric layer; A metal adhesive layer is formed in the gate opening above the power function layer; The metal adhesive layer is subjected to stress reduction treatment; as well as After the stress reduction treatment, a metal filler layer is formed in the gate opening above the metal adhesive layer, wherein the gate dielectric layer, the power function layer, the metal adhesive layer, and the metal filler layer form a gate stack that fills the gate opening. The gate structure includes a first gate spacer and a second gate spacer; the gate opening is located between the first gate spacer and the second gate spacer; before the metal adhesive layer is formed in the gate opening, there is a first distance between the first gate spacer and the second gate spacer; after the metal adhesive layer is formed in the gate opening, there is a second distance between the first gate spacer and the second gate spacer; and the stress reduction process is adjusted to reduce the second distance to the first distance.

11. The method according to claim 10, wherein, The metal adhesive layer has residual tensile stress, and the stress reduction treatment applied to the metal adhesive layer includes changing the residual tensile stress into residual compressive stress.

12. The method according to claim 10, wherein, The metal adhesive layer has a residual stress greater than about 1.0 gigapascal (GPa), and the stress reduction treatment applied to the metal adhesive layer includes reducing the residual stress to less than about 1.0 gigapascal, wherein "about" means within ±10% of the described value.

13. The method according to claim 10, wherein, The stress reduction treatment applied to the metal adhesive layer includes performing an ion implantation process on the metal adhesive layer.

14. The method according to claim 13, wherein, The ion implantation process is an argon implantation process.

15. The method according to claim 10, wherein, The stress reduction treatment performed on the metal adhesive layer includes annealing the metal adhesive layer in a gaseous atmosphere.

16. The method according to claim 15, wherein, The stress reduction treatment of the metal adhesive layer includes performing a wet cleaning process before annealing the metal adhesive layer in the gas atmosphere.

17. A semiconductor device, comprising: The channel region is located between the epitaxial source and drain. as well as A gate stack is disposed above the channel region, wherein the gate stack includes: a gate dielectric layer, a power function layer above the gate dielectric layer, a metal adhesive layer above the power function layer, wherein the metal adhesive layer has a residual stress of about -2.5 gigapascals (GPa) to about 0.8 gigapascals, wherein the about means within ±10% of the described value, wherein the metal adhesive layer includes a metal layer disposed between a first gluon layer and a second gluon layer, wherein the first gluon layer and the second gluon layer comprise metal and nitrogen, and the metal layer comprises the metal, and a metal filler layer is disposed above the metal adhesive layer.

18. The semiconductor device according to claim 17, wherein, The metal is a first metal, and the metal filling layer includes a second metal, and the second metal is different from the first metal.

19. The semiconductor device according to claim 18, wherein, The first metal is titanium and the second metal is tungsten.

20. The semiconductor device according to claim 17, wherein, The metal adhesive layer contains hydrogen.

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