Method of manufacturing a semiconductor structure

Abstract

The application relates to a preparation method of a semiconductor structure, which comprises the following steps: providing a substrate, a groove is formed in the substrate; forming a gate medium material layer on the bottom and the sidewall of the groove, and forming a gate material layer in the groove; synchronously etching the gate medium material layer and the gate material layer to obtain a gate medium layer located on the bottom and the sidewall of the groove and a shielding gate located in the groove and having an arc-shaped top surface; the top surface of the shielding gate is lower than the top surface of the groove, and the top surface of the gate medium layer is lower than the top surface of the shielding gate. The reliability of the formed SGT MOSFET can be ensured by adopting the method.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a preparation method of semiconductor structure. BACKGROUND

[0002] With the development of semiconductor technology, a split gate trench metal oxide semiconductor field effect transistor (SGTMOSFET) appears. The gate structure of the SGT MOSFET generally includes a shield gate and a control gate, both of which are formed in a trench, and the shield gate is generally located at the bottom of the trench and the control gate is located at the top of the trench. The shield gate and the control gate are generally separated by a layer of thermal oxide (TOX).

[0003] In the gate structure of the SGT MOSFET, the TOX needs to have a certain height difference with the top of the shield gate, and the topography of the shield gate also needs to be controlled to ensure the reliability of the finally formed SGT MOSFET. In the traditional preparation process of the SGTMOSFET, two etching processes, wet etching and dry etching, are used to cooperate to form a height difference between the TOX and the top of the shield gate. However, the traditional technology requires high coordination between the two etching processes, making it difficult to accurately control the height difference and accurately control the topography of the top of the shield gate, thereby resulting in the SGT MOSFET formed having low reliability. SUMMARY

[0004] Therefore, it is necessary to provide a preparation method of semiconductor structure to solve the problem of low reliability in the prior art.

[0005] To achieve the above-mentioned purpose, the present application provides a preparation method of semiconductor structure, characterized in that it comprises:

[0006] providing a substrate, a trench is formed in the substrate;

[0007] forming a gate dielectric material layer on the bottom and sidewall of the trench, and forming a gate material layer in the trench, the gate material layer filling the trench;

[0008] simultaneously etching the gate dielectric material layer and the gate material layer to obtain a gate dielectric layer located on the bottom and sidewall of the trench and a shield gate located in the trench and having an arc-shaped top surface; the top surface of the shield gate is lower than the top surface of the trench, and the top surface of the gate dielectric layer is lower than the top surface of the shield gate.

[0009] In one of the embodiments, the synchronously etching the gate dielectric material layer and the gate material layer to obtain the gate dielectric layer located at the bottom and sidewall of the trench and the shield gate located in the trench and having an arc-shaped top surface comprises:

[0010] The gate dielectric material layer and the gate material layer are synchronously etched by using a dry etching process, and in the synchronous etching process, the etching removal rate of the gate dielectric material layer is greater than the etching removal rate of the gate material layer, so as to obtain the gate dielectric layer located at the bottom and sidewall of the trench and the shield gate located in the trench and having an arc-shaped top surface.

[0011] On the basis of the above-mentioned embodiments, in one of the embodiments, in the process of synchronously etching the gate dielectric material layer and the gate material layer by using a dry etching process, the etching gas comprises carbon-based gas, fluorine-based gas and oxygen, wherein the atomic ratio of carbon:fluorine is between 1:1 and 1:30, and the atomic ratio of carbon:oxygen is between 300:1 and 1:1; the etching power is between 300 W and 8000 W.

[0012] In one of the embodiments, the synchronously etching the gate dielectric material layer and the gate material layer to obtain the gate dielectric layer located at the bottom and sidewall of the trench and the shield gate located in the trench and having an arc-shaped top surface comprises:

[0013] The gate dielectric material layer and the gate material layer are synchronously etched by using a dry etching process, and in the synchronous etching process, the etching removal rate of the gate dielectric material layer is greater than the etching removal rate of the gate material layer, so as to obtain the gate dielectric layer located at the bottom and sidewall of the trench and the shield gate located in the trench and having an arc-shaped top surface.

[0014] The gate dielectric material layer and the gate material layer are synchronously etched by using a dry etching process, and in the synchronous etching process, the etching removal rate of the gate dielectric material layer is greater than the etching removal rate of the gate material layer, so as to obtain the gate dielectric layer located at the bottom and sidewall of the trench and the shield gate located in the trench and having an arc-shaped top surface.

[0015] On the basis of the above-mentioned embodiments, in one of the embodiments,

[0016] In the first synchronous etching process, the etching gas comprises carbon-based gas, fluorine-based gas and oxygen, wherein the atomic ratio of carbon:fluorine is between 1:1 and 1:25, and the atomic ratio of carbon:oxygen is between 250:1 and 1:1; the etching power is between 500 W and 6000 W.

[0017] The second synchronous etching process includes carbon-based gas, fluorine-based gas and oxygen, wherein the atomic ratio of carbon to fluorine is between 1:1 and 1:20, and the atomic ratio of carbon to oxygen is between 200:1 and 1:1; and the etching power is between 500 W and 6000 W.

[0018] In one of the embodiments, the synchronous etching of the gate medium material layer and the gate material layer to obtain the gate medium layer on the bottom and sidewall of the trench and the shield gate with the arc-shaped top surface in the trench includes:

[0019] The first synchronous etching of the gate medium material layer and the gate material layer by the dry etching process, wherein the etching removal rate of the gate medium material layer is greater than that of the gate material layer; and the top surface of the gate medium material layer after the first synchronous etching is lower than that of the gate material layer after the first synchronous etching.

[0020] The second synchronous etching of the gate medium material layer and the gate material layer after the first synchronous etching by the dry etching process, wherein the etching removal rate of the gate material layer is greater than that of the gate medium material layer to obtain the shield gate with the arc-shaped top surface and the gate medium layer.

[0021] On the basis of the above embodiments, in one of the embodiments,

[0022] The first synchronous etching process includes carbon-based gas, fluorine-based gas and oxygen, wherein the atomic ratio of carbon to fluorine is between 1:1 and 1:12, and the atomic ratio of carbon to oxygen is between 150:1 and 1:1; and the etching power is between 800 W and 7000 W.

[0023] The second synchronous etching process includes carbon-based gas, fluorine-based gas and oxygen, wherein the atomic ratio of carbon to fluorine is between 1:1 and 1:15, and the atomic ratio of carbon to oxygen is between 180:1 and 1:1; and the etching power is between 800 W and 7000 W.

[0024] In one of the embodiments, the synchronous etching of the gate medium material layer and the gate material layer to obtain the gate medium layer on the bottom and sidewall of the trench and the shield gate with the arc-shaped top surface in the trench includes:

[0025] The dry etching process is used to perform first synchronous etching on the gate medium material layer and the gate material layer, and the etching removal rate of the gate material layer is greater than that of the gate medium material layer during the first synchronous etching; after the first synchronous etching, the top surface of the remaining gate material layer is lower than that of the remaining gate medium material layer;

[0026] The dry etching process is used to perform second synchronous etching on the gate medium material layer and the gate material layer after the first synchronous etching, and the etching removal rate of the gate medium material layer is greater than that of the gate material layer during the second synchronous etching, so as to obtain the gate medium layer, and the top surface of the gate medium layer is lower than that of the gate material layer after the second synchronous etching;

[0027] The top surface of the gate material layer after the second synchronous etching is repaired to obtain the shielding gate with an arc-shaped top surface.

[0028] On the basis of the above-mentioned embodiments, in one of the embodiments,

[0029] During the first synchronous etching, the etching gas comprises carbon-based gas, fluorine-based gas and oxygen, wherein the atomic ratio of carbon:fluorine is between 1:1 and 1:18, and the atomic ratio of carbon:oxygen is between 120:1 and 1:1; the etching power is 500W-5000W;

[0030] During the second synchronous etching, the etching gas comprises carbon-based gas, fluorine-based gas and oxygen, wherein the atomic ratio of carbon:fluorine is between 1:1 and 1:12, and the atomic ratio of carbon:oxygen is between 100:1 and 1:1; the etching power is 500W-5000W.

[0031] In one of the embodiments, before the synchronous etching of the gate medium material layer and the gate material layer, the method further comprises:

[0032] The gate material layer is etched and removed partially, so that the gate medium material layer and the gate material layer have a height difference.

[0033] The preparation method of the semiconductor structure comprises the following steps: providing a substrate, a trench is formed in the substrate; forming a gate dielectric material layer on the bottom and the sidewall of the trench and forming a gate material layer in the trench, the gate material layer fills the trench; synchronously etching the gate dielectric material layer and the gate material layer to obtain a gate dielectric layer on the bottom and the sidewall of the trench and a shield gate in the trench with an arc-shaped top surface; the top surface of the shield gate is lower than the top surface of the trench, and the top surface of the gate dielectric layer is lower than the top surface of the shield gate. In the synchronously etching process, the etching removal rates of the gate dielectric material layer and the gate material layer can be accurately controlled by adjusting the proportion of different gases in the etching gas and the power and other parameters, so that the height difference between the top surface of the gate dielectric layer and the top surface of the shield gate can reach the target height difference, and the reliability of the SGT MOSFET can be improved. Meanwhile, the top surface morphology of the shield gate can be accurately controlled, and the reliability of the SGT MOSFET can be ensured. BRIEF DESCRIPTION OF DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort.

[0035] Figure 1 Structure schematic diagram of a structure formed by a preparation method of a traditional thermal silicon oxide layer and a polysilicon shield gate in an embodiment;

[0036] Figure 2 Structure schematic diagram of a structure formed by a preparation method of a traditional thermal silicon oxide layer and a polysilicon shield gate in an embodiment;

[0037] Figure 3 Structure schematic diagram of a structure formed by a preparation method of a traditional thermal silicon oxide layer and a polysilicon shield gate in an embodiment;

[0038] Figure 4 Flowchart of a preparation method of a semiconductor structure provided in an embodiment;

[0039] Figure 5 Cross-sectional structure schematic diagram of a structure obtained in step S101 in a preparation method of a semiconductor structure provided in an embodiment;

[0040] Figure 6 Cross-sectional structure schematic diagram of a structure obtained in step S102 in a preparation method of a semiconductor structure provided in an embodiment;

[0041] Figure 7 A cross-sectional view of a structure obtained in step S103 of the method for manufacturing a semiconductor structure provided in an embodiment;

[0042] Figure 8 A cross-sectional view of a structure obtained after etching and removing part of the gate material layer in the method for manufacturing a semiconductor structure provided in an embodiment;

[0043] Figure 9 A cross-sectional view of a structure obtained after forming a gate dielectric material layer on the upper surface of the substrate in the method for manufacturing a semiconductor structure provided in an embodiment;

[0044] Figure 10 A cross-sectional view of a structure obtained after forming a hard mask layer on the gate dielectric material layer and on the gate material layer on the upper surface of the substrate in the method for manufacturing a semiconductor structure provided in an embodiment;

[0045] Figure 11 A cross-sectional view of a structure obtained after forming a patterned hard mask layer in the method for manufacturing a semiconductor structure provided in an embodiment;

[0046] Figure 12 A flowchart of the method for manufacturing a semiconductor structure provided in an embodiment;

[0047] Figure 13 A cross-sectional view of a structure obtained in step S1201 of the method for manufacturing a semiconductor structure provided in an embodiment;

[0048] Figure 14 A flowchart of the method for manufacturing a semiconductor structure provided in an embodiment;

[0049] Figure 15 A cross-sectional view of a structure obtained in step S1401 of the method for manufacturing a semiconductor structure provided in an embodiment;

[0050] Figure 16 A flowchart of the method for manufacturing a semiconductor structure provided in an embodiment;

[0051] Figure 17 A cross-sectional view of a structure obtained in step S1601 of the method for manufacturing a semiconductor structure provided in an embodiment;

[0052] Figure 18 A cross-sectional view of a structure obtained in step S1602 of the method for manufacturing a semiconductor structure provided in an embodiment.

[0053] Explanation of reference numerals in the attached figures: 10-substrate, 101-trench, 20-gate dielectric material layer, 201-gate dielectric layer, 30-gate material layer, 301-shielding gate, 40-hard mask layer, 401-patterned hard mask layer, 402-aperture, 50-patterned photoresist layer, 70-oxide material layer, 701-thermal silicon oxide layer, 80-polysilicon layer, 801-polysilicon shielding gate. Detailed Implementation

[0054] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0055] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0056] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this invention, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0057] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and / or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is inverted, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The devices can be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0058] As used herein, the singular form "a", "an" and "the" include plural references unless the context clearly dictates otherwise. As should also be apparent, the term "comprising" or "containing" or "having" or the like means the presence of the stated feature, integer, step, operation, component, or combination thereof, but does not exclude the presence or addition of one or more other features, integers, steps, operations, components, or combinations thereof.

[0059] Embodiments of the application are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the application. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments of the application should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and / or a gradient of implant concentration at its edges rather than a binary change between implanted and non-implanted regions. Similarly, a buried region formed by implantation can result in some implantation in a region between the buried region and a surface through which the implantation occurs. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the application.

[0060] In conventional technology, the steps of forming a thermal oxide (TOX) 701 and a polysilicon split gate 801 in a gate structure of a split gate trench metal oxide semiconductor field effect transistor (SGT MOSFET) are as shown in Figures 1 to 3 Referring first to Figure 1, the oxide material layer 70 is formed before the bottom and the sidewall of the trench 101 in the substrate 10, and then the polysilicon layer 80 is filled in the trench 101. Thereafter, please refer to Figure 2 , the polysilicon layer 80 filled in the trench 101 is etched by using a dry etching process to form the polysilicon shield gate 801, and finally please refer to Figure 3 , the oxide material layer 70 on the sidewall of the trench 101 is etched by using a wet etching process to form the thermal oxide layer 701. However, as shown in Figure 3 , the SGT MOSFET gate structure also needs to have a certain height difference between the thermal oxide layer 701 and the polysilicon shield gate 801 to improve the reliability of the subsequently formed SGT MOSFET device. The traditional process combining dry etching and wet etching has high requirements for the coordination of the two etching processes. Since the wet etching itself is anisotropic etching, it is difficult to accurately control the height of the formed thermal oxide layer 701, and thus it is difficult to accurately control the height difference between the thermal oxide layer 701 and the polysilicon shield gate 801, and it is also difficult to accurately control the top morphology of the polysilicon shield gate 801, thereby resulting in the problem of low reliability of the formed SGT MOSFET.

[0061] Please refer to Figure 4 , the present application provides a preparation method of a semiconductor structure, comprising the following steps:

[0062] S101: providing a substrate, wherein a trench is formed in the substrate;

[0063] S102: forming a gate dielectric material layer on the bottom and the sidewall of the trench, and forming a gate material layer in the trench;

[0064] S103: synchronously etching the gate dielectric material layer and the gate material layer to obtain a gate dielectric layer located on the bottom and the sidewall of the trench and a shield gate with an arc-shaped top surface located in the trench; the top surface of the shield gate is lower than the top surface of the trench, and the top surface of the gate dielectric layer is lower than the top surface of the shield gate.

[0065] In step S101, please refer to Figure 4 and Figure 5 , a substrate 10 is provided, and a trench 101 is formed in the substrate 10.

[0066] The substrate 10 can include monocrystalline, polycrystalline or amorphous silicon, or silicon germanium (SiGe), can be silicon-on-insulator (SOI), or can include other materials such as indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide or gallium antimonide. Although several examples of materials that can form the substrate 10 are described herein, any material that can be used as the substrate 10 falls within the scope of the present application.

[0067] In step S102, refer to step S102 in Figure 4 and Figure 6 , a gate dielectric material layer 20 is formed at the bottom and sidewall of the trench 101, and a gate material layer 30 is formed in the trench 101.

[0068] The gate dielectric material layer 20 can include a single layer or at least two layers of dielectric material, such as a silicon oxide layer formed by a thermal oxidation process or a silicon oxide layer formed by a low pressure chemical vapor deposition (LPCVD) process, without limitation in the present embodiment; the gate material layer 30 can include any suitable conductive material layer, such as a polysilicon layer formed by an LPCVD process, without limitation in the present embodiment.

[0069] In addition, it should be noted that, as shown in Figure 6 , the gate material layer 30 can fill the trench 101, i.e. the top surface of the gate material layer 30 can be flush with the top surface of the trench 101. In actual manufacturing processes, the top surface of the gate material layer 30 can also be higher than the top surface of the trench 101, or the top surface of the gate material layer 30 can also be lower than the top surface of the trench 101, depending on the specific preparation process of the previous layer, without limitation in the present embodiment.

[0070] In step S103, refer to step S103 in Figure 4 and Figure 7 , the gate dielectric material layer 20 and the gate material layer 30 are etched synchronously to obtain a gate dielectric layer 201 at the bottom and sidewall of the trench 101 and a shield gate 301 in the trench 101 with an arc-shaped top surface; the top surface of the shield gate 301 is lower than the top surface of the trench 101, and the top surface of the gate dielectric layer 201 is lower than the top surface of the shield gate 301.

[0071] Optionally, the height difference between the top surface of the gate dielectric layer 201 and the top surface of the shield gate 301 can be 500 angstroms to 1500 angstroms, without limitation in the present embodiment; specifically, the height difference between the top surface of the gate dielectric layer 201 and the top surface of the shield gate 301 can be 700 angstroms, 1000 angstroms, 1200 angstroms or 1500 angstroms.

[0072] The etching gas for the synchronous etching can include carbon-based gas, chlorine-based gas, fluorine-based gas, oxygen, and the like, which are not limited in the present embodiment. The chlorine-based gas can be boron chloride (BC13), silicon chloride (SiCl4), or carbon tetrachloride (CC14); the fluorine-based gas can be carbon tetrafluoride (CF4), sulfur fluoride (SF6), nitrogen fluoride (NF3), or trifluoromethane (CHF3).

[0073] In the process of the synchronous etching, the gate dielectric material layer 20 and the gate material layer 30 are etched simultaneously, and the etching selectivity between the gate dielectric material layer 20 and the gate material layer 30 can be adjusted by adjusting the proportion and power of the etching gas through the etching machine, so as to accurately control the etching removal rate of the gate dielectric material layer 20 and the gate material layer 30. The etching selectivity can be used to represent the relative etching removal rate between the gate dielectric material layer 20 and the gate material layer 30 under the same etching condition. For example, if the gate dielectric material layer 20 has a high etching selectivity relative to the gate material layer 30, the etching removal rate of the gate dielectric material layer 20 is higher than that of the gate material layer 30. By synchronously etching the gate dielectric material layer 20 and the gate material layer 30 and controlling the etching removal rate of the gate dielectric material layer 20 and the gate material layer 30 through the etching machine, the height difference between the gate dielectric material layer 20 and the gate material layer 30 can be accurately controlled, that is, the height difference between the top surface of the gate dielectric layer 201 and the top surface of the shield gate 301 can be accurately controlled.

[0074] The method for manufacturing the semiconductor structure in the present embodiment includes: providing a substrate with a trench formed therein; forming a gate dielectric material layer on the bottom and sidewall of the trench and a gate material layer in the trench; synchronously etching the gate dielectric material layer and the gate material layer to obtain a gate dielectric layer on the bottom and sidewall of the trench and a shield gate in the trench with an arc-shaped top surface; the top surface of the shield gate is lower than the top surface of the trench, and the top surface of the gate dielectric layer is lower than the top surface of the shield gate. In the process of the synchronous etching, the etching removal rate of the gate dielectric material layer and the gate material layer can be accurately controlled by adjusting the proportion and power of the etching gas, so as to accurately make the height difference between the top surface of the gate dielectric layer and the top surface of the shield gate reach the target height difference, thereby improving the reliability of the SGT MOSFET.

[0075] In addition, in this embodiment, while the height difference between the top surface of the gate dielectric layer and the top surface of the shield gate reaches the target height difference, the smoothness of the top surface of the shield gate can also be adjusted by the control of the etching machine, so that the top surface of the shield gate forms an arc surface, thereby further ensuring the reliability of the SGT MOSFET device.

[0076] Please see Figure 8 In one embodiment, prior to step S103, the method may further include etching away a portion of the gate material layer 30 to create a height difference between the gate dielectric material layer 20 and the gate material layer 30.

[0077] In the actual fabrication process, after the previous fabrication process, there may be a certain height difference between the gate dielectric material layer 20 and the gate material layer 30, such as... Figure 8 As shown. However, it should be noted that this application still applies even when there is no height difference between the gate dielectric material layer 20 and the gate material layer 30.

[0078] Please see Figure 9 In one embodiment, while a gate dielectric material layer 20 is formed at the bottom and sidewalls of the trench 101, a gate dielectric material layer 20 is also formed on the upper surface of the substrate 10.

[0079] Please see Figure 10 Based on the above embodiments, optionally, in one embodiment, after forming the gate material layer 30 in the trench 101, a hard mask layer 40 may also be formed on the gate dielectric material layer 20 and the gate material layer 30 on the upper surface of the substrate 10.

[0080] The hard mask layer 40 can be one or a combination of titanium nitride (TiN), silicon nitride (SiN), and silicon dioxide (SiO2).

[0081] Please see Figure 11 Based on the above embodiments, optionally, in one embodiment, after forming the hard mask layer, a patterned photoresist layer 50 can be formed on the upper surface of the hard mask layer, and an opening 402 is formed by etching the hard mask layer 40 and the gate dielectric material layer 20 on the upper surface of the substrate 10 based on the patterned photoresist layer 50 to form a patterned hard mask layer 401; the opening 402 exposes the top of the gate material layer 30.

[0082] Please refer to the following: Figure 11 as well as Figure 8 Part of the gate material layer 30 can be etched away based on the opening 402 in the patterned hard mask layer 401, so that there is a height difference between the gate dielectric material layer 20 and the gate material layer 30.

[0083] In one embodiment, the step S103 can include: synchronously etching the gate dielectric material layer 20 and the gate material layer 30 by using a dry etching process, and in the synchronous etching process, the etching removal rate of the gate dielectric material layer 20 is greater than the etching removal rate of the gate material layer 30, so as to obtain the gate dielectric layer 201 located at the bottom and sidewall of the trench 101 and the shield gate 301 located in the trench 101 and having an arc-shaped top surface.

[0084] Based on the above embodiment, in one embodiment, in the process of synchronously etching the gate dielectric material layer 20 and the gate material layer 30 by using the dry etching process, the etching gas includes carbon-based gas, fluorine-based gas and oxygen, wherein the atomic ratio of carbon:fluorine is between 1:1 and 1:30, and the atomic ratio of carbon:oxygen is between 300:1 and 1:1; and the etching power is between 300 W and 8000 W.

[0085] Please refer to Figure 12 In one embodiment, the step S103 can further include the following steps:

[0086] S1201: synchronously etching the gate dielectric material layer and the gate material layer by using a dry etching process, and in the synchronous etching process, the etching removal rate of the gate dielectric material layer is the same as the etching removal rate of the gate material layer;

[0087] S1202: synchronously etching the gate dielectric material layer and the gate material layer after the first synchronous etching by using a dry etching process, and in the second synchronous etching process, the etching removal rate of the gate dielectric material layer is greater than the etching removal rate of the gate material layer, so as to modify the top surface of the gate material layer after the first synchronous etching to be an arc-shaped surface to obtain the shield gate, and obtain the gate dielectric layer.

[0088] In the step S1201, please refer to the step S1201 in Figure 12 , and Figure 13 synchronously etching the gate dielectric material layer 20 and the gate material layer 30 by using a dry etching process, and in the synchronous etching process, the etching removal rate of the gate dielectric material layer 20 is the same as the etching removal rate of the gate material layer 30.

[0089] In the step S1202, please refer to the step S1202 in Figure 12 , and Figure 7 synchronously etching the gate dielectric material layer 20 and the gate material layer 30 after the first synchronous etching by using a dry etching process, and in the second synchronous etching process, the etching removal rate of the gate dielectric material layer 20 is greater than the etching removal rate of the gate material layer 30, so as to modify the top surface of the gate material layer 30 after the first synchronous etching to be an arc-shaped surface to obtain the shield gate 301, and obtain the gate dielectric layer 201.

[0090] Since the etching removal rate of the gate dielectric material layer 20 is greater than that of the gate material layer 30 in the second synchronous etching process, the top corner position of the gate material layer 30 is gradually exposed. Since the dry etching is a biased isotropic etching, the corner is gradually etched by the etching gas in the dry etching and becomes smooth after the top corner of the gate material layer 30 is exposed, so as to finally form a circular arc top surface.

[0091] On the basis of the above embodiments, in one of the embodiments, in the first synchronous etching process in step S1201, the etching gas comprises carbon-based gas, fluorine-based gas and oxygen, wherein the atomic ratio of carbon:fluorine is between 1:1 and 1:25, and the atomic ratio of carbon:oxygen is between 250:1 and 1:1; the etching power is 500W-6000W; in the second synchronous etching process in step S1202, the etching gas comprises carbon-based gas, fluorine-based gas and oxygen, wherein the atomic ratio of carbon:fluorine is between 1:1 and 1:20, and the atomic ratio of carbon:oxygen is between 200:1 and 1:1; the etching power is 500W-6000W.

[0092] Please refer to Figure 14 In one embodiment, the above step S103 can further include the following steps:

[0093] S1401: using a dry etching process to perform first synchronous etching on the gate dielectric material layer and the gate material layer, wherein the etching removal rate of the gate dielectric material layer is greater than that of the gate material layer; the top surface of the gate dielectric material layer after the first synchronous etching is lower than that of the gate material layer after the first synchronous etching;

[0094] S1402: using a dry etching process to perform second synchronous etching on the gate dielectric material layer and the gate material layer after the first synchronous etching, wherein the etching removal rate of the gate material layer is greater than that of the gate dielectric material layer, so as to obtain the shielding gate and the gate dielectric layer.

[0095] In step S1401, please refer to the step S1401 in Figure 14 and Figure 15 , using a dry etching process to perform first synchronous etching on the gate dielectric material layer 20 and the gate material layer 30, wherein the etching removal rate of the gate dielectric material layer 20 is greater than that of the gate material layer 30; the top surface of the gate dielectric material layer 20 after the first synchronous etching is lower than that of the gate material layer 30 after the first synchronous etching.

[0096] In step S1402, please refer toFigure 14 S1402, and Figure 7 In the second synchronous etching process, the etching removal rate of the gate material layer 30 is greater than that of the gate dielectric material layer 20, so as to obtain the shielding gate 301 and the gate dielectric layer 201 with arc-shaped top surface.

[0097] Since the etching removal rate of the gate dielectric material layer 20 is greater than that of the gate material layer 30 in the first synchronous etching process, the top corner position of the gate material layer 30 is gradually exposed (as shown in Figure 15 Since the dry etching is a partial isotropic etching, when the top corner of the gate material layer 30 is exposed, the corner will be gradually etched by the etching gas in the dry etching and become smooth, so as to finally form the arc-shaped top surface.

[0098] In one of the above embodiments, in the first synchronous etching process in step S1401, the etching gas includes carbon-based gas, fluorine-based gas and oxygen, wherein the atomic ratio of carbon:fluorine is between 1:1 and 1:12, and the atomic ratio of carbon:oxygen is between 150:1 and 1:1; the etching power is 800W-7000W; in the second synchronous etching process in step S1402, the etching gas includes carbon-based gas, fluorine-based gas and oxygen, wherein the atomic ratio of carbon:fluorine is between 1:1 and 1:15, and the atomic ratio of carbon:oxygen is between 180:1 and 1:1; the etching power is 800W-7000W.

[0099] Please refer to Figure 16 In one embodiment, the above step S103 can further include the following steps:

[0100] S1601: using a dry etching process to perform first synchronous etching on the gate dielectric material layer and the gate material layer, wherein the etching removal rate of the gate material layer is greater than that of the gate dielectric material layer; after the first synchronous etching, the top surface of the remaining gate material layer is lower than that of the remaining gate dielectric material layer;

[0101] S1602: using a dry etching process to perform second synchronous etching on the gate dielectric material layer and the gate material layer after the first synchronous etching, wherein the etching removal rate of the gate dielectric material layer is greater than that of the gate material layer, so as to obtain the gate dielectric layer, and the top surface of the gate dielectric layer is lower than that of the gate material layer after the second synchronous etching;

[0102] S1603: Repairing the top surface of the gate material layer after the second time of synchronous etching to obtain a shielding gate with an arc-shaped top surface.

[0103] In step S1601, refer to step S1601 in Figure 16 and Figure 17 , a first time of synchronous etching is performed on the gate dielectric material layer 20 and the gate material layer 30 by using a dry etching process, in which the etching removal rate of the gate material layer 30 is greater than that of the gate dielectric material layer 20; after the first time of synchronous etching, the top surface of the remaining gate material layer 30 is lower than that of the remaining gate dielectric material layer 20.

[0104] In step S1602, refer to step S1602 in Figure 16 and Figure 18 , a second time of synchronous etching is performed on the gate dielectric material layer 20 and the gate material layer 30 after the first time of synchronous etching by using a dry etching process, in which the etching removal rate of the gate dielectric material layer 20 is greater than that of the gate material layer 30 to obtain a gate dielectric layer 201, and the top surface of the gate dielectric layer 201 is lower than that of the gate material layer 30 after the second time of synchronous etching.

[0105] In step S1603, refer to step S1603 in Figure 16 and Figure 7 , the top surface of the gate material layer 30 after the second time of synchronous etching is repaired to obtain a shielding gate 301 with an arc-shaped top surface.

[0106] In this embodiment, in the first time of synchronous etching, the top corner position of the gate material layer 30 is not exposed (as shown in Figure 17 , and in the second time of synchronous etching, the top corner position of the gate material layer 30 is exposed, but it is not easy to form an arc-shaped top surface due to insufficient etching time (as shown in Figure 18 ). Therefore, in this embodiment, the etching gas and etching power and other parameters are adjusted in step S1603 to adjust the top surface of the gate material layer 30 to be arc-shaped by etching, so that the top surface of the gate material layer 30 can be repaired to obtain a shielding gate 301 with an arc-shaped top surface.

[0107] On the basis of the above-mentioned embodiments, in one of the embodiments, in the first time synchronous etching process in step S1601, the etching gas comprises carbon-based gas, fluorine-based gas and oxygen, wherein the atomic ratio of carbon:fluorine is between 1:1-1:18, and the atomic ratio of carbon:oxygen is between 120:1-1:1; the etching power is 500W-5000W; in the second time synchronous etching process in step S1602, the etching gas comprises carbon-based gas, fluorine-based gas and oxygen, wherein the atomic ratio of carbon:fluorine is between 1:1-1:12, and the atomic ratio of carbon:oxygen is between 100:1-1:1; the etching power is 500W-5000W.

[0108] In the description of the present specification, the description referring to the terms "some embodiments", "other embodiments", "ideal embodiments", and the like means that the specific features, structures, materials or characteristics described in connection with the embodiments or examples are contained in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above-mentioned terms does not necessarily refer to the same embodiment or example.

[0109] The technical features of the above-mentioned embodiments can be combined arbitrarily, and in order to make the description simple, all possible combinations of the technical features of the above-mentioned embodiments are not described, however, as long as the combination of the technical features does not exist contradictory, it should be considered as the scope of the present application.

[0110] The above-mentioned embodiments only express several implementation manners of the present application, and the description is more specific and detailed, but it should not be understood as a limitation to the patent scope of the application. It should be pointed out that for ordinary skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are all within the protection scope of the present application. Therefore, the patent protection scope of the present application should be subject to the appended claims.

Claims

1. A method of fabricating a semiconductor structure, characterized by, The method comprises the following steps: providing a substrate, a trench is formed in the substrate; forming a gate dielectric material layer on the bottom and sidewall of the trench, and forming a gate material layer in the trench; performing first synchronous etching on the gate dielectric material layer and the gate material layer by using dry etching process, and the etching removal rate of the gate dielectric material layer is the same as that of the gate material layer during the first synchronous etching; performing second synchronous etching on the gate dielectric material layer and the gate material layer after the first synchronous etching by using dry etching process, and the etching removal rate of the gate dielectric material layer is greater than that of the gate material layer during the second synchronous etching, so as to modify the top surface of the gate material layer after the first synchronous etching into an arc surface to obtain a shielding gate and a gate dielectric layer; the top surface of the shielding gate is lower than the top surface of the trench, and the top surface of the gate dielectric layer is lower than the top surface of the shielding gate.

2. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: The method for synchronously etching the gate dielectric material layer and the gate material layer to obtain the gate dielectric layer located on the bottom and sidewall of the trench and the shielding gate with an arc top surface in the trench comprises the following steps: synchronously etching the gate dielectric material layer and the gate material layer by using dry etching process, and the etching removal rate of the gate dielectric material layer is greater than that of the gate material layer during the synchronous etching, so as to obtain the gate dielectric layer located on the bottom and sidewall of the trench and the shielding gate with an arc top surface in the trench.

3. The method of claim 2, wherein the semiconductor structure is prepared by a method comprising: During the process of synchronously etching the gate dielectric material layer and the gate material layer by using dry etching process, the etching gas comprises carbon-based gas, fluorine-based gas and oxygen, wherein the atomic ratio of carbon to fluorine is between 1:1 and 1:30, and the atomic ratio of carbon to oxygen is between 300:1 and 1:1; the etching power is between 300 W and 8000 W.

4. The method for preparing the semiconductor structure according to claim 1, wherein during the first synchronous etching, the etching gas comprises carbon-based gas, fluorine-based gas and oxygen, wherein the atomic ratio of carbon to fluorine is between 1:1 and 1:25, and the atomic ratio of carbon to oxygen is between 250:1 and 1:1; the etching power is between 500 W and 6000 W; during the second synchronous etching, the etching gas comprises carbon-based gas, fluorine-based gas and oxygen, wherein the atomic ratio of carbon to fluorine is between 1:1 and 1:20, and the atomic ratio of carbon to oxygen is between 200:1 and 1:1; the etching power is between 500 W and 6000 W.

5. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: The method for synchronously etching the gate dielectric material layer and the gate material layer to obtain the gate dielectric layer located on the bottom and sidewall of the trench and the shielding gate with an arc top surface in the trench comprises the following steps: The dry etching process is used to perform first synchronous etching on the gate medium material layer and the gate material layer, and in the first synchronous etching process, the etching removal rate of the gate medium material layer is greater than that of the gate material layer; and the top surface of the gate medium material layer after the first synchronous etching is lower than that of the gate material layer after the first synchronous etching; The dry etching process is used to perform second synchronous etching on the gate medium material layer and the gate material layer after the first synchronous etching, and in the second synchronous etching process, the etching removal rate of the gate material layer is greater than that of the gate medium material layer, so as to obtain the shielding gate and the gate medium layer with the arc-shaped top surface.

6. The method of claim 5, wherein, in the first synchronous etching process, the etching gas comprises carbon-based gas, fluorine-based gas and oxygen, wherein the atomic ratio of carbon to fluorine is between 1:1 and 1:12, and the atomic ratio of carbon to oxygen is between 150:1 and 1:1; and the etching power is between 800 W and 7000 W; in the second synchronous etching process, the etching gas comprises carbon-based gas, fluorine-based gas and oxygen, wherein the atomic ratio of carbon to fluorine is between 1:1 and 1:15, and the atomic ratio of carbon to oxygen is between 180:1 and 1:1; and the etching power is between 800 W and 7000 W.

7. The method of claim 1, wherein the semiconductor structure is formed by a method comprising: The gate medium material layer and the gate material layer are synchronously etched to obtain the gate medium layer located at the bottom and the sidewall of the trench and the shielding gate located in the trench and having the arc-shaped top surface, and the method comprises: The dry etching process is used to perform first synchronous etching on the gate medium material layer and the gate material layer, and in the first synchronous etching process, the etching removal rate of the gate material layer is greater than that of the gate medium material layer; and the top surface of the remaining gate material layer is lower than that of the remaining gate medium material layer after the first synchronous etching; The dry etching process is used to perform second synchronous etching on the gate medium material layer and the gate material layer after the first synchronous etching, and in the second synchronous etching process, the etching removal rate of the gate medium material layer is greater than that of the gate material layer, so as to obtain the gate medium layer, and the top surface of the gate medium layer is lower than that of the gate material layer after the second synchronous etching; The top surface of the gate material layer after the second synchronous etching is repaired to obtain the shielding gate with the arc-shaped top surface.

8. The method of claim 7, wherein, in the first synchronous etching process, the etching gas comprises carbon-based gas, fluorine-based gas and oxygen, wherein the atomic ratio of carbon to fluorine is between 1:1 and 1:18, and the atomic ratio of carbon to oxygen is between 120:1 and 1:1; and the etching power is between 500 W and 5000 W; The second synchronous etching process includes carbon-based gas, fluorine-based gas and oxygen, wherein the atomic ratio of carbon to fluorine is between 1:1 and 1:12, and the atomic ratio of carbon to oxygen is between 100:1 and 1:1; and the etching power is between 500W and 5000W.

9. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: Before the synchronous etching of the gate medium material layer and the gate material layer, the method further includes: The gate material layer is etched to remove a part of the gate material layer, so that the gate medium material layer and the gate material layer have a height difference.

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