A semiconductor device and a method of fabricating the same

Abstract

This application provides a semiconductor device and its fabrication method. The device includes: a second substrate; a void layer located on one side of the second substrate; a nanosheet stack layer located on the side of the void layer away from the second substrate; the nanosheet stack layer comprises a stack of multiple nanosheets; the nanosheets are formed of a semiconductor material; the nanosheet stack layer constitutes multiple conductive channels; a surrounding gate surrounds the nanosheet stack layer; and source and drain electrodes located at both ends of the nanosheet stack layer; the source and drain electrodes are made of semiconductor materials doped with conductive elements. Therefore, by setting the void layer, this application can avoid the influence of the bottom parasitic channel effect, thereby reducing the influence of leakage current and gate capacitance, and further improving the electrical performance of the device. It can effectively solve the influence of the self-heating effect in the stacked nanosheets. It effectively reduces the drain-induced barrier reduction effect and improves parameters such as subthreshold slope and on / off ratio.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor device and its fabrication method. Background Technology

[0002] As transistor feature sizes continue to shrink, new materials, processes, and structures are constantly being introduced to improve device performance while reducing the impact of short-channel effects caused by size reduction. Device structures have evolved from two-dimensional planar CMOS (Complementary Metal Oxide Semiconductor) devices to three-dimensional FinFET (Fin Field-Effect Transistor) structures, and now to the mainstream Nanowire / Nanosheet gate-around transistors.

[0003] Gate-around transistors (GOT) are considered one of the most promising next-generation devices to replace FinFETs and achieve mass production at the 3nm technology node. GOT devices effectively increase the Weff (effective gate width) / footprint (package size), improve the gate's control over the channel, effectively suppress short-channel effects, and enhance the device's current drive capability.

[0004] Currently, research progress on Nanosheet-GAAFET (Nanosheet-Gate-all-around Field-Effect Transistor) has attracted widespread attention from academia and industry. Continuous optimization of process flows and key processes, along with the exploration of new structures based on this architecture, are also popular research directions for novel CMOS devices.

[0005] Nanosheet-GAAFETs can improve device performance by stacking more nanosheets. This novel device structure is highly compatible with current mainstream FinFET processes. However, both NSFETs (Nanosheet Field-Effect Transistors) and FinFETs inevitably have parasitic channels beneath their intrinsic channels. These parasitic channels contain parasitic capacitance and leakage current, causing degradation in the device's electrical performance and posing significant challenges to transistor scaling. Because NSFETs have wider parasitic channels, their impact is more pronounced. Therefore, mitigating the effects of parasitic channels becomes a critical issue. Summary of the Invention

[0006] In view of this, the purpose of this application is to provide a device that can avoid the effects of bottom parasitic channel effects, thereby reducing the effects of leakage current and gate capacitance, and further improving the electrical performance of the device.

[0007] To achieve the above objectives, this application provides the following technical solution:

[0008] In a first aspect, embodiments of this application provide a method for fabricating a semiconductor device, comprising:

[0009] Provide initial substrate;

[0010] An inert gas is injected into the initial substrate, and an annealing process is performed to form a void layer, thereby dividing the initial substrate into a first part substrate and a second part substrate.

[0011] On the surface of the first portion of the substrate that is opposite to the void layer and away from the void layer, a superlattice stack is epitaxially grown; the superlattice stack is formed by alternating layers of a first semiconductor layer and a second semiconductor layer.

[0012] The superlattice stack is etched to form multiple fins;

[0013] Deposit dummy gates on the fins;

[0014] The two ends of the fin are etched to the surface of the initial substrate. After etching, source and drain electrodes are epitaxially grown at both ends of the fin. The material of the source and drain electrodes is a semiconductor material doped with conductive elements.

[0015] The dummy gate is removed, the first semiconductor layer is etched away, and the channel of the second semiconductor layer nanosheet is released. The stack of nanosheets forms multiple conductive channels.

[0016] A surrounding gate is formed, encircling the nanosheet stack;

[0017] The first portion of the substrate is removed by etching.

[0018] In one possible implementation, the etching to remove the first portion of the substrate includes:

[0019] At least one etched via is formed to connect with the void layer, and the first portion of the substrate is removed by etching through the etched via.

[0020] In one possible implementation, the etching to remove the first portion of the substrate includes:

[0021] The first portion of the substrate is removed by wet etching.

[0022] In one possible implementation, after etching away the first portion of the substrate, the method further includes:

[0023] The first portion of the substrate and the void layer are filled with a gaseous and / or liquid medium whose dielectric constant is less than or equal to a preset threshold.

[0024] In one possible implementation, the etching of the superlattice stack to form a plurality of fins includes:

[0025] A first sidewall is formed on the superlattice stack; the superlattice stack is etched using the first sidewall as a mask to form the plurality of fins.

[0026] Secondly, embodiments of this application provide a semiconductor device, including:

[0027] Second part: substrate;

[0028] A void layer located on one side of the second portion of the substrate;

[0029] A stacked layer of nanosheets is located on the side of the void layer away from the second portion of the substrate; the stacked layer of nanosheets comprises a stack of multiple nanosheets; the nanosheets are formed of a semiconductor material; the stack of nanosheets forms a plurality of conductive channels;

[0030] A surrounding gate around the nanosheet stack;

[0031] The source and drain electrodes are located at both ends of the nanosheet stack; the source and drain electrodes are made of semiconductor materials doped with conductive elements.

[0032] In one possible implementation, it further includes shallow trench isolation located between the void layer and the all-around gate.

[0033] In one possible implementation, it further includes an isolation layer located on the side of the source / drain electrode away from the void layer.

[0034] In one possible implementation, a second sidewall is also included between the isolation layer and the all-around gate.

[0035] In one possible implementation, the device type includes: a positive-channel nanosheet-around-gate field-effect transistor or a negative-channel nanosheet-around-gate field-effect transistor.

[0036] Compared with the prior art, this application has the following beneficial effects:

[0037] This application provides a semiconductor device and its fabrication method. The device includes: a second substrate; a void layer located on one side of the second substrate; a nanosheet stacked layer located on the side of the void layer away from the second substrate; the nanosheet stacked layer comprises a stack of multiple nanosheets; the nanosheets are formed of a semiconductor material; the nanosheet stacks constitute multiple conductive channels; a surrounding gate surrounds the nanosheet stacked layer; and source and drain electrodes located at both ends of the nanosheet stacked layer; the source and drain electrodes are made of semiconductor materials doped with conductive elements. Therefore, by setting the void layer, this application can avoid the influence of the bottom parasitic channel effect, thereby reducing the influence of leakage current and gate capacitance, and further improving the electrical performance of the device. It can effectively solve the influence of the self-heating effect in the stacked nanosheets. It effectively reduces the drain-induced barrier reduction effect and improves parameters such as subthreshold slope and on / off ratio. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 A flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this application is shown;

[0040] Figure 2-13 Cross-sectional views of various structures during the fabrication process of a semiconductor device according to an embodiment of this application are shown;

[0041] Figure 14 A cross-sectional view of a semiconductor device provided in an embodiment of this application is shown;

[0042] Figure 15 A top view of a semiconductor device provided in an embodiment of this application is shown. Detailed Implementation

[0043] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the specific embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0044] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0045] As described in the background section, with the continuous miniaturization of transistor feature sizes, new materials, processes, and structures are constantly introduced to improve device performance while reducing the impact of short-channel effects caused by size reduction. Device structures have evolved from two-dimensional planar CMOS (Complementary Metal Oxide Semiconductor) devices to three-dimensional FinFET (Fin Field-Effect Transistor) structures, and now to the mainstream Nanowire / Nanosheet gate-around transistors.

[0046] Gate-around transistors (GOT) are considered one of the most promising next-generation devices to replace FinFETs and achieve mass production at the 3nm technology node. GOT devices effectively increase the Weff (effective gate width) / footprint (package size), improve the gate's control over the channel, effectively suppress short-channel effects, and enhance the device's current drive capability.

[0047] Currently, research progress on Nanosheet-GAAFET (Nanosheet-Gate-all-around Field-Effect Transistor) has attracted widespread attention from academia and industry. Continuous optimization of process flows and key processes, along with the exploration of new structures based on this architecture, are also popular research directions for novel CMOS devices.

[0048] Nanosheet-GAAFETs can improve device performance by stacking more nanosheets. This novel device structure is highly compatible with current mainstream FinFET processes. However, both NSFETs (Nanosheet Field-Effect Transistors) and FinFETs inevitably have parasitic channels beneath their intrinsic channels. These parasitic channels contain parasitic capacitance and leakage current, causing degradation in the device's electrical performance and posing significant challenges to transistor scaling. Because NSFETs have wider parasitic channels, their impact is more pronounced. Therefore, mitigating the effects of parasitic channels becomes a critical issue.

[0049] In addition, how to effectively reduce the leakage-induced barrier reduction effect and improve parameters such as subthreshold slope and on / off ratio are also technical problems that need to be solved in this field.

[0050] To address the above technical problems, this application provides a semiconductor device and its fabrication method. The device includes: a second substrate; a void layer located on one side of the second substrate; a nanosheet stack layer located on the side of the void layer away from the second substrate; the nanosheet stack layer comprises a stack of multiple nanosheets; the nanosheets are formed of a semiconductor material; the nanosheet stack forms multiple conductive channels; a surrounding gate surrounds the nanosheet stack layer; and source and drain electrodes located at both ends of the nanosheet stack layer; the source and drain electrodes are made of semiconductor materials doped with conductive elements. Therefore, by setting the void layer, this application can avoid the influence of the bottom parasitic channel effect, thereby reducing the impact of leakage current and gate capacitance, and further improving the electrical performance of the device. It effectively solves the problem of the self-heating effect in the stacked nanosheets. It effectively reduces the drain-induced barrier reduction effect and improves parameters such as subthreshold slope and on / off ratio.

[0051] See Figure 1 The diagram shown is a flowchart of a method for fabricating a semiconductor device according to an embodiment of this application, including:

[0052] S101: Provides the initial substrate.

[0053] In the embodiments of this application, see Figure 2 As shown, an initial substrate 0 can be prepared first. The initial substrate 0 can be a semiconductor substrate, such as a Si substrate, a Ge substrate, a SiGe substrate, SOI (Silicon On Insulator), or GOI (Germanium On Insulator). In other embodiments, the semiconductor substrate can also be a substrate including other elemental semiconductors or compound semiconductors, such as GaAs, InP, or SiC, and can also be a stacked structure, such as Si / SiGe, or other epitaxial structures, such as SGOI (Silicon Germanium On Insulator). In this embodiment, the initial substrate 0 is a bulk silicon substrate.

[0054] Specifically, the initial substrate 0 is a portion of a semiconductor wafer suitable for forming one or more semiconductor devices. When a bulk silicon substrate is used, a highly doped well region is formed in the bulk silicon substrate through impurity implantation, diffusion, and annealing to achieve the required well depth. For P (positive) type FETs, the aforementioned highly doped well region is an N-well, and the implanted impurity is an n-type impurity ion, such as phosphorus (P) ions; for N (negative) type FETs, the aforementioned highly doped well region is a P-well, and the implanted impurity is a p-type impurity ion, such as boron (B) ions.

[0055] S102: Inert gas is injected into the initial substrate, and annealing is performed to form a void layer, so as to divide the initial substrate into a first part substrate and a second part substrate.

[0056] In the embodiments of this application, see Figure 3 As shown, an inert gas, such as ammonia, can be injected into the initial substrate and annealed in a high-temperature inert gas environment to form a void layer 1, thereby dividing the initial substrate into a first part substrate 0' and a second part substrate 0.

[0057] A silicon dioxide layer 11 is grown on the surface of the first part of the substrate 0'.

[0058] S103: On the surface of the first portion of the substrate that is opposite to the void layer and away from the void layer, a superlattice stack is epitaxially grown; the superlattice stack is formed by alternating layers of a first semiconductor layer and a second semiconductor layer.

[0059] In the embodiments of this application, see Figure 4 As shown, silicon dioxide (SiO2) is removed from the surface of the first part of the substrate 0', and a superlattice structure of multiple periods of first semiconductor layer 51 / second semiconductor layer 52 is epitaxially grown on the first part of the substrate 0'. The thickness of the first semiconductor layer 51 in the superlattice structure can be set to 3-100nm, and the thickness of the second semiconductor layer 52 can be set to 1-50nm. The final thickness will directly determine the height of the nanosheet channel and the electrostatic properties.

[0060] The superlattice of the first semiconductor layer 51 / second semiconductor layer 52 can be a Si / SiGe stack, a SiGe / Si stack, a SiGe / Ge stack, a Ge / SiGe stack, a Si / Ge stack, or a Ge / Si stack.

[0061] S104: Etch the superlattice stack to form multiple fins.

[0062] In the embodiments of this application, see Figure 5 As shown, in one possible implementation, a first sidewall 61 can be formed on the superlattice stack; the superlattice stack can be etched using the first sidewall 61 as a mask to form multiple fins.

[0063] Specifically, a self-aligned sidewall transfer (SIT) process can be used to form a nanoscale first sidewall 61 device. The material of the first sidewall 61 can be silicon nitride (SiNx). The specific formation process is as follows: a sacrificial layer 62 is deposited on the superlattice stack. The sacrificial layer can be polycrystalline silicon (p-si) or amorphous silicon (a-si). Part of the sacrificial layer 62 is etched away, and a silicon nitride (SiNx) layer is deposited. Then, anisotropic etching is used to etch away the remaining sacrificial layer 62, so that only multiple periodic silicon nitride (SiNx) first sidewalls (spacers) 61 remain on the superlattice stack. The silicon nitride (SiNx) first sidewall 61 acts as a hard mask in photolithography.

[0064] See Figure 6 As shown, the epitaxially grown superlattice stack can be made into multiple periodically distributed fins through etching.

[0065] Specifically, etching is performed using the first sidewall 61 as a mask to form a fin with a superlattice stacked structure. The upper part of the fin is the conductive channel region formed by the superlattice stack, and the lower part is the first part of the substrate 0', forming a structure as shown in the image. Figure 6 The fins shown.

[0066] The fin comprises not only a superlattice stacked structure but also a single-crystal silicon structure extending into the substrate. The etching process can be dry etching, and in one embodiment, reactive ion etching (RIE) can be used. The fin will be used to form horizontal nanosheets of one or more n-type and / or p-type field-effect transistors.

[0067] It should be noted that, although Figure 6 A fin is shown, and it should be understood that any suitable number and shape of fins can be used in the embodiments of this application. The height of the fin is approximately 10nm-400nm, and the width is approximately 1-100nm.

[0068] like Figure 7 As shown, the first sidewall 61 is etched away, and then a shallow trench isolation (STI) region 7 can be formed between two adjacent fins. First, a dielectric insulating material is deposited, then planarized, for example using a CMP (chemical mechanical polishing) process, and then the dielectric insulating material is selectively etched back to expose the three-dimensional fin structure, thereby forming the shallow trench isolation region 7 adjacent to the fin.

[0069] The upper surface of the shallow trench isolation region 7 is generally flush with the interface between the superlattice stacked structure in the fin and the substrate single-crystal silicon, but may be higher or lower than this interface level. The shallow trench isolation region 7 can be formed of a suitable dielectric material, such as silicon dioxide (SiO2) or silicon nitride (SiNx). The function of the shallow trench isolation region 7 is to separate transistors on adjacent fins. The shallow trench isolation region 7 exposes the first semiconductor layer 51, the bottommost layer of the superlattice stack.

[0070] S105: Deposit a false gate on the fin.

[0071] In the embodiments of this application, see Figure 8 As shown, dummy gates 8 can be formed on the exposed fins in a direction perpendicular to the fin lines (i.e., the B-B' direction). These dummy gates 8 can be formed using processes such as thermal oxidation, chemical vapor deposition, and sputtering. The dummy gates 8 span the superlattice stack above the fins, and multiple dummy gates 8 are periodically distributed along the fin line direction.

[0072] The material used for the dummy gate 8 can be polysilicon (p-si) or amorphous silicon (a-si).

[0073] S106: Etch the two ends of the fin to the surface of the initial substrate, and epitaxially grow source and drain electrodes at both ends of the fin after etching. The material of the source and drain electrodes is a semiconductor material doped with conductive elements.

[0074] In the embodiments of this application, see Figure 9 As shown, silicon nitride or silicon oxide material can be deposited on both sides of each dummy gate 8 and etched to form a second sidewall 9.

[0075] Then, see Figure 10 As shown, the two ends of the fin can be etched to the surface of the initial substrate. After etching, source and drain electrodes 41 / 42 are epitaxially grown at both ends of the fin. The material of the source and drain electrodes 41 / 42 is a semiconductor material doped with conductive elements.

[0076] Specifically, semiconductor materials such as SiGe or Si can be deposited and heavily doped. For P-type semiconductor devices, the doping element is B or BF2, and for N-type semiconductor devices, the doping element is P / As, forming heavily doped source / drain electrodes 41 / 42. The source / drain electrodes 41 / 42 are then activated by low-temperature rapid thermal annealing.

[0077] S107: Remove the dummy gate, etch away the first semiconductor layer, and realize the channel release of the second semiconductor layer nanosheets. The stack of nanosheets forms multiple conductive channels.

[0078] In the embodiments of this application, see Figure 11As shown, an isolation layer 10 can be deposited on the source / drain electrodes 41 / 42, and the material of the isolation layer 10 can be an oxide such as silicon dioxide.

[0079] Then, through selective etching or etching processes, the aforementioned polycrystalline silicon (P-Si) or amorphous silicon is transformed.

[0080] The dummy gate 8 formed by silicon (a-Si) is etched or corroded away, that is, the dummy gate 8 is removed.

[0081] Subsequently, as Figure 12 The first semiconductor layer 51 in the superlattice stack is selectively etched to release the nanosheet 2 channel. The conductive channel region exposed by the fins is etched / etched to remove each first semiconductor layer 51, which serves as a sacrificial layer, to release the nanosheet 2 formed by the second semiconductor layer.

[0082] The width of the nanosheet 2 ranges from 1 to 100 nm, the thickness ranges from 1 to 50 nm, and the spacing between each nanosheet 2 ranges from 3 to 100 nm.

[0083] In one embodiment, for both P-type and N-type FETs, the sacrificial layer is a SiGe layer. The SiGe layer is selectively removed, leaving the Si layer, to form a Si horizontal stacked nanosheet device. The selective removal process can use an etchant that selectively etches SiGe at a faster rate relative to Si. In one embodiment, a conventional wet process isotropically etches the sacrificial layer to release the nanosheet channel, thereby forming a nanosheet conductive channel.

[0084] In another embodiment, channel release is performed separately for P-type and N-type FETs.

[0085] For P-type FETs, the sacrificial layer is a Si layer. The Si layer is selectively removed, leaving a SiGe layer, forming a SiGe horizontal stacked nanosheet device. In the selective removal process, an etchant that selectively etches Si at a faster rate than SiGe can be used. In one embodiment, a conventional wet process isotropically etches the sacrificial layer to release the nanosheet channel, thereby forming a nanosheet conductive channel.

[0086] For N-type FETs, the sacrificial layer is a SiGe layer. The SiGe layer is selectively removed, leaving the Si layer, forming a Si horizontal stacked nanosheet device. In the selective removal process, an etchant that selectively etches SiGe at a faster rate relative to Si can be used. In one embodiment, a conventional wet process isotropically etches the sacrificial layer to release the nanosheet channel, thereby forming a nanosheet conductive channel. A second semiconductor nanosheet is then stacked, forming the nanosheet stack.

[0087] Next, as Figure 12As shown, a high-k dielectric layer 12 is deposited such that the high-k dielectric layer 12 surrounds the surface of the nanosheet stack and covers the surface of the second sidewall 9. The high-k dielectric layer 12 may have a dielectric constant higher than about 6.0, and the material of the high-k dielectric layer 12 may be one or a combination of several of HfO2, HfSiOx, HfON, HfSiON, HfAlOx, HfLaOx, Al2O3, ZrO2, ZrSiOx, Ta2O5, or La2O3.

[0088] S108: Forms a surround gate that surrounds the nanosheet stack.

[0089] In the embodiments of this application, see Figure 13 As shown, a metal gate 3 is deposited outside the high-K dielectric layer 12 in the space formed by the dummy gate 8, forming a multilayer high-K / metal gate structure.

[0090] The metal gate 3 comprises a multilayer structure consisting of a capping layer, a barrier layer, a work function layer, and a filler layer. Different effective work functions can be formed by selecting photolithography and etching techniques to control the device threshold. The metal gate 3 is typically formed using processes such as chemical vapor deposition (CVD) and physical vapor deposition (PVD).

[0091] The metal gate 3 material is one or a combination of several of the following: TaC, TaN, TiN, TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTax, NiTax, MoNx, TiSiN, TiCN, TaAlC, TiAl, TiAlC, TiAlN, PtSix, Ni3Si, Pt, Ru, Ir, Mo, Ti, Al, W, Co, Cr, Au, Cu, Ag, HfRu, or RuOx.

[0092] like Figure 13 As shown, the metal gate 3 fills the space left by the removal of the dummy gate 8. Subsequently, the high-k dielectric layer 12 and the metal gate 3 structure are chemically and mechanically polished to planarize them, and excess high-k dielectric layer 12 and metal gate 3 material exposed outside the space of the dummy gate 8 is removed. The high-k dielectric layer 12 and the metal gate 3 fill the space of the original first semiconductor layer 51 to form a ring gate structure, i.e., a surround gate, which surrounds the nanosheet 2.

[0093] S109: Etch away the first portion of the substrate.

[0094] In the embodiments of this application, see Figure 15 The image shown is a top view of a semiconductor device provided in an embodiment of this application, including a device region, a wet-etched Si substrate region, etched vias, and the Si substrate region.

[0095] A-A' is the centerline of the fin along the fin line, and B-B' is the centerline of the fin perpendicular to the fin line. Figure 2-14 These are all cross-sectional schematic diagrams using lines A-A' and B-B'.

[0096] See Figure 14 As shown, at least one etchable via connected to the void layer can be formed by etching, and the first portion of the substrate can be removed by etching the via. Optionally, the first portion of the substrate can be removed by wet etching.

[0097] For example, by adjusting the etching selectivity ratio of the Si substrate to SiGe and SiO2, wet etching can be used to selectively remove the bulk silicon material, i.e., the first part of the substrate. That is, by increasing the etching pattern to form etched vias from top to bottom, wet etching is then used to selectively remove the sub-fin parasitic channels and the bulk silicon material under the STI.

[0098] This application embodiment accelerates the selective removal speed of wet etching by adding a SON (silicon on nothing) substrate structure. The thickness of the removed bulk silicon material can be controlled by adjusting the wet etching time and rate.

[0099] Optionally, after etching away the first portion of the substrate, the method further includes:

[0100] Filling the first part of the substrate and the void layer with a gas and / or liquid medium with a dielectric constant less than or equal to a preset threshold can effectively solve the influence of self-heating effect in stacked nanosheets.

[0101] This application embodiment combines conventional Nanasheet-GAAFET fabrication methods on a SON substrate, forming a SON substrate structure to reduce the impact of bottom parasitic channel effects, thereby increasing the electrical performance of the device.

[0102] This application provides a method for fabricating a semiconductor device. The device fabricated using this method includes: a second substrate; a void layer located on one side of the second substrate; a nanosheet stack layer located on the side of the void layer away from the second substrate; the nanosheet stack layer comprises a stack of multiple nanosheets; the nanosheets are formed of a semiconductor material; the nanosheet stack layer constitutes multiple conductive channels; a surrounding gate surrounds the nanosheet stack layer; and source and drain electrodes located at both ends of the nanosheet stack layer; the source and drain electrodes are made of semiconductor materials doped with conductive elements. Therefore, by setting the void layer, this application can avoid the influence of the bottom parasitic channel effect, thereby reducing the influence of leakage current and gate capacitance, and further improving the electrical performance of the device. It can effectively solve the influence of the self-heating effect in the stacked nanosheets. It effectively reduces the drain-induced barrier reduction effect and improves parameters such as subthreshold slope and on / off ratio.

[0103] Exemplary devices

[0104] See Figure 14 The diagram shown is a schematic representation of a semiconductor device provided in an embodiment of this application, comprising:

[0105] Second part, substrate 0”;

[0106] The void layer 1 is located on one side of the second portion of the substrate 0”;

[0107] A stacked layer of nanosheets is located on the side of the void layer 1 away from the second portion of the substrate 0”; the stacked layer of nanosheets includes a stack of multiple nanosheets 2; the nanosheets 2 are formed of semiconductor material; the stack of nanosheets 2 forms multiple conductive channels;

[0108] A surrounding gate 3 around the stacked layer of nanosheets 2;

[0109] The source / drain electrodes 41 / 42 are located at both ends of the nanosheet stacked layer; the material of the source / drain electrodes 41 / 42 is a semiconductor material doped with conductive elements.

[0110] In one possible implementation, it further includes a shallow trench isolation 7 located between the void layer 1 and the all-around gate 3.

[0111] In one possible implementation, it further includes an isolation layer 10 located on the side of the source / drain electrodes 41 / 42 away from the void layer 1.

[0112] In one possible implementation, a second sidewall 9 is also included, located between the isolation layer 10 and the surrounding gate 3.

[0113] In one possible implementation, the device type includes: a positive-channel nanosheet-around-gate field-effect transistor or a negative-channel nanosheet-around-gate field-effect transistor.

[0114] This application provides a semiconductor device comprising: a second substrate; a void layer located on one side of the second substrate; a nanosheet stack layer located on the side of the void layer away from the second substrate; the nanosheet stack layer comprising a stack of multiple nanosheets; the nanosheets being formed of a semiconductor material; the nanosheet stack forming multiple conductive channels; a surrounding gate around the nanosheet stack layer; and source and drain electrodes located at both ends of the nanosheet stack layer; the source and drain electrodes being made of a semiconductor material doped with conductive elements. Thus, by setting the void layer, this application can avoid the influence of the bottom parasitic channel effect, thereby reducing the influence of leakage current and gate capacitance, and further improving the electrical performance of the device. It can effectively solve the influence of the self-heating effect in the stacked nanosheets. It effectively reduces the drain-induced barrier reduction effect and improves parameters such as subthreshold slope and on / off ratio.

[0115] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on its differences from other embodiments. In particular, the device embodiments are basically similar to the method embodiments, so they are described more simply; relevant parts can be referred to the descriptions in the method embodiments.

[0116] The above description is merely a preferred embodiment of this application. Although this application has disclosed preferred embodiments above, it is not intended to limit this application. Any person skilled in the art can make many possible variations and modifications to the technical solutions of this application using the methods and techniques disclosed above, or modify them into equivalent embodiments with equivalent changes, without departing from the scope of the technical solutions of this application. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this application without departing from the content of the technical solutions of this application shall still fall within the protection scope of the technical solutions of this application.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: Provide initial substrate; An inert gas is injected into the initial substrate, and an annealing process is performed to form a portion of a void layer, thereby dividing the initial substrate into a first part substrate and a second part substrate. On the surface of the first portion of the substrate that is opposite to a portion of the void layer and is far from the portion of the void layer, a superlattice stack is epitaxially grown; the superlattice stack is formed by alternating layers of a first semiconductor layer and a second semiconductor layer. The superlattice stack is etched to form multiple fins; Deposit dummy gates on the fins; The two ends of the fin are etched to the surface of the initial substrate. After etching, source and drain electrodes are epitaxially grown at both ends of the fin. The material of the source and drain electrodes is a semiconductor material doped with conductive elements. The dummy gate is removed, and the first semiconductor layer is etched away to release the channel of the nanosheet formed by the second semiconductor layer. The stack of nanosheets forms multiple conductive channels. A surrounding gate is formed, encircling the nanosheet stack; The first portion of the substrate is etched away to obtain another portion of the void layer; Another part of the cavity layer is inverted T-shaped when viewed along the vertical fin line, and the bottom of the inverted T-shape is adjacent to a part of the cavity layer, and the cavity layer as a whole is also inverted T-shaped when viewed along the vertical fin line.

2. The method according to claim 1, characterized in that, The etching process to remove the first portion of the substrate includes: At least one etched via is formed to connect with the void layer, and the first portion of the substrate is removed by etching through the etched via.

3. The method according to claim 2, characterized in that, The etching process to remove the first portion of the substrate includes: The first portion of the substrate is removed by wet etching.

4. The method according to claim 1, characterized in that, After etching away the first portion of the substrate, the process further includes: The first portion of the substrate and the void layer are filled with a gaseous and / or liquid medium whose dielectric constant is less than or equal to a preset threshold.

5. The method according to claim 1, characterized in that, The etching of the superlattice stack Multiple fins are formed, including: A first sidewall is formed on the superlattice stack; the superlattice stack is etched using the first sidewall as a mask to form the plurality of fins.

6. A semiconductor device, characterized in that, include: Second part: substrate; A void layer located on one side of the second portion of the substrate; A portion of the void layer is formed by injecting an inert gas into an initial substrate and then annealing it; the portion of the void layer divides the initial substrate into a first part substrate and a second part substrate; A stacked layer of nanosheets is located on the side of the void layer away from the second portion of the substrate; the stacked layer of nanosheets comprises a stack of multiple nanosheets; the nanosheets are formed of a semiconductor material; the stack of nanosheets forms a plurality of conductive channels; A surrounding gate around the nanosheet stack; The source and drain electrodes are located at both ends of the nanosheet stack; the source and drain electrodes are made of semiconductor materials doped with conductive elements. The cavity layer also includes another part, which is inverted T-shaped when viewed along the vertical fin line, and the bottom of the inverted T-shape is adjacent to a part of the cavity layer, and the cavity layer as a whole is also inverted T-shaped when viewed along the vertical fin line.

7. The device according to claim 6, characterized in that, Also includes: Shallow trench isolation located between the void layer and the all-around gate.

8. The device according to claim 6, characterized in that, Also includes: An isolation layer located on the side of the source / drain electrode away from the void layer.

9. The device according to claim 8, characterized in that, Also includes: The second sidewall is located between the isolation layer and the surrounding gate.

10. The device according to claim 6, characterized in that, The types of devices include: positive channel nanosheet-around-gate field-effect transistors or negative channel nanosheet-around-gate field-effect transistors.

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