Chip packaging structure, preparation method thereof, and packaging method of semiconductor structure

Abstract

The present application provides a chip packaging structure, a preparation method thereof, and a packaging method for a semiconductor structure, relating to the technical field of semiconductors, and solving the technical problem of low chip yield. The chip packaging structure includes a chip, an intermediate insulating layer disposed on the chip, and a non-conductive adhesive layer disposed on the intermediate insulating layer; a plurality of conductive bumps are provided on the chip, and each of the conductive bumps penetrates through the intermediate insulating layer; at least one set of accommodation holes are provided in the intermediate insulating layer, and the non-conductive adhesive layer fills the accommodation holes, so that grooves matching the accommodation holes are formed on the surface of the non-conductive adhesive layer facing away from the intermediate insulating layer; a part of the non-conductive adhesive in the non-conductive adhesive layer overflows from the non-conductive adhesive layer and flows into the grooves at a first preset temperature and a preset pressure, so as to prevent the non-conductive adhesive from overflowing from the edge of the chip, thereby improving the chip yield.

Description

Technical Field

[0001] The present application relates to the field of packaging technology, and in particular, to a chip packaging structure and a preparation method thereof, and a packaging method for a semiconductor structure. Background Art

[0002] In a chip packaging structure, with the increase in the number of input / output (I / O) pins, when the chip size is reduced or the chip size is shrunk, the pitch of the functional bumps of the chip becomes smaller and smaller, resulting in that the ordinary capillary underfill process cannot fill into the chip to protect the electrode pads.

[0003] To solve the above problems, generally, a thermocompression bonding process is adopted. First, a non-conductive adhesive is pre-coated on a substrate, and then a semiconductor chip is flip-chip mounted on the substrate and thermocompression bonded to solve the problems such as difficult filling and false soldering in the ordinary capillary underfill process.

[0004] However, when the non-conductive adhesive is thermocompression bonded, the non-conductive adhesive easily overflows from the edge of the chip, resulting in a low yield of the chip. Summary of the Invention

[0005] In view of the above problems, embodiments of the present application provide a chip packaging structure and a preparation method thereof, and a packaging method for a semiconductor structure, which can improve the yield of the chip.

[0006] To achieve the above object, embodiments of the present application provide the following technical solutions:

[0007] In a first aspect, embodiments of the present application provide a chip packaging structure, which includes: a chip, an intermediate insulating layer disposed on the chip, and a non-conductive adhesive layer disposed on the intermediate insulating layer; a plurality of conductive studs are provided on the chip, and each of the conductive studs penetrates through the intermediate insulating layer; the intermediate insulating layer is provided with at least one set of receiving holes, and the non-conductive adhesive layer fills the receiving holes so that a groove matching the receiving holes is formed on the surface of the non-conductive adhesive layer facing away from the intermediate insulating layer.

[0008] In the chip packaging structure as described above, the chip packaging structure further includes a plurality of support columns; the plurality of support columns form at least one set of support column groups, and each of the support columns is respectively and spacedly disposed on the intermediate insulating layer; the plurality of conductive studs form at least one set of conductive stud groups, and the pattern formed by arranging each of the conductive studs in the conductive stud group is different from the pattern formed by arranging each of the support columns in the support column group.

[0009] In the chip packaging structure as described above, each set of the receiving holes includes a first receiving hole and a second receiving hole that are communicated with each other, the first receiving hole is disposed on one side of the conductive stud group, and the second receiving hole is disposed on one side of the support column group.

[0010] For the chip packaging structure as described above, the pattern of the first receiving hole matches the arrangement pattern of each of the conductive bumps in the conductive bump group; the pattern of the second receiving hole matches the arrangement pattern of each of the support posts in the support post group.

[0011] For the chip packaging structure as described above, there are at least two groups of the conductive bump group, and at least two groups of the conductive bump groups are arranged at intervals on the chip, and one group of the conductive bump groups corresponds to one of the first receiving holes.

[0012] For the chip packaging structure as described above, there are at least two groups of the support post group, and at least two groups of the support post groups are arranged at intervals on the intermediate insulating layer, and one group of the support post groups corresponds to one of the second receiving holes.

[0013] For the chip packaging structure as described above, the intermediate insulating layer is provided with exhaust channels communicating with each group of the receiving holes, wherein one group of the receiving holes corresponds to one of the exhaust channels, and each of the exhaust channels extends to the edge of the intermediate insulating layer and communicates with the outside.

[0014] For the chip packaging structure as described above, the sum of the areas of the projections of the receiving holes on the intermediate insulating layer is 3.5 to 4 times the sum of the areas of the projections of the plurality of conductive bumps and the plurality of support posts on the intermediate insulating layer.

[0015] For the chip packaging structure as described above, a welding portion is provided at one end of the conductive bump away from the chip, and the welding portion is an arc surface bent away from the conductive bump.

[0016] Compared with the related art, the chip packaging structure provided by the embodiment of the present application has at least the following advantages:

[0017] In the chip packaging structure provided by the embodiment of the present application, by providing an intermediate insulating layer on the chip, and at least one group of receiving holes are provided on the intermediate insulating layer. When forming a non-conductive adhesive layer on the intermediate insulating layer, the part of the non-conductive adhesive corresponding to each receiving hole in the non-conductive adhesive layer will first fill the receiving hole. In this way, grooves matching the receiving holes will be formed on the surface of the non-conductive adhesive layer facing away from the intermediate insulating layer. During the packaging process of the chip packaging structure, part of the non-conductive adhesive in the non-conductive adhesive layer overflows from the surface of the non-conductive adhesive layer under a first preset temperature and a preset pressure and flows to fill the grooves. In this way, it is possible to prevent the part of the non-conductive adhesive that overflows from the non-conductive adhesive layer from overflowing from the edge of the chip, thereby improving the yield of the chip.

[0018] Second aspect, an embodiment of the present application provides a method for manufacturing a chip packaging structure, which includes: providing a chip; forming an intermediate insulating layer on the chip; forming at least one set of receiving holes and a plurality of depressions exposing the circuit layer in the chip on the intermediate insulating layer; forming a plurality of conductive bumps in each of the depressions, wherein one end of the conductive bump away from the chip has a welding portion, and the welding portion is an arc surface bent away from the conductive bump; forming a non-conductive adhesive layer on the intermediate insulating layer, and the non-conductive adhesive layer fills the receiving holes to form grooves matching the receiving holes on the surface of the non-conductive adhesive facing away from the intermediate insulating layer.

[0019] For the method for manufacturing the chip packaging structure as described above, forming at least one set of receiving holes and a plurality of depressions exposing the circuit layer in the chip on the intermediate insulating layer specifically includes: patterning the intermediate insulating layer to form a first pattern set and a second pattern set on the intermediate insulating layer; removing the intermediate insulating layer according to the first pattern set to form at least one set of the receiving holes; removing the intermediate insulating layer and part of the chip according to the second pattern set to expose the metal wiring layer in the chip and form a plurality of the depressions.

[0020] For the method for manufacturing the chip packaging structure as described above, after removing the intermediate insulating layer according to the first pattern set to form at least one set of the receiving holes, and removing the intermediate insulating layer and part of the chip according to the second pattern set to expose the metal wiring layer in the chip and form a plurality of the depressions, it includes: forming conductive posts in each of the depressions and on the intermediate insulating layer respectively; forming welding portions on each of the conductive posts, and the conductive posts and the welding portions in each of the depressions form the conductive bumps; the conductive posts and the welding portions on the intermediate insulating layer form support posts.

[0021] For the method for manufacturing the chip packaging structure as described above, after forming welding portions on each of the conductive posts, and the conductive posts and the welding portions in each of the depressions form the conductive bumps, and the conductive posts and the welding portions on the intermediate insulating layer form the support posts, it further includes: at a second preset temperature, reflowing the welding portions so that one end of the welding portion away from the chip forms an arc surface bent away from the conductive bump.

[0022] Third aspect, an embodiment of the present application provides a method for packaging a semiconductor structure, which includes:

[0023] Provide a substrate with a plurality of pads thereon; provide a chip packaging structure of the first aspect, the chip packaging structure having a plurality of conductive bumps corresponding to the respective pads; flip the chip packaging structure onto the substrate so that the respective conductive bumps on the chip packaging structure correspond one-to-one to the respective pads on the substrate; provide a pressure device, the pressure device being located above the chip packaging structure; the pressure device provides a first preset temperature and a preset pressure to the chip packaging structure; so that the respective conductive bumps on the chip packaging structure are bonded and electrically connected to the corresponding pads on the substrate.

[0024] For the packaging method of the semiconductor structure as described above, after the pressure device provides a first preset temperature and a preset pressure to the chip packaging structure so that the respective conductive bumps on the chip packaging structure are bonded and electrically connected to the corresponding pads on the substrate, it further includes: baking the chip packaging structure and the substrate; forming a plastic encapsulation layer on the baked substrate and the chip packaging structure to wrap the substrate and the chip packaging structure; forming solder balls on the surface of the substrate facing away from the chip packaging structure after plastic encapsulation; cutting the substrate, and the cut substrate, the corresponding solder balls on the cut substrate, and the corresponding chip packaging structure on the cut substrate form a packaged chip.

[0025] The preparation method of the chip packaging structure and the packaging method of the semiconductor structure provided by the embodiments of the present application have the same beneficial effects as the chip packaging structure, and will not be elaborated here one by one.

[0026] In addition to the technical problems solved by the embodiments of the present application described above, the technical features constituting the technical solutions, and the beneficial effects brought by these technical features of the technical solutions, the other technical problems that can be solved by the chip packaging structure and the preparation method, and the packaging method of the semiconductor structure provided by the embodiments of the present application, the other technical features included in the technical solutions, and the beneficial effects brought by these technical features will be further described in detail in the specific implementation manner. Description of the Drawings

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following drawings are some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0028] Figure 1 It is a schematic diagram of the structure after thermocompression bonding of a chip packaging structure and a substrate in the prior art;

[0029] Figure 2 It is a schematic structural diagram of the chip packaging structure in the embodiment of the present application;

[0030] Figure 3 It is a top view schematic diagram of the chip and the intermediate insulating layer in the embodiment of the present application;

[0031] Figure 4 It is a schematic flow diagram of the preparation method of the chip packaging structure in the embodiment of the present application;

[0032] Figure 5 It is a schematic structural diagram of forming an intermediate insulating layer on the chip in the embodiment of the present application;

[0033] Figure 6 It is a schematic structural diagram of forming a receiving hole on the intermediate insulating layer in the embodiment of the present application;

[0034] Figure 7 It is a schematic structural diagram of forming a mask layer on the intermediate insulating layer in the embodiment of the present application;

[0035] Figure 8 It is a schematic structural diagram of patterning the mask layer in the embodiment of the present application;

[0036] Figure 9 It is a schematic structural diagram of forming conductive bumps in the embodiment of the present application;

[0037] Figure 10 It is a schematic structural diagram of removing the mask layer in the embodiment of the present application;

[0038] Figure 11 It is a schematic structural diagram after reflow of the conductive bumps in the embodiment of the present application;

[0039] Figure 12 It is a schematic flow diagram of the packaging method of the semiconductor structure in another embodiment of the present application;

[0040] Figure 13 It is a schematic structural diagram during the thermocompression bonding process of the chip packaging structure and the substrate in another embodiment of the present application;

[0041] Figure 14 It is a schematic structural diagram after the thermocompression bonding of the chip packaging structure and the substrate in another embodiment of the present application;

[0042] Figure 15 It is a schematic structural diagram of the packaged chip formed after packaging the chip and the substrate in another embodiment of the present application.

[0043] Reference numerals:

[0044] 100 - Chip packaging structure; 101 - Chip;

[0045] 1011 - Metal wiring layer; 102 - Intermediate insulating layer;

[0046] 103- non-conductive adhesive layer; 1031- groove;

[0047] 104-conductive column; 1041-welding portion;

[0048] 104a-conductive protrusion; 104b-supporting column;

[0049] 105-accommodation hole; 1051-first accommodation hole;

[0050] 1052 - second receiving hole; 106 - exhaust channel;

[0051] 107-mask layer; 1071-recess;

[0052] 200-substrate; 201-soldering pad;

[0053] 300-pressure equipment; 400-solder balls;

[0054] 500-plastic sealing layer. DETAILED DESCRIPTION

[0055] In related technologies, such as Figure 1 As shown, a conductive protrusion 104a is provided on the chip packaging structure 100, and a solder pad is provided on the substrate 200. When the chip packaging structure 100 and the substrate 200 are thermocompression bonded, a layer of non-conductive glue of a certain thickness is usually first coated on the substrate 200. In this way, when the chip packaging structure 100 is flipped on the substrate 200 and thermocompression bonded with the substrate 200, the non-conductive glue fills the capillaries on the substrate 200 to solve the problem that the bottom of the capillary cannot be filled into the interior of the chip 101 and the problem of cold solder joints. However, when the chip packaging structure and the substrate are thermocompression bonded, the non-conductive glue will overflow from the side of the chip due to squeezing, resulting in a low chip yield.

[0056] In order to solve the above problems, the embodiments of the present application provide a chip packaging structure and a preparation method, and a packaging method for a semiconductor structure. In the chip packaging structure, an intermediate insulating layer is set on the chip, and at least one group of accommodating holes is provided on the intermediate insulating layer. When a non-conductive adhesive layer is formed on the intermediate insulating layer, part of the non-conductive adhesive in the non-conductive adhesive layer corresponding to each accommodating hole will first fill the accommodating hole. In this way, grooves matching the accommodating holes will be formed on the surface of the non-conductive adhesive layer facing away from the intermediate insulating layer. During the packaging process of the chip packaging structure, part of the non-conductive adhesive in the non-conductive adhesive layer overflows from the surface of the non-conductive adhesive layer at a first preset temperature and preset pressure and flows to fill the grooves. In this way, part of the non-conductive adhesive that overflows from the non-conductive adhesive layer can be prevented from overflowing from the edge of the chip, thereby improving the yield of the chip.

[0057] In order to make the above-mentioned objectives, features, and advantages of the embodiments of the present application more obvious and understandable, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the scope of protection of the present application.

[0058] Figure 2 It is a schematic structural diagram of the chip packaging structure in the embodiment of the present application; Figure 3 It is a top view schematic diagram of the chip and the intermediate insulating layer in the embodiment of the present application.

[0059] As Figure 2 and Figure 3 shown, the chip packaging structure 100 provided by the embodiment of the present application includes: a chip 101, an intermediate insulating layer 102 disposed on the chip 101, and a non-conductive adhesive layer 103 disposed on the intermediate insulating layer 102; a plurality of conductive studs 104a are provided on the chip 101, and each conductive stud 104a penetrates the intermediate insulating layer 102; at least one set of receiving holes 105 are provided in the intermediate insulating layer 102, and the non-conductive adhesive layer 103 fills the receiving holes 105, so that a groove 1031 matching the receiving holes 105 is formed on the surface of the non-conductive adhesive layer 103 facing away from the intermediate insulating layer 102.

[0060] It can be understood that when the non-conductive adhesive layer 103 is at the first preset temperature and the preset pressure, part of the non-conductive adhesive has fluidity and will overflow from the surface of the non-conductive adhesive layer 103. Since the surface of the non-conductive adhesive layer 103 has the groove 1031, when part of the non-conductive adhesive overflows from the surface of the non-conductive adhesive layer 103, the overflowing non-conductive adhesive will flow on the surface of the non-conductive adhesive layer 103 to fill into the groove 1031. In this way, it is possible to prevent the non-conductive adhesive from overflowing from the edge of the chip, thereby improving the yield of the chip.

[0061] Among them, the first preset temperature refers to the temperature at which the non-conductive adhesive can be converted from a solid state to a liquid state, so that the non-conductive adhesive has fluidity and adhesiveness; and the preset pressure refers to the pressure required when the chip packaging structure 100 is packaged with structures such as a substrate.

[0062] Exemplarily, the non-conductive adhesive layer 103 can be a thermosetting resin, gum, synthetic resin, etc., and the intermediate insulating layer 102 can be a photoresist layer, etc. In this regard, no specific limitations are made in this embodiment.

[0063] In a specific implementation, when encapsulating the chip packaging structure 100 with structures such as a substrate, at a first preset temperature and a preset pressure, part of the non-conductive adhesive will overflow from the surface of the non-conductive adhesive layer 103, and the overflowed non-conductive adhesive will flow into the groove 1031 on the surface of the non-conductive adhesive layer 103. In this way, it is possible to prevent the non-conductive adhesive that overflows from the non-conductive adhesive layer 103 from overflowing from the edge of the chip 101, thereby improving the yield of the chip 101.

[0064] It can be understood that the groove 1031 formed on the non-conductive adhesive layer 103 is used to accommodate part of the non-conductive adhesive that overflows from the surface of the non-conductive adhesive layer 103, preventing the overflowed non-conductive adhesive from overflowing from the edge of the chip 101.

[0065] Therefore, in the embodiment of the present application, by providing an intermediate insulating layer 102 on the chip 101, at least one set of receiving holes 105 is provided on the intermediate insulating layer 102. When forming the non-conductive adhesive layer 103 on the intermediate insulating layer 102, part of the non-conductive adhesive in the non-conductive adhesive layer 103 corresponding to each receiving hole 105 will first fill the receiving hole 105. In this way, a groove 1031 matching the receiving hole 105 will be formed on the surface of the non-conductive adhesive layer 103 facing away from the intermediate insulating layer 102. During the encapsulation process of the chip packaging structure 100, part of the non-conductive adhesive in the non-conductive adhesive layer 103 overflows from the surface of the non-conductive adhesive layer 103 and flows to fill the groove 1031 under the first preset temperature and the preset pressure. In this way, it is possible to prevent part of the non-conductive adhesive that overflows from the non-conductive adhesive layer 103 from overflowing from the edge of the chip, thereby improving the yield of the chip.

[0066] Continue to refer to Figure 2 and Figure 3 As shown, a plurality of conductive bumps 104a form at least one set of conductive bump groups, and each conductive bump 104a is disposed on the chip 101 and electrically connected to the metal wiring layer 1011 in the chip 101. One end of each conductive bump 104a away from the chip 101 penetrates the intermediate insulating layer 102, so that the conductive bump 104a can be welded to the pad on the substrate for subsequent electrical conduction; in addition, the chip packaging structure further includes a plurality of support posts 104b, and the plurality of support posts 104b form at least one set of support post groups, and each support post 104b is respectively disposed at intervals on the intermediate insulating layer 102. It can be understood that when the chip packaging structure 100 is flip-chip mounted on the substrate, the support posts 104b are mainly used to support the chip 101.

[0067] It can be understood that the material of the conductive bump 104a includes one or a combination of several of tin, copper, aluminum, nickel, gold, silver, and titanium.

[0068] A plurality of sets of receiving holes 105 are provided near the edges of the conductive bumps 104a and the support posts 104b, and a plurality of grooves 1031 matching the receiving holes 105 are formed on the non-conductive adhesive layer 103. When the chip packaging structure 100 is subjected to a preset extrusion force, the non-conductive adhesive between each conductive bump 104a and the support post 104b and the pads 201 on the substrate and other structures will be extruded and overflow. The overflowing conductive adhesive will first fill in the grooves 1031 at the edges of the conductive bumps 104a and the support posts 104b, thereby preventing the conductive adhesive from overflowing from the edge of the chip 101, and further improving the yield of the chip 101.

[0069] Among them, the patterns formed by arranging the conductive bumps 104a in the conductive bump group are different from the patterns formed by arranging the support posts 104b in the support bump group; for example, the conductive bump group forms a rectangle with its length direction extending along the first direction, while the support post group forms a rectangle with its length direction extending along the second direction, where the first direction and the second direction can be perpendicular in the horizontal plane.

[0070] Each set of receiving holes 105 includes a first receiving hole 1051 and a second receiving hole 1052 that are connected and communicate with each other. The first receiving hole 1051 is provided on one side of the conductive bump group, and the second receiving hole 1052 is provided on one side of the support post group. In this way, at the positions on the non-conductive adhesive layer 103 corresponding to the first receiving hole 1051 and the second receiving hole 1052 respectively, grooves 1031 matching the first receiving hole 1051 and the second receiving hole 1052 are formed. When the chip packaging structure 100 is packaged with the substrate, the grooves 1031 near the conductive bump group can receive the non-conductive adhesive that overflows due to extrusion near the conductive bump group, and the grooves 1031 near the support post group can receive the non-conductive adhesive that overflows due to extrusion near the support post group, thereby preventing the non-conductive adhesive from overflowing from the edge of the chip 101, and further improving the yield of the chip 101.

[0071] Preferably, continuing to refer to Figure 10 As shown, the pattern of the first receiving hole 1051 can match the pattern formed by arranging the conductive bumps 104a in the conductive bump group. In this way, the grooves 1031 formed on the non-conductive adhesive layer 103 also match the arrangement pattern of the conductive bump group; the pattern of the second receiving hole 1052 matches the pattern formed by arranging the support posts 104b in the support post group. In this way, the grooves 1031 formed on the non-conductive adhesive layer 103 also match the arrangement pattern of the support post group.

[0072] Exemplarily, the conductive posts 104a in the conductive post group are arranged to form a rectangle. Therefore, the pattern of the first receiving hole 1051 is also a rectangle that matches the shape and size of this rectangle. The groove 1031 formed on the non-conductive adhesive layer 103 and matching the first receiving hole 1051 is also a rectangle, so as to better accommodate the non-conductive adhesive that overflows near the conductive post group and prevent the non-conductive adhesive from overflowing the edge of the chip 101. Of course, when the support posts 104b in the support post group are arranged to form a rectangle, the pattern of the second receiving hole 1052 is also a rectangle that matches the shape and size of this rectangle. The groove 1031 formed on the non-conductive adhesive layer 103 and matching the second receiving hole 1052 is also a rectangle, so as to better accommodate the non-conductive adhesive that overflows near the support post group and prevent the non-conductive adhesive from overflowing the edge of the chip 101.

[0073] In the embodiment of the present application, the distance from the first receiving hole 1051 to the edge of each conductive post 104a corresponding to the first receiving hole 1051 can be 9 - 11 μm. Preferably, the distance from the first receiving hole 1051 to the edge of each conductive post 104a corresponding to the first receiving hole 1051 is 10 μm. In this way, the distance from the groove 1031 formed on the non-conductive adhesive layer 103 and matching the first receiving hole 1051 to the edge of the conductive post 104a is also 9 - 11 μm. When the non-conductive adhesive corresponding to the conductive post 104a is extruded and overflows, the overflowing non-conductive adhesive can be filled in the groove 1031, thereby preventing the non-conductive adhesive from overflowing the edge of the chip 101 and further improving the yield of the chip 101.

[0074] The distance from the second receiving hole 1052 to the edge of each support post 104b corresponding to the second receiving hole 1052 can be 9 - 11 μm. Preferably, the distance from the second receiving hole 1052 to the edge of each support post 104b corresponding to the second receiving hole 1052 is 10 μm. In this way, the distance from the groove 1031 formed on the non-conductive adhesive layer 103 and matching the second receiving hole 1052 to the edge of the support post 104b is also 9 - 11 μm. When the non-conductive adhesive corresponding to the support post 104b is extruded and overflows, the overflowing non-conductive adhesive can be filled in the groove 1031, thereby preventing the non-conductive adhesive from overflowing the edge of the chip 101 and further improving the yield of the chip 101.

[0075] There are at least two sets of conductive posts, and the at least two sets of conductive posts are arranged at intervals on the chip 101. One set of conductive posts corresponds to one first accommodation hole 1051; there are at least two sets of support posts, and the at least two sets of support posts are arranged at intervals on the chip 101. One set of support posts corresponds to one second accommodation hole 1052. In this way, grooves 1031 that match the first accommodation hole 1051 and the second accommodation hole 1052 respectively will be formed on the non-conductive adhesive layer 103. The non-conductive adhesive overflowing near the conductive post group is filled in the groove 1031 corresponding to the conductive post group, while the non-conductive adhesive overflowing near the support post group is filled in the groove 1031 corresponding to the support post group, so as to prevent the non-conductive adhesive from overflowing the edge of the chip 101, thereby improving the yield of the chip 101.

[0076] Continue to refer to Figure 3 As shown, the intermediate insulating layer 102 is provided with an exhaust channel 106 communicating with the accommodation hole 105. Among them, one set of accommodation holes 105 corresponds to one exhaust channel 106, and each exhaust channel 106 extends to the edge of the intermediate insulating layer 102 and communicates with the outside.

[0077] By providing the exhaust channel 106 communicating with the accommodation hole 105 in the intermediate insulating layer 102, in this way, when the non-conductive adhesive layer 103 is formed or when the chip packaging structure 100 is packaged with the substrate, the air in the accommodation hole 105 and the bubbles in the non-conductive adhesive can be discharged from the exhaust channel 106.

[0078] The sum of the areas of the projections of the accommodation holes 105 on the intermediate insulating layer 102 is 3.5 to 4 times the sum of the areas of the projections of all the conductive posts 104a and all the support posts 104b on the intermediate insulating layer 102 of the chip packaging structure 100.

[0079] It can be understood that the area of the projection of the groove 1031 formed corresponding to the accommodation hole 105 in the non-conductive adhesive layer 103 on the intermediate insulating layer 102 is 3.5 to 4 times the sum of the areas of the projections of all the conductive posts 104a and all the support posts 104b on the intermediate insulating layer 102 of the chip 101. In this way, the accommodation capacity of the groove 1031 for the non-conductive adhesive overflowing near the conductive post 104a is increased, and the non-conductive adhesive is prevented from overflowing the edge of the chip 101, thereby improving the yield of the chip 101.

[0080] The thickness of the intermediate insulating layer 102 is 4.5 to 5 μm. In this way, the depth of the groove 1031 formed on the non-conductive adhesive layer 103 can be made appropriate, avoiding the surface of the non-conductive adhesive layer 103 being uneven due to the too deep depth of the groove 1031, and also avoiding partial non-conductive adhesive from overflowing the edge of the chip 101 due to the too shallow depth of the groove 1031.

[0081] It can be understood that the conductive bump 104a and the support post 104b respectively include a conductive post 104 and a welding portion 1041 provided on the conductive post 104. Among them, the conductive post 104 and the welding portion 1041 located on the metal wiring layer 1011 form the conductive bump 104a, and the conductive bump 104a is electrically connected to the metal wiring layer 1011. The conductive post 104 located on the intermediate insulating layer and the welding portion 1041 located on the conductive post 104 form the support post 104b, which is mainly used to support devices such as chips.

[0082] It can be understood that the conductive bump 104a and the support post 104b can be formed by an integral process to reduce the processing procedures and lower the processing cost.

[0083] Among them, the welding portion 1041 is an arc surface bent away from the conductive post 104. By setting the welding portion 1041 as an arc surface, it is convenient for the conductive bump 104a to abut against and be electrically connected to the pads on structures such as the substrate.

[0084] It can be understood that the welding portion 1041 is a circular arc surface or can also be an elliptical arc surface. In this regard, the present embodiment does not make specific limitations.

[0085] Figure 4 It is a schematic flow chart of the preparation method of the chip packaging structure in the embodiment of the present application.

[0086] As Figure 4 shown, the embodiment of the present application also provides a preparation method of a chip packaging structure, which includes:

[0087] Step S101: Provide a chip.

[0088] As Figure 5 shown, the chip 101 includes a silicon substrate and a dielectric layer provided on the silicon substrate. There is an opening on the dielectric layer that exposes the silicon substrate, and a conductive layer is formed in the opening. The dielectric layer includes polyimide or a polymer material, and the dielectric layer can play a role in insulation and buffering to avoid damage to the chip 101.

[0089] Step S102: Form an intermediate insulating layer on the chip.

[0090] Continue to refer to Figure 5 shown, an intermediate insulating layer 102 is formed on the dielectric layer and the opening. Among them, the intermediate insulating layer 102 can be a photoresist layer formed by coating on the dielectric layer and the opening.

[0091] Step S103: Form at least one set of receiving holes and a plurality of depressions exposing the metal wiring layer in the chip on the intermediate insulating layer.

[0092] Specifically, it includes: a patterned intermediate insulating layer, and a first pattern group is formed on the intermediate insulating layer. Additionally, a second pattern group can be formed on the intermediate insulating layer simultaneously.

[0093] As Figure 6 shown, the intermediate insulating layer 102 is removed according to the first pattern group to form at least one set of accommodation holes 105; the intermediate insulating layer 102 and a part of the chip 101 are removed according to the second pattern group to expose the metal wiring layer in the chip 101, forming a plurality of depressions 1071.

[0094] Among them, the cross-sectional shape of the depression 1071 can match the cross-sectional shape of its corresponding conductive stud 104a.

[0095] Step S104: A plurality of conductive studs are formed in each depression. Among them, one end of the conductive stud away from the chip has a welding portion, and the welding portion is an arc-shaped surface that bends away from the conductive stud.

[0096] After forming a plurality of depressions on the intermediate insulating layer, a conductive stud and a support post are formed in each depression. Specifically, it includes:

[0097] As Figure 7 shown, a mask layer 107 is formed on the intermediate insulating layer 102; and the mask layer 107 is patterned.

[0098] As Figure 8 shown, according to the patterned mask layer 107, part of the mask layer 107 can be removed by wet etching or dry etching, removing the mask layer 107 corresponding to the depression 1071 to expose the metal wiring layer 1011 in the depression 1071, and removing part of the mask layer on the intermediate insulating layer 102 to expose part of the intermediate insulating layer, so as to form a conductive post 104 in each depression 1071 and on the exposed intermediate insulating layer 102, and form a welding portion 1041 at one end of each conductive post 104 away from the chip. Among them, the conductive post 104 and the welding portion 1041 on the conductive post 104 in each depression 1071 form a conductive stud 104a, and the conductive post 104 and the welding portion 1041 on the conductive post 104 on the intermediate insulating layer 102 form a support post 104b.

[0099] It can be understood that the conductive post 104 and the welding portion 1041 on the metal wiring layer 1011, and the conductive post 104 and the welding portion 1041 on the intermediate insulating layer 102 are formed by an integral molding method, that is, the conductive stud 104a and the support post 104b are formed by an integral molding process.

[0100] As Figure 9 shown, it can be understood that a welding portion 1041 can be formed at one end of the conductive post 104 away from the chip 101 by electroplating.

[0101] As Figure 10 shown, after forming the conductive studs 104a and the support studs 104b in the respective recesses 1071, the mask layer 107 is removed.

[0102] As Figure 11 shown, at a second preset temperature, the side of the welding portion 1041 facing the conductive stud 104 is refluxed so that the welding portion 1041 forms an arc surface that bends away from the conductive stud 104. Among them, the arc surface can be a circular arc surface, an elliptical arc surface, etc.

[0103] Step S105: Form a non-conductive adhesive layer on the intermediate insulating layer. The non-conductive adhesive layer fills the accommodation holes to form grooves matching the accommodation holes on the surface of the non-conductive adhesive facing away from the intermediate insulating layer. The non-conductive adhesive flows and fills the grooves under a first preset temperature and a preset pressure.

[0104] As Figure 2 shown, a non-conductive adhesive layer 103 is formed on the intermediate insulating layer 102. The non-conductive adhesive will first fill the accommodation holes 105. Therefore, grooves 1031 matching the accommodation holes 105 will be formed on the non-conductive adhesive layer 103 corresponding to each accommodation hole 105. In this way, when the chip packaging structure 100 is packaged with the substrate, the non-conductive adhesive between and near the conductive stud 104a and the substrate 200 will be extruded and overflow around the conductive stud 104a, and the overflowing non-conductive adhesive will fill into the grooves 1031 near the edge of the conductive stud 104a, thereby preventing the non-conductive adhesive from overflowing the edge of the chip 101, and further improving the yield of the packaged chip 101.

[0105] As Figure 14 shown, the semiconductor structure provided by the embodiment of the present application includes: a substrate 200 and the chip packaging structure 100 provided in the above embodiment. Among them, the chip packaging structure 100 includes a plurality of spaced conductive studs 104a. A plurality of pads 201 corresponding to the respective conductive studs 104a are provided on the substrate 200. When the chip packaging structure 100 is located on the substrate 200 and packaged with the substrate 200, each conductive stud 104a is welded and electrically connected to its corresponding pad 201.

[0106] Figure 12 It is a schematic flow chart of the packaging method of the semiconductor structure in another embodiment of the present application.

[0107] As Figure 12 shown, the packaging method of the semiconductor structure provided by the embodiment of the present application further includes the following steps:

[0108] Step S201: Provide a substrate, and a plurality of pads are provided on the substrate.

[0109] Among them, the material of the pad includes one or a combination of several of copper, aluminum, nickel, gold, silver, and titanium. The material of the substrate includes one or a combination of several of resin, silicon, glass, silicon oxide, ceramic, and metal.

[0110] Step S202: Provide a chip packaging structure prepared by the method for preparing a chip packaging structure provided in the above embodiment. The chip packaging structure has a plurality of conductive bumps corresponding to each pad.

[0111] Step S203: Flip the chip packaging structure on the substrate so that each conductive bump on the chip packaging structure corresponds to each pad on the substrate one by one.

[0112] Step S204: Provide a pressure device, and the pressure device is located above the chip packaging structure.

[0113] Step S205: The pressure device provides a first preset temperature and a preset pressure to the chip packaging structure; so that each conductive bump on the chip packaging structure is bonded and electrically connected to its corresponding pad on the substrate.

[0114] As Figure 13 and Figure 14 shown, while the pressure device 300 provides pressure to the chip packaging structure 100 and the substrate 200, it also heats the chip packaging structure 100 and the substrate 200, so that the pressure and temperature for thermocompression bonding are reached between the chip packaging structure 100 and the substrate 200, so that the conductive bumps 104a on the chip packaging structure 100 are respectively welded and electrically connected to each pad 201.

[0115] It can be understood that the heating temperature of the heating device on the chip 101 itself is 60°C to 70°C; so that the first preset temperature between the chip packaging structure 100 and the substrate 200 reaches 240°C to 250°C, the preset pressure is 5 to 12 N, and the bonding time is 3 to 5 s.

[0116] As Figure 15 shown, after the pressure device 300 provides a first preset temperature and a preset pressure to the chip packaging structure 100 so that each conductive bump 104a on the chip packaging structure 100 is bonded and electrically connected to its corresponding pad 201 on the substrate 200, the chip packaging structure 100 and the substrate 200 are baked; a plastic encapsulation layer 500 that wraps the substrate 200 and the chip packaging structure 100 is formed on the baked substrate 200 and the chip packaging structure 100; solder balls 400 are formed on the surface of the substrate 200 facing away from the chip packaging structure 100 after encapsulation; the substrate 200 is cut, and the cut substrate 200, the corresponding solder balls 400 on the cut substrate 200, and the corresponding chip packaging structure 100 on the cut substrate 200 form a packaged chip.

[0117] The beneficial effects of the method for manufacturing the chip packaging structure, the semiconductor structure, and the packaging method of the semiconductor structure provided in the above embodiments are the same as those of the chip packaging structure, and will not be elaborated herein one by one.

[0118] The embodiments or implementation manners in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts among the various embodiments can be referred to each other.

[0119] In the description of this specification, the description with reference to terms such as "one implementation manner", "some implementation manners", "illustrative implementation manner", "example", "specific example", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the implementation manner or example are included in at least one implementation manner or example of the present application. In this specification, the schematic description of the above terms does not necessarily refer to the same implementation manner or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more implementation manners or examples.

[0120] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the various embodiments of the present application.

Claims

1. A chip packaging structure, characterized in that, Comprising: a chip, an intermediate insulating layer disposed on the chip, and a non-conductive adhesive layer disposed on the intermediate insulating layer; a plurality of conductive bumps are provided on the chip, and each of the conductive bumps penetrates through the intermediate insulating layer; the intermediate insulating layer is provided with at least one set of receiving holes, and the non-conductive adhesive layer fills the receiving holes, so that grooves matching the receiving holes are formed on the surface of the non-conductive adhesive layer facing away from the intermediate insulating layer.

2. The chip packaging structure according to claim 1, wherein, The chip packaging structure further includes a plurality of support pillars; the plurality of support pillars form at least one set of support pillar groups, and each of the support pillars is respectively and spacedly disposed on the intermediate insulating layer; a plurality of conductive bumps form at least one set of conductive bump groups, and the pattern formed by the arrangement of each of the conductive bumps in the conductive bump group is different from the pattern formed by the arrangement of each of the support pillars in the support pillar group.

3. The chip packaging structure according to claim 2, wherein The receiving hole includes a first receiving hole and a second receiving hole that are communicated with each other, the first receiving hole is disposed on one side of the conductive bump group, and the second receiving hole is disposed on one side of the support pillar group.

4. The chip packaging structure according to claim 3, wherein The pattern of the first receiving hole matches the arrangement pattern of each of the conductive bumps in the conductive bump group; the pattern of the second receiving hole matches the arrangement pattern of each of the support pillars in the support pillar group.

5. The chip packaging structure according to claim 4, characterized in that, The conductive bump group is at least two groups, and at least two groups of the conductive bump groups are spacedly arranged on the chip, and one group of the conductive bump groups corresponds to one of the first receiving holes.

6. The chip packaging structure according to claim 4, wherein, The support pillar group is at least two groups, and at least two groups of the support pillar groups are spacedly arranged on the intermediate insulating layer, and one group of the support pillar groups corresponds to one of the second receiving holes.

7. The chip packaging structure according to any one of claims 2-6, characterized in that, The intermediate insulating layer is provided with an exhaust channel communicated with each group of the receiving holes, wherein one group of the receiving holes corresponds to one of the exhaust channels, and each of the exhaust channels extends to the edge of the intermediate insulating layer and is communicated with the outside.

8. The chip packaging structure according to claim 7, wherein The sum of the areas of the projections of the receiving holes on the intermediate insulating layer is 3.5 to 4 times the sum of the areas of the projections of the plurality of conductive bumps and the plurality of support pillars on the intermediate insulating layer.

9. The chip packaging structure according to claim 1, wherein, The end of the conductive bump away from the chip is provided with a welding portion, and the welding portion is an arc surface.

10. A method for preparing a chip packaging structure, characterized in that, Comprising: providing a chip; forming an intermediate insulating layer on the chip; forming at least one set of receiving holes and a plurality of recesses exposing the metal wiring layer in the chip on the intermediate insulating layer; forming a plurality of conductive bumps in each of the recesses, wherein the end of the conductive bump away from the chip has a welding portion, and the welding portion is an arc surface bent away from the conductive bump; forming a non-conductive adhesive layer on the intermediate insulating layer, and the non-conductive adhesive layer fills the receiving holes to form grooves matching the receiving holes on the surface of the non-conductive adhesive layer facing away from the intermediate insulating layer.

11. The method for manufacturing the chip packaging structure according to claim 10, wherein Forming at least one set of receiving holes and a plurality of recesses exposing the circuit layer in the chip on the intermediate insulating layer specifically includes: patterning the intermediate insulating layer to form a first pattern group and a second pattern group on the intermediate insulating layer; Remove the intermediate insulating layer according to the first pattern group to form at least one group of the receiving holes; remove the intermediate insulating layer and part of the chip according to the second pattern group to expose the metal wiring layer in the chip, and form a plurality of the depressions.

12. The method for manufacturing the chip packaging structure according to claim 11, wherein Remove the intermediate insulating layer according to the first pattern group to form at least one group of the receiving holes; After removing the intermediate insulating layer and part of the chip according to the second pattern group to expose the metal wiring layer in the chip and form a plurality of the depressions, it includes: Form conductive posts in each of the depressions and on the intermediate insulating layer respectively; Form welding parts on each of the conductive posts, and the conductive posts and the welding parts in each of the depressions form the conductive bumps; the conductive posts and the welding parts on the intermediate insulating layer form the support posts.

13. The method for manufacturing the chip packaging structure according to claim 12, wherein, Form welding parts on each of the conductive posts, and the conductive posts and the welding parts in each of the depressions form the conductive bumps; After the conductive posts and the welding parts on the intermediate insulating layer form the support posts, it further includes: At a second preset temperature, reflow the welding parts so that the welding parts form an arc surface bent away from the conductive posts.

14. A packaging method for a semiconductor structure, characterized in that, It includes: Provide a substrate, and a plurality of pads are provided on the substrate; Provide the chip package structure according to any one of claims 1 to 9, and the chip package structure has a plurality of conductive bumps corresponding to each of the pads; Flip the chip package structure on the substrate so that each of the conductive bumps on the chip package structure corresponds to each of the pads on the substrate one by one; Provide a pressure device, and the pressure device is located above the chip package structure; The pressure device provides a first preset temperature and a preset pressure to the chip package structure; so that each of the conductive bumps on the chip package structure is bonded and electrically conducted with the corresponding pad on the substrate.

15. The encapsulation method of the semiconductor structure according to claim 14, characterized in that, After the pressure device provides a first preset temperature and a preset pressure to the chip package structure so that each of the conductive bumps on the chip package structure is bonded and electrically conducted with the corresponding pad on the substrate, it further includes: Bake the chip package structure and the substrate; Form a plastic encapsulation layer covering the substrate and the chip package structure on the baked substrate and the chip package structure; Form solder balls on the surface of the plastic-encapsulated substrate facing away from the chip package structure; Cut the substrate, and the cut substrate, the corresponding solder balls on the cut substrate, and the corresponding chip package structure on the cut substrate form a packaged chip.

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