A semiconductor structure
By optimizing the electrode structure and lead layout of the capacitor trench unit, the problem of high ESR in the capacitor in the interposer was solved, achieving low ESR and efficient charge transfer of the capacitor, thus improving the stability and power consumption performance of the circuit.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SEMICON MFG INT (BEIJING) CORP
- Filing Date
- 2021-09-17
- Publication Date
- 2026-06-30
AI Technical Summary
In the prior art, the capacitors in the interposer have a high ESR when suppressing high-frequency noise, resulting in high power consumption and easy heat loss, which affects circuit stability.
A semiconductor structure is designed to shorten the conductive path and increase the conductive area by optimizing the electrode structure and lead layout in the capacitor trench unit, and to form a large-area conductive contact by using continuous or discontinuous lead layer structures to connect electrodes in parallel.
This significantly reduces the equivalent series resistance (ESR) of the capacitor, thereby reducing power consumption and improving circuit stability and efficiency.
Smart Images
Figure CN115831937B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor integrated circuits, and more particularly to a semiconductor structure. Background Technology
[0002] With Moore's Law slowing down, 2.5D packaging is an on-chip stacking technology that can expand the range of complex chips, and the industry is embarking on a new path to surpass Moore's Law, rapidly providing large-scale complex chip integration while reducing power consumption and cost. To address the issue of insufficient wiring density on organic substrates, silicon substrates with TSV (Through Silicon Via) vertical interconnects and high-density metal wiring have emerged. Silicon-based passive platforms with TSVs are called TSV interposers, and packaging structures using TSV interposers are called 2.5D interposers.
[0003] In interposer circuits, decoupling capacitors are widely used in the power supply networks of various subsystems. They are typically connected between the power supply and ground, utilizing the principle that the impedance decreases with increasing frequency to reduce high-frequency noise in the power supply network, thus suppressing noise. Generally, the smaller the capacitance value, the lower the parasitic inductance and resistance, making it suitable for suppressing high frequencies. However, due to the small capacitance value, its low-frequency decoupling effect is poor. Conversely, when the capacitance value is larger, the low-frequency decoupling effect is better, but the parasitic inductance and resistance are also larger, resulting in a worse high-frequency decoupling effect.
[0004] Therefore, there is an urgent need to find a semiconductor structure that can give the interposer a large capacitance value and reduce the equivalent series resistance (ESR). Summary of the Invention
[0005] The technical problem to be solved by this application is to provide a semiconductor structure that can effectively reduce the ESR of capacitors.
[0006] To address the aforementioned technical problems, this application provides a semiconductor structure including at least one capacitor trench unit. The capacitor trench unit comprises: a plurality of capacitor trench groups located in a semiconductor substrate, the plurality of capacitor trench groups arranged around a specific position, each capacitor trench group including at least two parallel capacitor trenches; a capacitor structure including an upper electrode, a middle electrode, and a lower electrode is formed in each capacitor trench; wherein the lower electrode continuously covers the inner wall of the capacitor trench, the semiconductor substrate between the capacitor trenches, and portions of the semiconductor substrate on both sides of the capacitor trench group; the middle electrode is located on a portion of the lower electrode and continuously distributed within any capacitor trench group, and forms a first step with the lower electrode on both sides of each capacitor trench group; the upper electrode is located on a portion of the middle electrode and continuously distributed within any capacitor trench group, and is located on the same plane as the sidewall of the middle electrode on the outer side of each capacitor trench group, and forms a second step with the middle electrode on the inner side of each capacitor trench group.
[0007] In this embodiment, a first lead layer is formed on a portion of the upper electrode surface of each capacitor trench group; a second lead layer is formed on a portion of the middle electrode surface at a second stepped position inside each capacitor trench group; and a third lead layer is formed on a portion of the lower electrode surface at a first stepped position on both sides of each capacitor trench group.
[0008] In this embodiment, the first lead layer extends in the same direction as the corresponding capacitor trench group, and the first lead layer is a continuous structure or a discontinuous structure.
[0009] In this embodiment, the first lead layer spans over two capacitor trenches of the corresponding capacitor trench group.
[0010] In this embodiment of the application, the width of the first lead layer is 0.2μm-2μm and the length is 2μm-20μm.
[0011] In the embodiments of this application, the second lead layer is a continuous or discontinuous annular structure.
[0012] In this embodiment of the application, the width of the annular structure is 0.2μm-1μm.
[0013] In this embodiment, the third lead layers on the outer side of each capacitor trench group are not connected to each other; the inner side of each capacitor trench group shares a third lead layer.
[0014] In this embodiment, the third lead layer on the outer side of each capacitor trench group extends in the same direction as the corresponding capacitor trench group; the extension direction of the third lead layer shared on the inner side of each capacitor trench group extends in the same direction as a portion of the capacitor trench groups.
[0015] In the embodiments of this application, the width of the third lead layer on the outer side of each capacitor trench group is 0.2μm-1μm, and the length is 2μm-20μm; the width of the third lead layer shared on the inner side of each capacitor trench group is 0.2μm-2μm, and the length is 2μm-20μm.
[0016] In this embodiment, the upper electrode forms a third step with the middle electrode at both ends of each capacitor trench group, and a fourth lead layer is formed on a portion of the surface of the middle electrode at the third step position, and adjacent ends of adjacent capacitor trench groups share a fourth lead layer.
[0017] In this embodiment, the cross-sectional area of the fourth lead layer is 0.25 μm. 2 -4μm 2 .
[0018] In the embodiments of this application, the top surfaces of the first lead layer, the second lead layer, the third lead layer, and the fourth lead layer are coplanar.
[0019] In the embodiments of this application, a conductor layer is formed on the surface of the first lead layer, the second lead layer, the third lead layer and the fourth lead layer.
[0020] In the embodiments of this application, opposing capacitor trench groups have the same size, and capacitor trenches within the same capacitor trench group have the same size.
[0021] In this embodiment, a first dielectric layer is further included between the lower electrode and the semiconductor substrate, a second dielectric layer is further included between the lower electrode and the middle electrode, and a third dielectric layer is further included between the middle electrode and the upper electrode.
[0022] This application's technical solution effectively shortens the conductive path of the electrodes and reduces their inherent resistance by arranging the capacitor trench group around a specific location and configuring the structures of the upper, middle, and lower electrodes. Through the design of the conductive lead structure, the conductive area is maximized. Compared to existing technologies that place a limited number of conventionally sized leads at both ends of the capacitor trench group, the conductive area is significantly increased, thereby significantly reducing the capacitor's ESR. Attached Figure Description
[0023] The following accompanying drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals denote similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting and exemplary, and the drawings are for illustrative purposes only and are not intended to limit the scope of this application. Other embodiments may similarly fulfill the inventive intent of this application. It should be understood that the drawings are not drawn to scale. Wherein:
[0024] Figure 1 This is a schematic diagram of the capacitor trench unit in an embodiment of this application;
[0025] Figure 2 A layout diagram of the semiconductor structure of this application embodiment after removing the shielding film layer on the surface of each electrode;
[0026] Figure 3 for Figure 2 Sectional view at point AA;
[0027] Figure 4 for Figure 2 One type of sectional view at point BB;
[0028] Figure 5 for Figure 2 Sectional view at CC;
[0029] Figure 6 for Figure 2 Another sectional view at point BB;
[0030] Figure 7 Another layout diagram of the semiconductor structure in this application embodiment after removing the shielding film layer on the surface of each electrode. Detailed Implementation
[0031] The following description provides specific application scenarios and requirements for this application, intended to enable those skilled in the art to make and use the content of this application. Various partial modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but rather to the widest scope consistent with the claims.
[0032] ESR is a critical parameter in capacitors. ESR is related to capacitor power dissipation (I). 2The ESR (Equivalent Series Resistance) of a capacitor is related to the current (I is the current). A high ESR leads to greater power dissipation and heat generation, potentially causing circuit failure. The equivalent series resistance of a silicon-based capacitor is obtained by connecting the resistance of the electrode plates and the dielectric in series (if the electrode is made of heavily doped polycrystalline material, the electrode resistance dominates). Using parallel capacitor structures to reduce impedance theoretically lowers the resistance value by connecting resistors in parallel. However, in interposers, multiple basic capacitor components (such as a capacitor trench) are connected in parallel to form a capacitor trench group. Several capacitor trench groups then form a capacitor trench unit. Depending on the capacitance requirement, the electrodes of several capacitor trench units are connected in parallel to form a capacitor. If a typical parallel structure is used, such as placing a limited number of leads at both ends of the capacitor trench group to connect the electrode plates and the conductor layer, the path of the series resistance between the electrodes is long. Furthermore, using leads with conventional node sizes results in insufficient contact area between the electrode plates and the conductor layer. Although the capacitor structure is gradually increased in size, it still cannot effectively reduce the capacitor's ESR.
[0033] In view of this, the technical solution of this application designs the structure of each electrode in the capacitor structure to minimize the conductive path and increase the conductive area of the conductive structure. It carries charge between the electrodes with the maximum parallelism on the conductive path, thereby effectively reducing the ESR of the capacitor.
[0034] The semiconductor structure of the technical solution of this application will be described in detail below with reference to the accompanying drawings and specific embodiments.
[0035] This application provides a semiconductor structure that can be used as a capacitor. (Reference) Figure 1 The semiconductor structure includes at least one capacitor trench unit 10, and the distribution of the capacitor trench units 10 is designed according to actual needs. As an example, the capacitor trench units 10 can be arranged in a longitudinal and transverse uniform manner, and the number of capacitor trench units 10 distributed in each row and column can be determined according to the required capacitance.
[0036] Each of the capacitor trench units 10 may include a plurality of capacitor trench groups 110. The capacitor trench groups 110 are located in the semiconductor substrate 100. The capacitor trench groups 110 are arranged around a specific location and are not interconnected. As an example, the capacitor trench groups 110 are arranged in a quadrilateral shape. The number of capacitor trench groups 110 is not specifically limited and is determined according to the size of the device and the required capacitance. As an example, each of the capacitor trench units 10 includes four capacitor trench groups 110 arranged in a quadrilateral shape, wherein two capacitor trench groups 110 are arranged opposite each other and both extend laterally, and the remaining two capacitor trench groups 110 are arranged opposite each other and both extend longitudinally. In some embodiments, opposite capacitor trench groups 110 have the same dimensions, while adjacent capacitor trench groups 110 have different dimensions; the dimensions of the capacitor trench groups 110 mainly refer to their width and length. As an example, each of the capacitor trench units 10 includes two opposing and laterally extending capacitor trench groups 110 and two opposing and longitudinally extending capacitor trench groups 110, wherein the two laterally extending capacitor trench groups 110 have the same size, and the two longitudinally extending capacitor trench groups 110 have the same size. The size difference between adjacent capacitor trench groups 110 can be determined according to the actual situation.
[0037] Each of the capacitor trench groups 110 includes at least two parallel capacitor trenches 111. The number of capacitor trenches 111 in each of the capacitor trench groups 110 may be the same or different. As an example, oppositely arranged capacitor trench groups 110 have the same number of capacitor trenches 111, while adjacently arranged capacitor trench groups 110 have different numbers of capacitor trenches 111. The capacitor trenches 111 within the same capacitor trench group 110 have the same dimensions, where the dimensions of the capacitor trenches 111 mainly refer to their length. As an example, a pair of oppositely arranged and laterally extending capacitor trench groups 110 includes three capacitor trenches 111 of the same size, and another pair of oppositely arranged and longitudinally extending capacitor trench groups 110 includes two capacitor trenches 111 of the same size, wherein the length of the laterally extending capacitor trenches 111 is greater than the length of the longitudinally extending capacitor trenches 111.
[0038] In some embodiments, the width of the capacitor trench 111 is 0.5 μm-1 μm, the length is 2 μm-20 μm, and the depth is 5 μm-30 μm. The spacing between adjacent capacitor trenches 111 is 0.2 μm-1 μm. As an example, Figure 1 The transverse capacitor trench 111 has a width of 0.5μm, a length of 6μm, and a depth of 8μm. The longitudinal capacitor trench 111 has a width of 0.5μm, a length of 3μm, and a depth of 8μm. The trench spacing between the transverse capacitor trench 111 and the longitudinal capacitor trench 111 is 0.5μm.
[0039] Figure 2 This is a layout diagram of the semiconductor structure according to an embodiment of this application. To facilitate understanding of the distribution of capacitor trenches and electrodes, the shielding film layer on the surface of each electrode has been removed. Figure 3 for Figure 2 Sectional view at point AA. Figure 4 for Figure 2 Sectional view at point BB. Figure 5 for Figure 2 Sectional view at point CC.
[0040] Combination Figures 2 to 5 Each capacitor trench 111 has a capacitor structure formed therein, the capacitor structure including an upper electrode 330, a middle electrode 320 and a lower electrode 310. The lower electrode 310 continuously covers the inner wall of the capacitor trench 111, the semiconductor substrate 100 between the capacitor trenches 111 and a portion of the semiconductor substrate 100 on both sides of the capacitor trench group 110.
[0041] The intermediate electrode 320 is located on a portion of the lower electrode 310 and is continuously distributed within any capacitor trench group 110. The intermediate electrode 320 forms a first stepped shape with the lower electrode 310 on both sides of each capacitor trench group 110. Figure 3 and Figure 5 In this context, the two sides of the capacitor trench group 110 are the left and right sides. The purpose of designing it in a first-step shape is to expose a portion of the lower electrode 310 on the middle electrode 320, allowing a conductive structure to be formed on the surface of the exposed portion of the lower electrode 310. This design also allows for a larger exposed surface area of the lower electrode 310, thereby allowing for a larger contact area between the conductive structure and the lower electrode 310, resulting in a larger conductive area and thus helping to reduce ESR.
[0042] The upper electrode 330 is located on a portion of the middle electrode 320 and is continuously distributed within any capacitor trench group 110. On the outer side of each capacitor trench group 110, it is coplanar with the sidewall of the middle electrode 320, while on the inner side of each capacitor trench group 110, it forms a second stepped shape with the middle electrode 320. Figure 3 and Figure 5In this configuration, the outer side of the capacitor trench group 110 is also the left side of the capacitor trench group 110, and the inner side of the capacitor trench group 110 is also the right side of the capacitor trench group 110. This structure allows the middle electrode 320 to have a larger exposed area, thereby allowing subsequent processes to form a wire structure with a larger contact area on the exposed surface of the middle electrode 320, improving the device's ESR. In some embodiments, several capacitor trench groups 110 are arranged in a quadrilateral shape, and the exposed surface of the middle electrode 320 on the inner side of the capacitor trench group 110 has a ring-shaped structure, such as... Figure 2 As shown.
[0043] refer to Figures 3 to 5 In each capacitor trench 111, a first dielectric layer 210 for insulating purposes may be included between the lower electrode 310 and the semiconductor substrate 100. A second dielectric layer 220 for insulating purposes may be included between the middle electrode 320 and the lower electrode 310. A third dielectric layer 230 for insulating purposes may be included between the middle electrode 320 and the upper electrode 330. The materials of the first dielectric layer 210, the second dielectric layer 220, and the third dielectric layer 230 may be the same or different. As an example, the materials of the first dielectric layer 210, the second dielectric layer 220, and the third dielectric layer 230 include silicon oxide.
[0044] In order to bring out the upper electrode 330, middle electrode 320 and upper electrode 310 of each capacitor trench 111, the wire structure of each electrode also needs to be designed. At the same time, the wire structure should have the shortest possible conductive path.
[0045] Continue to refer to Figures 3 to 5 A first lead layer 410 is formed on the surface of a portion of the upper electrode 330 on each of the capacitor trench groups 110. The first lead layer 410 is used to lead out the corresponding upper electrode 330. The first lead layer 410 extends in the same direction as the corresponding capacitor trench group 110. The first lead layer 410 can be a continuous structure or a discontinuous structure. In some embodiments, the first lead layer 410 spans over two capacitor trenches of the corresponding capacitor trench group. As an example, the first lead layer 410 is elongated. The width of the first lead layer 410 can be 0.2 μm-2 μm, and the length can be 2 μm-20 μm. When the length and width are within the above ranges, the contact area between the first lead layer 410 and the upper electrode 330 can be large, thereby significantly increasing the conduction area of the conductive structure and helping to reduce ESR.
[0046] refer to Figure 6The first lead layer 410 can also be a discontinuous structure, formed by several short first lead layer units 411 connected in parallel. The number of first lead layer units 411 is not specifically limited, but depends on the length of each first lead layer unit 411. If the length of each first lead layer unit 411 is short, the number can be more; if the length of each first lead layer unit 411 is long, the number can be appropriately reduced to meet the requirements of the conductive area.
[0047] Combination Figure 2 , 3 and Figure 5 A second lead layer 420 is further formed on the surface of the intermediate electrode 320 at a second stepped position inside each capacitor trench group 110. The second lead layer 420 is used to lead out the intermediate electrode 320. In some embodiments, the surface of the intermediate electrode 320 exposed inside the capacitor trench group 110 has a ring-shaped structure, so a ring-shaped second lead layer 420 can be formed on the exposed surface of the intermediate electrode 320. The ring-shaped second lead layer 420 can have a large conductive area and can also effectively reduce the conductive path. In some embodiments, the width of the ring structure can be 0.2 μm-1 μm.
[0048] To maximize the conductive area, the second lead layer 420 can be a continuous ring structure. However, in some embodiments, the second lead layer 420 can also be a discontinuous ring structure, such as... Figure 7 As shown. The second lead layer 420 includes a plurality of short, spaced-apart second lead layer units 421. The number of second lead layer units 421 is not specifically limited, but depends on the length of each second lead layer unit 421. If the length of each second lead layer unit 421 is short, the number will be more; if the length of each second lead layer unit 421 is long, the number can be appropriately reduced to meet the requirements for conductive area.
[0049] Combination Figure 2 , Figure 3 and Figure 5 and Figure 7 A third lead layer 430 is further formed on a portion of the lower electrode surface at the first step position on both sides of each of the capacitor trench groups 110. The third lead layer 430 is used to lead out the lower electrode 310. The third lead layers 430 located on the outer side of each capacitor trench group 110 are not connected to each other and extend in the same direction as the corresponding capacitor trench group 110. In some embodiments, the width of the third lead layer 430 on the outer side of each capacitor trench group 110 is 0.2 μm-1 μm, and the length is 2 μm-20 μm.
[0050] Each of the capacitor trench groups 110 shares a third lead layer 430 on its inner side, and the extension direction is the same as that of a portion of the capacitor trench groups 110. For example, the extension direction of the shared third lead layer 430 is the same as that of the transverse capacitor trench groups 110. The width of the shared third lead layer on the inner side of each capacitor trench group is 0.2 μm-2 μm, and the length is 2 μm-20 μm, to maximize the conductive area of the third lead layer 430.
[0051] refer to Figure 2 , Figure 4 and Figure 6 In some embodiments, the upper electrode 330 forms a third-step shape with the middle electrode 320 at both ends of each capacitor trench group 110, and a fourth lead layer 440 is formed on the surface of a portion of the middle electrode 320 at the third-step position, with adjacent ends of adjacent capacitor trench groups 110 sharing a single fourth lead layer 440. The fourth lead layer 440 is used to lead out the middle electrode 320. The cross-sectional area of the fourth lead layer 440 can be 0.25 μm. 2 -4μm 2 This maximizes the conductive area of the fourth lead layer 440. The cross-sectional shape of the fourth lead layer 440 can be any shape, for example, it can be square.
[0052] In some embodiments, the top surfaces of the first lead layer 410, the second lead layer 420, the third lead layer 430, and the fourth lead layer 440 are coplanar. In some embodiments, a first conductor layer 510 is formed on the surface of the first lead layer 410, a second conductor layer 520 is formed on the surface of the second lead layer 420, a third conductor layer 530 is formed on the surface of the third lead layer 430, and a fourth conductor layer 540 is further formed on the surface of the fourth lead layer 440. The first conductor layer 510, the second conductor layer 520, the third conductor layer 530, and the fourth conductor layer 540 are made of conductive materials, and the materials of each conductor layer may be the same or different.
[0053] In some embodiments, a dielectric layer 600 is further included. The dielectric layer 600 is located on the surface of the semiconductor substrate 100 and each electrode layer, and the surface of the dielectric layer 600 is coplanar with the surface of each conductor layer. The dielectric layer 600 serves as an electrical insulator. The material of the dielectric layer 600 may include silicon nitride.
[0054] Tests have shown that capacitors employing the semiconductor structure of this application can reduce ESR to below 50mΩ.
[0055] In summary, the embodiments of this application, on the one hand, can minimize the conductive path of each electrode and effectively reduce the inherent resistance of each electrode by optimizing the layout of the capacitor trench and combining it with the structural settings of each electrode; on the other hand, by designing the lead structure, the conductive area of the conductive structure can be increased, and the charge can be carried between the electrodes with the maximum parallelism on the conductive path, thereby significantly reducing the ESR of the capacitor.
[0056] After reading this application, those skilled in the art will understand that the foregoing content is presented by way of example only and is not restrictive. Although not explicitly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. Such changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of this application.
[0057] It should be understood that the term "and / or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be an intermediate element.
[0058] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it may be directly on that other element, or there may be intermediate elements present. Conversely, the term "directly" means without intermediate elements. It should also be understood that the terms "comprising," "including," "including," or "comprises," as used in this application, indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.
[0059] It should also be understood that although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of this application, a first element in some embodiments may be referred to as a second element in other embodiments. The same reference numerals or the same reference signs denote the same elements throughout the specification.
[0060] Furthermore, this application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Therefore, differences from the illustrated shapes are foreseeable due to factors such as manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in shape caused, for example, by manufacturing processes. For instance, etched areas shown as rectangular typically have circular or curved features. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to illustrate the actual shape of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.
Claims
1. A semiconductor structure, characterized in that, Includes at least one capacitor trench unit, the capacitor trench unit comprising: A plurality of capacitor trench groups located in a semiconductor substrate, the plurality of said capacitor trench groups being arranged around a specific position, each said capacitor trench group including at least two parallel capacitor trenches. Each of the aforementioned capacitor trenches forms a capacitor structure comprising an upper electrode, a middle electrode, and a lower electrode; wherein, The lower electrode continuously covers the inner wall of the capacitor trench, the semiconductor substrate between the capacitor trenches, and a portion of the semiconductor substrate on both sides of the capacitor trench group. The middle electrode is located on a portion of the lower electrode and is continuously distributed within any capacitor trench group, and is in a first stepped shape with the lower electrode on both sides of each capacitor trench group; The upper electrode is located on a portion of the middle electrode and is continuously distributed within any capacitor trench group. On the outer side of each capacitor trench group, it is located on the same plane as the sidewall of the middle electrode, while on the inner side of each capacitor trench group, it forms a second step shape with the middle electrode.
2. The semiconductor structure according to claim 1, characterized in that, A first lead layer is also formed on a portion of the upper electrode surface of each of the capacitor trench groups; a second lead layer is also formed on a portion of the middle electrode surface at a second stepped position inside each of the capacitor trench groups; and a third lead layer is also formed on a portion of the lower electrode surface at a first stepped position on both sides of each of the capacitor trench groups.
3. The semiconductor structure according to claim 2, characterized in that, The first lead layer extends in the same direction as the corresponding capacitor trench group, and the first lead layer can be a continuous structure or a discontinuous structure.
4. The semiconductor structure according to claim 3, characterized in that, The first lead layer spans over the two capacitor trenches of the corresponding capacitor trench group.
5. The semiconductor structure according to claim 4, characterized in that, The width of the first lead layer is 0.2μm-2μm, and the length is 2μm-20μm.
6. The semiconductor structure according to claim 2, characterized in that, The second lead layer is a continuous or discontinuous ring structure.
7. The semiconductor structure according to claim 6, characterized in that, The width of the annular structure is 0.2μm-1μm.
8. The semiconductor structure according to claim 2, characterized in that, The third lead layers on the outer side of each capacitor trench group are not connected to each other; the inner side of each capacitor trench group shares a third lead layer.
9. The semiconductor structure according to claim 8, characterized in that, The third lead layer on the outer side of each capacitor trench group extends in the same direction as the corresponding capacitor trench group; the third lead layer shared on the inner side of each capacitor trench group extends in the same direction as a portion of the capacitor trench groups.
10. The semiconductor structure according to claim 9, characterized in that, The width of the third lead layer on the outer side of each capacitor trench group is 0.2μm-1μm, and the length is 2μm-20μm; the width of the third lead layer shared on the inner side of each capacitor trench group is 0.2μm-2μm, and the length is 2μm-20μm.
11. The semiconductor structure according to claim 2, characterized in that, The upper electrode forms a third step with the middle electrode at both ends of each capacitor trench group, and a fourth lead layer is formed on a portion of the surface of the middle electrode at the third step position, and adjacent ends of adjacent capacitor trench groups share a fourth lead layer.
12. The semiconductor structure according to claim 11, characterized in that, The cross-sectional area of the fourth lead layer is 0.25 μm. 2 -4μm 2 .
13. The semiconductor structure according to claim 11, characterized in that, The top surfaces of the first lead layer, the second lead layer, the third lead layer, and the fourth lead layer are coplanar.
14. The semiconductor structure according to claim 13, characterized in that, A conductor layer is formed on the surface of the first lead layer, the second lead layer, the third lead layer and the fourth lead layer.
15. The semiconductor structure according to claim 1, characterized in that, Opposite capacitor trench groups have the same size, and capacitor trenches within the same capacitor trench group have the same size.
16. The semiconductor structure according to claim 1, characterized in that, The lower electrode and the semiconductor substrate are further provided with a first dielectric layer, the lower electrode and the middle electrode are further provided with a second dielectric layer, and the middle electrode and the upper electrode are further provided with a third dielectric layer.