Hydrogen-terminated diamond / gallium oxide hetero-integrated complementary device and method of manufacture
By using hydrogen-terminated diamond/gallium oxide heterogeneous complementary devices, combining diamond PMOS and gallium oxide NMOS, the doping problem of CMOS inverters was solved, realizing high-performance CMOS devices suitable for ultra-high temperature and high radiation environments.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- XIDIAN UNIV
- Filing Date
- 2022-12-01
- Publication Date
- 2026-07-07
AI Technical Summary
Existing technologies make it difficult to simultaneously achieve n-type doping of diamond and p-type doping of gallium oxide, both ultra-wide bandgap semiconductor materials, which makes it difficult to fabricate CMOS inverters.
A CMOS device is fabricated by combining hydrogen-terminated diamond/gallium oxide heterogeneous complementary devices on the same substrate, utilizing the high thermal conductivity of diamond and the high breakdown field strength of gallium oxide.
A high-performance CMOS inverter was achieved, suitable for applications in ultra-high temperature and high-irradiation environments. The device's heat dissipation performance and switching speed were improved, and the doping problem was solved.
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Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor device technology, specifically relating to a hydrogen-terminated diamond / gallium oxide heterogeneous integrated complementary device and its fabrication method. Background Technology
[0002] In recent years, to adapt to market application demands, the pace of semiconductor material upgrading has accelerated: from first-generation semiconductor materials represented by silicon (Si) and germanium (Ge), to second-generation semiconductor materials mainly based on gallium arsenide (AsGa), and then to third-generation semiconductor materials such as gallium nitride (GaN) and silicon carbide (SiC), which are currently widely used, progressing towards wider bandgap and broader application scenarios. In recent years, ultra-wide bandgap semiconductor materials such as diamond and gallium oxide (Ga2O3) have gradually come into focus.
[0003] Compared to previous generations of semiconductor materials, gallium oxide (Ga₂O₃) possesses a larger bandgap (4.6–4.9 eV) and a higher breakdown field strength (8 MV / cm). Furthermore, its Baliga figure of merit is as high as 3000, four times that of gallium nitride (GaN) and ten times that of silicon carbide (SiC). In addition, gallium oxide (Ga₂O₃) exhibits relatively stable other physicochemical properties, including electrical and luminescent properties. In terms of material growth and fabrication, gallium oxide can be grown over large areas while maintaining low dislocation rates, highlighting its significant advantage in low cost. However, several problems remain to be solved in the application of gallium oxide materials. On the one hand, taking the widely used β-Ga2O3 as an example, it contains many donor defects, such as oxygen vacancies, gallium vacancies, interstitial oxygen and interstitial gallium, which gives it a certain n-type conductivity, making it relatively easy to achieve high-quality n-type doping and use it to fabricate high-performance n-type devices. However, achieving high-quality p-type doping of β-Ga2O3 becomes very difficult. In addition, gallium oxide materials have extremely low thermal conductivity, which will lead to a reduction in device performance due to thermal effects in practical applications.
[0004] Diamond, also a type of ultrawide bandgap semiconductor material, has a large bandgap (5.47 eV), high breakdown field strength (10 MV / cm), and high carrier mobility (electrons 4500 cm⁻¹). 2 / V·s, cavity 3800cm 2 With a high thermal conductivity (22 W / cm·K) and an extremely high Baliga figure of merit, it is well-suited for use in harsh environments. Studies have found that when hydrogen-terminated diamond treated with hydrogen plasma is exposed to air for a period of time, a layer of two-dimensional cavitation gas (2DHG) forms on its surface, exhibiting p-type conductivity, with a hole concentration typically around 10⁻⁶ V·s. 12 -10 14 cm-2 The surface hole mobility is generally around 300 cm⁻¹. 2 It has a density of approximately / V·s, making it suitable for fabricating high-performance p-type field-effect transistors. However, its n-type doping is difficult to achieve.
[0005] As a crucial component in logic circuit applications, the design of CMOS inverters has always been a research hotspot. In applications, CMOS inverters offer advantages such as low static power consumption, large output swing, and strong anti-interference capabilities. However, for traditional Si-based CMOS inverters, existing ultra-wide bandgap semiconductors struggle to simultaneously achieve the n-type and p-type doping required for CMOS device fabrication. Summary of the Invention
[0006] To address the aforementioned problems in the prior art, this invention provides a hydrogen-terminated diamond / gallium oxide heterostructure integrated complementary device and its fabrication method. The technical problem to be solved by this invention is achieved through the following technical solution:
[0007] This invention provides a hydrogen-terminated diamond / gallium oxide heterogeneous complementary device, comprising: a diamond substrate layer, a gallium oxide substrate layer, a first source electrode, a first drain electrode, a first dielectric layer, a first gate electrode, a hydrogen-terminated surface layer, a second source electrode, a second drain electrode, a second dielectric layer, and a second gate electrode, wherein...
[0008] The gallium oxide substrate is located on one side of the diamond substrate, the first source electrode is located on one side of the gallium oxide substrate, the first drain electrode is located on the other side of the gallium oxide substrate, the first dielectric layer covers the upper surface and inner side of the first source electrode, the upper surface and inner side of the first drain electrode and the upper surface of the gallium oxide substrate, and the first gate electrode is located on the first dielectric layer between the first source electrode and the first drain electrode.
[0009] The hydrogen terminal surface layer is located on the other side of the diamond substrate layer, the second source electrode is located on one side of the hydrogen terminal surface layer, the second drain electrode is located on the other side of the hydrogen terminal surface layer, the second dielectric layer covers the upper surface and inner side of the second source electrode, the upper surface and inner side of the second drain electrode, and the upper surface of the hydrogen terminal surface layer, and the second gate electrode is located on the second dielectric layer between the second source electrode and the second drain electrode.
[0010] In one embodiment of the present invention, the material of the diamond substrate layer includes single-crystal diamond with a thickness of 500-600 μm.
[0011] In one embodiment of the present invention, the thickness of the gallium oxide substrate layer is 1-2 μm; the material of the first source electrode includes one or more of Ti, Al, Ni, and Au, and the thickness is 250 nm; the material of the first drain electrode includes one or more of Ti, Al, Ni, and Au, and the thickness is 250 nm; the material of the first dielectric layer includes SiO2, and the thickness is 15-20 nm; the material of the first gate electrode includes one or more of Ni and Au, and the thickness is 180 nm.
[0012] In one embodiment of the present invention, the thickness of the hydrogen terminal surface layer is 2-3 nm; the material of the second source electrode includes Au and the thickness is 60-120 nm; the material of the second drain electrode includes Au and the thickness is 60-120 nm; the material of the second dielectric layer includes Al2O3 and the thickness is 15-20 nm; and the material of the second gate electrode includes Al and the thickness is 60-120 nm.
[0013] In one embodiment of the present invention, the first drain electrode and the second drain electrode are connected by a first lead, the first gate electrode and the second gate electrode are connected by a second lead, the first source electrode is grounded, and the second source electrode is connected to the power supply voltage.
[0014] Another embodiment of the present invention provides a method for fabricating a hydrogen-terminated diamond / gallium oxide heterostructure complementary device, comprising the steps of:
[0015] S1. Prepare a hydrogen terminal surface layer on a diamond substrate, and deposit a first protective layer and a second protective layer on the hydrogen terminal surface layer;
[0016] S2. Etch away the second protective layer and the first protective layer in the NMOS device area until the hydrogen terminal surface layer is exposed, and wait for the exposed hydrogen terminal surface layer to degrade to expose the diamond substrate layer.
[0017] S3. Transfer the gallium oxide substrate layer onto the exposed diamond substrate layer;
[0018] S4. A first source electrode and a first drain electrode are fabricated on the gallium oxide substrate, such that the first source electrode is located on one side of the gallium oxide substrate and the first drain electrode is located on the other side of the gallium oxide substrate.
[0019] S5. Erode away the remaining second protective layer and the first protective layer to expose the remaining hydrogen terminal surface layer;
[0020] S6. Deposit an electrode metal layer on the exposed hydrogen terminal surface layer;
[0021] S7. Deposit a gate oxide dielectric material on the surface of the gallium oxide substrate, the surface of the first source electrode and the surface of the first drain electrode to obtain a first dielectric layer;
[0022] S8. Deposit gate metal on the first dielectric layer between the first source electrode and the first drain electrode to obtain the first gate electrode;
[0023] S9. Etch the electrode metal layer on the surface layer of the hydrogen terminal to form a second source electrode and a second drain electrode, such that the second source electrode is located on one side of the surface layer of the hydrogen terminal and the second drain electrode is located on the other side of the surface layer of the hydrogen terminal.
[0024] S10. Deposit a gate oxide dielectric material on the surface of the hydrogen terminal surface layer, the surface of the second source electrode and the surface of the second drain electrode to obtain a second dielectric layer;
[0025] S11. Deposit gate metal on the second dielectric layer between the second source electrode and the second drain electrode to obtain the second gate electrode.
[0026] In one embodiment of the present invention, step S1 includes:
[0027] The surface of the diamond substrate is treated with hydrogen plasma using an MPCVD device to form the hydrogen-terminated surface layer.
[0028] SiO2 is deposited on the surface layer of the hydrogen terminal to form a first protective layer;
[0029] Au is deposited on the first protective layer to form a second protective layer.
[0030] In one embodiment of the present invention, step S2, which involves etching away the second protective layer and the first protective layer in the NMOS device region until the hydrogen terminal surface layer is exposed, includes:
[0031] The Au material of the second protective layer is etched away using an I2 solution of KI, and the SiO2 material of the first protective layer is etched away using an acid solution until the hydrogen terminal surface layer is exposed.
[0032] In one embodiment of the present invention, the electrode metal layer is made of Au and has a thickness of 60-120 nm.
[0033] In one embodiment of the present invention, step S11 is followed by the following step:
[0034] S12. A first lead is fabricated on the surface of the device to connect the first drain electrode and the second drain electrode, and a second lead is fabricated to connect the first gate electrode and the second gate electrode.
[0035] Compared with the prior art, the beneficial effects of the present invention are as follows:
[0036] 1. This invention combines hydrogen-terminated diamond PMOS and gallium oxide NMOS to fabricate ultra-wide bandgap semiconductor CMOS devices using a heterogeneous integration method. This effectively solves the key problems of achieving n-type doping in diamond and p-type doping in gallium oxide, ensuring the high performance of each device and the overall high quality. It realizes a high-performance ultra-wide bandgap semiconductor CMOS inverter suitable for ultra-high temperature and strong radiation environments.
[0037] 2. This invention uses a heterogeneous integration method to fabricate NMOS and PMOS on the same substrate, which reduces the device spacing and improves the switching speed.
[0038] 3. In this invention, diamond, as an ultrawide bandgap semiconductor material with high thermal conductivity, is applied to CMOS substrates, which significantly improves the heat dissipation performance of the device and effectively solves the problem of low thermal conductivity of gallium oxide materials. Attached Figure Description
[0039] Figure 1 This is a schematic diagram of the structure of a hydrogen-terminated diamond / gallium oxide heterostructure integrated complementary device provided in an embodiment of the present invention;
[0040] Figures 2a-2k This is a schematic diagram illustrating the process of fabricating a hydrogen-terminated diamond / gallium oxide heterostructure complementary device according to an embodiment of the present invention. Detailed Implementation
[0041] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.
[0042] Example 1
[0043] Please see Figure 1 , Figure 1 This is a schematic diagram of a hydrogen-terminated diamond / gallium oxide heterogeneous complementary device provided in an embodiment of the present invention. The CMOS inverter includes a diamond substrate 10, a gallium oxide substrate 19, a first source electrode 18, a first drain electrode 15, a first dielectric layer 16, a first gate electrode 17, a hydrogen-terminated surface layer 20, a second source electrode 11, a second drain electrode 14, a second dielectric layer 13, and a second gate electrode 12. The gallium oxide substrate 19, the first source electrode 18, the first drain electrode 15, the first dielectric layer 16, and the first gate electrode 17 form a Ga2O3 NMOS device, while the hydrogen-terminated surface layer 20, the second source electrode 11, the second drain electrode 14, the second dielectric layer 13, and the second gate electrode 12 form a hydrogen-terminated diamond PMOS device. The Ga2O3 NMOS device and the hydrogen-terminated diamond PMOS device are separated by a distance and do not contact each other.
[0044] In the Ga2O3 NMOS device, the gallium oxide substrate 19 is located on one side of the diamond substrate 10, the first source electrode 18 is located on one side of the gallium oxide substrate 19, the first drain electrode 15 is located on the other side of the gallium oxide substrate 19, the first dielectric layer 16 covers the upper surface and inner side of the first source electrode 18, the upper surface and inner side of the first drain electrode 15, and the upper surface of the gallium oxide substrate 19, and the first gate electrode 17 is located on the first dielectric layer 16 between the first source electrode 18 and the first drain electrode 15.
[0045] In a hydrogen-terminated diamond PMOS device, the hydrogen terminal surface layer 20 is located on the other side of the diamond substrate layer 10, the second source electrode 11 is located on one side of the hydrogen terminal surface layer 20, the second drain electrode 14 is located on the other side of the hydrogen terminal surface layer 20, the second dielectric layer 13 covers the upper surface and inner side of the second source electrode 11, the upper surface and inner side of the second drain electrode 14, and the upper surface of the hydrogen terminal surface layer 20, and the second gate electrode 12 is located on the second dielectric layer 13 between the second source electrode 11 and the second drain electrode 14.
[0046] Specifically, the diamond substrate 10 is made of single-crystal diamond with a thickness of 500-600 μm.
[0047] Specifically, in the Ga2O3 NMOS device, the thickness of the gallium oxide substrate layer 19 is 1-2 μm; the material of the first source electrode 18 includes one or more of Ti, Al, Ni, and Au, and the thickness is 250 nm. For example, the material of the first source electrode 18 is a stacked structure of Ti, Al, Ni, and Au stacked from bottom to top, with a thickness of 20 / 140 / 50 / 40 nm; the material of the first drain electrode 15 includes one or more of Ti, Al, Ni, and Au, and the thickness is 250 nm. For example, the material of the first drain electrode 15 is a stacked structure of Ti, Al, Ni, and Au stacked from bottom to top, with a thickness of 20 / 140 / 50 / 40 nm; the material of the first dielectric layer 16 includes SiO2, and the thickness is 15-20 nm; the material of the first gate electrode 17 includes one or more of Ni and Au, and the thickness is 180 nm. For example, the material of the first gate electrode 17 is a stacked structure of Ni and Au stacked from bottom to top, with a thickness of 60 / 120 nm.
[0048] Specifically, in the hydrogen-terminated diamond PMOS device, the thickness of the hydrogen-terminated surface layer 20 is 2-3 nm; the material of the second source electrode 11 includes Au, with a thickness of 60-120 nm; the material of the second drain electrode 14 includes Au, with a thickness of 60-120 nm; the material of the second dielectric layer 13 includes Al2O3, with a thickness of 15-20 nm; and the material of the second gate electrode 12 includes Al, with a thickness of 60-120 nm.
[0049] Specifically, in the above-mentioned device, the first drain electrode 15 and the second drain electrode 14 are interconnected through the first lead 21, and the first gate electrode 17 and the second gate electrode 12 are interconnected through the second lead 22. When using this device, the first source electrode 18 is grounded, and the second source electrode 11 is connected to the power supply voltage.
[0050] This embodiment combines hydrogen-terminated diamond PMOS and gallium oxide NMOS to fabricate an ultra-wide bandgap semiconductor CMOS device using a heterogeneous integration method. This effectively solves the key challenges of achieving n-type doping in diamond and p-type doping in gallium oxide, ensuring the high performance of each device and the overall high quality. This is of great significance to the development of ultra-wide bandgap semiconductors and integrated circuits.
[0051] This embodiment uses a heterogeneous integration method to fabricate NMOS and PMOS on the same substrate, reducing the device spacing and improving the switching speed.
[0052] In this embodiment, diamond, as an ultrawide bandgap semiconductor material with high thermal conductivity, is applied to a CMOS substrate, which significantly improves the heat dissipation performance of the device and effectively solves the problem of low thermal conductivity of gallium oxide material. This enables a high-performance ultrawide bandgap semiconductor CMOS inverter suitable for ultra-high temperature and strong radiation environments.
[0053] Example 2
[0054] Based on Example 1, please refer to Figures 2a-2k , Figures 2a-2k This is a schematic diagram illustrating a process for fabricating a hydrogen-terminated diamond / gallium oxide heterogeneous complementary device according to an embodiment of the present invention. The fabrication method includes the following steps:
[0055] S1. A hydrogen-terminated surface layer 20 is prepared on a diamond substrate 10, and a first protective layer 30 and a second protective layer 40 are deposited on the hydrogen-terminated surface layer 20, such as... Figure 2a As shown. The specific steps include:
[0056] First, the surface of the diamond substrate 10 is treated with hydrogen plasma using an MPCVD device to form a hydrogen-terminated surface layer 20.
[0057] Then, SiO2 is deposited on the hydrogen terminal surface layer 20 to form a first protective layer 30. Optionally, the thickness of the SiO2 is 200 nm.
[0058] Finally, Au is deposited on the first protective layer 30 to form the second protective layer 40. Optionally, the thickness of Au is 100 nm.
[0059] In this embodiment, since the hydrogen terminal surface layer 20 has poor stability and the process of gallium oxide NMOS device is long, two protective layers are prepared to protect the hydrogen terminal surface layer 20 in order to ensure the performance of the hydrogen terminal surface layer 20.
[0060] S2. Etch away the second protective layer 40 and the first protective layer 30 in the NMOS device region until the hydrogen terminal surface layer 20 is exposed, and wait for the exposed hydrogen terminal surface layer 20 to degrade to expose the diamond substrate layer 10, as shown. Figure 2b As shown.
[0061] Specifically, firstly, the Au material of the second protective layer 40 is etched away using a KI I2 solution. Then, the SiO2 material of the first protective layer 30 is etched away using an acid solution until the hydrogen-terminated surface layer 20 is exposed. Finally, the exposed hydrogen-terminated surface layer 20 is allowed to naturally degrade until the diamond substrate layer 10 is exposed.
[0062] S3. Transfer the gallium oxide substrate 19 onto the exposed diamond substrate 10, as follows: Figure 2c As shown.
[0063] Specifically, the pre-prepared gallium oxide substrate 19 is transferred onto the exposed diamond substrate 10, so that it is a certain distance away from the hydrogen terminal surface layer 20.
[0064] S4. A first source electrode 18 and a first drain electrode 15 are fabricated on the gallium oxide substrate 19, such that the first source electrode 18 is located on one side of the gallium oxide substrate 19, and the first drain electrode 15 is located on the other side of the gallium oxide substrate 19. Figure 2d As shown.
[0065] Specifically, firstly, a Ti / Al / Ni / Au alloy layer with a thickness of 250 nm (20 / 140 / 50 / 40) is deposited on a gallium oxide substrate 19; photoresist is coated and spin-spinned onto the Ti / Al / Ni / Au alloy, and then baked on a 100°C hot plate for 90 seconds; the device is placed in a photolithography machine to expose the photoresist in the active region, and the exposed device is then developed in a developer for 30 seconds to remove the photoresist outside the active region. After cleaning, it is dried with a nitrogen gun; the metal in the areas without photoresist is etched away until the gallium oxide surface is exposed, forming the active region. The process involves: applying and spinning photoresist onto the metal layer, then baking it on a hot plate at 100°C for 90 seconds; placing the device in a photolithography machine to expose the photoresist in the corresponding areas of the first source electrode and the first drain electrode; immersing the exposed device in a developing solution to remove the photoresist outside the source and drain electrode areas, washing it, and then drying it with a nitrogen gun; etching away the metal in the areas without photoresist until the Ga2O3 surface is exposed, forming the first source electrode 18 and the first drain electrode 15; and annealing the metal layer at 470°C in a N2 atmosphere for 60 seconds to form the ohmic contact between the first source electrode 18 and the first drain electrode 15.
[0066] S5. Erode away the remaining second protective layer 40 and the first protective layer 30, exposing the remaining hydrogen terminal surface layer 20.
[0067] Specifically, firstly, the Au material of the second protective layer 40 is etched away using a KI I2 solution. Then, the SiO2 material of the first protective layer 30 is etched away using an acid solution until the hydrogen-terminated surface layer 20 is exposed.
[0068] S6. Deposit an electrode metal layer 50 on the exposed hydrogen terminal surface layer 20, such as... Figure 2e As shown.
[0069] Specifically, using photoresist 60 located on gallium oxide substrate 19, first source electrode 18 and first drain electrode 15, a layer of Au with a thickness of 60-120 nm is deposited on hydrogen terminal surface layer 20, optionally with an Au thickness of 100 nm, to form electrode metal layer 50.
[0070] S7. Deposit gate oxide dielectric material on the surface of gallium oxide substrate 19, the surface of the first source electrode 18, and the surface of the first drain electrode 15 to obtain the first dielectric layer 16, such as... Figure 2f As shown.
[0071] Specifically, an ALD process is used to deposit a 20nm thick SiO2 layer on the surface of the gallium oxide substrate 19, the surface of the first source electrode 18, and the surface of the first drain electrode 15, forming a first dielectric layer 16 covering the upper and inner surfaces of the first source electrode 18, the upper and inner surfaces of the first drain electrode 15, and the upper surface of the gallium oxide substrate 19.
[0072] S8. Deposit gate metal on the first dielectric layer 16 between the first source electrode 18 and the first drain electrode 15 to obtain the first gate electrode 17, as shown. Figure 2g As shown.
[0073] Specifically, photoresist is applied and spin-coated onto the first dielectric layer 16, and then baked on a hot plate at 100°C for 90 seconds. The device is placed in a photolithography machine to expose the photoresist in the area corresponding to the gate strip. The exposed device is then placed in a developing solution for 35 seconds to remove the photoresist in the area corresponding to the gate strip. After cleaning, the device is dried with a nitrogen gun. A Ni / Au alloy layer is deposited on the device surface as the gate metal, and finally, the first gate electrode 17 is obtained by stripping.
[0074] S9. Erode the electrode metal layer 50 on the hydrogen terminal surface layer 20 to form a second source electrode 11 and a second drain electrode 14, such that the second source electrode 11 is located on one side of the hydrogen terminal surface layer 20, and the second drain electrode 14 is located on the other side of the hydrogen terminal surface layer 20. Figure 2h As shown.
[0075] Specifically, photoresist is applied and spun onto the electrode metal layer 50, and then baked on a hot plate. The device is placed in a lithography machine to expose the photoresist in the corresponding area of the active region. After exposure, the device is placed in a developing solution to remove the photoresist outside the active region, washed, and dried with a nitrogen gun. The metal in the areas without photoresist is etched away until the diamond surface is exposed, forming the active region. Photoresist is applied and spun onto the electrode metal layer 50, and then baked on a hot plate. The device is placed in a lithography machine to expose the photoresist in the corresponding areas of the second source electrode and the second drain electrode. After exposure, the device is placed in a developing solution to remove the photoresist outside the source and drain electrode areas, washed, and dried with a nitrogen gun. The metal in the areas without photoresist is etched away until the gallium oxide surface is exposed, forming the second source electrode 11 and the second drain electrode 14.
[0076] S10. Deposit a gate oxide dielectric material on the surface of the hydrogen terminal surface layer 20, the surface of the second source electrode 11, and the surface of the second drain electrode 14 to obtain the second dielectric layer 13, such as... Figure 2i As shown.
[0077] Specifically, using the ALD process, Al2O3 is deposited on the surface of the hydrogen terminal surface layer 20, the surface of the second source electrode 11, and the surface of the second drain electrode 14. The deposition temperature is 300℃, the aluminum source is trimethylaluminum TMA, the oxidant is H2O, and the deposition thickness is 20nm, to obtain the second dielectric layer 13.
[0078] S11. Deposit gate metal on the second dielectric layer 13 between the second source electrode 11 and the second drain electrode 14 to obtain the second gate electrode 12, as shown. Figure 2j As shown.
[0079] Specifically, photoresist is applied and spin-coated onto the second dielectric layer 13, and then baked on a hot plate at 100°C for 90 seconds. The device is placed in a photolithography machine to expose the photoresist in the area corresponding to the gate strip. The exposed device is then placed in a developing solution for 35 seconds to remove the photoresist in the area corresponding to the gate strip. After cleaning, the device is dried with a nitrogen gun. A layer of Al with a thickness of 100 nm is deposited on the surface of the device as the gate metal. Finally, the second gate electrode 12 is obtained by stripping.
[0080] S12. Fabricate a first lead 21 on the device surface to connect the first drain electrode 15 and the second drain electrode 14, and fabricate a second lead 22 to connect the first gate electrode 17 and the second gate electrode 12, as follows: Figure 2k As shown.
[0081] Specifically, metal leads are fabricated to interconnect the first drain electrode 15 and the second drain electrode 14, as well as the first gate electrode 17 and the second gate electrode 12.
[0082] In this embodiment, a gallium oxide MOSFET device was fabricated on a diamond substrate. Utilizing the high thermal conductivity of diamond, it was used as a heat sink, achieving a breakthrough in heat dissipation and cooling for the gallium oxide MOSFET device, effectively expanding its application range. Simultaneously, a MOSFET device was fabricated using the p-type conductivity of hydrogen-terminated diamond, successfully realizing heterogeneous integration of gallium oxide n-type and diamond p-type devices. Furthermore, a CMOS device was successfully fabricated through metal interconnects. In addition, this fabrication method has the advantages of reducing device cost and improving device performance.
[0083] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.
Claims
1. A hydrogen-terminated diamond / gallium oxide heterogeneous complementary device, characterized in that, include: The structure comprises a diamond substrate (10), a gallium oxide substrate (19), a first source electrode (18), a first drain electrode (15), a first dielectric layer (16), a first gate electrode (17), a hydrogen terminal surface layer (20), a second source electrode (11), a second drain electrode (14), a second dielectric layer (13), and a second gate electrode (12), wherein... The gallium oxide substrate (19) is located on one side of the diamond substrate (10) by heterogeneous integration. The first source electrode (18) is located on one side of the gallium oxide substrate (19), and the first drain electrode (15) is located on the other side of the gallium oxide substrate (19). The first dielectric layer (16) covers the upper and inner surfaces of the first source electrode (18), the upper and inner surfaces of the first drain electrode (15), and the upper surface of the gallium oxide substrate (19). The first gate electrode (17) is located on the first dielectric layer (16) between the first source electrode (18) and the first drain electrode (15) to form a gallium oxide NMOS device. The hydrogen terminal surface layer (20) is located on the other side of the diamond substrate layer (10), the second source electrode (11) is located on one side of the hydrogen terminal surface layer (20), the second drain electrode (14) is located on the other side of the hydrogen terminal surface layer (20), the second dielectric layer (13) covers the upper surface and inner side of the second source electrode (11), the upper surface and inner side of the second drain electrode (14) and the upper surface of the hydrogen terminal surface layer (20), and the second gate electrode (12) is located on the second dielectric layer (13) between the second source electrode (11) and the second drain electrode (14) to form a hydrogen terminal diamond PMOS device; The gallium oxide NMOS device and the hydrogen-terminated diamond PMOS device are formed on the same diamond substrate (10) through heterogeneous integration. The first drain electrode (15) and the second drain electrode (14) are connected by a first lead (21), the first gate electrode (17) and the second gate electrode (12) are connected by a second lead (22), the first source electrode (18) is grounded, and the second source electrode (11) is connected to the power supply voltage to form a CMOS inverter.
2. The hydrogen-terminated diamond / gallium oxide heterogeneous complementary device according to claim 1, characterized in that, The diamond substrate (10) is made of single-crystal diamond and has a thickness of 500-600 μm.
3. The hydrogen-terminated diamond / gallium oxide heterogeneous complementary device according to claim 1, characterized in that, The thickness of the gallium oxide substrate layer (19) is 1-2 μm; the material of the first source electrode (18) includes one or more of Ti, Al, Ni, and Au, and the thickness is 250 nm; the material of the first drain electrode (15) includes one or more of Ti, Al, Ni, and Au, and the thickness is 250 nm; the material of the first dielectric layer (16) includes SiO2, and the thickness is 15-20 nm; the material of the first gate electrode (17) includes one or more of Ni and Au, and the thickness is 180 nm.
4. The hydrogen-terminated diamond / gallium oxide heterogeneous complementary device according to claim 1, characterized in that, The hydrogen terminal surface layer (20) has a thickness of 2-3 nm; the material of the second source electrode (11) includes Au and has a thickness of 60-120 nm; the material of the second drain electrode (14) includes Au and has a thickness of 60-120 nm; the material of the second dielectric layer (13) includes Al2O3 and has a thickness of 15-20 nm; the material of the second gate electrode (12) includes Al and has a thickness of 60-120 nm.
5. A method for fabricating a hydrogen-terminated diamond / gallium oxide heterogeneous complementary device, characterized in that, Including the following steps: S1. A hydrogen terminal surface layer (20) is prepared on a diamond substrate (10), and a first protective layer (30) and a second protective layer (40) are deposited on the hydrogen terminal surface layer (20); S2. Etch away the second protective layer (40) and the first protective layer (30) of the NMOS device region until the hydrogen terminal surface layer (20) is exposed, and wait for the exposed hydrogen terminal surface layer (20) to degrade to expose the diamond substrate layer (10). S3. Transfer the gallium oxide substrate (19) onto the exposed diamond substrate (10); S4. A first source electrode (18) and a first drain electrode (15) are prepared on the gallium oxide substrate (19), such that the first source electrode (18) is located on one side of the gallium oxide substrate (19) and the first drain electrode (15) is located on the other side of the gallium oxide substrate (19). S5. Erode away the remaining second protective layer (40) and the first protective layer (30) to expose the remaining hydrogen terminal surface layer (20); S6. Deposit an electrode metal layer (50) on the exposed hydrogen terminal surface layer (20); S7. Deposit gate oxide dielectric material on the surface of the gallium oxide substrate (19), the surface of the first source electrode (18) and the surface of the first drain electrode (15) to obtain a first dielectric layer (16); S8. Deposit gate metal on the first dielectric layer (16) between the first source electrode (18) and the first drain electrode (15) to obtain the first gate electrode (17); S9. Etch the electrode metal layer (50) on the hydrogen terminal surface layer (20) to form a second source electrode (11) and a second drain electrode (14), such that the second source electrode (11) is located on one side of the hydrogen terminal surface layer (20) and the second drain electrode (14) is located on the other side of the hydrogen terminal surface layer (20). S10. Deposit a gate oxide dielectric material on the surface of the hydrogen terminal surface layer (20), the surface of the second source electrode (11) and the surface of the second drain electrode (14) to obtain a second dielectric layer (13); S11. Deposit gate metal on the second dielectric layer (13) between the second source electrode (11) and the second drain electrode (14) to obtain the second gate electrode (12); S12. A first lead (21) is fabricated on the device surface to connect the first drain electrode (15) and the second drain electrode (14), and a second lead (22) is fabricated to connect the first gate electrode (17) and the second gate electrode (12) to form a CMOS inverter; wherein, the gallium oxide substrate layer (19), the first source electrode (18), the first drain electrode (15), the first dielectric layer (16), and the first gate electrode (17) form a Ga2O3 NMOS device, and the hydrogen-terminated surface layer (20), the second source electrode (11), the second drain electrode (14), the second dielectric layer (13), and the second gate electrode (12) form a hydrogen-terminated diamond PMOS device, the first source electrode (18) is grounded, and the second source electrode (11) is connected to the power supply voltage.
6. The method for fabricating a hydrogen-terminated diamond / gallium oxide heterogeneous complementary device according to claim 5, characterized in that, Step S1 includes: The surface of the diamond substrate (10) is treated with hydrogen plasma using an MPCVD device to form the hydrogen terminal surface layer (20); SiO2 is deposited on the hydrogen terminal surface layer (20) to form a first protective layer (30); Au is deposited on the first protective layer (30) to form a second protective layer (40).
7. The method for fabricating a hydrogen-terminated diamond / gallium oxide heterogeneous complementary device according to claim 6, characterized in that, Step S2 involves etching away the second protective layer (40) and the first protective layer (30) of the NMOS device region until the hydrogen terminal surface layer (20) is exposed, including: The Au material of the second protective layer (40) is etched away using an I2 solution of KI, and the SiO2 material of the first protective layer (30) is etched away using an acid solution until the hydrogen terminal surface layer (20) is exposed.
8. The method for fabricating a hydrogen-terminated diamond / gallium oxide heterogeneous complementary device according to claim 5, characterized in that, The electrode metal layer (50) is made of Au and has a thickness of 60-120 nm.