A high-performance TFT array substrate with active layer bridge blocks and its manufacturing method

Abstract

The application relates to the technical field of liquid crystal display screens, and provides a high-performance TFT array substrate with an active layer bridging block and a manufacturing method thereof, which comprises a glass substrate, a first metal layer forming a gate electrode, a gate insulating layer fixedly arranged on the upper surface of the first metal layer and the glass substrate, a left active layer and a right active layer, a bridging layer with the left end and the right end connected with the left active layer and the right active layer respectively, a left etching blocking layer fixedly arranged on the upper surface of the gate insulating layer and the left active layer and provided with a left hole, a right etching blocking layer fixedly arranged on the upper surface of the gate insulating layer and the right active layer and provided with a right hole, a left bridging block fixedly arranged in the left hole, and a right bridging block fixedly arranged in the right hole.The application has the advantages that the active layer channel length is shortened without shortening the source-drain distance of the TFT device, and the TFT array substrate has the advantages of quick response, large on-state current, small threshold voltage and the like.

Description

Technical Field

[0001] The present invention relates to the technical field of liquid crystal display screens, and in particular to a high-performance TFT array substrate with an active layer bridge block and a manufacturing method thereof. Background Art

[0002] With the rapid development of artificial intelligence, TFT-LCD screen technology has also been continuously improved. High definition, fast speed, and low power consumption will become the development trend of TFT-LCD screens.

[0003] To achieve high-performance displays, one of the current manufacturing methods used by manufacturers is to miniaturize TFT devices by shortening the active layer channel length. This shortened active layer channel length can achieve higher on-state current, improve device response speed, and reduce threshold voltage, among other advantages. However, in practice, the design of the active layer channel length is limited to the distance between the source and drain of the TFT device, mainly considering the risk of short circuits if the source and drain are too close. After years of technological development, the source and drain spacing of current thin-film transistors (TFTs) is selected to a safe minimum distance, generally controlled by the industry at 5-6μm.

[0004] See Figure 1 , which is a schematic diagram of the structure of a traditional TFT device. The active layer is a semiconductor, and the active layer channel length refers to the length of the semiconductor from the source to the drain.

[0005] Therefore, how to shorten the active layer channel length without shortening the source-drain distance of the TFT device is a technical problem that needs to be solved urgently in this field. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide a high-performance TFT array substrate with an active layer bridge block and a manufacturing method thereof, which can shorten the active layer channel length without shortening the source-drain distance of the TFT device.

[0007] The present invention is implemented as follows: a high-performance TFT array substrate with an active layer bridge block, comprising:

[0008] glass substrate;

[0009] A first metal layer is fixedly disposed on the upper surface of the glass substrate to form a gate;

[0010] a gate insulating layer fixedly disposed on the upper surfaces of the first metal layer and the glass substrate;

[0011] a left active layer, fixedly disposed on the upper surface of the gate insulating layer and also located above the left end of the first metal layer;

[0012] a right active layer, fixedly disposed on the upper surface of the gate insulating layer and also located above the right end of the first metal layer;

[0013] a bridging layer, fixedly disposed on the upper surface of the gate insulating layer, with left and right ends respectively connected to the left active layer and the right active layer;

[0014] a left etching stop layer, fixedly disposed on the upper surfaces of the gate insulating layer and the left active layer, and further having a left hole;

[0015] a right etching stop layer, fixedly disposed on the upper surfaces of the gate insulating layer and the right active layer, and further having a right hole;

[0016] A left bridging block, fixedly disposed in the left hole;

[0017] a right bridging block, fixedly disposed in the right hole;

[0018] A second metal layer is fixedly disposed on the upper surface of the left etching stop layer and is connected to the left active layer via a left bridge block to form a source electrode;

[0019] a third metal layer, fixedly disposed on the upper surface of the right etching stop layer, and connected to the right active layer via a right bridge block to form a drain;

[0020] The left bridging block, the right bridging block and the bridging layer are all made of the same material.

[0021] Furthermore, it also includes:

[0022] a pixel electrode, fixedly disposed on the upper surface of the right etching stop layer and connected to the third metal layer;

[0023] a conductive layer fixedly disposed on the upper surface of the right etching stop layer;

[0024] A passivation layer is fixedly disposed on the upper surfaces of the second metal layer, the third metal layer, the left etching stop layer, the right etching stop layer, the bridge layer, the pixel electrode, and the conductive layer, wherein the passivation layer is provided with a through hole;

[0025] The common electrode is fixedly arranged on the upper surface of the passivation layer and is connected to the conductive layer through the through hole.

[0026] Furthermore, it also includes:

[0027] A common electrode is fixedly disposed on the upper surface of the right etching stop layer;

[0028] a conductive layer, fixedly disposed on the upper surface of the right etching stop layer and connected to the common electrode;

[0029] A passivation layer is fixedly arranged on the upper surface of the second metal layer, the third metal layer, the left etching blocking layer, the right etching blocking layer, the bridging layer, the common electrode and the conductive layer, and the passivation layer is provided with a through hole;

[0030] A pixel electrode is fixedly arranged on the upper surface of the passivation layer and connected with the third metal layer through the through hole.

[0031] Further, the first metal layer, the second metal layer, the third metal layer and the conductive layer are any one of MO single-layer structure, Ti single-layer structure, MO / AL / MO three-layer structure, Ti / AL / Ti three-layer structure, AL / MO double-layer structure and AL / Ti double-layer structure.

[0032] Further, the left active layer and the right active layer are IGZO material, the left etching blocking layer and the right etching blocking layer are SiOx material, and the bridging layer, the pixel electrode, the left bridging block, the right bridging block and the common electrode are ITO material.

[0033] Further, the gate insulating layer is SiOx single-layer structure or SiNx / SiOx double-layer structure, and the passivation layer is SiOx, SiNO or SiNx material.

[0034] Further, the left hole, the right hole and the through hole are all inverted conical.

[0035] A manufacturing method of a high-performance TFT array substrate with an active layer bridging block comprises the following steps:

[0036] S1, plating a first metal layer on the upper surface of a glass substrate to form a gate electrode;

[0037] S2, plating a gate insulating layer on the upper surface of the first metal layer and the glass substrate;

[0038] S3, plating a left active layer and a right active layer on the upper surface of the gate insulating layer, and the left active layer and the right active layer are located above the first metal layer;

[0039] S4, plating a left etching blocking layer on the upper surface of the gate insulating layer and the left active layer, the left etching blocking layer is provided with a left hole, and the left active layer is exposed in the left hole;

[0040] plating a right etching blocking layer on the upper surface of the gate insulating layer and the right active layer, the right etching blocking layer is provided with a right hole, and the right active layer is exposed in the right hole;

[0041] S5, plating a bridging layer on the upper surface of the gate insulating layer, and the left and right ends of the bridging layer are connected with the left active layer and the right active layer respectively;

[0042] A left bridge block is plated in the left hole, and the left bridge block is also connected with the left active layer;

[0043] A right bridge block is plated in the right hole, and the right bridge block is also connected with the right active layer;

[0044] S6, a second metal layer is plated on the upper surface of the left etching barrier layer, and the second metal layer is also connected with the left bridge block to form a source electrode;

[0045] A third metal layer is plated on the upper surface of the right etching barrier layer, and the third metal layer is also connected with the right bridge block to form a drain electrode.

[0046] Further, the S5 further comprises: a pixel electrode is plated on the upper surface of the right etching barrier layer, and the pixel electrode is located on the side of the bridge layer;

[0047] The S6 further comprises: the third metal layer is also connected with the pixel electrode; and a conductive layer is plated on the upper surface of the right etching barrier layer, and the conductive layer is located on the side of the pixel electrode;

[0048] Further, it further comprises:

[0049] S7, a passivation layer is plated on the upper surfaces of the second metal layer, the third metal layer, the left etching barrier layer, the right etching barrier layer, the bridge layer, the pixel electrode and the conductive layer, and the passivation layer is provided with a through hole, and the conductive layer is exposed to the through hole;

[0050] S8, a common electrode is plated on the upper surface of the passivation layer, and the common electrode is also connected with the conductive layer through the through hole.

[0051] The advantages of the present application are as follows: 1. Different from the traditional TFT device, the present application replaces a section in the middle of the active layer with a bridge layer, the bridge layer is a conductor and the active layer is a semiconductor, so that the overall active layer channel length is shortened, but the distance between the source and the drain remains unchanged, ensuring the safety of the device; that is, the active layer channel length is shortened without shortening the source-drain distance of the TFT device, the TFT array substrate of the present application has the advantages of fast response, large on-state current, small threshold voltage and the like, and improves the performance of the display screen after practical application. 2. The left etching barrier layer and the right etching barrier layer prevent the etching acid used in the subsequent ITO film layer process from damaging the left active layer and the right active layer. 3. The left bridge block, the right bridge block and the bridge layer are of the same material, and when the bridge layer is plated between the two active layers, the left bridge block is also plated in the reserved left hole, and the right bridge block is plated in the reserved right hole, which are performed in the same process, improving the production capacity and reducing the cost. 4. Since the ITO material has excellent conductivity and light transmission characteristics, the materials of the bridge layer, the left bridge block, the right bridge block and the pixel electrode of the TFT device of the present application are all ITO, and the bridge layer, the left bridge block, the right bridge block and the pixel electrode are formed in the same process, which simplifies the structure of the array substrate, improves the production capacity and reduces the cost. BRIEF DESCRIPTION OF DRAWINGS

[0052] The present application will be further described below with reference to the accompanying drawings and in conjunction with the embodiments.

[0053] Figure 1 is a schematic diagram of the structure of the traditional TFT device in the background art.

[0054] Figure 2 is the manufacturing process of the high-performance TFT array substrate with active layer bridge block of the present application Figure 1 .

[0055] Figure 3 is the manufacturing process of the high-performance TFT array substrate with active layer bridge block of the present application Figure 2 .

[0056] Figure 4 is the manufacturing process of the high-performance TFT array substrate with active layer bridge block of the present application Figure 3 .

[0057] Figure 5 is the manufacturing process of the high-performance TFT array substrate with active layer bridge block of the present application Figure 4 .

[0058] Figure 6 is the manufacturing process of the high-performance TFT array substrate with active layer bridge block of the present application Figure 5 .

[0059] Figure 7 The manufacturing process of the high-performance TFT array substrate with active layer bridge block of the present invention is as follows Figure 6 .

[0060] Figure 8 The manufacturing process of the high-performance TFT array substrate with active layer bridge block of the present invention is as follows Figure 7 .

[0061] Figure 9 The manufacturing process of the high performance TFT array substrate with active layer bridge block of the present invention is as follows Figure 8 .

[0062] Figure 10 It will Figure 9 Schematic diagram after the positions of the pixel electrode and the common electrode are swapped.

[0063] Figure 1: Glass substrate 1; gate 2; gate insulating layer 3; active layer 4; left active layer 41; right active layer 42; bridge layer 5; source 6; drain 7; pixel electrode 8; conductive layer 9; passivation layer 10; through hole 101; common electrode 20; left etch stop layer 30; left hole 301; right etch stop layer 40; right hole 401; left bridge block 50; right bridge block 60. DETAILED DESCRIPTION

[0064] The embodiments of the present invention provide a high-performance TFT array substrate with an active layer bridging block and a manufacturing method thereof, thereby resolving the disadvantage in the background art that the design of the active layer channel length is limited to the distance between the source and drain of the TFT device. When the source-drain distance is at a safe minimum distance, if the source-drain distance is further shortened, a source-drain short circuit will occur. The embodiments of the present invention achieve the shortening of the active layer channel length without shortening the source-drain distance of the TFT device. The TFT device carried by the array substrate of the present invention has the advantages of fast response, large on-state current, and low threshold voltage, thereby improving the performance of the display screen after practical application.

[0065] The technical solution in the embodiment of the present invention is to solve the above shortcomings, and the overall idea is as follows:

[0066] The difference from traditional TFT devices is that the TFT device of the present invention replaces the middle section of the active layer with a bridge layer. The bridge layer is a conductor and the active layer is a semiconductor, so that the overall active layer channel length is shortened, that is, the length of the semiconductor is shortened, but the distance between the source and the drain remains unchanged, ensuring the safety of the device; the active layer channel length is shortened without shortening the source-drain distance of the TFT device.

[0067] Before plating the bridge layer, the left etch stop layer and the right etch stop layer are first plated on the left active layer and the right active layer. The function of the left etch stop layer and the right etch stop layer is to prevent the etching acid used in the subsequent ITO film process from damaging the left active layer and the right active layer.

[0068] The left bridge block, the right bridge block and the bridge layer are all made of the same material. When the bridge layer is plated between the two active layers, the left bridge block is also plated in the reserved left hole, and the right bridge block is also plated in the reserved right hole. This is done in the same process to improve production capacity and reduce costs.

[0069] The influence of the active layer channel length on the gate characteristics of thin film transistors (TFTs) is very significant. The general trend is: the shorter the channel, the greater the on-state current, and the longer the channel, the smaller the on-state current. This can be attributed to the fact that as the channel length increases, the probability of carriers being captured during the drift process increases, and the decrease in carrier density causes the threshold voltage to increase, which also causes the source-drain current I DS The growth slows down, resulting in an increase in the subthreshold swing, which means that the response speed of the device will decrease.

[0070] In order to better understand the above technical solution, the above technical solution will be described in detail below with reference to the accompanying drawings and specific implementation methods.

[0071] See Figures 1 to 10 , a preferred embodiment of the present invention.

[0072] Combine Figure 9 , a high-performance TFT array substrate with an active layer bridge block, comprising:

[0073] Glass substrate 1;

[0074] A first metal layer is fixedly disposed on the upper surface of the glass substrate 1 to form a gate 2;

[0075] a gate insulating layer 3 fixedly disposed on the upper surface of the first metal layer and the glass substrate 1;

[0076] a left active layer 41 fixedly disposed on the upper surface of the gate insulating layer 3 and also located above the left end of the first metal layer;

[0077] a right active layer 42 fixedly disposed on the upper surface of the gate insulating layer 3 and also located above the right end of the first metal layer;

[0078] a bridge layer 5 fixedly disposed on the upper surface of the gate insulating layer 3 , with its left and right ends respectively connected to the left active layer 41 and the right active layer 42 ;

[0079] A left etching stop layer 30 is fixedly disposed on the upper surface of the gate insulating layer 3 and the left active layer 41 and further has a left hole 301 formed therein;

[0080] A right etching stop layer 40 is fixedly disposed on the upper surface of the gate insulating layer 3 and the right active layer 42 and is further provided with a right hole 401;

[0081] The left bridging block 50 is fixedly disposed in the left hole 301;

[0082] The right bridging block 60 is fixedly disposed in the right hole 401;

[0083] A second metal layer is fixedly disposed on the upper surface of the left etching stop layer 30 and is connected to the left active layer 41 via a left bridge block 50 to form a source electrode 6;

[0084] A third metal layer is fixedly disposed on the upper surface of the right etching stop layer 40 and is connected to the right active layer 42 via a right bridge block 60 to form a drain 7;

[0085] The left bridging block 50 , the right bridging block 60 and the bridging layer 5 are made of the same material.

[0086] The difference from the traditional TFT device is that the TFT device of the present invention replaces the middle section of the active layer with a bridge layer 5. The bridge layer 5 is a conductor, and the left active layer 41 and the right active layer 42 are both semiconductors, so that the overall active layer channel length is shortened, that is, the length of the semiconductor is shortened, but at this time the distance between the source 6 and the drain 7 remains unchanged, ensuring the safety of the device; that is, without shortening the distance between the source 6 and the drain 7 of the TFT device, the active layer channel length is shortened. The TFT array substrate of the present invention has the advantages of fast response, large on-state current, and low threshold voltage, and improves the performance of the display screen after actual application.

[0087] It also includes: a pixel electrode 8, fixedly disposed on the upper surface of the right etching stop layer 40 and connected to the third metal layer;

[0088] A conductive layer 9 is fixedly disposed on the upper surface of the right etching stop layer 40;

[0089] A passivation layer 10 is fixedly disposed on the upper surface of the second metal layer, the third metal layer, the left etching stop layer 30, the right etching stop layer 40, the bridge layer 5, the pixel electrode 8, and the conductive layer 9. The passivation layer 10 is provided with a through hole 101;

[0090] The common electrode 20 is fixedly disposed on the upper surface of the passivation layer 10 and is connected to the conductive layer 9 through the through hole 101 .

[0091] The first metal layer (gate 2), the second metal layer (source 6), the third metal layer (drain 7), and the conductive layer 9 are any one of a MO single-layer structure, a Ti single-layer structure, a MO / AL / MO three-layer structure, a Ti / AL / Ti three-layer structure, an AL / MO double-layer structure, and an AL / Ti double-layer structure.

[0092] The left active layer 41 and the right active layer 42 are made of IGZO, the left etching stop layer 30 and the right etching stop layer 40 are made of SiOx, and the bridge layer 5, the pixel electrode 8, the left bridge block 50, the right bridge block 60, and the common electrode 20 are all made of ITO.

[0093] The gate insulating layer 3 is a SiOx single-layer structure or a SiNx / SiOx double-layer structure, and the passivation layer 10 is made of SiOx, SiNO or SiNx.

[0094] The left hole 301, the right hole 401 and the through hole 101 are all in an inverted cone shape, which facilitates the deposition and fixing of materials in the holes.

[0095] Combine Figures 2 to 9 The method for manufacturing a high-performance TFT array substrate with an active layer bridging block of this embodiment includes the following steps:

[0096] S1, plating a first metal layer on the upper surface of the glass substrate 1 to form a gate 2;

[0097] The function of gate 2 is to transmit gate 2 signals to turn on and off the TFT device. The material can be any one of MO single-layer structure, Ti single-layer structure, MO / AL / MO three-layer structure, Ti / AL / Ti three-layer structure, AL / MO double-layer structure, and AL / Ti double-layer structure. PVD film formation and acid wet etching are used.

[0098] S2, coating a gate insulating layer 3 on the upper surface of the first metal layer and the glass substrate 1;

[0099] The gate insulating layer 3 serves as an insulating medium and also as a capacitor medium between the gate 2 and the active layer. The material is a SiOx single-layer structure or a SiNx / SiOx double-layer structure, and is formed by CVD and dry etching.

[0100] Considering that the current requirements for TFT devices are fast response and low power consumption, which are achieved by shrinking TFT devices, in order to achieve miniaturization of the device, a suitable high-K material (such as HfO2) needs to be selected for the gate insulating layer. However, considering that there are many defects in the interface of HfO2, if it is directly in contact with the active layer or gate metal, it may affect the stability of the device. Therefore, it is possible to consider using SiOx or SiNx with a better interface (SiNx can only be used as a contact film layer with the gate metal layer. If it is used as a contact surface with IGZO, the H remaining in the SiNx film during the film formation process will destroy the IGZO characteristics) as the contact surface, such as a SiOx / HfO2 / SiOx three-layer structure as the GI insulating layer. In order to ensure that the advantages of high-K materials are reflected, the thickness of HfO2 in the three-layer structure needs to be larger than that of SiOx.

[0101] S3, plating a left active layer 41 and a right active layer 42 on the upper surface of the gate insulating layer 3, wherein the left active layer 41 and the right active layer 42 are located above the first metal layer;

[0102] The left active layer 41 and the right active layer 42 serve as semiconductor layers, providing or closing carrier channels under the action of the gate 2 voltage. The material used is metal oxide semiconductors such as IGZO, PVD film formation, and acid wet etching.

[0103] S4, coating a left etching stopper layer 30 on the upper surfaces of the gate insulating layer 3 and the left active layer 41, wherein the left etching stopper layer 30 is provided with a left hole 301, and the left active layer 41 is exposed in the left hole 301;

[0104] A right etching stopper layer 40 is plated on the upper surface of the gate insulating layer 3 and the right active layer 42 , wherein the right etching stopper layer 40 is provided with a right hole 401 , and the right active layer 42 is exposed in the right hole 401 ;

[0105] The left etch stop layer 30 and the right etch stop layer 40 are used to prevent the metal oxide semiconductor (left active layer and right active layer) from being damaged by the etching acid used in the subsequent ITO film process. The material is SiOx, the film is formed by CVD, and the dry etching is performed.

[0106] S5, coating a bridge layer 5 on the upper surface of the gate insulating layer 3, with the left and right ends of the bridge layer 5 connected to the left active layer 41 and the right active layer 42 respectively;

[0107] Plating a pixel electrode 8 on the upper surface of the right etching stop layer 40 , wherein the pixel electrode 8 is located on the side of the bridge layer 5 ;

[0108] Plating a left bridging block 50 on the left hole 301 , wherein the left bridging block 50 is also connected to the left active layer 41 ;

[0109] Plating a right bridging block 60 on the right hole 401 , wherein the right bridging block 60 is also connected to the right active layer 42 ;

[0110] The function of the bridging layer 5 is to connect the left and right active layers together, the function of the pixel electrode 8 is to act as an electrode to provide an electric field to the liquid crystal molecules, the function of the left bridging block 50 is to connect the source 6 and the left active layer 41, and the function of the right bridging block 60 is to connect the drain 7 and the right active layer 42. All four are made of ITO, so they are formed together by PVD and wet-etched with acid.

[0111] S6, plating a second metal layer on the upper surface of the left etching stop layer 30, wherein the second metal layer is also connected to the left bridge block 50 to form a source electrode 6;

[0112] A third metal layer is plated on the upper surface of the right etching stop layer 40 , and the third metal layer is also connected to the right bridge block 60 and the pixel electrode 8 to form a drain electrode 7 ;

[0113] A conductive layer 9 is plated on the upper surface of the right etching stop layer 40 , and the conductive layer 9 is located on the side of the pixel electrode 8 ;

[0114] The source electrode 6, the drain electrode 7 and the conductive layer 9 are used to provide signals to the pixel electrode 8 and the common electrode 20. The film is formed by PVD magnetron sputtering. The material can be any one of MO single-layer structure, Ti single-layer structure, MO / AL / MO three-layer structure, Ti / AL / Ti three-layer structure, AL / MO double-layer structure, and AL / Ti double-layer structure. The etching method is acid wet etching.

[0115] S7, coating a passivation layer 10 on the upper surfaces of the second metal layer, the third metal layer, the left etching stop layer 30, the right etching stop layer 40, the bridge layer 5, the pixel electrode 8, and the conductive layer 9, wherein the passivation layer 10 is provided with a through hole 101, and the conductive layer 9 is exposed through the through hole 101;

[0116] The passivation layer 10 protects the TFT device and acts as a capacitor between the pixel electrode 8 and the common electrode 20. It can be made of insulating materials such as SiOx, SiNO, or SiNx, and is deposited using CVD and dry etching. The purpose of drilling holes above the conductive layer 9 is to transmit signals from the conductive layer 9 to the common electrode 20.

[0117] S8 , plating a common electrode 20 on the upper surface of the passivation layer 10 , wherein the common electrode 20 is connected to the conductive layer 9 through the through hole 101 .

[0118] The common electrode 20 serves as an electrode for providing an electric field to the liquid crystal molecules. The common electrode 20 is made of ITO, formed by PVD and wet-etched with acid.

[0119] In combination Figure 7 In embodiments, the positions of the common electrode 20 and the pixel electrode 8 can be interchangeable, i.e.:

[0120] The common electrode 20 is fixedly arranged on the upper surface of the right etching barrier layer 40;

[0121] The conductive layer 9 is fixedly arranged on the upper surface of the right etching barrier layer 40 and is connected with the common electrode 20;

[0122] The passivation layer 10 is fixedly arranged on the upper surfaces of the second metal layer, the third metal layer, the left etching barrier layer 30, the right etching barrier layer 40, the bridge layer 5, the common electrode 20 and the conductive layer 9, and the passivation layer 10 is provided with a through hole 101;

[0123] The pixel electrode 8 is fixedly arranged on the upper surface of the passivation layer 10 and is connected with the third metal layer through the through hole 101.

[0124] Since the ITO material has excellent conductivity and light transmission characteristics, the bridge layer 5, the left bridge block 50, the right bridge block 60 and the pixel electrode 8 of the TFT array substrate of the present application are all made of ITO, and the film formation of the bridge layer 5, the left bridge block 50, the right bridge block 60 and the pixel electrode 8 is performed in the same process, so that the structure of the array substrate can be simplified, the production capacity can be improved and the cost can be reduced.

[0125] Although the specific embodiments of the present application are described above, those skilled in the art should understand that the specific embodiments described are only illustrative and are not intended to limit the scope of the present application, and equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present application should be covered within the scope of the claims of the present application.

Claims

1. A high-performance TFT array substrate with an active layer bridge block, characterized in that: include: glass substrate; A first metal layer is fixedly disposed on the upper surface of the glass substrate to form a gate; a gate insulating layer fixedly disposed on the upper surfaces of the first metal layer and the glass substrate; a left active layer, fixedly disposed on the upper surface of the gate insulating layer and also located above the left end of the first metal layer; a right active layer, fixedly disposed on the upper surface of the gate insulating layer and also located above the right end of the first metal layer; a bridging layer, fixedly disposed on the upper surface of the gate insulating layer, with left and right ends respectively connected to the left active layer and the right active layer; a left etching stop layer, fixedly disposed on the upper surfaces of the gate insulating layer and the left active layer, and further having a left hole; a right etching stop layer, fixedly disposed on the upper surfaces of the gate insulating layer and the right active layer, and further having a right hole; A left bridging block, fixedly disposed in the left hole; a right bridging block, fixedly disposed in the right hole; A second metal layer is fixedly disposed on the upper surface of the left etching stop layer and is connected to the left active layer via a left bridge block to form a source electrode; a third metal layer, fixedly disposed on the upper surface of the right etching stop layer, and connected to the right active layer via a right bridge block to form a drain; The left bridging block, the right bridging block and the bridging layer are all made of the same material; The left active layer and the right active layer are both made of IGZO material, the left etching stop layer and the right etching stop layer are both made of SiOx material, and the bridge layer, the left bridge block and the right bridge block are all made of ITO material; The left dug hole, the right dug hole and the through hole are all in an inverted cone shape.

2. The high-performance TFT array substrate with active layer bridge blocks according to claim 1, characterized in that: Also includes: a pixel electrode, fixedly disposed on the upper surface of the right etching stop layer and connected to the third metal layer; a conductive layer fixedly disposed on the upper surface of the right etching stop layer; A passivation layer is fixedly disposed on the upper surfaces of the second metal layer, the third metal layer, the left etching stop layer, the right etching stop layer, the bridge layer, the pixel electrode, and the conductive layer, wherein the passivation layer is provided with a through hole; The common electrode is fixedly arranged on the upper surface of the passivation layer and is connected to the conductive layer through the through hole.

3. The high-performance TFT array substrate with active layer bridge blocks according to claim 1, characterized in that: Also includes: A common electrode is fixedly disposed on the upper surface of the right etching stop layer; a conductive layer, fixedly disposed on the upper surface of the right etching stop layer and connected to the common electrode; A passivation layer is fixedly arranged on the upper surfaces of the second metal layer, the third metal layer, the left etching stop layer, the right etching stop layer, the bridge layer, the common electrode, and the conductive layer, and the passivation layer is provided with a through hole; The pixel electrode is fixedly arranged on the upper surface of the passivation layer and is connected to the third metal layer through the through hole.

4. The high-performance TFT array substrate with active layer bridge blocks according to claim 2, characterized in that: The first metal layer, the second metal layer, the third metal layer, and the conductive layer are any one of a MO single-layer structure, a Ti single-layer structure, a MO / AL / MO three-layer structure, a Ti / AL / Ti three-layer structure, an AL / MO double-layer structure, and an AL / Ti double-layer structure.

5. The high-performance TFT array substrate with active layer bridge blocks according to claim 2, characterized in that: The gate insulating layer is a SiOx single-layer structure or a SiNx / SiOx double-layer structure, and the passivation layer is made of SiOx, SiNO or SiNx.

6. A method for manufacturing a high-performance TFT array substrate with an active layer bridge block, characterized in that: The following steps are involved: S1, plating a first metal layer on the upper surface of the glass substrate to form a gate; S2, coating a gate insulating layer on the upper surface of the first metal layer and the glass substrate; S3, plating a left active layer and a right active layer on the upper surface of the gate insulating layer, wherein the left active layer and the right active layer are located above the first metal layer; S4, coating a left etching stop layer on the upper surfaces of the gate insulating layer and the left active layer, wherein the left etching stop layer is provided with a left hole, and the left active layer is exposed in the left hole; Plating a right etching stop layer on the upper surface of the gate insulating layer and the right active layer, wherein the right etching stop layer is provided with a right hole, and the right active layer is exposed in the right hole; S5, plating a bridge layer on the upper surface of the gate insulating layer, wherein the left and right ends of the bridge layer are connected to the left active layer and the right active layer respectively; Plating a left bridging block on the left hole, wherein the left bridging block is also connected to the left active layer; Plating a right bridging block on the right hole, wherein the right bridging block is also connected to the right active layer; S6, plating a second metal layer on the upper surface of the left etching stop layer, wherein the second metal layer is also connected to the left bridge block to form a source electrode; Plating a third metal layer on the upper surface of the right etching stop layer, wherein the third metal layer and the right bridge block form a drain; The left active layer and the right active layer are both made of IGZO material, the left etching stop layer and the right etching stop layer are both made of SiOx material, and the bridge layer, the left bridge block and the right bridge block are all made of ITO material.

7. The method for manufacturing a high-performance TFT array substrate with an active layer bridge block according to claim 6, wherein: The S5 further includes: plating a pixel electrode on the upper surface of the right etching stop layer, wherein the pixel electrode is located on the side of the bridge layer; The step S6 further includes: the third metal layer is further connected to the pixel electrode; and a conductive layer is plated on the upper surface of the right etching stop layer, wherein the conductive layer is located on the side of the pixel electrode.

8. The method for manufacturing a high-performance TFT array substrate with an active layer bridge block according to claim 7, wherein: Also includes: S7, coating a passivation layer on the upper surfaces of the second metal layer, the third metal layer, the left etching stop layer, the right etching stop layer, the bridge layer, the pixel electrode, and the conductive layer, wherein the passivation layer is provided with a through hole, and the conductive layer is exposed through the through hole; S8. Plating a common electrode on the upper surface of the passivation layer, wherein the common electrode is connected to the conductive layer through the through hole.

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