IGBT device

Abstract

The application discloses an IGBT device, which comprises a plurality of first trench gates, a first gate dielectric layer and a first gate conductive material layer filled in a first gate trench, and the first gate conductive material layer is connected to a gate. On a layout structure, each first gate trench is arranged in parallel. A Miller capacitance continuous adjustment structure is arranged on at least one first gate trench, which comprises a second trench gate, a second gate dielectric layer and a second gate conductive material layer filled in a second gate trench. The second gate trench intersects with the corresponding first gate trench, the second and first gate trenches are communicated, and the second and first gate conductive material layers are electrically connected. By using the characteristic that the second gate trench intersects with the first gate trench, the length, spacing and quantity of the second gate trench are independent of the first gate trench, the Miller capacitance is adjusted by adjusting the length, spacing or quantity of the second gate trench, the continuous adjustment of the Miller capacitance is realized, and the performance of the chip is more finely controlled.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor integrated circuit, and in particular, to an insulated gate bipolar transistor (IGBT) device. BACKGROUND

[0002] The dynamic characteristics of IGBT have a major impact on the application, among which the Miller capacitance has the greatest impact on the application of the chip. Excessive Miller capacitance can cause more energy consumption, and even cause other bridge arms to be mistakenly turned on during the off process. However, if the Miller capacitance is too small, the charging and discharging during the switching process of the IGBT chip is too fast, which causes serious spurious phenomenon during the switching process, and is easy to cause electromagnetic interference phenomenon. Or in the short circuit process, the gate voltage produces oscillation phenomenon. Therefore, the Miller capacitance has an optimal value of energy consumption and safety, and this optimal value is different for chips of different current levels.

[0003] In the design of IGBT chip, there will be a certain proportion of gate trenches and emitter trenches, and the way to increase or decrease the Miller capacitance is generally to change the proportion of gate trenches and emitter trenches to achieve it. However, because the way to increase or decrease the number of gate trenches changes the proportion of the Miller capacitance too much, it is impossible to achieve continuous adjustment of the Miller capacitance. In the present application, the process structures of the gate trench and the emitter trench are the same and are formed at the same time, and the gate dielectric layer and the gate conductive material layer filled in the gate trench and the emitter trench are also the same. The difference between the two is that the gate conductive material layer in the gate trench is connected to the gate composed of the front metal layer, and the gate conductive material layer in the emitter trench is connected to the emitter composed of the front metal layer. In the present application, the trench gate is composed of the gate dielectric layer filled in the gate trench and the gate conductive material layer connected to the gate. The structure composed of the gate dielectric layer filled in the emitter trench and the gate conductive material layer connected to the emitter is defined as the first pseudo gate trench filling structure, that is, the difference between the first pseudo gate trench filling structure and the trench gate is only that the top of the gate conductive material layer is connected to the emitter or the gate.

[0004] The Miller capacitance is the capacitance between the gate and the collector, that is, Cgc. The gate conductive material layer of the trench gate is connected to the gate, so the more the number of the trench gate, the greater the Miller capacitance. By connecting the gate conductive material layer of the trench gate to the emitter, that is, changing the trench gate to the first pseudo gate trench filling structure, the capacitance between the gate conductive material layer of the first pseudo gate trench filling structure and the collector is the capacitance between the emitter and the collector, that is, Cec. In the existing method, the Miller capacitance is adjusted by connecting the gate conductive material layer of part of the trench gate to the emitter.

[0005] The following will be described in combination with Figure 1 and Figure 2Further detailed description of the Miller capacitance adjusting structure of the existing IGBT

[0006] As shown in Figure 1 , it is a layout of the existing IGBT device with low Miller capacitance structure; Figure 1 In the figure, the process structure of the gate trench 101 and the emitter trench 102 is the same, and the difference between the two lies in that the gate conductive material layer filled in the gate trench 101, such as polysilicon gate, is connected to the gate, while the polysilicon gate filled in the emitter trench 102 is connected to the emitter. It can be seen that the gate trench 101 and the emitter trench 102 are parallel to each other, and the gate trench 101 or the emitter trench 102 is arranged at equal intervals.

[0007] The emitter region of the IGBT device is connected to the emitter through the contact hole 103, Figure 1 In the figure, the area between the two contact holes 103 forms a periodic unit of the IGBT device in the arrangement direction of the gate trench 101 or the emitter trench 102, and the area between the two contact holes 103 can be calculated according to the area between the center lines parallel to the length side of the two contact holes 103.

[0008] It can be seen that in the area between the two contact holes 103, Figure 1 4 emitter trenches 102 and 2 gate trenches 101 are arranged, and since the number of gate trenches 101 is small, Figure 1 the IGBT device has low Miller capacitance.

[0009] As shown in Figure 2 , it is a layout of the existing IGBT device with high Miller capacitance structure; Figure 2 and Figure 1 The difference between the two lies in that in the area between the two contact holes 103, Figure 2 2 emitter trenches 102 and 4 gate trenches 101 are arranged, and since the number of gate trenches 101 is large, Figure 2 the IGBT device has high Miller capacitance.

[0010] Comparison Figure 1 and Figure 2As shown, the existing method is to adjust the Miller capacitance by connecting the polysilicon gate in part of the gate trench 101 to the emitter, but in the actual structure, the length of the gate trench 101 is large, and after converting one gate trench 101 into an emitter trench 102, the change of the Miller capacitance is relatively large. As described above, the Miller capacitance has an optimized value for energy consumption and safety, and the optimized value is different for chips of different current levels. Therefore, the optimized value of the Miller capacitance required by different chips is different, and when the adjustment range of the Miller capacitance adjustment structure for the Miller capacitance is large, the optimized value of the Miller capacitance required by the chip cannot be obtained in many applications. SUMMARY

[0011] The technical problem to be solved by the present application is to provide an IGBT device capable of continuously adjusting the Miller capacitance, so as to achieve more fine control of the performance of the chip, such as dynamic characteristics.

[0012] To solve the above technical problem, the IGBT device provided by the present application comprises:

[0013] A plurality of first trench gates, the first trench gate comprising a first gate dielectric layer and a first gate conductive material layer filled in a first gate trench, the first gate conductive material layer being connected to a gate electrode composed of a front metal layer.

[0014] On the layout structure, each of the first gate trenches is arranged in parallel.

[0015] A Miller capacitance continuous adjustment structure is arranged on at least one of the first gate trenches.

[0016] The Miller capacitance continuous adjustment structure comprises:

[0017] A second trench gate, the second trench gate comprising a second gate dielectric layer and a second gate conductive material layer filled in a second gate trench.

[0018] The second gate trench intersects with the corresponding first gate trench, the second gate trench and the first gate trench are connected, and the second gate conductive material layer and the first gate conductive material layer are electrically connected.

[0019] By using the feature that the second gate trench intersects with the first gate trench, the length, spacing and number of the second gate trench are independent of the first gate trench, and the Miller capacitance is adjusted and the continuous adjustment of the Miller capacitance is realized by adjusting the length, spacing or number of the second gate trench.

[0020] Further improvement is that it further comprises:

[0021] one or more first dummy gate trench filling structures, each of the first dummy gate trench filling structures comprising a third gate dielectric layer and a third gate conductive material layer filled in a third gate trench, the third gate conductive material layer being connected to an emitter consisting of a front metal layer.

[0022] In a layout structure, the third gate trench and each of the first gate trenches are arranged in parallel.

[0023] Further improvement is that the second gate trench and the corresponding first gate trench intersect perpendicularly.

[0024] Further improvement is that the width of the second gate trench is equal to the width of the first gate trench.

[0025] Further improvement is that the second gate trench intersects one side of the corresponding first gate trench.

[0026] Further improvement is that the second gate trench is provided on one side of the corresponding first gate trench or on both sides of the corresponding first gate trench.

[0027] Further improvement is that the second gate trench passes through both sides of the corresponding first gate trench.

[0028] Further improvement is that a fourth gate trench is connected between a plurality of the second gate trenches intersecting one side of the corresponding first gate trench.

[0029] A fourth trench gate consisting of a fourth gate dielectric layer and a fourth gate conductive material layer filled in the fourth gate trench.

[0030] Further improvement is that in a cross-sectional structure, the IGBT device comprises a body region of a second conductive type, a drift region of a first conductive type, a first conductive type heavily doped emitter region formed on the surface of the body region, and a second conductive type heavily doped collector region located on the back of the drift region.

[0031] The first gate trench, the second gate trench, the third gate trench and the fourth gate trench all pass through the body region.

[0032] The emitter region and the top of the body region are connected to the emitter through a first contact hole.

[0033] Further improvement is that in a layout structure, each of the first contact holes and the first gate trenches are arranged in parallel.

[0034] In the arrangement direction of the first gate trench, the region between two adjacent first contact holes constitutes a periodic unit of the IGBT device.

[0035] A further improvement is that there is more than one second dummy gate trench filling structure, the second dummy gate trench filling structure comprising a fifth gate dielectric layer and a fifth gate conductive material layer filled in a fifth gate trench, and the fifth gate conductive material layer is connected to an emitter composed of a front metal layer.

[0036] On the layout structure, the fifth dummy gate trench and the second gate trench are parallel, and a plurality of fifth dummy gate trenches are arranged between adjacent second gate trenches.

[0037] A further improvement is that the width of the fifth dummy gate trench between each second gate trench is equal, the pitch is equal, or the pitch is unequal.

[0038] The prior art adjusts the Miller capacitance by connecting the gate conductive material layer of the corresponding trench gate to the emitter, and the length of the trench gate is very long, so that changing a trench gate into a first dummy gate trench filling structure connected to the emitter will greatly change the Miller capacitance, which is not applicable in many applications; unlike the prior art, the present application provides a Miller capacitance continuous adjustment structure, which is realized by setting a second trench gate intersecting the first trench gate, and the second gate trench of the second trench gate and the first gate trench of the first trench gate intersect, so that the structural characteristics of the second gate trench, such as length, pitch or number, can be independently adjusted, and the continuous adjustment of the Miller capacitance can be realized by adjusting the structure of the second gate structure, and finally the performance of the chip, such as dynamic characteristics, can be more finely controlled.

[0039] This invention further extends beyond the first pseudo-gate trench filling structure, which involves setting a third pseudo-gate trench parallel to the first gate trench and filling it with a third gate dielectric layer and a third gate conductive material layer. It also includes a second pseudo-gate trench filling structure formed by setting a fifth pseudo-gate trench parallel to the second gate trench in the gap between adjacent second gate trenches and filling it with a fifth gate dielectric layer and a fifth gate conductive material layer. Since the fifth gate conductive material layer is also connected to the emitter, the introduction of the second pseudo-gate trench filling structure can adjust the capacitance (Cec) between the emitter and collector. Simultaneously, the introduction of the second pseudo-gate trench filling structure can make the potential at the bottom region of the larger gap second gate trench more uniform, thereby improving the breakdown voltage (BV). Therefore, this invention, by combining the second trench gate formed in the second gate trench and the second pseudo-gate trench filling structure formed in the fifth pseudo-gate trench, can make the potential at the bottom of each trench more uniform while adjusting the Miller capacitance, thereby further optimizing Cec and BV. Attached Figure Description

[0040] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0041] Figure 1 It is a layout of an existing IGBT device with a low Miller capacitance structure;

[0042] Figure 2 It is a layout of an existing IGBT device with a high Miller capacitance structure;

[0043] Figure 3 This is a first layout of the IGBT device with a Miller capacitance continuously adjustable structure according to the first embodiment of the present invention;

[0044] Figure 4 This is a second layout of the IGBT device with a Miller capacitance continuously adjustable structure according to the second embodiment of the present invention;

[0045] Figure 5 This is a third layout of the IGBT device with a Miller capacitance continuously adjustable structure according to the third embodiment of the present invention;

[0046] Figure 6 This is the fourth layout of the IGBT device with a Miller capacitance continuously adjustable structure according to the fourth embodiment of the present invention;

[0047] Figure 7 These are dynamic curves showing the changes in collector current and collector voltage over time for existing IGBT devices and the IGBT device of the first embodiment of this invention. Detailed Implementation

[0048] like Figure 3The first embodiment of the IGBT device with the Miller capacitance continuous adjustment structure is shown in the first layout of the IGBT device.

[0049] The first trench gate includes a first gate dielectric layer (not shown) and a first gate conductive material layer (not shown) filled in the first gate trench 201, and the first gate conductive material layer is connected to a gate electrode (not shown) composed of a front metal layer.

[0050] In the layout structure, the first gate trenches 201 are arranged in parallel.

[0051] The Miller capacitance continuous adjustment structure is arranged on at least one of the first gate trenches 201.

[0052] The Miller capacitance continuous adjustment structure includes:

[0053] The second trench gate includes a second gate dielectric layer and a second gate conductive material layer filled in the second gate trench 204.

[0054] The second gate trench 204 intersects with the corresponding first gate trench 201, and the second gate trench 204 and the first gate trench 201 are connected in communication, and the second gate conductive material layer and the first gate conductive material layer are electrically connected.

[0055] By using the feature that the second gate trench 204 intersects with the first gate trench 201, the length, spacing, and number of the second gate trench 204 are independent of the first gate trench 201, and the Miller capacitance is adjusted and the continuous adjustment of the Miller capacitance is achieved by adjusting the length, spacing, or number of the second gate trench 204. Since the second gate conductive material layer is finally connected to the gate electrode, the capacitance between the second trench gate and the collector also belongs to part of the Miller capacitance, so the greater the length of the second gate trench 204, the greater the Miller capacitance will be, and the greater the number of the second gate trench 204, the greater the Miller capacitance will be. The smaller the spacing of the second gate trench 204, the greater the arrangement density of the second gate trench 204, and the greater the Miller capacitance will be.

[0056] In the first embodiment of the application, the second gate trench 204 and the corresponding first gate trench 201 intersect perpendicularly. In other embodiments, the angle at which the second gate trench 204 and the corresponding first gate trench 201 intersect can also be other angles.

[0057] In the first embodiment of the present application, the width of the second gate trench 204 is equal to the width of the first gate trench 201. In other embodiments, the width of the second gate trench 204 can also be not equal to the width of the first gate trench 201.

[0058] In the first embodiment of the present application, the width of the second gate trench 204 is equal to the width of the first gate trench 201. In other embodiments, the width of the second gate trench 204 can also be not equal to the width of the first gate trench 201. Figure 3 In the first embodiment of the present application, the second gate trench 204 intersects one side of the corresponding first gate trench 201. Figure 3 In the first embodiment of the present application, the second gate trench 204 intersects one side of the corresponding first gate trench 201. In other embodiments, the second gate trench 204 can also be arranged on two sides of the corresponding first gate trench 201.

[0059] In the first embodiment of the present application, the width of the second gate trench 204 is equal to the width of the first gate trench 201. In other embodiments, the width of the second gate trench 204 can also be not equal to the width of the first gate trench 201.

[0060] one or more first dummy gate trench filling structures, the first dummy gate trench filling structure comprising a third gate dielectric layer and a third gate conductive material layer filled in a third dummy gate trench 202, the third gate conductive material layer being connected to an emitter composed of a front metal layer. Since the third gate conductive material layer is connected to the emitter, the third dummy gate trench 202 actually becomes an emitter trench as described in the prior art. Figure 1 In the first embodiment of the present application, the width of the second gate trench 204 is equal to the width of the first gate trench 201. In other embodiments, the width of the second gate trench 204 can also be not equal to the width of the first gate trench 201.

[0061] In the first embodiment of the present application, the width of the second gate trench 204 is equal to the width of the first gate trench 201. In other embodiments, the width of the second gate trench 204 can also be not equal to the width of the first gate trench 201. Figure 3 In the first embodiment of the present application, the second gate trench 204 intersects one side of the corresponding first gate trench 201. In other embodiments, the second gate trench 204 can also be arranged on two sides of the corresponding first gate trench 201.

[0062] In the first embodiment of the present application, the width of the second gate trench 204 is equal to the width of the first gate trench 201. In other embodiments, the width of the second gate trench 204 can also be not equal to the width of the first gate trench 201.

[0063] In the first embodiment of the present application, the width of the second gate trench 204 is equal to the width of the first gate trench 201. In other embodiments, the width of the second gate trench 204 can also be not equal to the width of the first gate trench 201.

[0064] In the first embodiment of the present application, the width of the second gate trench 204 is equal to the width of the first gate trench 201. In other embodiments, the width of the second gate trench 204 can also be not equal to the width of the first gate trench 201.

[0065] In the first embodiment of the present application, the width of the second gate trench 204 is equal to the width of the first gate trench 201. In other embodiments, the width of the second gate trench 204 can also be not equal to the width of the first gate trench 201.

[0066] In the first embodiment of the present application, the width of the second gate trench 204 is equal to the width of the first gate trench 201. In other embodiments, the width of the second gate trench 204 can also be not equal to the width of the first gate trench 201. Figure 3 In the first embodiment of the present application, the width of the second gate trench 204 is equal to the width of the first gate trench 201. In other embodiments, the width of the second gate trench 204 can also be not equal to the width of the first gate trench 201.

[0067] In the arrangement direction of the first gate trench 201, the region between two adjacent first contact holes 203 constitutes a periodic unit of the IGBT device. The region included in the periodic unit can be the region between the center lines of the two adjacent first contact holes 203 parallel to the length side.

[0068] As shown by Figure 3 , Figure 4 , Figure 5 and Figure 6 It can be seen that, by setting the layout, the first embodiment of the present application can easily adjust the Miller capacitance and can achieve fine adjustment, and the adjustment accuracy can be achieved by setting the length or width of the second gate trench 204, and the length or width of the second gate trench 204 is not limited, so theoretically the continuous adjustment of the size of the Miller capacitance can be realized. The adjustment accuracy of the Miller capacitance in the existing structure is determined by the length of the first gate trench 201, and obviously the first embodiment of the present application can achieve fine adjustment of the Miller capacitance.

[0069] In the first embodiment of the present application, on the basis of the layout definition, the first gate trench 201, the second gate trench 204 and the third pseudo gate trench 202 can be formed at the same time by the same process; the process structure of the first gate dielectric layer, the second gate dielectric layer and the third gate dielectric layer is the same and can be formed at the same time by the same process, such as the first gate dielectric layer, the second gate dielectric layer and the third gate dielectric layer can be gate oxide layer. The process structure of the first gate conductive material layer, the second gate conductive material layer and the third gate conductive material layer is the same and can be formed at the same time by the same process, such as the first gate conductive material layer, the second gate conductive material layer and the third gate conductive material layer can be polysilicon gate. The prior art is to adjust the Miller capacitance by connecting the gate conductive material layer of the corresponding trench gate to the emitter, and the length of the trench gate is very long. Changing a trench gate into a first pseudo gate trench filling structure connected to the emitter will greatly change the Miller capacitance, so it cannot be used in many applications; unlike the prior art, the first embodiment of the present application sets a continuous adjustment structure of the Miller capacitance, which is realized by setting a second trench gate intersecting the first trench gate. The intersection of the second gate trench 204 of the second trench gate and the first gate trench 201 of the first trench gate makes the structure characteristics such as the length, spacing or number of the second gate trench 204 adjustable independently, and the continuous adjustment of the Miller capacitance can be realized by adjusting the structure of the second gate structure, and finally the performance of the chip such as the dynamic characteristics can be controlled more finely.

[0070] In summary, the gate trenches perpendicularly connected to the original gate in the first embodiment of the present invention can be used to adjust the size of the Miller capacitance. Furthermore, the length and distance of these vertical gate trenches are not limited by the unit cell period and can be freely adjusted to achieve continuous control of the Miller capacitance. During the fabrication process, the emitter trench 101 and the gate trench 101 are identical and arranged periodically. The unit cell period refers to… Figure 1 In the middle, the sum of the width and the spacing of a gate trench 101.

[0071] like Figure 4 The diagram shown is a second layout of the IGBT device with a continuously adjustable Miller capacitance structure according to the second embodiment of the present invention. The difference between the IGBT device of the second embodiment of the present invention and the IGBT device of the first embodiment of the present invention is as follows:

[0072] exist Figure 4 In the second layout shown, a fourth gate trench 205 is connected between a plurality of second gate trenches 204 intersecting one side of the corresponding first gate trench 201; the fourth trench gate is composed of a fourth gate dielectric layer and a fourth gate conductive material layer filled in the fourth gate trench 205. The fourth trench gate also belongs to the Miller capacitance continuously adjustable structure. The greater the length of the fourth gate trench 205, the larger the Miller capacitance; the greater the number of fourth gate trenches 205, the larger the Miller capacitance. By setting the fourth gate trench 205, the Miller capacitance can be further adjusted.

[0073] like Figure 5 The diagram shown is a third layout of the IGBT device with a continuously adjustable Miller capacitance structure according to the third embodiment of the present invention; in Figure 5 In the third layout shown, the second gate trench 204 passes through the two sides of the corresponding first gate trench 201.

[0074] like Figure 6 The diagram shown is a fourth layout of the IGBT device with a Miller capacitance continuously adjustable structure according to the fourth embodiment of the present invention.

[0075] exist Figure 6 In the fourth layout shown, there is one or more second pseudo-gate trench filling structures. The second pseudo-gate trench filling structure includes a fifth gate dielectric layer and a fifth gate conductive material layer filled in the fifth gate trench 206. The fifth gate conductive material layer is connected to the emitter composed of a front metal layer.

[0076] In terms of layout structure, the fifth gate trench 206 and the second gate trench 204 are parallel, and a plurality of fifth gate trenches 206 are provided between adjacent second gate trenches 204.

[0077] The fifth dummy gate trench 206 between each of the second gate trenches 204 is equal in width, equal in spacing, and equal in length. In other embodiments, the fifth dummy gate trench 206 can also be adjusted accordingly, such as making the spacing between the fifth dummy gate trench 206 unequal.

[0078] and Figure 3 As can be seen by comparing the first layout structure shown in Figure 3 with the fourth layout structure shown in Figure 6 , by adding the fifth dummy gate trench 206 with different spacing in the gap of the second gate trench 204, the potential at the bottom of each trench is more uniform while adjusting the Miller capacitance, thereby further optimizing Cec and BV.

[0079] As can be seen by comparing the first layout structure shown in Figure 3 , the fourth embodiment of the present application can further set the third dummy gate trench 202 parallel to the first gate trench 201 and fill the third gate dielectric layer and the third gate conductive material layer in the third dummy gate trench 202 to form a first dummy gate trench filling structure, and further set the fifth dummy gate trench 206 parallel to the second gate trench 204 in the gap between adjacent second gate trenches 204 and fill the fifth gate dielectric layer and the fifth gate conductive material layer in the fifth dummy gate trench 206 to form a second dummy gate trench filling structure. Since the fifth gate conductive material layer is also connected to the emitter, the introduction of the second dummy gate trench filling structure can adjust the capacitance between the emitter and the collector, i.e. Cec; at the same time, the introduction of the second dummy gate trench filling structure can also make the potential at the bottom region of the second gate trench 204 with a larger gap more uniform, thereby improving the breakdown voltage (BV); therefore, the fourth embodiment of the present application can combine the second trench gate formed in the second gate trench 204 and the second dummy gate trench filling structure formed in the fifth dummy gate trench 206, thereby adjusting the Miller capacitance while making the potential at the bottom of each trench more uniform, thereby further optimizing Cec and BV.

[0080] According to the features disclosed in the first to fourth embodiments of the present application, the features used in the first to fourth embodiments of the present application can be combined to obtain more embodiments, which will not be listed one by one here.

[0081] As shown in Figure 7 , the collector current and collector voltage of the existing IGBT device and the first embodiment of the IGBT device of the present application vary with time, wherein:

[0082] Curve 301 is a dynamic curve of the collector voltage of the existing IGBT device varying with time, and the vertical coordinate corresponding to the collector voltage uses the right coordinate axis;

[0083] Curve 302 is a dynamic curve of collector voltage of the IGBT device of the first embodiment of the present application versus time;

[0084] Curve 303 is a dynamic curve of collector current of the prior art IGBT device versus time, and the ordinate corresponding to the collector current uses the left coordinate axis;

[0085] Curve 304 is a dynamic curve of collector current of the IGBT device of the first embodiment of the present application versus time.

[0086] By comparing curve 302 with curve 301, it can be seen that in the turn-on process, the collector voltage in curve 302 changes more slowly, i.e. dv / dt is smaller, where dv / dt represents the rate of change of the collector voltage versus time, i.e. the derivative of the two.

[0087] Similarly, by comparing curve 304 with curve 303, it can be seen that the collector current also changes more slowly.

[0088] The above has described the present application in detail through specific embodiments, but these do not constitute a limitation on the present application. Those skilled in the art can also make many modifications and improvements without departing from the principles of the present application, and these should also be considered as falling within the protection scope of the present application.

Claims

1. An IGBT device, characterized in that, include: A plurality of first trench gates, each first trench gate including a first gate dielectric layer and a first gate conductive material layer filled in a first gate trench, the first gate conductive material layer being connected to a gate composed of a front metal layer; In terms of layout structure, each of the first gate trenches is arranged in parallel; A Miller capacitance continuously adjustable structure is provided on at least one of the first gate trenches; The Miller capacitance continuous adjustment structure includes: The second trench gate includes a second gate dielectric layer and a second gate conductive material layer filled in a second gate trench; The second gate trench intersects with the corresponding first gate trench, the second gate trench and the first gate trench are connected, and the second gate conductive material layer and the first gate conductive material layer are electrically connected. Taking advantage of the fact that the second gate trench intersects with the first gate trench, the length, spacing, and number of the second gate trench are independent of the first gate trench. The Miller capacitance can be adjusted by adjusting the length, spacing, or number of the second gate trench, and the Miller capacitance can be continuously adjusted.

2. The IGBT device as described in claim 1, characterized in that, Also includes: One or more first pseudo-gate trench filling structures, wherein the first pseudo-gate trench filling structure includes a third gate dielectric layer and a third gate conductive material layer filled in a third pseudo-gate trench, and the third gate conductive material layer is connected to an emitter composed of a front metal layer; In terms of layout structure, the third pseudo-gate trench and each of the first gate trenches are arranged in parallel.

3. The IGBT device as described in claim 2, characterized in that: The second gate trench and the corresponding first gate trench intersect perpendicularly.

4. The IGBT device as described in claim 3, characterized in that: The width of the second gate trench is equal to the width of the first gate trench.

5. The IGBT device as described in claim 3, characterized in that: The second gate trench intersects with one side of the corresponding first gate trench.

6. The IGBT device as described in claim 5, characterized in that: The second gate trench is provided on one side of the corresponding first gate trench, or the second gate trench is provided on both sides of the corresponding first gate trench.

7. The IGBT device as described in claim 3, characterized in that: The second gate trench passes through the two sides of the corresponding first gate trench.

8. The IGBT device as described in claim 6, characterized in that: A fourth gate trench is connected between a plurality of second gate trenches that intersect with one side of the corresponding first gate trench; The fourth trench gate is composed of a fourth gate dielectric layer and a fourth gate conductive material layer filled in the fourth gate trench.

9. The IGBT device as described in claim 8, characterized in that: In cross-sectional structure, the IGBT device includes: a body region doped with a second conductivity type, a drift region doped with a first conductivity type, an emitter region heavily doped with a first conductivity type formed on the surface of the body region, and a collector region heavily doped with a second conductivity type located on the back side of the drift region. The first gate trench, the second gate trench, the third dummy gate trench, and the fourth gate trench all pass through the body region; The top of the emitting region and the body region are connected to the emitting electrode through a first contact hole.

10. The IGBT device as described in claim 9, characterized in that: In terms of layout structure, each of the first contact holes and the first gate trenches are arranged in parallel; In the arrangement direction of the first gate trench, the region between two adjacent first contact holes forms a periodic unit of the IGBT device.

11. The IGBT device as described in claim 1 or 2, characterized in that, Also includes: One or more second pseudo-gate trench filling structures, the second pseudo-gate trench filling structure including a fifth gate dielectric layer and a fifth gate conductive material layer filled in a fifth pseudo-gate trench, the fifth gate conductive material layer being connected to an emitter composed of a front metal layer; In terms of layout structure, the fifth pseudo-gate trench is parallel to the second gate trench, and a plurality of the fifth pseudo-gate trenches are provided between adjacent second gate trenches.

12. The IGBT device as described in claim 11, characterized in that: The widths, spacings, or spacings of the fifth pseudo-gate trenches between each of the second gate trenches are equal.

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