An SOI-LDMOS device with full-encircling charge compensation

Abstract

The present application belongs to the field of power LDMOS devices, and provides a SOI-LDMOS device adopting full-surrounding charge compensation, which is used to improve the contradictory relationship between the breakdown voltage and the specific on-resistance of the device, improve the Baliga merit figure of the SOI-LDMOS, and improve the anti-charge deviation capability of the device and the robustness. In the present application, the HK layer and the fin-shaped P-type variable-doped region form full-surrounding charge compensation for the fin-shaped N-type drift region; the P-type variable-doped region and the N-type drift region are depleted with each other, form a variable electric field distribution in the longitudinal direction, reduce the surface electric field intensity of the device, form double RESURF, and improve the voltage-withstanding characteristics of the device; at the same time, the HK layer forms three-face charge compensation for the N-type drift region, so that the surface of the N-type drift region obtains enhanced RESURF effect, thereby improving the surface electric field distribution of the device and further optimizing the relationship between the breakdown voltage and the specific on-resistance of the device; in addition, the HK material also endows the device with the capability of resisting charge deviation, and improves the robustness of the device.

Description

Technical Field

[0001] This invention belongs to the field of power LDMOS (Lateral Double-Diffused MOSFET) devices, and mainly relates to a new power SOI-LDMOS structure with full-around charge compensation. This structure has a high Baliga figure of merit and good robustness, and has a wide range of applications. Background Technology

[0002] Power LDMOS is a unipolar voltage-controlled device with advantages such as easy drive, low power consumption, high breakdown voltage, high integration density, and fast switching speed. Therefore, it is widely used in power integrated circuits in various fields, such as switching power supplies, automotive electronics, and industrial motors. However, LDMOS uses a lateral breakdown voltage design. To increase the device's breakdown voltage (BV), it is usually necessary to increase the drift region length or reduce the drift region doping dose, which leads to an increase in the device's specific on-resistance (R). ON，SP The power consumption of the device increases rapidly due to the sharp increase in power consumption.

[0003] To optimize the BV and R of power LDMOS ON，SP To address the inherent contradictions between these factors, researchers have proposed various optimization techniques, such as reducing the surface electric field (RESURF), lateral variable doping (VLD), field plate (FP), and lateral superjunction (LSJ). Over time, these techniques have generally developed along three trends: First, by introducing a heterogeneous space charge layer into power LDMOS to compensate for the charge in its drift region, this not only flattens the electric field distribution in the drift region and increases the bottom voltage (BV), but also maximizes the doping concentration in the drift region while maintaining charge balance, thereby reducing the specific on-resistance. Second, various methods are used to optimize the lateral and longitudinal electric fields of power LDMOS to achieve a flattened electric field distribution, thereby improving the device breakdown voltage. VLD or FP are typical techniques for addressing this trend. Third, with the development of non-planar processes, non-planar LDMOS structures are expected to achieve even better performance.

[0004] Charge compensation is a crucial technique for optimizing LDMOS performance. However, existing charge compensation mechanisms primarily compensate the drift region from two or at most three directions. Therefore, this invention proposes a novel all-around charge compensation mechanism where the charge compensation layer surrounds the drift region from four sides, providing comprehensive compensation. This invention maintains high breakdown voltage while increasing the doping concentration in the drift region and reducing the specific on-resistance, thereby improving the device's Baliga figure of merit. Furthermore, the high dielectric constant (HK) dielectric, present in the form of a charge compensation layer, can suppress performance degradation caused by deviations between the actual charge distribution and the ideal design (charge deviation), increasing the product's robustness. Summary of the Invention

[0005] The purpose of this invention is to propose a novel all-around charge compensation mechanism to optimize the performance of SOI-LDMOS, further improve the contradictory relationship between device breakdown voltage and specific on-resistance, enhance the Baliga figure of merit of SOI-LDMOS, and improve the device's resistance to charge deviation and robustness.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0007] A SOI-LDMOS device employing full-around charge compensation includes: a silicon substrate (01), a buried oxide layer (02), a finned P-type well region (03), a finned P-type variable-doped region (04), a finned N-type drift region (05), an HK layer (06), a drain N+ region (07), a source N+ region (08), a source P+ region (09), a gate oxide layer (10), a source (11), a gate (12), and a drain (13); characterized in that,

[0008] The buried oxide layer (02) is disposed above the silicon substrate (01); the fin-shaped P-type well region (03) and the fin-shaped P-type variable doping region (04) are disposed above the buried oxide layer (02); the fin-shaped N-type drift region (05) is disposed above the fin-shaped P-type variable doping region (04), and both are adjacent to the fin-shaped P-type well region (03);

[0009] The source N+ region (08) and source P+ region (09) are adjacent to each other in the fin-shaped P-type well region (03), and the source (11) is disposed on the outer surface of the source N+ region (08) and source P+ region (09); the drain N+ region (07) is disposed in the fin-shaped N-type drift region (05), and the drain (13) is disposed on the outer surface of the drain N+ region (07); the gate oxide layer (10) is disposed on the outer surface of the fin-shaped P-type well region (03), and the gate (12) is disposed on the outer surface of the gate oxide layer (10); the HK layer (06) is disposed on the outer surface of the fin-shaped P-type variable doped region (04) and the fin-shaped N-type drift region (05), and is located between the gate and the drain;

[0010] The HK layer (06) provides charge compensation on three sides of the fin-shaped N-type drift region (05), and the fin-shaped P-type variable doped region (04) provides charge compensation on the bottom surface of the fin-shaped N-type drift region (05). The doping dose of the fin-shaped P-type variable doped region (04) decreases linearly or stepwise along the direction from the source end to the drain end.

[0011] Furthermore, the finned P-type well region (03), the finned P-type variable doping region (04), and the finned N-type drift region (05) are all trapezoidal in cross-section perpendicular to the direction from the source end to the drain end, and the base angle is 45 degrees.

[0012] Furthermore, the HK layer is made of strontium titanate (SrTiO3, abbreviated as STO).

[0013] Furthermore, a P-type floating sublayer is also provided in the fin-shaped N-type drift zone (05), and it is located in the middle of the fin-shaped N-type drift zone.

[0014] Furthermore, a P-type compensation layer is also provided on the top of the fin-shaped N-type drift region (05).

[0015] The advantages of this invention are:

[0016] This invention provides a novel LDMOS structure employing a novel all-around charge compensation mechanism. The HK layer and the fin-shaped P-type variable-doped region provide all-around charge compensation to the fin-shaped N-type drift region. When the device is in the off state, the P-type variable-doped region and the N-type drift region deplete each other, creating a varying electric field distribution in the vertical direction. This electric field, on the one hand, introduces part of the electric field from the device surface into the bulk, thereby reducing the surface electric field intensity and forming a double resurface; on the other hand, the varying electric field helps to weaken the influence of substrate-assisted depletion effect, achieving the goal of improving the device's breakdown voltage characteristics. Simultaneously, the HK layer provides three-sided charge compensation to the N-type drift region. The HK material guides the flow of current, enhancing the resurface effect on the surface of the N-type drift region, thereby improving the surface electric field distribution and ultimately further optimizing the relationship between the device's breakdown voltage and specific on-resistance.

[0017] The use of HK material not only serves as charge compensation but also endows the device with the ability to resist charge deviation, thus improving its robustness. When charge deviation occurs, the amount of deviated charge generates an additional electric field, perturbing the original electric field distribution and reducing the breakdown voltage. In the structure of this invention, when charge deviation occurs, the HK layer generates a depolarization electric field opposite to the direction of the additional electric field, causing the surface electric field to tend to return to its original state, thereby minimizing the impact of charge deviation.

[0018] In addition, this invention employs a finned drift region, with the gate surrounding the channel formed by the source and drain on three sides, drastically widening the channel and reducing the channel resistance, thereby lowering the on-resistance of the device. In terms of fabrication, strontium titanate is proposed as the HK material, due to its high dielectric constant and compatibility with silicon processes. To achieve a high-quality interface between the HK film and silicon, anisotropic etching can be used to obtain a finned substrate with a Si(001) platform and Si(011) sidewalls. With the sidewalls tilted at 45°, the lattice mismatch at the interface between the HK film and the sidewalls is only 1.7%, resulting in an ideal interface. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the SOI-LDMOS device with full-surround charge compensation in Embodiment 1 of the present invention.

[0020] Figure 2 for Figure 1 The diagram shows a cross-sectional view of an SOI-LDMOS device with full-around charge compensation along AA' and BB'.

[0021] Figure 3 This is a process flow diagram of the fabrication of the SOI-LDMOS device with full-surround charge compensation in Embodiment 2 of the present invention.

[0022] Figure 4 This is a schematic diagram of the SOI-LDMOS device with full-surround charge compensation in Embodiment 3 of the present invention.

[0023] Figure 5 for Figure 4 The diagram shows a cross-sectional view of an SOI-LDMOS device with full-around charge compensation along AA' and BB'.

[0024] Figure 6 This is a schematic diagram of the SOI-LDMOS device with full-surround charge compensation in Embodiment 4 of the present invention.

[0025] Figure 7 for Figure 6 The diagram shows a cross-sectional view of an SOI-LDMOS device with full-around charge compensation along AA' and BB'.

[0026] Figure 8 This is a schematic diagram of the comparative example in Embodiment 1 of the present invention.

[0027] Figure 9 for Figure 8 The diagram shows a comparative example with cross-sections along AA' and BB'.

[0028] Figure 10 This is a diagram showing the electric field distribution in the critical breakdown state of Embodiment 1 of the present invention.

[0029] Figure 11 The diagram shows the IV characteristics of Embodiment 1 and the comparative example of the present invention under reverse withstand voltage.

[0030] Figure 12 In Example 1 and the comparative example of the present invention, the doping concentration in the drift region was 4 × 10⁻⁶. 16 cm -3 Comparison of one-dimensional surface electric field distribution over time.

[0031] Figure 13 This is a schematic diagram illustrating the principle of the HK layer's resistance to charge deviation when charge deviation occurs along the AA' section in Embodiment 1 of the present invention. Detailed Implementation

[0032] To make the objectives, technical solutions, and technical effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0033] Example 1

[0034] This embodiment provides an SOI-LDMOS device employing full-wrap charge compensation, the structure of which is as follows: Figure 1 , Figure 2 As shown, to better illustrate the device structure, coordinate axes are added to the device structure: the x-axis (length) represents the left-right direction, the y-axis (height) represents the up-down direction, and the z-axis (width) represents the front-back direction; specifically, it includes: silicon substrate (01), buried oxide layer (02), finned P-type well region (03), finned P-type variable doped region (04), finned N-type drift region (05), HK layer (06), drain N+ region (07), source N+ region (08), source P+ region (09), gate oxide layer (10), source (11), gate (12), and drain (13), among which,

[0035] The buried oxide layer (02) is disposed above the silicon substrate (01); the fin-shaped P-type well region (03) and the fin-shaped P-type variable doping region (04) are disposed above the buried oxide layer (02); the fin-shaped N-type drift region (05) is disposed above the fin-shaped P-type variable doping region (04), and both are adjacent to the fin-shaped P-type well region (03);

[0036] The source N+ region (08) and source P+ region (09) are adjacent to each other in the fin-shaped P-type well region (03), and the source (11) is disposed on the outer surface of the source N+ region (08) and source P+ region (09); the drain N+ region (07) is disposed in the fin-shaped N-type drift region (05), and the drain (13) is disposed on the outer surface of the drain N+ region (07); the gate oxide layer (10) is disposed on the outer surface of the fin-shaped P-type well region (03), and the gate (12) is disposed on the outer surface of the gate oxide layer (10); the HK layer (06) is disposed on the outer surface of the fin-shaped P-type variable doped region (04) and the fin-shaped N-type drift region (05), and is located between the gate and the drain;

[0037] The HK layer (06) provides charge compensation on three sides of the fin-shaped N-type drift region (05), and the fin-shaped P-type variable doped region (04) provides charge compensation on the bottom surface of the fin-shaped N-type drift region (05). The doping dose of the fin-shaped P-type variable doped region (04) decreases linearly or stepwise along the direction from the source end to the drain end.

[0038] The finned P-type well region (03), the finned P-type variable doped region (04), and the finned N-type drift region (05) are all trapezoidal in cross-section perpendicular to the direction from the source end to the drain end, and the base angle is 45 degrees.

[0039] The HK layer is made of strontium titanate (SrTiO3, abbreviated as STO).

[0040] In terms of working principle:

[0041] When the device is in the off-voltage state, the P-type variable-doped region (P-VLD region) and the N-type drift region are mutually depleted, resulting in a roughly rectangular distribution of the lateral electric field on the device surface. This increases the reverse breakdown voltage of the device without increasing the specific on-resistance. Therefore, under the same breakdown voltage conditions, the doping concentration of the N-type drift region can be designed to be very high, and the specific on-resistance of the device structure can be greatly reduced. Furthermore, the doping amount of the P-VLD region in this invention decreases linearly or stepwise from the main junction to the drain, so that after charge compensation, the doping concentration of the drift region can be approximately considered to increase linearly or stepwise from the main junction to the drain. This reduces the electric field at the main junction and increases the electric field at the drain, thereby increasing the average electric field strength of the device drift region and improving the breakdown voltage of the device.

[0042] Simultaneously, the N-type drift region is also subject to charge compensation from the HK layer film. During reverse breakdown, the gate is at a low potential, and there is a potential difference between the gate and the N-type drift region. This potential difference generates an electric field in the HK film that points from the N-type drift region to the gate. This electric field polarizes the HK film, generating negative charges on the lower surface of the high dielectric constant film. These negative charges can attract the electric field lines emitted by ionized donor impurities near the surfaces of the fin-shaped N-type drift region, thereby enhancing the RESURF in three dimensions and optimizing the relationship between the device breakdown voltage and specific on-resistance.

[0043] This embodiment uses a traditional SOI-LDMOS device with a charge-compensating drift region surrounded on three sides by HK material as a comparative example. Its structure is as follows: Figure 8 , 9 As shown in the figure; and the Sentaurus simulation software was used for simulation testing to verify that the performance of the SOI-LDMOS device structure with full-around charge compensation in this invention has been optimized and improved compared with the traditional structure; since it is difficult to achieve precise gradient doping in current processes, a segmented uniform doping method (i.e., step-like decrease) was adopted in the P-VLD region, dividing the P-VLD region into 4 regions with different doping concentrations along the x-direction. The 4 regions have the same length in the x-direction. The relevant simulation parameters are shown in Tables 1 and 2, and the simulation results are as follows. Figure 10 , 11 As shown in Figures 1 and 12.

[0044] Table 1: Relevant Parameters of Device Simulation Structure

[0045]

[0046] Figure 10 This is a power line distribution diagram of the SOI-LDMOS device with full-around charge compensation in the critical breakdown state, obtained along the BB′ section at x = 3 μm. In the diagram, some power lines at the top and sides of the N-type drift region are absorbed by the HK thin film, forming an enhanced RESURF effect under a mechanism similar to three-sided charge compensation; in addition to some power lines at the bottom of the N-type drift region being absorbed by the substrate under buried oxide, a considerable portion of the power lines are absorbed by the P-VLD region, completing the charge compensation of the bottom surface of the N-type drift region.

[0047] Figure 11 The diagram shows a comparison of the reverse breakdown IV characteristics of the present invention and the comparative example. At this point, the breakdown voltage of both device structures is 98V, and the doping concentration in each region is shown in Table 2. With the fully encircling charge compensation mechanism, the N-type drift region of the present invention is compensated more thoroughly, thus maintaining the same breakdown voltage while increasing the doping concentration in the drift region by 53%.

[0048] Table 2: Doping concentration in different regions inside the device at 98V breakdown

[0049]

[0050] Figure 12 To achieve a doping concentration of 4 × 10⁻⁶ in the drift region 16 cm -3 The figure shows a comparison of the one-dimensional surface electric field distribution of a conventional SOI-LDMOS device with a three-sided charge compensation drift region using HK material and a SOI-LDMOS device with a fully surrounded charge compensation region. The figure is obtained along the x-direction at y = 2 μm and z = 2.95 μm. As can be seen from the figure, the surface electric field distribution of the device structure of the present invention is more uniform and flat. At this time, the breakdown voltage of the conventional structure is 38V, while the breakdown voltage of the device structure of the present invention is 98V.

[0051] Figure 13 This diagram illustrates the principle of charge deviation resistance of the HK layer in the structure of this invention when charge deviation occurs. The diagram is obtained along the AA' section of the structure. When the actual doping concentration in the drift region deviates from the ideal design, an additional charge ΔQ will appear in the drift region. N ΔQ N It will create an additional electric field E N This disturbs the original electric field distribution in the device structure, reducing BV. However, the structure of this invention exhibits a load deflection ΔQ. N At that time, the additional electric field E N The electrode extends into the HK layer, generating a large number of electric dipole moments in the HK dielectric, thus inducing a polarization charge ΔQ at its lower boundary. P Polarization charge ΔQ P Always produced within the membrane with E N The depolarization electric field in the opposite direction, therefore ΔQ P With ΔQ N The opposite sign will eventually compensate for ΔQ. N This allows the electric field in the device structure to return to its original distribution. The higher the relative permittivity and the greater the thickness of the HK layer, the greater the ΔQ. P The closer to ΔQ N The more sufficient the compensation, the better the anti-load bias effect.

[0052] Example 2

[0053] This embodiment provides a method for fabricating the SOI-LDMOS device with full-surround charge compensation as described in Embodiment 1, such as... Figure 3As shown, the specific steps are as follows: (a) Take a single-crystal Si with a surface crystal orientation of (001) as the intrinsic SOI substrate; (b) Perform ion implantation using a VLD plate, and obtain a P-type variable doped region by high-temperature diffusion; (c) Fabricate epitaxy to obtain an N-type drift region; (d) Form a FIN drift region using related processes; (e) Epitaxially grow a thin single-crystal silicon buffer layer to further optimize the preferred orientation between the platform and the sidewall; (f) Form a P-well using ion implantation and high-temperature push junction, and then dope the buffer layer on the right side of the P-well by ion implantation to make the doping concentration of the buffer layer and the drift region the same; (g) Deposit STO to fabricate an HK thin film, and expose the active region after partial etching; (h) Deposit and etch SiO2 and Gate-poly to form a gate; (i) After ion implantation, rapidly anneal to form N+ and P+ on the buffer layer; (j) Deposit SiO2 to isolate the source and gate, and obtain the illustrated structure after metal patterning, and then fabricate the chip through conventional back-end processes.

[0054] Example 3

[0055] This embodiment provides an SOI-LDMOS device employing full-around charge compensation and buried layer technology, the structure of which is as follows: Figure 4 , Figure 5 As shown, its basic structure is the same as that of Example 1. The only difference is that a P-type floating buried layer is also provided in the fin-shaped N-type drift region (05), and it is located in the middle of the fin-shaped N-type drift region. The addition of the P-type floating buried layer not only achieves the effect of multiple RESURF, but also more comprehensively compensates the drift region, which is conducive to further increasing the doping concentration of the drift region and reducing the specific on-resistance while maintaining high withstand voltage.

[0056] Example 4

[0057] This embodiment provides an SOI-LDMOS device employing full-around charge compensation and buried layer technology, the structure of which is as follows: Figure 6 , Figure 7 As shown, its basic structure is the same as that of Embodiment 1. The only difference is that a P-type compensation layer is also provided on the top of the fin-shaped N-type drift region (05). The addition of the top P-type compensation layer not only achieves the effect of double RESURF, but also provides more comprehensive compensation for the drift region, thereby further optimizing the device performance.

[0058] The above description is merely a specific embodiment of the present invention. Any feature disclosed in this specification may be replaced by other equivalent or similar features unless otherwise specified. All disclosed features, or steps in all methods or processes, may be combined in any way except for mutually exclusive features and / or steps.

Claims

1. A SOI-LDMOS device employing full-wrap charge compensation, comprising: The silicon substrate (01), buried oxide layer (02), finned P-type well region (03), finned P-type variable doped region (04), finned N-type drift region (05), HK layer (06), drain N+ region (07), source N+ region (08), source P+ region (09), gate oxide layer (10), source (11), gate (12), and drain (13); characterized in that, The buried oxide layer (02) is disposed above the silicon substrate (01); the fin-shaped P-type well region (03) and the fin-shaped P-type variable doping region (04) are disposed above the buried oxide layer (02); the fin-shaped N-type drift region (05) is disposed above the fin-shaped P-type variable doping region (04), and both are adjacent to the fin-shaped P-type well region (03); The source N+ region (08) and source P+ region (09) are adjacent to each other in the fin-shaped P-type well region (03), and the source (11) is disposed on the outer surface of the source N+ region (08) and source P+ region (09); the drain N+ region (07) is disposed in the fin-shaped N-type drift region (05), and the drain (13) is disposed on the outer surface of the drain N+ region (07); the gate oxide layer (10) is disposed on the outer surface of the fin-shaped P-type well region (03), and the gate (12) is disposed on the outer surface of the gate oxide layer (10); the HK layer (06) is disposed on the outer surface of the fin-shaped P-type variable doped region (04) and the fin-shaped N-type drift region (05), and is located between the gate and the drain; The HK layer (06) provides charge compensation on three sides of the fin-shaped N-type drift region (05), and the fin-shaped P-type variable doped region (04) provides charge compensation on the bottom surface of the fin-shaped N-type drift region (05). The doping dose of the fin-shaped P-type variable doped region (04) decreases linearly or stepwise along the direction from the source end to the drain end.

2. The SOI-LDMOS device with full-around charge compensation as described in claim 1, characterized in that, The finned P-type well region (03), the finned P-type variable doped region (04), and the finned N-type drift region (05) are all trapezoidal in cross-section perpendicular to the direction from the source end to the drain end, and the base angle is 45 degrees.

3. The SOI-LDMOS device with full-around charge compensation as described in claim 1, characterized in that, The HK layer is made of strontium titanate.

4. The SOI-LDMOS device with full-around charge compensation as described in claim 1, characterized in that, The fin-shaped N-type drift zone (05) is also provided with a P-type floating buried layer, which is located in the middle of the fin-shaped N-type drift zone.

5. The SOI-LDMOS device with full-surround charge compensation as described in claim 1, characterized in that, A P-type compensation layer is also provided on the top of the fin-shaped N-type drift region (05).

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