A switched capacitor voltage converter

Abstract

The application discloses a switched capacitor voltage converter, and relates to the technical field of electronic circuits, which comprises a switched capacitor voltage conversion circuit, a monitoring module, a clamping transistor and a clamping circuit. The monitoring module is used for monitoring the electrical parameters of an input terminal VBUS and an output terminal VOUT, and outputting a voltage to the gate terminal of the clamping transistor according to the electrical parameters, so that the voltage value of the output terminal VOUT is stabilized at a target value. The clamping circuit is used for making the voltage difference between the drain terminal and the source terminal of the clamping transistor less than the withstand voltage of the clamping transistor. By introducing a clamping module on the clamping transistor, the voltage difference between the drain terminal and the source terminal of the clamping transistor is made less than the withstand voltage of the clamping transistor, so that the withstand voltage of the clamping transistor is reduced, the area of the transistor is reduced, and the cost is reduced.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, and in particular to a switched capacitor voltage converter. Background Technology

[0002] See Figure 1 Existing adjustable switched-capacitor voltage converter circuits have a transistor QB between the input terminals VBUS and PMID. The substrate of QB is connected to the source terminal, PMID, and the diode QB points from PMID to VBUS, thus completely disconnecting the input terminal VOUT and the output terminal VBUS. During operation, the loop regulation module monitors the error between the output voltage VOUT, the input current IBUS, or other parameters and the target value, and adjusts the gate voltage QB_GT of QB to regulate the voltage difference between PMID and VBUS. Changes in the PMID voltage cause changes in the output voltage VOUT, the input current IBUS, or other parameters, thus stabilizing these parameters at the target value.

[0003] The disadvantage of the above-mentioned adjustable switched capacitor voltage converter structure is that the withstand voltage of transistor QB needs to exceed the maximum value of the input voltage VBUS, but such transistors have a large area and high cost. Summary of the Invention

[0004] The purpose of this application is to provide a switched capacitor voltage converter that allows the transistor's withstand voltage to not exceed the maximum value of the input VBUS voltage, thereby reducing the transistor's area and lowering costs.

[0005] To achieve the above objectives, the following solutions are provided:

[0006] A switched capacitor voltage converter includes: a switched capacitor voltage conversion circuit, a monitoring module, a clamping transistor, and a clamping circuit;

[0007] The gate terminal of the clamping transistor is connected to the voltage output terminal of the monitoring module, the drain terminal of the clamping transistor is connected to the input terminal VBUS of the switched capacitor voltage converter, and the source terminal of the clamping transistor is connected to the input terminal of the switched capacitor voltage conversion circuit.

[0008] The monitoring module is used to monitor the electrical parameters of the input terminal VBUS and the output terminal VOUT of the switched capacitor voltage converter, and output voltage to the gate terminal of the clamping transistor according to the electrical parameters, so that the voltage value of the output terminal VOUT is stabilized at the target value.

[0009] The clamping circuit is used to ensure that the voltage difference between the drain and source terminals of the clamping transistor is less than or equal to the withstand voltage of the clamping transistor.

[0010] Optionally, the clamping circuit includes a first resistor, a first gate adjustment element, a first diode, and a first transistor;

[0011] The negative terminal of the first gate adjustment element is connected to the drain terminal of the clamping transistor, and the positive terminal of the first gate adjustment element is connected to the source terminal of the clamping transistor through the first resistor.

[0012] The anode of the first diode is connected to the drain of the clamping transistor, the cathode of the first diode is connected to the drain of the first transistor, the source of the first transistor is connected to the gate of the clamping transistor, and the gate of the first transistor is connected to a first connection point, which is a point on the connection line between the first gate adjustment element and the first resistor.

[0013] Optionally, the first gate adjustment element is a Zener diode, a diode connected in series, or a transistor connected in series.

[0014] Optionally, the clamping circuit includes a second resistor, a second gate adjustment element, a second diode, and a second transistor;

[0015] The positive terminal of the second gate adjustment element is connected to the source terminal of the clamping transistor, and the negative terminal of the second gate adjustment element is connected to the drain terminal of the clamping transistor through the second resistor.

[0016] The negative terminal of the second diode is connected to the gate terminal of the clamping transistor, the positive terminal of the second diode is connected to the drain terminal of the second transistor, the source terminal of the second transistor is connected to the drain terminal of the clamping transistor, and the gate terminal of the second transistor is connected to a second connection point, which is a point on the connection line between the second gate adjustment element and the second resistor.

[0017] Optionally, the second gate adjustment element is a Zener diode, a diode connected in series, or a transistor connected in series.

[0018] Optionally, the switched capacitor voltage conversion circuit is a dual-channel 2:1 switched capacitor voltage conversion circuit.

[0019] Optionally, the switched capacitor voltage conversion circuit includes a first branch and a second branch; one end of the first branch is connected to a reference point, and the other end of the first branch is grounded; one end of the second branch is connected to the reference point, and the other end of the second branch is grounded; the reference point is the input terminal of the switched capacitor voltage conversion circuit.

[0020] The first branch includes a first switched capacitor and a first switched transistor, a second switched transistor, a third switched transistor, and a fourth switched transistor connected in series; the first switched capacitor is connected in parallel with the second switched transistor and the third switched transistor; the second branch includes a second switched capacitor and a fifth switched transistor, a sixth switched transistor, a seventh switched transistor, and an eighth switched transistor connected in series; the second switched capacitor is connected in parallel with the sixth switched transistor and the seventh switched transistor.

[0021] The connection points of the first branch and the second branch are both connected to the output terminal VOUT of the switched capacitor voltage converter; the connection point of the first branch is a point on the connection line between the second switch and the third switch; the connection point of the second branch is a point on the connection line between the sixth switch and the seventh switch.

[0022] Optionally, it also includes: a first substrate switching module and a second substrate switching module; the first substrate switching module is connected to the substrate of the second switching transistor, and is used to connect the source terminal of the second switching transistor to the output terminal VOUT when the switched capacitor voltage conversion circuit is in the working state, and to ground the source terminal of the second switching transistor when the switched capacitor voltage conversion circuit is in the stopped working state.

[0023] The second substrate switching module is connected to the substrate of the sixth switching transistor and is used to connect the source terminal of the sixth switching transistor to the output terminal VOUT when the switched capacitor voltage conversion circuit is in operation, and to ground the source terminal of the sixth switching transistor when the switched capacitor voltage conversion circuit is in operation.

[0024] Optionally, the input terminal of the switched capacitor voltage conversion circuit is grounded through a reference capacitor.

[0025] Optionally, the output terminal VOUT is grounded through an output capacitor; the output capacitor is connected in parallel with an output resistor.

[0026] According to the specific embodiments provided in this application, the following technical effects are disclosed: The switched-capacitor voltage converter provided in this application includes: a switched-capacitor voltage conversion circuit, a monitoring module, a clamping transistor, and a clamping circuit; the gate terminal of the clamping transistor is connected to the voltage output terminal of the monitoring module, the drain terminal of the clamping transistor is connected to the input terminal VBUS of the switched-capacitor voltage converter, and the source terminal of the clamping transistor is connected to the input terminal of the switched-capacitor voltage conversion circuit; the monitoring module is used to monitor the electrical parameters of the input terminal VBUS and the output terminal VOUT of the switched-capacitor voltage converter, and outputs a voltage to the gate terminal of the clamping transistor according to the electrical parameters, so that the voltage value of the output terminal VOUT is stabilized at a target value; the clamping circuit is used to make the voltage difference between the drain terminal and the source terminal of the clamping transistor less than or equal to the withstand voltage of the clamping transistor. This application introduces a clamping module on the clamping transistor, making the voltage difference between the drain terminal and the source terminal of the clamping transistor less than the withstand voltage of the clamping transistor, thereby reducing the withstand voltage of the clamping transistor, reducing the transistor area, and reducing the cost. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 A circuit diagram of an existing adjustable switched-capacitor voltage converter provided for embodiments of this application;

[0029] Figure 2 A circuit diagram of a novel adjustable switched-capacitor voltage converter provided for embodiments of this application;

[0030] Figure 3 Circuit diagrams of two clamping circuits provided in embodiments of this application;

[0031] Figure 4 A diagram showing the connection relationship between a series-connected transistor and a series-connected diode, provided for an embodiment of this application. Detailed Implementation

[0032] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0033] Figure 1The diagram shows an existing adjustable switched-capacitor voltage converter circuit with an input voltage VBUS of approximately 10V and an output voltage of approximately 5V. This switched-capacitor voltage converter meets two requirements: a) when the switched-capacitor voltage converter is not operating, the input terminal VBUS and the output terminal VOUT are bidirectionally isolated; b) the output voltage VOUT, the input current IBUS, or other parameters can be adjusted to target values.

[0034] Between the voltages PMID and VOUT is a dual-path 2:1 switched-capacitor voltage converter. The substrates of Q1A, Q3A, Q4A, Q1B, Q3B, and Q4B are each connected to their respective source terminals. The substrates of Q2A and Q2B are connected to the BD SW module. When the switched-capacitor voltage converter is operating normally, the BD SW module connects the substrates to their source terminals (i.e., the output voltage VOUT). When the switched-capacitor voltage converter stops operating, its substrates are connected to ground (GND). This ensures a complete disconnection between VOUT and PMID when the switched-capacitor voltage converter stops operating, as there is no diode path between VOUT and PMID.

[0035] The aforementioned adjustable switched-capacitor voltage converter circuit has a transistor QB between the input terminals VBUS and PMID. The substrate of QB is connected to the source terminal, PMID, and the diode QB points from PMID to VBUS, thus completely disconnecting the input terminal VOUT and the output terminal VBUS. During operation, the loop regulation module monitors the error between the output voltage VOUT, the input current IBUS, or other parameters and the target value, and adjusts the gate voltage QB_GT of QB to regulate the voltage difference between PMID and VBUS. Changes in the PMID voltage cause changes in the output voltage VOUT, the input current IBUS, or other parameters, thus stabilizing these parameters at the target values. The disadvantage of this adjustable switched-capacitor voltage converter structure is that the voltage rating of transistor QB needs to exceed the maximum value of the input voltage VBUS, but such a transistor has a larger area and higher cost.

[0036] The purpose of this application is to provide a switched capacitor voltage converter that allows the transistor's withstand voltage to not exceed the maximum value of the input VBUS voltage, thereby reducing the transistor's area and lowering the cost.

[0037] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0038] like Figure 2As shown, the switched capacitor voltage converter provided in this embodiment of the application includes:

[0039] Switched capacitor voltage conversion circuit, monitoring module (LOOP REGULATION), clamping transistor QB, and clamping circuit (VDS CLAMP).

[0040] The clamping transistor QB has its gate terminal QB_GT connected to the voltage output terminal of the monitoring module LOOP REGULATION, its drain terminal connected to the input terminal VBUS, and its source terminal connected to the input terminal (i.e., the reference point PMID) of the switched capacitor voltage conversion circuit; VDS represents the voltage difference between the drain and source terminals of QB.

[0041] The monitoring module (LOOP REGULATION) monitors the electrical parameters of the input terminal VBUS and the output terminal VOUT, and outputs a voltage to the gate terminal of the clamping transistor according to the electrical parameters to stabilize the voltage value of the output terminal VOUT at a target value. In this embodiment, stabilizing at the target value means that the voltage value of the output terminal VOUT is less than or equal to the target value; in this embodiment, the electrical parameters may include the voltage of the output terminal VOUT, the input current IBUS, or other parameters.

[0042] A clamping circuit is used to ensure that the voltage difference between the drain and source terminals of a clamping transistor is less than the withstand voltage of the clamping transistor.

[0043] The following example uses an input voltage of 10V and a target output voltage of 5V for VOUT. Figure 2 The circuit shown is explained below:

[0044] In this embodiment, the switched-capacitor voltage conversion circuit between the reference point PMID and the output terminal VOUT can be a dual-channel 2:1 switched-capacitor voltage conversion circuit. In other embodiments, depending on the needs of the actual application, the switched-capacitor voltage conversion circuit can also have other structures, and the ratio is not limited to 2:1.

[0045] like Figure 2 As shown, the above dual-path 2:1 switched capacitor voltage conversion circuit includes a first branch and a second branch; one end of the first branch is connected to the reference point PMID, and the other end of the first branch is grounded; one end of the second branch is connected to the reference point PMID, and the other end of the second branch is grounded; the reference point PMID is the input terminal of the switched capacitor voltage conversion circuit.

[0046] The first branch includes a first switched capacitor CFA and a first switched transistor Q1A, a second switched transistor Q2A, a third switched transistor Q3A, and a fourth switched transistor Q4A connected in series. The first switched capacitor CFA is connected in parallel with Q2A and Q3A. The second branch includes a second switched capacitor CFB and a fifth switched transistor Q1B, a sixth switched transistor Q2B, a seventh switched transistor Q3B, and an eighth switched transistor Q4B connected in series. The second switched capacitor CFB is connected in parallel with Q2B and Q3B.

[0047] The connection points of the first branch and the second branch are both connected to the output terminal VOUT. The connection point of the first branch is a point on the connection line between the second switch Q2A and the third switch Q3A; the connection point of the second branch is a point on the connection line between the sixth switch Q2B and the seventh switch Q3B. In this embodiment, the connection point can be the midpoint of the connection line or any other point on the connection line. In this embodiment, the input terminal PMID of the switched capacitor voltage conversion circuit is grounded through the reference capacitor CPMID, and the output terminal VOUT is grounded through the output capacitor COUT. An output resistor ROUT is connected in parallel with the output capacitor COUT.

[0048] In this circuit, the substrates of the first switch Q1A, third switch Q3A, fourth switch Q4A, fifth switch Q1B, seventh switch Q3B, and eighth switch Q4B are all connected to their respective source terminals. The substrate of the second switch Q2A is connected to the first substrate switching module BD_SW1, and the substrate of the sixth switch Q2B is connected to the second substrate switching module BD_SW2. When the switched-capacitor voltage converter is operating normally, modules BD_SW1 and BD_SW2 respectively connect the substrates to the source terminals (VOUT voltage) of the second and sixth switches Q2A and Q2B. When the switched-capacitor voltage converter is not operating, the substrates of the second and sixth switches Q2A are connected to ground (GND). This ensures that when the switched-capacitor voltage converter is not operating, there is no diode path from VOUT to PMID, and no diode path from PMID to VOUT, guaranteeing a complete disconnection between VOUT and PMID.

[0049] In this embodiment, the purpose of connecting the substrates of the second switch Q2A and the sixth switch Q2B to a substrate switching module BD_SW is that when the switched capacitor voltage converter stops working, there is no diode path from the output terminal VOUT to the reference point PMID, and there is no diode path from the reference point PMID to the output terminal VOUT, so that the VOUT terminal and the PMID terminal are completely disconnected.

[0050] A clamping transistor QB is located between the input terminal VBUS and the reference point PMID. The substrate of QB is connected to the source terminal, i.e., the reference point PMID, and QB points from PMID to VBUS, thus completely disconnecting the output terminal VOUT from the input terminal VBUS. When the switched-capacitor voltage conversion circuit is in operation, the module LOOP REGULATION monitors the error between the output terminal VOUT voltage, the input current IBUS, or other parameters and their target values. All three must not exceed their respective target values. The module adjusts the gate voltage QB_GT of QB, thereby regulating the voltage difference between the reference point PMID and the input terminal VBUS. Changes in the PMID voltage cause changes in the output terminal VOUT voltage, the input current IBUS, or other parameters. This, in turn, stabilizes the output terminal VOUT voltage, the input current IBUS, or other parameters within the target values ​​through the switched-capacitor voltage conversion circuit.

[0051] The clamping transistor QB has a clamping circuit VDS CLAMP (VDS represents the voltage difference between the drain and source of QB). The clamping circuit keeps the drain and source voltages of QB within a certain range. If the voltage difference VDS between the drain and source of QB exceeds the allowable range, it will pull up the gate voltage QB_GT, thereby raising the source voltage or lowering the drain voltage. For example... Figure 2 QB is a 5V withstand transistor. VDS CLAMP will limit the VDS of QB to around 5V. If VDS exceeds around 5V, the gate voltage QB_GT will be raised to increase the source voltage in order to keep VDS below around 5V.

[0052] This application introduces a clamping circuit VDS CLAMP onto the clamping transistor QB, and the withstand voltage of the clamping transistor QB only needs to meet the following two conditions:

[0053] (1) The withstand voltage of the clamping transistor QB exceeds the maximum voltage difference between the input terminal VBUS and the reference point PMID when the switched capacitor voltage conversion circuit is working normally (e.g., 0.5V).

[0054] (2) The voltage rating of clamp transistor QB plus the voltage rating of Q1A / Q1B exceeds the maximum voltage of input terminal VBUS.

[0055] In this embodiment, when the switched capacitor voltage conversion circuit is in operation, if the input VBUS voltage is below 5V, the VDS CLAMP module on QB does not function, and the reference point PMID voltage remains at 0. If the input VBUS voltage exceeds 5V, the VDS CLAMP module on QB starts functioning, and the reference point PMID voltage remains approximately equal to the input VBUS voltage minus 5V (i.e., PMID = VBUS - 5). Because the reference point PMID and the output VOUT are completely disconnected, the input VBUS and the output VOUT remain completely disconnected. Furthermore, when VBUS reaches its maximum voltage of 10V, the PMID voltage is 5V, the voltages at CFHA / CFHB are both 0V, and the voltages across Q1A / B are also approximately 5V. All transistors do not exceed their withstand voltage values ​​(e.g., 5V).

[0056] When the switched capacitor voltage converter circuit is working normally, the input terminal VBUS is connected to the voltage source, and the output terminal VOUT voltage is half of the PMID voltage. The monitoring module LOOP REGULATION monitors the error between the output terminal VOUT voltage, the input current IBUS, or other parameters and the target value, and adjusts the gate voltage QB_GT of QB, thereby adjusting the voltage difference between PMID and the input terminal VBUS. Changes in the PMID voltage will cause changes in the output terminal VOUT voltage, the input current IBUS, or other parameters. In turn, the switched capacitor voltage converter circuit can regulate and stabilize the output terminal VOUT voltage, the input current IBUS, or other parameters at the target value.

[0057] For example, if the output voltage VOUT exceeds the target value, the LOOP REGULATION module will reduce the gate voltage QB_GT of QB, and the source voltage PMID of QB will also decrease. Since the switched capacitor voltage conversion circuit is a dual-channel 2:1 switched capacitor voltage conversion circuit, the output voltage VOUT is half of the PMID voltage, and the output voltage VOUT will also decrease accordingly. Such a loop can stabilize the VOUT voltage at the target value.

[0058] The following section introduces two classic structures of the clamping circuit described above.

[0059] (1) The clamping circuit includes a first resistor, a first gate adjustment element, a first diode, and a first transistor;

[0060] The negative terminal of the first gate adjustment element is connected to the drain terminal of the clamping transistor, and the positive terminal of the first gate adjustment element is connected to the source terminal of the clamping transistor through the first resistor.

[0061] The anode of the first diode is connected to the drain of the clamping transistor, the cathode of the first diode is connected to the drain of the first transistor, the source of the first transistor is connected to the gate of the clamping transistor, and the gate of the first transistor is connected to a first connection point, which is a point on the connection line between the first gate adjustment element and the first resistor.

[0062] (2) The clamping circuit includes a second resistor, a second gate adjustment element, a second diode, and a second transistor;

[0063] The positive terminal of the second gate adjustment element is connected to the source terminal of the clamping transistor, and the negative terminal of the second gate adjustment element is connected to the drain terminal of the clamping transistor through the second resistor.

[0064] The negative terminal of the second diode is connected to the gate terminal of the clamping transistor, the positive terminal of the second diode is connected to the drain terminal of the second transistor, the source terminal of the second transistor is connected to the drain terminal of the clamping transistor, and the gate terminal of the second transistor is connected to a second connection point, which is a point on the connection line between the second gate adjustment element and the second resistor.

[0065] In this embodiment, the first gate adjustment element can be a Zener diode, a series diode, or a series transistor, and the second gate adjustment element can be a Zener diode, a series diode, or a series transistor. Other structures may also be used depending on the requirements of different clamping voltages.

[0066] The following section uses Zener diodes as examples of the first and second gate adjustment elements to introduce the two clamping circuits mentioned above.

[0067] like Figure 3 As shown in (a), the clamping circuit includes a first resistor R1, a first Zener diode D1, a first diode E1, and a first transistor MNO.

[0068] The cathode of the first Zener diode D1 is connected to the drain of the clamping transistor, and the anode of the first Zener diode D1 is connected to the source of the clamping transistor through the first resistor R1.

[0069] The positive terminal of the first diode E1 is connected to the drain terminal of the clamping transistor, the negative terminal of the first diode E1 is connected to the drain terminal of the first transistor MNO, the source terminal of the first transistor MNO is connected to the gate terminal of the clamping transistor, and the gate terminal of the first transistor MNO is connected to the first connection point, which is any point on the connection line between the first Zener diode D1 and the first resistor R1.

[0070] like Figure 3As shown in (b), the clamping circuit includes a second resistor R2, a second Zener diode D2, a second diode E2, and a second transistor MPO.

[0071] The positive terminal of the second Zener diode D2 is connected to the source terminal of the clamping transistor, and the negative terminal of the second Zener diode D2 is connected to the drain terminal of the clamping transistor through the second resistor R2.

[0072] The negative terminal of the second diode E2 is connected to the gate terminal of the clamping transistor, the positive terminal of the second diode E2 is connected to the drain terminal of the second transistor MPO, the source terminal of the second transistor MPO is connected to the drain terminal of the clamping transistor, and the gate terminal of the second transistor MPO is connected to the second connection point, which is a point on the connection line between the second Zener diode D2 and the second resistor R2.

[0073] Figure 3 The function of the two clamping circuits shown is to raise the gate voltage when the voltage difference between the drain and source exceeds a certain value, thereby increasing the source voltage or decreasing the drain voltage to maintain the voltage difference between the drain and source.

[0074] Specifically, when Figure 3 (a) When the voltage difference between the drain and source terminals of the clamping transistor exceeds the voltage of the first Zener diode D1, a voltage begins to appear across the first resistor R1, and the gate voltage of the first transistor MN0 increases. The first transistor MN0 raises the source terminal, i.e., the gate voltage of MN0, which in turn raises the gate voltage of the external transistor. In this embodiment, the external transistor is the clamping transistor QB.

[0075] When the voltage difference between the drain and source terminals of the clamping transistor in 3(b) exceeds the voltage of the second Zener diode D2, a voltage begins to appear across the second resistor R2, the gate voltage of the second transistor MP0 decreases, and the second transistor MP0 raises the drain voltage of MP0, thus also raising the gate voltage of the external transistor through the second diode E2.

[0076] In this embodiment, Figure 3 The Zener diode in the example is merely one option for clamping the first gate adjustment element at around 5V. Depending on the clamping voltage requirements, the first gate adjustment element can also have other structures, such as a diode or a transistor connected in series. Similarly, the second gate adjustment element can also be a diode or a transistor connected in series, or other structures, depending on the clamping voltage requirements.

[0077] Specifically, such as Figure 4As shown in (a), multiple transistors MN1-MN connected in series can be used. n To replace the first Zener diode D1, the drain and gate of the first transistor MN1 are connected to the drain of the clamping transistor, and the source of MN1 is connected to the drain and gate of the next transistor MN2; the drain and gate of each intermediate transistor are connected to the source of the previous transistor, and the source of the intermediate transistor is connected to the drain and gate of the next transistor; the last transistor MN... n The source end is connected to the first resistor R1.

[0078] like Figure 4 (b) shows multiple transistors MP1-MP connected in series. n To replace the second Zener diode D2, the source of the first transistor MP1 is connected to the second resistor, and the drain and gate of MP1 are connected to the source of the next transistor MP2; the drain and gate of each intermediate transistor are connected to the source of the next transistor, and the source of the intermediate transistor is connected to the drain and gate of the previous transistor; the last transistor MP... n The drain terminal is connected to the source terminal of the clamping transistor.

[0079] like Figure 4 (c) shows that when multiple diodes connected in series replace the first Zener diode, the anode of the first diode is connected to the drain of the clamping transistor, the cathode of the first diode is connected to the anode of the next diode, and the last diode D... n The negative terminal of the first diode is connected to the first resistor R1. When replacing the second Zener diode with multiple diodes connected in series, the positive terminal of the first diode is connected to the first resistor R1, the negative terminal of the first diode is connected to the positive terminal of the next diode, and the last diode D... n The negative terminal is connected to the source terminal of the clamping transistor.

[0080] In this embodiment, the novel adjustable switched-capacitor voltage converter of this application further includes a CP module. The clamping transistor QB in this embodiment is an NMOS transistor, which requires a higher voltage for control. The CP module is used to raise a voltage across PMID to turn on or control QB.

[0081] The novel adjustable switched capacitor voltage converter provided in this application can meet three requirements:

[0082] (1) When the switched capacitor voltage conversion circuit is in operation, the input terminal VBUS and the output terminal VOUT are bidirectionally isolated and will not leak current to each other.

[0083] (2) When the switched capacitor voltage conversion circuit is working normally, the output voltage VOUT, input current IBUS or other electrical parameters can be adjusted to make these electrical parameters the target values.

[0084] (3) Figure 2 All transistors in the system can be 5V transistors with the same voltage rating and output voltage VOUT.

[0085] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0086] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. Furthermore, those skilled in the art will recognize that, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A switched-capacitor voltage converter, characterized in that, include: Switched capacitor voltage conversion circuit, monitoring module, clamping transistor and clamping circuit; The gate terminal of the clamping transistor is connected to the voltage output terminal of the monitoring module, the drain terminal of the clamping transistor is connected to the input terminal VBUS of the switched capacitor voltage converter, and the source terminal of the clamping transistor is connected to the input terminal of the switched capacitor voltage conversion circuit. The monitoring module is used to monitor the electrical parameters of the input terminal VBUS and the output terminal VOUT of the switched capacitor voltage converter, and output voltage to the gate terminal of the clamping transistor according to the electrical parameters, so that the voltage value of the output terminal VOUT is stabilized at the target value. The clamping circuit is used to ensure that the voltage difference between the drain and source terminals of the clamping transistor is less than or equal to the withstand voltage of the clamping transistor. The clamping circuit includes a first resistor, a first gate adjustment element, a first diode, and a first transistor; the negative terminal of the first gate adjustment element is connected to the drain terminal of the clamping transistor, and the positive terminal of the first gate adjustment element is connected to the source terminal of the clamping transistor through the first resistor; the positive terminal of the first diode is connected to the drain terminal of the clamping transistor, the negative terminal of the first diode is connected to the drain terminal of the first transistor, the source terminal of the first transistor is connected to the gate terminal of the clamping transistor, and the gate terminal of the first transistor is connected to a first connection point, which is a point on the connection line between the first gate adjustment element and the first resistor; Alternatively, the clamping circuit includes a second resistor, a second gate adjustment element, a second diode, and a second transistor; the positive terminal of the second gate adjustment element is connected to the source terminal of the clamping transistor, and the negative terminal of the second gate adjustment element is connected to the drain terminal of the clamping transistor through the second resistor; the negative terminal of the second diode is connected to the gate terminal of the clamping transistor, the positive terminal of the second diode is connected to the drain terminal of the second transistor, the source terminal of the second transistor is connected to the drain terminal of the clamping transistor, and the gate terminal of the second transistor is connected to a second connection point, which is a point on the connection line between the second gate adjustment element and the second resistor.

2. The switched capacitor voltage converter according to claim 1, characterized in that, The first gate adjustment element is a Zener diode, a diode connected in series, or a transistor connected in series.

3. The switched capacitor voltage converter according to claim 1, characterized in that, The second gate adjustment element is a Zener diode, a diode connected in series, or a transistor connected in series.

4. The switched capacitor voltage converter according to claim 1, characterized in that, The switched capacitor voltage conversion circuit is a dual-channel 2:1 switched capacitor voltage conversion circuit.

5. The switched capacitor voltage converter according to any one of claims 1-4, characterized in that, The switched capacitor voltage conversion circuit includes a first branch and a second branch; one end of the first branch is connected to a reference point, and the other end of the first branch is grounded; one end of the second branch is connected to the reference point, and the other end of the second branch is grounded; the reference point is the input terminal of the switched capacitor voltage conversion circuit. The first branch includes a first switched capacitor and a first switched transistor, a second switched transistor, a third switched transistor, and a fourth switched transistor connected in series; the first switched capacitor is connected in parallel with the second switched transistor and the third switched transistor; the second branch includes a second switched capacitor and a fifth switched transistor, a sixth switched transistor, a seventh switched transistor, and an eighth switched transistor connected in series; the second switched capacitor is connected in parallel with the sixth switched transistor and the seventh switched transistor. The connection points of the first branch and the second branch are both connected to the output terminal VOUT of the switched capacitor voltage converter; the connection point of the first branch is a point on the connection line between the second switch and the third switch; the connection point of the second branch is a point on the connection line between the sixth switch and the seventh switch.

6. The switched capacitor voltage converter according to claim 5, characterized in that, Also includes: A first substrate switching module and a second substrate switching module; the first substrate switching module is connected to the substrate of the second switching transistor and is used to connect the source terminal of the second switching transistor to the output terminal VOUT when the switched capacitor voltage conversion circuit is in the working state, and to ground the source terminal of the second switching transistor when the switched capacitor voltage conversion circuit is in the non-working state. The second substrate switching module is connected to the substrate of the sixth switching transistor and is used to connect the source terminal of the sixth switching transistor to the output terminal VOUT when the switched capacitor voltage conversion circuit is in operation, and to ground the source terminal of the sixth switching transistor when the switched capacitor voltage conversion circuit is in operation.

7. The switched capacitor voltage converter according to claim 1, characterized in that, The input terminal of the switched capacitor voltage conversion circuit is grounded through a reference capacitor.

8. The switched capacitor voltage converter according to claim 1, characterized in that, The output terminal VOUT is grounded through an output capacitor; the output capacitor is connected in parallel with an output resistor.

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