A successive approximation analog-to-digital converter with monotonic switching of bottom plate sampling timing
By employing bottom plate sampling timing and multi-clock time-division control in SAR ADC, combined with non-binary redundant capacitor array and digital error correction circuit, the problems of large area and slow speed of high-precision analog-to-digital converters are solved, and high-speed and high-precision analog-to-digital conversion is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- DALIAN UNIV OF TECH
- Filing Date
- 2022-12-12
- Publication Date
- 2026-05-15
AI Technical Summary
The implementation of high-precision analog-to-digital converters in existing SAR ADCs requires large-area capacitors, resulting in high chip costs and limited sampling speed. Furthermore, the traditional top plate sampling timing introduces non-ideal characteristics that affect accuracy.
A monotonic switching successive approximation analog-to-digital converter with bottom plate sampling timing is used, combined with multi-clock time-division control and non-binary redundant capacitor array. Bottom plate sampling technology replaces top plate sampling timing, reducing the number of capacitors. Asynchronous timing and digital error correction circuits are used to optimize the conversion process.
It effectively reduces the area of the capacitor array, avoids the influence of non-ideal characteristics, and improves the sampling speed and accuracy. At the same time, it achieves high-speed and high-precision analog-to-digital conversion by optimizing the conversion process through asynchronous timing.
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Figure CN115833839B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of analog integrated circuit design technology, specifically relating to a monotonic switching successive approximation analog-to-digital converter (SAR ADC) that uses bottom plate sampling timing. Background Technology
[0002] With the rapid development of science and technology and the continuous advancement of integrated circuit technology, the requirements for analog-to-digital converters in some circuit systems are also constantly increasing. Analog-to-digital converters are beginning to develop towards high speed and high precision. Due to its serial structure and fewer analog modules in the circuit, SAR ADCs exhibit good performance in medium-to-high precision and medium speed.
[0003] Currently, the most widely used SAR ADC employs a charge redistribution structure. In this type of SAR ADC, the digital-to-analog converter (DAC) is composed of a capacitor array. The number of capacitors per unit changes exponentially with the increase in the accuracy of the DAC. Therefore, the implementation of a high-precision DAC comes at the cost of a large area of capacitors, resulting in a large chip area and excessively high costs. At the same time, the larger the capacitor, the longer its charging and discharging time, which also limits the improvement of the sampling speed of the DAC.
[0004] To improve sampling speed, asynchronous SAR ADCs are usually used, so that the time for each conversion is allocated on demand, maximizing the time utilization of the conversion stage. However, the settling time for large capacitors is relatively long. If the DAC reference voltage is not fully established, sending the incompletely established DAC reference voltage to the comparator for comparison will cause the comparator comparison result to be incorrect.
[0005] In the existing switching strategy of SAR ADC, after each comparison, only one side of the capacitor array needs to be switched according to the comparison result. This switching strategy adopts the top plate sampling method and timing. After the input signal sampling is completed, the sampled signal is directly output to the comparator for comparison during the first comparison process. There is no need to switch capacitors, which can save a capacitor of the highest bit. However, the timing of top plate sampling will introduce non-ideal characteristics of the switch, which will affect the performance of the analog-to-digital converter. Summary of the Invention
[0006] To address the aforementioned issues, this invention proposes a monotonic switching successive approximation analog-to-digital converter (ADC) employing bottom-plate sampling timing. The successive approximation control logic utilizes multi-clock time-division control, replacing the top-plate sampling timing of the monotonic switching successive approximation ADC with the switching timing of the bottom-plate sampling technique. During the sampling phase, the input signal remains connected to the top plate of the capacitor array and the comparator input in the ADC via a sample-and-hold circuit. However, the switches in the sample-and-hold circuit and the bottom-plate control switches of the capacitor array switch switch using the bottom-plate sampling timing to complete signal sampling. This method saves one most significant bit capacitor, effectively reducing the total capacitance per unit in the capacitor-type ADC; it also saves chip area; and simultaneously avoids the impact of the non-ideal characteristics of the sampling switches—channel charge injection effect and clock feedthrough effect—introduced in the sampling phase of traditional monotonic switching successive approximation ADCs on the ADC accuracy. The analog-to-digital converter employs a segmented capacitor architecture based on the charge redistribution principle and non-binary redundancy technology, which further reduces the number of unit capacitors and improves the tolerance to DAC reference voltage establishment error during the conversion process.
[0007] The technical solution of the present invention is as follows:
[0008] A monotonic switching successive approximation analog-to-digital converter (ADC) employing bottom-plate sampling timing includes a sample-and-hold circuit, a comparator, a digital-to-analog converter (DAC), an asynchronous clock generation module, a multi-clock time-division controlled successive approximation control module, and a digital error correction (DEC) circuit. An external analog signal is provided as input. This input signal passes through the sample-and-hold circuit and is output to the top plate of the capacitor array in the DAC and the input of the comparator. The output of the comparator is connected to the asynchronous clock generation module, controlling the rising edge of each conversion. Simultaneously, the comparator's output is connected to both the output of the asynchronous clock generation module and the input of the multi-clock time-division controlled successive approximation control module. The input of the multi-clock time-division controlled successive approximation control module is connected to the rising edge control clock signal output from the asynchronous clock generation module. This module controls the switching of the capacitor array based on the comparator result and stores the comparator result, outputting it to the digital error correction circuit. The digital error correction circuit converts the non-binary digital code into binary digital code and outputs the final binary digital code.
[0009] The analog-to-digital converter adopts a segmented capacitor architecture based on the charge redistribution principle, dividing the capacitor array into two segments connected by bridging capacitors. Each segment of the capacitor array uses a non-binary redundant capacitor array. The top plates of all capacitors in the capacitor array are connected together and connected to the input of the comparator, which receives the sampling signal output from the sample-and-hold circuit. The bottom plate of each capacitor in the capacitor array is connected to the output of the successive approximation control module with multi-clock time-division control. The level of the bottom plate of the corresponding bit of the capacitor is switched according to the comparison result of each comparison.
[0010] The multi-clock time-division multiplexing successive approximation control module includes a successive approximation register module and a control logic module. It requires four square wave signals and a power supply signal (VDD) from independent sources as system input signals. The four square wave signals provided by independent sources are: a sampling clock signal (clks) for the analog-to-digital converter, two clock signals (valid1 and valid2) for implementing the bottom plate sampling timing, and a control signal (select) for implementing the bottom plate timing. The periods of select, clks, valid1, and valid2 are all the same. The duty cycle of select is slightly larger than that of clks, the duty cycle of valid1 is smaller than that of clks, the rising edge of valid2 is generated a few nanoseconds after the falling edge of valid1, and the rising edge of valid2 is generated before the falling edge of clks.
[0011] Furthermore, the successive approximation register module mainly consists of a D-flip-flop, a digital domain 2-to-1 multiplexer, two analog domain 2-to-1 multiplexers, and an inverter. The select signal, provided by an independent source, serves as the control signal for the digital and analog domain 2-to-1 multiplexers, controlling the input signal at either the "0" or "1" terminal. The "1" input signal of the digital domain 2-to-1 multiplexer is connected to VDD, and the "0" input signal is connected to the output of the comparator, whose output is connected to the D input of the D-flip-flop. The "1" input signal of the first analog domain 2-to-1 multiplexer is connected to valid1, and the "0" input signal is connected to clks. Its output is connected to the input of the inverter, whose output is connected to the RN terminal of the D-flip-flop. The "1" input signal of the second analog domain 2-to-1 multiplexer is connected to valid2, and the "0" input signal is connected to the rising edge control clock (clk) output from the asynchronous clock generation module. Its output is connected to the clock input of a D-flip-flop, and the Q input of the D-flip-flop latches the comparator result and serves as the output signal. This eliminates the need for a separate latch to store the comparator result, saving power and area in the digital circuitry.
[0012] Furthermore, the control logic module mainly consists of three transmission transistors, a two-input AND gate, a two-input XOR gate, an inverter, and a delay module. The clock terminal of the D-flip-flop serves as the input terminal of the delay module. The output terminal of the delay module and the Q terminal of the D-flip-flop serve as the two input terminals of the two-input AND gate. The output terminal of the two-input AND gate is connected to the source terminals of the first and second transmission transistors. Select serves as the gate control signal for the first and second transmission transistors. The drain terminal of the first transmission transistor is connected to the gate terminal of the third transmission transistor. The source terminal of the third transmission transistor is connected to the reference voltage signal (vrefp) provided by an independent source. The drain terminal of the second transmission transistor is connected to the input terminal of the inverter. clks and select serve as the two input signals of the two-input XOR gate. The output terminal of the two-input XOR gate is connected to the gate terminal of the third transmission transistor. The output terminal of the inverter and the drain terminal of the third transmission transistor serve as the final output terminal, used to control the switching of the bottom plate level of the capacitors participating in the conversion in the capacitor array.
[0013] Furthermore, after all bit comparisons of the analog-to-digital converter are completed, the successive approximation control module with multi-clock time-division control inputs all latched comparator results into the digital error correction circuit. The digital error correction circuit converts the non-binary weighted digital code into a binary weighted digital code for output, which is the final output of the analog-to-digital converter.
[0014] Furthermore, the digital error correction circuit consists of M D-flip-flops, M AND gates, and multiple full adders, where M represents the resolution of the analog-to-digital converter. Each non-binary weight is represented by adding its corresponding binary weights, resulting in a non-binary digital code for each weight. These bits are then added together. One or more non-binary digital codes corresponding to each binary weight are input into one or more full adders. The outputs of the M full adders are connected to the D terminals of the M D-flip-flops. The clock terminals of all D-flip-flops are connected to the rising edge control clock indicating conversion completion, and the RN terminals are connected to the inverted select signal. Each D-flip-flop corresponds one-to-one with a two-input AND gate. The Q terminal of the D-flip-flop serves as the first input of the two-input AND gate, and the power supply signal provided by an independent source serves as the second input. Each AND gate outputs a binary digital code, and the outputs of all AND gates constitute the final binary code. The addition of the AND gates prevents the D-flip-flops from outputting an intermediate level, avoiding errors when the output is a "1".
[0015] The beneficial effects of this invention are as follows:
[0016] 1. The multi-clock time-division control successive approximation control module enables the input signal to be sampled at the top plate while using the switching timing of the bottom plate. This not only allows for direct comparison after sampling, saving half of the capacitor array, but also avoids the impact of clock feedthrough and charge injection effects on the accuracy of the analog-to-digital converter, which are common in traditional monotonic switching successive approximation analog-to-digital converters.
[0017] 2. The digital-to-analog converter (DAC) employs a non-binary redundant segmented capacitor array. This array provides redundancy to the DAC, preventing dynamic performance degradation due to comparator errors and preventing code loss during analog-to-digital conversion. This is beneficial for high-speed DAC design. The segmented capacitor array technique reduces the number of capacitors per unit, significantly decreasing the area of the capacitor array and effectively saving space within the DAC chip.
[0018] 3. The analog-to-digital converter uses asynchronous timing, which generates an asynchronous clock through the output of the comparator, thereby avoiding the generation of an external high-frequency clock. The asynchronous timing can be allocated as needed according to the comparison time of each bit, so the use of asynchronous timing will greatly improve the sampling speed. Attached Figure Description
[0019] Figure 1 It is an equivalent model for top plate sampling in a traditional monotonic switching SAR ADC;
[0020] Figure 2 It is an equivalent model for existing bottom plate sampling;
[0021] Figure 3 This invention presents a sampling equivalent model for a monotonic switching SAR ADC that uses bottom plate sampling timing.
[0022] Figure 4 This is the circuit schematic of the successive approximation control module with multi-clock time-division control proposed in this invention;
[0023] Figure 5 Timing diagram of the successive approximation control module with multi-clock time-division control proposed in this invention;
[0024] Figure 6 This is a system block diagram of the SAR ADC proposed in this invention;
[0025] Figure 7 This is a circuit schematic diagram of the SAR ADC with capacitance value proposed in this invention.
[0026] Figure 8 This is the circuit diagram of the first four digits error correction circuit proposed in this invention;
[0027] Figure 9 This is the calculation method used in this invention to convert non-binary digital codes into binary digital codes. Detailed Implementation
[0028] The specific embodiments of the present invention will now be described in conjunction with the accompanying drawings and technical solutions.
[0029] Combination Figure 1 Explain the working principle of the top plate sampling technique in a traditional monotonic switching SAR ADC:
[0030] Assuming the sample-and-hold circuit samples at the rising edge of clock CLK and ends sampling at the falling edge of clock CLK, entering the hold phase, during the sampling phase, the lower plate of the capacitor is equivalent to being connected to AC ground (GND), the sampling switch is closed, and at this time the top plate of the capacitor is connected to the input signal (V) through the switch. in When the falling edge of clock CLK arrives, the sampling switch is turned off. At this time, charge is stored on the top plate of the capacitor. According to the law of conservation of charge on the top plate, the amount of charge stored is Q = V. in *C, Input signal V in The information is stored on the sampling capacitor C, and the top plate of the sampling capacitor C samples the input signal V. in The sampling process is now complete.
[0031] The sampling described above is the sampling under ideal conditions. In practical applications, the sampling switch is usually implemented by a MOSFET, which will have channel charge injection and clock feedthrough at the moment the switch is turned off, introducing nonlinear components into the sampling signal.
[0032] Combination Figure 2 Explanation of the working principle of existing bottom plate sampling technology: SW1, SW2, and SW3 are switches controlling the top and bottom plates of the capacitor, respectively. PH1, PH1D, and PH2 are clock signals controlling the switching of SW1, SW2, and SW3, respectively. The switches close on the rising edge of the clock and open on the falling edge. The switching sequence of the three switches is as follows: In the first stage, SW1 and SW3 are closed, and the input signal V is... in The data is stored in the sampling capacitor C; in the second stage, SW1 is disconnected, and after a delay, SW3 is disconnected; in the third stage, SW2 is closed, and the sampling is completed.
[0033] PH1(PH1D) = "1", PH2 = "0", SW1 and SW3 are closed, and the voltage V at the top plate of the sampling capacitor C is measured. TOP =0, the voltage V at the bottom plate of the sampling capacitor C BOT =Vin, at this time the charge stored in the sampling capacitor C is Q1 = (0 - V) in )*C; PH1(PH1D)="0", PH2="1", SW1 and SW3 are open, SW2 is closed, sampling capacitor C's top plate voltage V TOP =V x The voltage V at the bottom plate of the sampling capacitor C BOT =0, at this time the charge stored in the sampling capacitor C is Q2 = (V x -0)*C; After the falling edge of PH1, due to charge conservation, Q1=Q2, V x =-V in Sampling complete.
[0034] The channel charge and clock feedthrough of SW1 will introduce a signal V in The error is irrelevant and will not introduce nonlinear error. The channel charge and clock feedthrough of switches SW2 and SW3 have no impact on accuracy, and the bottom plate sampling will achieve relatively high accuracy.
[0035] Combination Figure 3 The working principle of the monotonic switching SAR ADC using bottom plate sampling timing described in this invention is as follows: SW4 and SW5 are switches connected to the bottom and top plates of the sampling capacitor C, respectively, and the voltage of the top plate is V. TOP The voltage at the bottom plate is V. BOT PH3 and PH4 are the control clocks for SW4, and PH3D is the control clock for SW5. When PH3 (PH3D) = "1" and PH4 = "0", SW4 and SW5 are closed. At time t1, SW4 is open, and the input signal V... in The charge Q1 stored on the sampling capacitor C ’ =(0-V in )*C=-V in *C; At time t2, SW5 is disconnected. Assume that the voltage V at the top plate of sampling capacitor C is... TOP =V in +V1, the voltage V of its bottom plate BOT =V x The charge Q2 across the sampling capacitor C ’ =(V x -V in -V1)*C, according to the charge conservation of the bottom plate of the sampling capacitor C, Q1 ’ =Q2 ’ V can be obtained x =V1, and according to the charge conservation of the top plate of the sampling capacitor C, the charge at its two ends Q3 can be obtained. ’ =(V in +V1-Vx)*C=V in *C; At time t3, SW4 is closed. Assume that the voltage V of its top plate is V at this time. TOP =V y Then the charge at both ends is Q4 ’ =V y *C, based on the charge conservation of the top plate of the sampling capacitor C, we know that Q3 ’ =Q4 ’ V y =V in The sampling is now complete.
[0036] like Figure 4 As shown, this invention applies the bottom plate sampling timing to a monotonic switching SAR ADC through a multi-clock time-division controlled successive approximation control module, which consists of a successive approximation register module and a control logic module. Combined with... Figure 4 and Figure 5 To explain its working process:
[0037] At time t1, clks = "1", the input signal Vin is connected to the top plate of the capacitor array via the gate voltage bootstrap switch, select = "1", the two analog domain 2-to-1 multiplexers output valid1 and valid2 respectively, the digital domain 2-to-1 multiplexer outputs VDD, valid1 = "1", valid2 = "0", the D-flip-flop is in the reset state, outputting Q = "0", the AND gate output is "0", and the output terminal Cout is connected to the vrefp signal, that is, the bottom plate of the capacitor array is connected to the vrefp signal; at time t2, select = "1", valid1 = "0", valid2 changes from "0" to "1", the D-flip-flop outputs Q = "1", the AND gate output is "1", and the output terminal Cout is disconnected from the vrefp signal; at time t3, select = "1", clks = "0", the gate voltage bootstrap switch is off, and the output terminal Cout remains disconnected from the vrefp signal; at time t4, select = "0", the two analog domain 2-to-1 multiplexers output clks and clk respectively. ,clk (i = 1 ~ 14) is the clock signal output by the asynchronous clock generation circuit. The output result of the digital domain 2-to-1 multiplexer comparator is VON, clks = "0". The output terminal Cout is connected to the vrefp signal. At this time, the level of the bottom plate of the capacitor array is set to vrefp, and the sampling phase ends.
[0038] Figure 6 The system block diagram of the SAR ADC proposed in this invention is given, including a sample-and-hold circuit, a comparator, a successive approximation control logic with multi-clock time-division control, an asynchronous clock generation module, and a digital error correction circuit (DEC). The sample-and-hold circuit samples the input signal and outputs it to the input of the comparator and the top plate of the capacitor array in the digital-to-analog converter. The output of the comparator is connected to the successive approximation control logic with multi-clock time-division control and the asynchronous clock generation module. When the asynchronous clock is input on the rising edge, the successive approximation control logic controls the capacitor array according to the output result and latches it, outputting it to the digital error correction circuit, and finally obtaining the binary digital code output.
[0039] like Figure 7 As shown, the SAR ADC proposed in this invention adopts a fully differential architecture based on the charge redistribution principle. The capacitor array is divided into two segments, with bridging capacitor C... b Take 2C u The high-order segment and the low-order segment each have 7 capacitors C1 to C14 involved in the conversion and two compensation capacitors Cd1 and Cd2. The capacitor weights of the high-order and low-order segments, from high to low, are 32C. u 18C u 10C u 6C u 3C u 2C u 1C u Since the bridging capacitor is taken as an integer multiple of the unit capacitance, in order to ensure that the weights of the capacitors on both sides remain unchanged after the capacitor array is segmented, a compensation capacitor C is added. d1 38C u C d2 For 1C u C u As a unit capacitor, during the normal conversion process of the SAR ADC, the voltage of the bottom plate of the compensation capacitor does not switch, and it is connected to a fixed level vrefp.
[0040] Each conversion process of this SAR ADC includes two stages: a sampling stage and a comparison stage, and each conversion requires one sampling and 14 comparisons.
[0041] During the sampling phase, S p0 With S n0 Closed, capacitor array and gate voltage bootstrap switch (S p0 S n0 The sample-and-hold circuit, composed of [variable name], holds the input analog signal V. ip With V in Sampling. The switching sequence of the sampling process switches is as follows: First, S... p0 S n0 With S n1 ~S n14 S p1 ~S p14 Close; next, S n1 ~S n14 S p1 ~S p14 Disconnect, delay for a period of time, S p0 S n0 Disconnect again; finally, S again. n1 ~S n14 S p1 ~S p14 Reset to the initial state and connect it to the initial level vrefp.
[0042] The following describes the conversion process of the SAR ADC proposed in this invention using the first two comparison processes as an example. The digital code output by the first comparison is B13, the result of the second comparison is B12, and so on, with the digital code output by the last comparison being B0.
[0043] After sampling, the first comparison begins immediately. If V P >V N Output numeric code B13 = 1, V P Terminal capacitor C 14 Corresponding switch S p1 Switch from Vrefp to Vrefn, V N Terminal capacitor C 14 Corresponding switch S n1 Keep it connected to Vrefp unchanged; otherwise, B13 = 0, V N Terminal capacitor C 14 Corresponding switch S n1 Switch from Vrefp to Vrefn, V P Terminal capacitor C 14 Corresponding switch S p1 Keep it connected to Vrefp unchanged, V P End and V N Switch S corresponding to the capacitors at other terminals n2 ~S n14 S p2 ~S p14 All remain connected to Vrefp unchanged.
[0044] The second comparison process is as follows: The second comparison re-establishes the V after the first comparison. P With V N Comparing the magnitudes, assuming V after charge redistribution P With V N The voltages at the terminals are respectively V P2 With V N2 If V P2 >V N2 Then the output numeric code B12 = 1, V P Terminal capacitor C 13 Corresponding switch S p2 Switch from Vrefp to Vrefn, V N Terminal capacitor C 13 Corresponding switch S n1 Keep it connected to Vrefp unchanged; otherwise, B12 = 0, V N Terminal capacitor C 13 Corresponding switch S n2 Switch from Vrefp to Vrefn, V P Terminal capacitor C 13 Corresponding switch S p2 Keep it connected to Vrefp unchanged, V P End and V N Switch S corresponding to the capacitors at other terminals n1 S p1 S n3 ~S n14 S p3 ~S p14 All comparisons are kept at Vrefp. The remaining 12 comparisons follow the same principle as the first two comparisons. This continues until the last bit of digital code B0 is output, completing one conversion. This SAR ADC converts the input differential signal (Vip-Vin) into 14-bit digital codes B13 to B0, and finally uses a digital error correction circuit to convert the non-binary digital codes B13 to B0 into binary digital codes D11 to D0, thus realizing the conversion from analog signal to digital signal.
[0045] like Figure 8 As shown, a circuit diagram for converting the first four non-binary digits into binary digits is presented. Each full adder has five terminals: the first input terminal, the second input terminal, the carry input terminal, the carry output terminal, and the summation output terminal. According to... Figure 9 The calculation method involves addition. Taking the first two additions as an example, the inverted select signal is connected to the RN terminals of all D-flip-flops. The D-flip-flops can only work normally when select = "0". B0 and B2 are the two inputs of the first full adder. The input carry is connected to the ground signal (GND), and the output carry is connected to the carry input of the second full adder. The summation signal of the first full adder is output to the D terminal of the D-flip-flop. The clock terminal of the D-flip-flop is input to the rising edge control clock to determine the completion of the conversion. The Q terminal of the D-flip-flop is connected to the first input of the two-input AND gate. The second input is the power supply signal (VDD). The output of the two-input AND gate is the binary code D0 of the current bit. For the second addition, B1 and B2 are the two inputs of the second full adder. The input carry is connected to the output carry of the first addition, and the summation output... The carry-out of the second full adder is connected to the second bit. B3 and B4 are the two inputs of the second full adder. The summation output is connected to the carry-out of the third full adder. B5 and GND are its two inputs. Its summation output is connected to the D terminal of the D-flip-flop. The clock terminal of the D-flip-flop is used to control the clock by the rising edge of the conversion completion. The Q terminal of the D-flip-flop is connected to the input of the second two-input AND gate. The output of the second two-input AND gate is used as the second binary code D1. The carry-out outputs of the three full adders of the second bit are respectively connected to the carry-out or input of the third full adder, and so on, until the final 12-bit binary code is output.
Claims
1. A monotonic switching successive approximation analog-to-digital converter employing bottom-plate sampling timing, characterized in that, The monotonic switching successive approximation analog-to-digital converter (ADC) employing bottom-plate sampling timing includes a sample-and-hold circuit, a comparator, an ADC, an asynchronous clock generation module, a multi-clock time-division controlled successive approximation control module, and a digital error correction circuit. An external analog signal is provided as input, and the input signal is output through the sample-and-hold circuit to the top plate of the capacitor array in the ADC and the input of the comparator. The output of the comparator is connected to the asynchronous clock generation module, which outputs the rising edge control clock for each conversion. Simultaneously, the output of the comparator is connected to both the output of the asynchronous clock generation module and the input of the multi-clock time-division controlled successive approximation control module. The input of the multi-clock time-division controlled successive approximation control module is connected to the rising edge control clock signal output by the asynchronous clock generation module. This module controls the switching of the capacitor array based on the comparator result and stores the comparator result, outputting it to the digital error correction circuit. The digital error correction circuit converts the non-binary digital code into binary digital code and outputs the final binary digital code. The analog-to-digital converter adopts a segmented capacitor architecture based on the charge redistribution principle, dividing the capacitor array into two segments connected by bridging capacitors. Each segment of the capacitor array uses a non-binary redundant capacitor array. The top plates of all capacitors in the capacitor array are connected together and connected to the input of the comparator, which receives the sampling signal output from the sample-and-hold circuit. The bottom plate of each capacitor in the capacitor array is connected to the output of the successive approximation control module with multi-clock time-division control. The level of the bottom plate of the corresponding bit of the capacitor is switched according to the comparison result of each comparison. The multi-clock time-division control successive approximation control module includes a successive approximation register module and a control logic module. It requires four square wave signals and a power supply signal from independent sources as system input signals. The four square wave signals provided by independent sources are: a sampling clock signal clks for the analog-to-digital converter, two clock signals valid1 and valid2 used to implement the bottom plate sampling timing, and a control signal select used to implement the bottom plate timing. The periods of select, clks, valid1, and valid2 are all the same. The duty cycle of select is slightly larger than that of clks, the duty cycle of valid1 is smaller than that of clks, the rising edge of valid2 is generated a few nanoseconds after the falling edge of valid1, and the rising edge of valid2 is generated before the falling edge of clks. Furthermore, the successive approximation register module mainly consists of a D-flip-flop, a digital domain 2-to-1 multiplexer, two analog domain 2-to-1 multiplexers, and an inverter. The select signal, provided by an independent source, serves as the control signal for the digital and analog domain 2-to-1 multiplexers, controlling the input signal at either the "0" or "1" terminal. The "1" input signal of the digital domain 2-to-1 multiplexer is connected to VDD, and the "0" input signal is connected to the output of the comparator, whose output is connected to the D input of the D-flip-flop. The "1" input signal of the first analog domain 2-to-1 multiplexer is connected to valid1, and the "0" input signal is connected to clks. Its output is connected to the input of the inverter, and the output of the inverter is connected to the RN terminal of the D-flip-flop. The "1" input signal of the second analog domain 2-to-1 multiplexer is connected to valid2, and the "0" input signal is connected to the rising edge control clock clk from the asynchronous clock generation module. Its output is connected to the clock input of the D-flip-flop, and the Q input of the D-flip-flop latches the comparator result and serves as the output signal. Furthermore, the control logic module mainly consists of three transmission transistors, a two-input AND gate, a two-input XNOR gate, an inverter, and a delay module. The clock terminal of the D-flip-flop serves as the input terminal of the delay module, and the output terminal of the delay module and the Q terminal of the D-flip-flop serve as the two input terminals of the two-input AND gate. The output terminal of the two-input AND gate is connected to the source terminals of the first and second transmission transistors. Select serves as the gate control signal for the first and second transmission transistors. The drain terminal of the first transmission transistor is connected to the gate terminal of the third transmission transistor. The source terminal of the third transmission transistor is connected to the reference voltage signal vrefp provided by an independent source. The drain terminal of the second transmission transistor is connected to the input terminal of the inverter. clks and select serve as the two input signals of the two-input XNOR gate. The output terminal of the two-input XNOR gate is connected to the gate terminal of the third transmission transistor. The output terminal of the inverter and the drain terminal of the third transmission transistor serve as the final output terminal, used to control the switching of the bottom plate level of the capacitors participating in the conversion in the capacitor array. Furthermore, after all bit comparisons of the analog-to-digital converter are completed, the successive approximation control module with multi-clock time-division control inputs all latched comparator results into the digital error correction circuit. The digital error correction circuit converts the non-binary weighted digital code into a binary weighted digital code for output, which is the final output of the analog-to-digital converter. Furthermore, the digital error correction circuit consists of M D-flip-flops, M AND gates, and multiple full adders, where M represents the resolution of the analog-to-digital converter. Each non-binary weight is represented by adding binary weights to obtain the non-binary digital code corresponding to each weight. These are then added bit by bit. One or more non-binary digital codes corresponding to each binary weight are input into one or more full adders. The outputs of M full adders are respectively connected to the D terminals of the M D-flip-flops. The clock terminals of all D-flip-flops are connected to the rising edge control clock that determines the completion of the conversion, and the RN terminals are connected to the inverted select signal. Each D-flip-flop corresponds one-to-one with a two-input AND gate. The Q terminal of the D-flip-flop serves as the first input terminal of the two-input AND gate, and the power supply signal provided by an independent source serves as the second input terminal of the two-input AND gate. Each AND gate outputs a binary digital code, and the outputs of all AND gates are the final binary code.