A semiconductor structure and a manufacturing method thereof

Abstract

Embodiments of the present application disclose a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate; a gate structure located on the substrate; an interconnect structure, the interconnect structure including a first structure and a second structure, the second structure protruding from the first structure; wherein, the first structure is connected to the substrate, and the second structure is connected to the top of the gate structure. The interconnect structure of the present application is in contact with the substrate and the gate structure, which can reduce the occupied volume of the interconnect structure, increase the interconnect density, and improve the interconnect process window.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor structures and manufacturing methods thereof. Specifically, it relates to a semiconductor structure with an interconnect structure and a manufacturing method thereof. Background Art

[0002] In a dynamic random access memory (DRAM) of the prior art, it includes memory cells and peripheral control devices. With the progress of semiconductor manufacturing technology, the critical dimensions defined in the semiconductor device design specifications are getting smaller and smaller, which increases the manufacturing difficulty of peripheral control devices. Summary of the Invention

[0003] The purpose of the embodiments of the present application is to provide a semiconductor structure and a manufacturing method thereof. Through the design of the interconnect structure connected to the substrate and the gate structure, the volume occupied by the interconnect structure can be reduced, the interconnect density can be increased, and the interconnect process window can be improved.

[0004] The first aspect of the embodiments of the present application provides a semiconductor structure, including:

[0005] A substrate;

[0006] A gate structure located on the substrate;

[0007] An interconnect structure, the interconnect structure includes a first structure and a second structure, and the second structure protrudes from the first structure;

[0008] Wherein, the first structure is connected to the substrate, and the second structure is connected to the top of the gate structure.

[0009] In an exemplary embodiment, the gate structure includes a gate dielectric layer and a gate electrode layer;

[0010] The first structure is in direct contact with the side surface of the gate electrode layer;

[0011] The second structure is in direct contact with the top surface of the gate electrode layer.

[0012] In an exemplary embodiment, it further includes:

[0013] A barrier layer, the barrier layer covers at least a part of the surface of the first structure and a part of the surface of the second structure.

[0014] In an exemplary embodiment, it further includes:

[0015] An isolation layer located on the side of the gate structure;

[0016] The first structure is in direct contact with the isolation layer.

[0017] In an exemplary embodiment, it further includes:

[0018] A first dielectric layer, located on the substrate;

[0019] The gate structure and the interconnect structure are located in the first dielectric layer, and the top surface of the second structure is lower than the top surface of the first dielectric layer.

[0020] In an exemplary embodiment, it further includes:

[0021] A second dielectric layer, located on the first dielectric layer and covering the second structure;

[0022] Wherein, the top surface of the first structure is flush with the top surface of the second dielectric layer.

[0023] In an exemplary embodiment, it further includes:

[0024] A capacitive contact pad, the etched bottom of the capacitive contact pad is flush with the top surface of the second structure; the top surface of the capacitive contact pad is flush with the top surface of the first structure.

[0025] In an exemplary embodiment, the gate structure and the interconnect structure form part of an SRAM memory cell.

[0026] In an exemplary embodiment, the substrate includes an isolation structure;

[0027] The projection of the gate structure on the substrate at least partially covers the isolation structure.

[0028] According to the second aspect of the embodiments of the present application, there is provided a method for manufacturing a semiconductor structure, including:

[0029] Provide a substrate;

[0030] Form a gate structure and a first dielectric layer on the substrate, the first dielectric layer covering the gate structure;

[0031] Form a first opening in the first dielectric layer, the first opening exposing part of the substrate and at least part of the top of the gate structure;

[0032] Form an interconnect structure in the first opening;

[0033] Wherein, the interconnect structure includes a first structure and a second structure, the first structure is connected to the substrate, and the second structure is connected to the top of the gate structure.

[0034] In an exemplary embodiment, forming the interconnect structure in the first opening includes:

[0035] Form a conductive layer in the first opening;

[0036] A mask pattern layer with a first mask pattern is formed on the conductive layer, and the first mask pattern covers at least a part of the conductive layer in the first opening.

[0037] The conductive layer is etched using the first mask pattern, such that the top surface of the conductive layer on the gate structure is lower than the top surface of the first dielectric layer.

[0038] In an exemplary embodiment, the projection of the first mask pattern on the substrate coincides with the part of the substrate exposed by the first opening.

[0039] In an exemplary embodiment, it further includes:

[0040] A third dielectric layer with a capacitor contact hole is formed on the substrate, and the conductive layer is also formed in the capacitor contact hole and on the surface of the third dielectric layer.

[0041] The mask pattern layer further has a second mask pattern covering a part of the conductive layer in the capacitor contact hole and a part of the conductive layer on the third dielectric layer.

[0042] A part of the conductive layer in the capacitor contact hole and a part of the third dielectric layer are etched using the second mask pattern.

[0043] In an exemplary embodiment, the etching of a part of the conductive layer in the capacitor contact hole and a part of the third dielectric layer using the second mask pattern includes:

[0044] The bottom of the etching is flush with the top surface of the second structure.

[0045] In an exemplary embodiment, an isolation structure is further formed on the substrate, and the projection of the gate structure on the substrate at least partially covers the isolation structure.

[0046] In an exemplary embodiment, it further includes:

[0047] An SRAM memory cell is fabricated using the gate structure and the interconnect structure.

[0048] An embodiment of the present application provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes an interconnect structure in contact with a substrate and a gate structure. The interconnect structure of the present application is in contact with the substrate and the gate structure, which can reduce the occupied volume of the interconnect structure, increase the interconnect density, and improve the interconnect process window. Description of the Drawings

[0049] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the several views denote the same or similar components or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments disclosed in accordance with the embodiments of the present application, and should not be regarded as limiting the scope of the embodiments of the present application.

[0050] FIGS. 1-3 are schematic structural diagrams of a semiconductor structure according to an embodiment of the present application;

[0051] Figure 4 -8 are schematic diagrams of the formation process of the semiconductor structure according to an embodiment of the present application;

[0052] Among them, Figure 1a , Figures 2 - 5 , Figure 6a , Figure 7a , Figure 8a are schematic diagrams of the peripheral region of the semiconductor structure, Figure 1b , Figure 6b , Figure 7b and Figure 8b are schematic diagrams of the storage region of the semiconductor structure. Detailed Embodiments

[0053] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the following further details the embodiments of the present application in conjunction with the specific embodiments and with reference to the accompanying drawings. It should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the embodiments of the present application. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessarily obscuring the concepts of the embodiments of the present application.

[0054] Obviously, the described embodiments are some, but not all, of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts fall within the scope of protection of the present application.

[0055] It should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the embodiments of the present application, the first element may be referred to as the second element, and similarly, the second element may be referred to as the first element.

[0056] The following details the embodiments of the present application with reference to the accompanying drawings. According to an embodiment of the present application, a semiconductor structure is provided, and a schematic structural diagram of the semiconductor structure is shown in FIGS. 1-3. In one embodiment, with reference to Figure 1a, the semiconductor structure includes a substrate 100 and a gate structure 500 located on the substrate 100. The semiconductor structure may further include an interconnect structure 400, and the interconnect structure 400 includes a first structure 401 and a second structure 402, and the second structure 402 protrudes from the first structure 401; wherein, the first structure 401 is connected to the substrate 100, and the second structure 402 is connected to the top of the gate structure 500.

[0057] In one example, the substrate 100 includes semiconductor substrates such as a silicon substrate, gallium arsenide, gallium nitride, gallium carbide, silicon on insulator (SOI), etc. Taking the DRAM chip structure as an example, the chip may include a storage area and a peripheral area. Figure 1a It may be a device structure on the peripheral area. For example, the device structure on the peripheral area may include a gate structure 500 and an interconnect structure 400; Figure 1b It may be a device structure on the storage area. The device structure on the storage area may include a capacitor contact pad 801, and the capacitor contact pad 801 may be electrically connected to the substrate 100. In other examples, the capacitor contact pad 801 may also be electrically connected to the substrate 100 through a polysilicon plug.

[0058] In one example, the gate structure 500 may include a gate dielectric layer 502 and a gate electrode layer 501. The gate dielectric layer 502 is in direct contact with the substrate 100, the gate electrode layer 501 is located above the gate dielectric layer 502, the first structure 401 is in direct contact with the side surface of the gate electrode layer 501, and the second structure 402 is in direct contact with the top surface of the gate electrode layer 501. By way of example, the gate dielectric layer 502 may include one or a combination of silicon oxide and silicon oxynitride, or may also include high-k materials such as hafnium oxide. The gate electrode layer 501 may include any one or any combination of conductive materials such as polysilicon, titanium nitride, tungsten, and aluminum. The material of the first structure 401 may be a metal such as tungsten or cobalt, and the material of the second structure 402 may be a metal such as tungsten or cobalt. The materials of the first structure 401 and the second structure 402 may be the same or different. By way of example, the first structure 401 may be in direct contact with the side surface of the gate electrode layer 501 to form an electrical connection; the second structure 402 is in direct contact with the top surface of the gate electrode layer 501 to form an electrical connection.

[0059] In one example, the substrate 100 may include an isolation structure 101, refer to Figure 2 , the projection of the gate structure 500 on the substrate 100 at least partially covers the isolation structure 101. By way of example, the isolation structure 101 may be a shallow trench isolation structure (STI) for isolating active regions. The gate structure 500 may be partially located above the isolation structure 101.

[0060] In one example, the semiconductor structure may further include a barrier layer that covers at least a partial surface of the first structure 401 and a partial surface of the second structure 402. The material of the barrier layer may be one or a combination of titanium nitride and tantalum nitride.

[0061] In one example, the semiconductor structure may further include a first dielectric layer 200. The first dielectric layer 200 is located on the substrate 100. The gate structure 500 and the interconnect structure 400 are located in the first dielectric layer 200, and the top surface of the second structure 402 is lower than the top surface of the first dielectric layer 200, which can reduce the distance between the second structure 402 and the surrounding conductive connection lines, increase the process window, and improve the yield. For example, the first dielectric layer 200 may include any one or any combination of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, etc. For example, after forming the gate structure 500 on the substrate 100, a silicon oxide layer may be formed on the substrate 100 by a deposition method such as chemical vapor deposition, and the silicon oxide layer also covers the gate structure 500.

[0062] In one example, the semiconductor structure may further include a second dielectric layer 300. The second dielectric layer 300 is located on the first dielectric layer 200 and covers the second structure 402; wherein, the top surface of the first structure 401 is flush with the top surface of the second dielectric layer 300. For example, the second dielectric layer 300 may include any one or any combination of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, etc. For example, a silicon nitride layer may be formed on the first dielectric layer 200 and the interconnect structure 400 by a deposition method such as chemical vapor deposition, and the silicon nitride layer and the first structure 401 are polished to a predetermined position by a chemical mechanical polishing process to obtain a flat surface where the top surface of the first structure 401 is flush with the top surface of the second dielectric layer 300.

[0063] In one example, the semiconductor structure may further include an isolation layer 600 that is located on the side of the gate structure 500 to protect the gate structure 500. As Figure 1a shown, the isolation layer 600 is located on one side of the gate structure 500, and the first structure 401 is in direct contact with the isolation layer 600. In another example, as Figure 3 shown, the isolation layer 600 may also be located on the other side of the gate structure 500, and the isolation layer 600 is in direct contact with the first dielectric layer 200. In other examples, the isolation layer 600 may also be located on two sides of the gate structure 500 respectively, as Figure 2 shown.

[0064] In one example, the semiconductor structure may further include a capacitor contact pad 801. Refer to Figure 1a and Figure 1b, the etched bottom A1 of the capacitor contact pad 801 is flush with the top surface of the second structure 402; the top surface A2 of the capacitor contact pad 801 is flush with the top surface of the first structure 401. The gate structure 500 and the interconnect structure 400 can be used to form part of an SRAM memory cell. The material of the capacitor contact pad 801 can be any one of W, Cu, Ti, Ni, Al, Co, TiN, or metal silicide, or any combination thereof. The capacitor contact pad 801 can be isolated by the second dielectric layer 300 and the third dielectric layer 201. The second dielectric layer 300 is used to isolate the upper part of the capacitor contact pad 801, and the third dielectric layer 201 is used to isolate the lower part of the capacitor contact pad 801. In one example, the etched bottom A1 of the capacitor contact pad 801 can be understood as the bottom of the second dielectric layer 300.

[0065] In one example, the gate structure 500 and the interconnect structure 400 form part of an SRAM memory cell.

[0066] According to another embodiment of the embodiments of the present application, a method for manufacturing a semiconductor structure is provided. Figure 4 -8 shows a schematic process diagram of the manufacturing method. The method for manufacturing a semiconductor structure includes the following steps: Refer to Figure 4 , provide a substrate 100, and form a gate structure 500 and a first dielectric layer 200 on the substrate 100. The first dielectric layer 200 covers the gate structure 500. The material of the substrate 100 can be silicon (Si), germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); it can also be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or it can also be other semiconductor materials, such as group III-V compounds such as gallium arsenide. The first dielectric layer 200 can be a single layer or a multi-layer stacked structure. The material of the first dielectric layer 200 can be silicon oxide, silicon nitride, silicon oxynitride, FSG (fluorine-doped silicon dioxide), BSG (boron-doped silicon dioxide), PSG (phosphorus-doped silicon dioxide), or BPSG (boron-phosphorus-doped silicon dioxide), low dielectric constant materials, other suitable materials, and / or combinations of the above.

[0067] Form a first opening 700 in the first dielectric layer 200. Refer to Figure 5 , the first opening 700 exposes a part of the substrate 100 and the top of at least part of the gate structure 500.

[0068] Form an interconnect structure 400 in the first opening 700. As an example, the following steps can be carried out: Refer to Figure 6a , form a conductive layer 800 in the first opening 700, and form a mask pattern layer on the conductive layer 800. The mask pattern layer has a first mask pattern 900. Refer to Figure 7a, the first mask pattern 900 covers at least a part of the conductive layer 800 in the first opening 700; the conductive layer 800 is etched using the first mask pattern 900 such that the top surface of the conductive layer 800 on the gate structure 500 is lower than the top surface of the first dielectric layer 200 to form the interconnect structure 400. The interconnect structure 400 includes a first structure 401 and a second structure 402. The first structure 401 is connected to the substrate 100, and the second structure 402 is connected to the top of the gate structure 500.

[0069] In one example, the projection of the first mask pattern 900 on the substrate 100 coincides with the part of the substrate 100 exposed by the first opening 700. The material of the conductive layer 800 includes conductive materials such as tungsten or cobalt.

[0070] In one example, as Figure 6b shown, the method for fabricating the semiconductor structure may further include forming a third dielectric layer 201 and a capacitor contact hole in the third dielectric layer 201 on the storage area of the substrate 100. The conductive layer 800 is also formed in the capacitor contact hole and on the surface of the third dielectric layer 201. The mask pattern layer further has a second mask pattern 901, and the second mask pattern 901 covers a part of the conductive layer 800 in the capacitor contact hole and a part of the conductive layer 801 on the third dielectric layer 201. The part of the conductive layer 800 in the capacitor contact hole and a part of the third dielectric layer 201 are etched using the second mask pattern 901. For example, referring to Figure 7a and Figure 7b and Figure 8a and Figure 8b , the gate structure 500 is located in the peripheral area of the substrate 100, the capacitor contact hole in the third dielectric layer 201 is located in the storage area of the substrate 100, the conductive layer 800 fills the first opening 700 and the capacitor contact hole, and at the same time covers the surfaces of the first dielectric layer 200 and the third dielectric layer 201. The conductive layer 800 can be processed by chemical mechanical polishing or back etching processes such that the upper surfaces of the conductive layer 800 in the storage area and the peripheral area are on the same horizontal plane or substantially the same horizontal plane. The conductive layer 800 in the peripheral area is etched using the first mask pattern 900 such that the top surface of the remaining conductive layer 800 above the gate structure 500 is lower than the top surface of the first dielectric layer 200. At the same time, the conductive layer 800 in the storage area and the third dielectric layer 201 are etched using the second mask pattern 901 to form a second opening 902. The bottom part of the second opening 902 is located in the conductive layer 800 and partly in the third dielectric layer 201. The etched bottom A1 is flush with the top surface of the remaining conductive layer 800 above the gate structure 500. That is, the etched bottom A1 is flush with the top surface of the second structure 402 of the interconnect structure 400. Such an arrangement can simplify the process steps and reduce costs.

[0071] In one example, a method for fabricating a semiconductor structure may further include: forming an isolation structure 101 on a substrate 100, and a projection of a gate structure 500 on the substrate 100 at least partially covers the isolation structure 101.

[0072] In one example, as Figure 8a and Figure 8b , Figure 1a and Figure 1b shown, a second dielectric layer 300 may also be formed on the first dielectric layer 200 and in a second opening 902. The second dielectric layer 300 is located on the first dielectric layer 200 and covers the second structure 402; wherein, a top surface of the first structure 401 is flush with a top surface of the second dielectric layer 300.

[0073] In one example, an SRAM memory cell is fabricated using the gate structure 500 and the interconnect structure 400.

[0074] Embodiments of the present application provide a semiconductor structure and a method for fabricating the same. The semiconductor structure includes an interconnect structure in contact with a substrate and a gate structure. The interconnect structure of the present application is in contact with the substrate and the gate structure, which can reduce the occupied volume of the interconnect structure, increase the interconnect density, and improve the interconnect process window.

[0075] It should be understood that the above specific embodiments of the embodiments of the present application are only used for exemplary illustration or explanation of the principles of the embodiments of the present application, and do not constitute a limitation on the embodiments of the present application. Therefore, any modifications, equivalent replacements, improvements, etc. made without departing from the spirit and scope of the embodiments of the present application shall be included within the protection scope of the embodiments of the present application. In addition, the appended claims of the embodiments of the present application are intended to cover all changes and modifications that fall within the scope and boundaries of the appended claims, or equivalent forms of such scope and boundaries.

[0076] The steps in the method of the embodiments of the present application can be adjusted, combined, and deleted according to actual needs. The modules in the devices of the embodiments of the present application can be combined, divided, and deleted according to actual needs.

Claims

1. A semiconductor structure, characterized in that, Comprising: A substrate; A gate structure located on the substrate; An interconnect structure, the interconnect structure comprising a first structure and a second structure, the second structure protruding from the first structure; Wherein, the first structure is connected to the substrate, and the second structure is connected to the top of the gate structure; A capacitive contact pad, the etched bottom of the capacitive contact pad being flush with the top surface of the second structure; the top surface of the capacitive contact pad being flush with the top surface of the first structure.

2. The semiconductor structure according to claim 1, characterized in that, The gate structure comprises a gate dielectric layer and a gate electrode layer; The first structure is in direct contact with the side surface of the gate electrode layer; The second structure is in direct contact with the top surface of the gate electrode layer.

3. The semiconductor structure according to claim 2, characterized in that, Further comprising: A barrier layer, the barrier layer covering at least a part of the surface of the first structure and a part of the surface of the second structure.

4. The semiconductor structure according to claim 1, characterized in that, Further comprising: An isolation layer located on the side of the gate structure; The first structure is in direct contact with the isolation layer.

5. The semiconductor structure according to claim 1, characterized in that, Further comprising: A first dielectric layer located on the substrate; The gate structure and the interconnect structure are located in the first dielectric layer, and the top surface of the second structure is lower than the top surface of the first dielectric layer.

6. The semiconductor structure according to claim 5, characterized in that, Further comprising: A second dielectric layer located on the first dielectric layer and covering the second structure; Wherein, the top surface of the first structure is flush with the top surface of the second dielectric layer.

7. The semiconductor structure according to claim 1, characterized in that, The gate structure and the interconnect structure form part of an SRAM memory cell.

8. The semiconductor structure according to any one of claims 1-7, characterized in that, The substrate comprises an isolation structure; The projection of the gate structure on the substrate at least partially covers the isolation structure.

9. A method for manufacturing a semiconductor structure, characterized in that, Comprising: Providing a substrate; Forming a gate structure and a first dielectric layer on the substrate, the first dielectric layer covering the gate structure; Forming a first opening in the first dielectric layer, the first opening exposing part of the substrate and at least part of the top of the gate structure; Forming an interconnect structure in the first opening; Wherein, the interconnect structure comprises a first structure and a second structure, the first structure is connected to the substrate, and the second structure is connected to the top of the gate structure; The forming of the interconnect structure in the first opening comprises: Forming a conductive layer in the first opening; Forming a mask pattern layer having a first mask pattern on the conductive layer, the first mask pattern covering at least part of the conductive layer in the first opening; Etching the conductive layer using the first mask pattern such that the top surface of the conductive layer on the gate structure is lower than the top surface of the first dielectric layer; A third dielectric layer having a capacitive contact hole is formed on the substrate, and the conductive layer is also formed in the capacitive contact hole and on the surface of the third dielectric layer; The mask pattern layer further has a second mask pattern covering a part of the conductive layer in the capacitive contact hole and a part of the conductive layer on the third dielectric layer; Etch a part of the conductive layer in the capacitive contact hole and a part of the third dielectric layer by using the second mask pattern; The etching of a part of the conductive layer in the capacitive contact hole and a part of the third dielectric layer by using the second mask pattern includes: The bottom of the etching is flush with the top surface of the second structure.

10. The method for manufacturing a semiconductor structure according to claim 9, wherein The projection of the first mask pattern on the substrate coincides with the part of the substrate exposed by the first opening.

11. The method for manufacturing a semiconductor structure according to any one of claims 9-10, wherein An isolation structure is further formed on the substrate, and the projection of the gate structure on the substrate at least partially covers the isolation structure.

12. The method for manufacturing a semiconductor structure according to claim 9, wherein Further comprising: Manufacture an SRAM memory cell by using the gate structure and the interconnect structure.

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