Semiconductor structure and method of manufacturing the same

Abstract

The application relates to a semiconductor structure and a preparation method thereof, which comprises a substrate, a voltage adjustment layer, a thin gate oxide layer and a thick gate oxide layer. The substrate comprises a first transistor region and a second transistor region. The voltage adjustment layer is located in the first transistor region. The thin gate oxide layer is located on the voltage adjustment layer. The thick gate oxide layer is located in the second transistor region. The density of at least part of the thick gate oxide layer is different from that of the thin gate oxide layer. The application is beneficial to the threshold voltage of a thin gate PMOS reaching the device requirement.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and in particular to a semiconductor structure and a preparation method thereof. BACKGROUND

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor structure in electronic devices such as computers. DRAM is composed of a plurality of memory cells, each of which usually includes a transistor and a capacitor.

[0003] At present, transistors generally adopt high dielectric constant metal gates (HKMG), in which a thin gate oxide layer P-type metal oxide semiconductor (thin gate PMOS) uses a SiGe layer to adjust the threshold voltage.

[0004] However, the SiGe layer is consumed during the growth of the thick gate oxide layer, so that the threshold voltage of the thin gate PMOS cannot meet the device requirements. SUMMARY

[0005] Therefore, it is necessary to provide a semiconductor structure and a preparation method thereof to solve the problem that the threshold voltage of the thin gate PMOS in the prior art cannot meet the device requirements.

[0006] To achieve the above-mentioned purpose, in one aspect, the present application provides a semiconductor structure, comprising:

[0007] a substrate comprising a first transistor region and a second transistor region;

[0008] a voltage adjustment layer located in the first transistor region;

[0009] a thin gate oxide layer located on the voltage adjustment layer;

[0010] a thick gate oxide layer located in the second transistor region, at least part of the thick gate oxide layer has a different density from that of the thin gate oxide layer.

[0011] In one embodiment, the density of part of the thick gate oxide layer is less than that of the thin gate oxide layer.

[0012] In one embodiment, the thick gate oxide layer comprises at least two sub-oxide layers with different densities, and the density of at least one of the sub-oxide layers is less than or equal to that of the thin gate oxide layer.

[0013] In one embodiment, the at least two sub-oxide layers comprise:

[0014] a first sub-oxide layer located in the second transistor region, the first sub-oxide layer having a same density as the thin gate oxide layer;

[0015] a second sub-oxide layer located on the first sub-oxide layer, the second sub-oxide layer having a smaller density than the thin gate oxide layer.

[0016] In one embodiment, the at least two sub-oxide layers further comprise:

[0017] a third sub-oxide layer located on the second sub-oxide layer, the third sub-oxide layer having a same density as the thin gate oxide layer.

[0018] In one embodiment, the first sub-oxide layer has a thickness of 8-12 angstroms, and the second sub-oxide layer has a thickness of 60-65 angstroms.

[0019] In one embodiment, the voltage adjustment layer comprises a silicon germanium layer.

[0020] In one embodiment, the voltage adjustment layer has a thickness of 8-12 nanometers.

[0021] In one embodiment, the first transistor region is a P-type transistor region, and the second transistor region comprises an N-type transistor region and / or a P-type transistor region.

[0022] In one embodiment, the substrate further comprises a third transistor region, the third transistor region being an N-type transistor region, and the thin gate oxide layer is also located in the third transistor region.

[0023] The present application also provides a method for manufacturing a semiconductor structure, comprising:

[0024] providing a substrate, the substrate comprising a first transistor region and a second transistor region;

[0025] forming a voltage adjustment layer in the first transistor region;

[0026] forming a thick gate oxide layer in the second transistor region;

[0027] forming a thin gate oxide layer on the voltage adjustment layer, the thin gate oxide layer having a different density than the thick gate oxide layer.

[0028] In one embodiment, forming a thick gate oxide layer in the second transistor region comprises:

[0029] forming a first sub-oxide layer in the second transistor region using an in-situ water vapor generation process or a regenerative thermal oxidation process;

[0030] forming a second sub-oxide layer on the first sub-oxide layer using an atomic layer deposition process.

[0031] In one of the embodiments, forming a thin gate oxide layer on the voltage adjustment layer comprises:

[0032] forming a thin gate oxide layer on the voltage adjustment layer using an in-situ water vapor generation process.

[0033] In one of the embodiments, forming a thick gate oxide layer on the second transistor region further comprises:

[0034] forming a third sub-oxide layer on the second sub-oxide layer using an in-situ water vapor generation process when forming a thin gate oxide layer on the voltage adjustment layer using an in-situ water vapor generation process.

[0035] In one of the embodiments, forming a thin gate oxide layer on the voltage adjustment layer comprises:

[0036] forming a first thin gate oxide layer on the voltage adjustment layer using an in-situ water vapor generation process when forming a first sub-oxide layer on the second transistor region using an in-situ water vapor generation process;

[0037] forming a second thin gate oxide layer on the first thin gate oxide layer using an atomic layer deposition process when forming a second sub-oxide layer on the first sub-oxide layer using an atomic layer deposition process;

[0038] removing the second thin gate oxide layer to expose the first thin gate oxide layer to form the thin gate oxide layer using a mask etching process.

[0039] In one of the embodiments, forming a thick gate oxide layer on the second transistor region further comprises:

[0040] forming a third sub-oxide layer on the second sub-oxide layer using an in-situ water vapor generation process;

[0041] forming a thin gate oxide layer on the voltage adjustment layer further comprises:

[0042] forming a third thin gate oxide layer on the second thin gate oxide layer using an in-situ water vapor generation process when forming a third sub-oxide layer on the second sub-oxide layer using an in-situ water vapor generation process;

[0043] removing the third thin gate oxide layer using a mask etching process.

[0044] In one of the embodiments, further comprising:

[0045] nitriding the thick gate oxide layer using a remote plasma nitridation process;

[0046] densifying the thick gate oxide layer using a post-nitridation annealing process.

[0047] The semiconductor structure and the preparation method thereof have the following advantages:

[0048] The semiconductor structure comprises a substrate, a voltage adjustment layer, a thin gate oxide layer and a thick gate oxide layer. The substrate comprises a first transistor region and a second transistor region, and the thin gate oxide layer and the thick gate oxide layer can be formed respectively. The voltage adjustment layer is located in the first transistor region, and the thin gate oxide layer is located on the voltage adjustment layer, so that the thin gate PMOS can use the voltage adjustment layer to adjust the threshold voltage of the MOS. The thick gate oxide layer is located in the second transistor region, and the density of at least part of the thick gate oxide layer is different from that of the thin gate oxide layer, so that by sacrificing the density of the thick gate oxide layer, the consumption of the voltage adjustment layer in the growth process of the thick gate oxide layer can be reduced, and the threshold voltage of the thin gate PMOS can meet the requirements of the device.

[0049] The preparation method of the semiconductor structure comprises the following steps: providing a substrate, the substrate comprising a first transistor region and a second transistor region, and the thin gate oxide layer and the thick gate oxide layer can be formed respectively. Forming a voltage adjustment layer in the first transistor region, and finally forming a thin gate oxide layer on the voltage adjustment layer, so that the thin gate PMOS can use the voltage adjustment layer to adjust the threshold voltage of the MOS. In addition, after the voltage adjustment layer is formed in the first transistor region and before the thin gate oxide layer is formed on the voltage adjustment layer, the thick gate oxide layer is formed in the second transistor region, and the density of the thin gate oxide layer is different from that of at least part of the thick gate oxide layer, so that by sacrificing the density of the thick gate oxide layer, the consumption of the voltage adjustment layer in the growth process of the thick gate oxide layer can be reduced, and the threshold voltage of the thin gate PMOS can meet the requirements of the device. BRIEF DESCRIPTION OF DRAWINGS

[0050] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort.

[0051] Figure 1 It is a structural schematic diagram of the semiconductor structure provided in an embodiment;

[0052] Figure 2 It is a structural schematic diagram of the thick gate oxide layer provided in an embodiment;

[0053] Figure 3 It is a structural schematic diagram of the thick gate oxide layer provided in another embodiment;

[0054] Figure 4A cross-sectional view of a structure provided in another embodiment for a thick gate oxide layer;

[0055] Figure 5 A flowchart of a method for fabricating a semiconductor structure provided in an embodiment;

[0056] Figure 6 A cross-sectional view of a structure provided in an embodiment for a semiconductor structure;

[0057] Figure 7 A cross-sectional view of a structure provided in an embodiment for a semiconductor structure;

[0058] Figure 8 A cross-sectional view of a structure provided in an embodiment for a semiconductor structure;

[0059] Figure 9 A cross-sectional view of a structure provided in an embodiment for a semiconductor structure;

[0060] Figure 10 A flowchart of a method for fabricating a semiconductor structure provided in an embodiment;

[0061] Figure 11 A flowchart of a method for fabricating a semiconductor structure provided in another embodiment;

[0062] Figure 12 A flowchart of a method for fabricating a semiconductor structure provided in another embodiment;

[0063] Figure 13 A flowchart of a method for fabricating a semiconductor structure provided in another embodiment.

[0064] BRIEF DESCRIPTION OF DRAWINGS

[0065] 10, substrate, 11, first transistor region, 12, second transistor region, 13, third transistor region;

[0066] 20, voltage adjustment layer;

[0067] 30, thin gate oxide layer;

[0068] 40, thick gate oxide layer, 41, first sub-oxide layer, 42, second sub-oxide layer, 43, third sub-oxide layer, 44, fourth sub-oxide layer, 45, fifth sub-oxide layer. DETAILED DESCRIPTION

[0069] For the purposes of the present application, the following terms are intended to have the meanings set forth below. The following terms are intended to have the following meanings throughout the specification and claims:

[0070] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description herein is for describing particular embodiments only and is not intended to be limiting of the application.

[0071] It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or connected to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers present. It will also be understood that, when a term is used herein to refer to a process, operation, etc., that includes two or more steps, the term can be used to refer to those two or more steps individually or collectively. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section; for example, a first dopant type could be termed a second dopant type, and similarly, a second dopant type could be termed a first dopant type; a first dopant type and a second dopant type are different dopant types, for example, a first dopant type can be P-type and a second dopant type can be N-type, or a first dopant type can be N-type and a second dopant type can be P-type. It will be understood that the terms "comprises" and / or "comprising," or "includes" and / or "including" when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and / or groups thereof.

[0072] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" can include both upper and lower orientations. In addition, the device can also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0073] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "comprising" and / or "including" are used in this specification, they may specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0074] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic illustrations of idealized embodiments (and intermediate structures) of the invention, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Accordingly, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs. Accordingly, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the invention.

[0075] At present, in the HKMG device, the thin gate PMOS uses the SiGe layer to adjust the threshold voltage. Generally, the 1 angstrom thickness SiGe layer can affect the threshold voltage of the thin gate PMOS by 1 millivolt. Correspondingly, in the preparation process of the HKMG device, firstly, the thickness of the SiGe layer is determined according to the required threshold voltage of the device, and the SiGe layer with the determined thickness is formed on the thin gate PMOS. Then, the thick gate oxide layers are respectively formed on the thick gate oxide N-type metal oxide semiconductor (NMOS) and the thick gate oxide P-type metal oxide semiconductor (PMOS). Finally, the thin gate oxide layers are formed on the thin gate oxide N-type metal oxide semiconductor (NMOS) and the SiGe layer of the thin gate PMOS, and the thickness of the thin gate oxide layer is less than that of the thick gate oxide layer.

[0076] However, in the conventional technology, the thick gate oxide layer is formed by using the in-situ steam generation (ISSG) process. Thus, during the growth of the thick gate oxide layer, the SiGe layer with a certain thickness is consumed, so that the threshold voltage of the thin gate PMOS is too high to meet the requirement of the device. If the thickness of the SiGe layer consumed during the growth of the thick gate oxide layer is increased on the basis of the thickness of the SiGe layer determined according to the required threshold voltage of the device, that is, the thickness of the SiGe layer consumed during the growth of the thick gate oxide layer is pre-compensated during the formation of the SiGe layer, then the device will have defects and lattice mismatch, the performance of the device will be reduced, and the requirement of the device cannot be met.

[0077] In view of the above problems, the embodiment of the present application provides a semiconductor structure and a preparation method thereof. By changing the formation process of the thick gate oxide layer, the density of the thick gate oxide layer is sacrificed to reduce the consumption of the voltage adjustment layer during the growth of the thick gate oxide layer, so that the threshold voltage of the thin gate PMOS meets the requirement of the device.

[0078] Please refer to Figure 1 The present application provides a semiconductor structure, which comprises a substrate 10, a voltage adjustment layer 20, a thin gate oxide layer 30 and a thick gate oxide layer 40. The substrate 10 comprises a first transistor region 11 and a second transistor region 12. The voltage adjustment layer 20 is located on the first transistor region 11. The thin gate oxide layer 30 is located on the voltage adjustment layer 20. The thick gate oxide layer 40 is located on the second transistor region 12. The density of at least part of the thick gate oxide layer 40 is different from that of the thin gate oxide layer 30.

[0079] The semiconductor structure includes a substrate, a voltage adjustment layer, a thin gate oxide layer, and a thick gate oxide layer. The substrate includes a first transistor region and a second transistor region, wherein the thin gate oxide layer and the thick gate oxide layer can be formed, respectively. The voltage adjustment layer is located in the first transistor region, and the thin gate oxide layer is located on the voltage adjustment layer. In this way, the threshold voltage of the thin-gate PMOS can be adjusted using the voltage adjustment layer. The thick gate oxide layer is located in the second transistor region, and the density of at least a portion of the thick gate oxide layer is different from that of the thin gate oxide layer. By sacrificing the density of the thick gate oxide layer, the consumption of the voltage adjustment layer during the growth of the thick gate oxide layer can be reduced, so that the threshold voltage of the thin-gate PMOS meets the device requirements.

[0080] For example, the substrate 10 may be made of a semiconductor material, an insulating material, a conductive material, or any combination thereof. The substrate 10 may be a single-layer structure or a multi-layer structure. For example, the substrate 10 may be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. For another example, the substrate 10 may be a layered substrate including Si / SiGe, Si / SiC, silicon on insulator (SOI), or silicon germanium on insulator.

[0081] A shallow trench isolation (STI) structure may be formed in the substrate 10 . The STI structure may isolate a plurality of active areas (AA) arranged at intervals in the substrate 10 .

[0082] The active region may be a P-type active region or an N-type active region. The P-type active region may be formed by implanting N-type ions to form a source region and a drain region to form an NMOS device. As an example, the P-type ions may include but are not limited to any one or more of boron (Boron, B) ions, gallium (Magnesium, Mg) ions or indium (Indium, In) ions, etc. The N-type active region may be formed by implanting P-type ions to form a source region and a drain region to form a PMOS device. As an example, the N-type ions may include but are not limited to one or more of phosphorus (P) ions, arsenic (As) ions or antimony (Sb) ions.

[0083] In some embodiments, as Figure 1 As shown, the first transistor region 11 is a P-type transistor region, and the second transistor region 12 includes an N-type transistor region and a P-type transistor region.

[0084] In other embodiments, the second transistor region 12 can also be one of the N-type transistor region and the P-type transistor region, i.e., the second transistor region 12 is the N-type transistor region, or the second transistor region 12 is the P-type transistor region.

[0085] Optionally, the type of the second transistor region 12 can be determined by the type of the thick gate MOS. If the thick gate MOS includes the thick gate NMOS and the thick gate PMOS, the second transistor region 12 includes the N-type transistor region and the P-type transistor region; if the thick gate MOS includes the thick gate NMOS, the second transistor region 12 includes the N-type transistor region; if the thick gate MOS includes the thick gate PMOS, the second transistor region 12 includes the P-type transistor region.

[0086] In the above embodiments, the first transistor region 11 is the P-type transistor region, and the voltage adjustment layer 20 is arranged between the thin gate oxide layer 30 and the first transistor region 11, so that the threshold voltage of the thin gate PMOS can be adjusted by the voltage adjustment layer.

[0087] Exemplarily, as shown in FIG. 1, the substrate 10 further includes a third transistor region 13, the third transistor region 13 is the N-type transistor region, and the thin gate oxide layer 30 is also arranged on the third transistor region 13. Figure 1

[0088] Optionally, whether the substrate 10 includes the third transistor region 13 can be determined by the type of the thin gate MOS. If the thin gate MOS includes the thin gate NMOS and the thin gate PMOS, the substrate 10 includes the first transistor region 11 and the third transistor region 13; if the thin gate MOS includes the thin gate PMOS, the substrate 10 includes the first transistor region 11.

[0089] In the above embodiments, unlike the thin gate PMOS, the threshold voltage of the thin gate NMOS is not adjusted by the voltage adjustment layer, at this time, the thin gate oxide layer 30 is directly arranged on the third transistor region 13 to meet the requirements of the device.

[0090] In some embodiments, the voltage adjustment layer 20 includes a silicon germanium (SiGe) layer.

[0091] In the above embodiments, the voltage adjustment layer 20 is the SiGe layer, and the threshold voltage of the thin gate PMOS can be adjusted by the SiGe layer, such as determining the thickness of the SiGe layer according to the threshold voltage required by the device, and forming the SiGe layer with the determined thickness on the thin gate PMOS, so that the threshold voltage of the thin gate PMOS meets the requirements of the device.

[0092] Exemplarily, the thickness of the voltage adjustment layer 20 is 8 nanometers to 12 nanometers, such as 8 nanometers, 9 nanometers, 10 nanometers, 11 nanometers, 12 nanometers, etc.

[0093] ​In the above embodiment, the thickness of the voltage adjustment layer 20 is 8 nanometers to 12 nanometers, which can make the threshold voltage of the thin-gate PMOS meet the device requirements.

[0094] In some embodiments, the thin gate oxide layer 30 includes but is not limited to a silicon oxide layer (SiO 2 ), an aluminum oxide (Al 2 O 3 ) or a silicon oxynitride layer (SiON).

[0095] Exemplarily, the thickness of the thin gate oxide layer 30 is smaller than the thickness of the thick gate oxide layer 40 .

[0096] In some embodiments, the density of the portion of the thick gate oxide layer 40 is less than the density of the thin gate oxide layer 30 .

[0097] In the above embodiment, the density of a portion of the thick gate oxide layer 40 is less than the density of the thin gate oxide layer 30. Sacrificing the density of the thick gate oxide layer 40 can reduce the consumption of the voltage adjustment layer 20 during the growth of the thick gate oxide layer 40, so that the threshold voltage of the thin gate PMOS meets the device requirements.

[0098] In some embodiments, the thick gate oxide layer 40 includes at least two sub-oxide layers with different densities, and the density of at least one sub-oxide layer is less than or equal to the density of the thin gate oxide layer 30 .

[0099] In the above embodiment, the thick gate oxide layer 40 includes at least two sub-oxide layers with different densities, and the density of at least one sub-oxide layer is less than or equal to the density of the thin gate oxide layer 30. In this way, the density of a portion of the sub-oxide layers is the same as the density of the thin gate oxide layer 30, which is beneficial for achieving the function of the thick gate oxide layer 40. At the same time, the density of another portion of the sub-oxide layers is less than the density of the thin gate oxide layer 30. In this way, the overall density of the thick gate oxide layer 40 can be less than the density of the thin gate oxide layer 30, which can reduce the consumption of the voltage adjustment layer 20 during the growth of the thick gate oxide layer 40, and ensure that the threshold voltage of the thin-gate PMOS meets the device requirements.

[0100] In some embodiments, see Figure 2 The at least two sub-oxide layers include a first sub-oxide layer 41 and a second sub-oxide layer 42. The first sub-oxide layer 41 is located in the second transistor region 12, and the density of the first sub-oxide layer 41 is the same as the density of the thin gate oxide layer 30. The second sub-oxide layer 42 is located on the first sub-oxide layer 41, and the density of the second sub-oxide layer 42 is less than the density of the thin gate oxide layer 30.

[0101] In the above embodiment, the first sub-oxide layer 41 with higher density is located in the second transistor region 12, and has stronger adhesion, which is beneficial to the adhesion of the thick gate oxide layer 40 on the substrate 10. The second sub-oxide layer 42 with lower density is located on the first sub-oxide layer 41, which can reduce the overall density of the thick gate oxide layer 40 and reduce the consumption of the voltage adjustment layer 20 during the growth of the thick gate oxide layer 40, so that the threshold voltage of the thin gate PMOS meets the device requirements.

[0102] In some embodiments, the thickness of the second sub-oxide layer 42 is 5 times to 8 times the thickness of the first sub-oxide layer 41.

[0103] In the above embodiment, the thickness of the first sub-oxide layer 41 with higher density is much smaller than the thickness of the second sub-oxide layer 42 with lower density, which can reduce the consumption of the voltage adjustment layer during the growth of the thick gate oxide layer as much as possible.

[0104] For example, the thickness of the first sub-oxide layer 41 is 8 angstroms to 12 angstroms, such as 8 angstroms, 9 angstroms, 10 angstroms, 11 angstroms, 12 angstroms, etc.

[0105] In the above embodiment, the thickness of the first sub-oxide layer 41 is 8 angstroms to 12 angstroms, which can reduce the consumption of the voltage adjustment layer during the growth of the thick gate oxide layer as much as possible on the basis of ensuring that the thick gate oxide layer 40 is attached to the substrate 10.

[0106] For example, the thickness of the second sub-oxide layer 42 is 60 angstroms to 65 angstroms, such as 60 angstroms, 61 angstroms, 62 angstroms, 63 angstroms, 64 angstroms, 65 angstroms, etc.

[0107] In the above embodiment, the thickness of the second sub-oxide layer 42 is 60 angstroms to 65 angstroms, which can meet the thickness requirement of the thick gate oxide layer 40 and effectively reduce the consumption of the voltage adjustment layer 20 during the growth of the thick gate oxide layer 40, so that the threshold voltage of the thin gate PMOS meets the device requirements.

[0108] In some embodiments, referring to Figure 3 , the at least two sub-oxide layers further include a third sub-oxide layer 43. The third sub-oxide layer 43 is located on the second sub-oxide layer 42, and the density of the third sub-oxide layer 43 is the same as the density of the thin gate oxide layer 30.

[0109] In the above embodiment, the at least two sub-oxide layers further include a third sub-oxide layer 43 located on the second sub-oxide layer 42, and the second transistor region is sequentially stacked with the first sub-oxide layer 41, the second sub-oxide layer 42 and the third sub-oxide layer 43, the first sub-oxide layer 41 and the third sub-oxide layer 43 have the same density as the thin gate oxide layer 30 and are located on both sides of the thick gate oxide layer 40, which is conducive to the function of the thick gate oxide layer 40. The density of the second sub-oxide layer 42 is less than that of the thin gate oxide layer 30, and is located between the first sub-oxide layer 41 and the third sub-oxide layer 43, which can avoid affecting the function of the thick gate oxide layer 40 as much as possible, and reduce the consumption of the voltage adjustment layer 20 during the growth of the thick gate oxide layer 40, so that the threshold voltage of the thin gate PMOS reaches the device requirement.

[0110] Exemplarily, the thickness of the third sub-oxide layer 43 is the same as that of the thin gate oxide layer 30.

[0111] In the above embodiment, the third sub-oxide layer 43 can be formed at the same time as the thin gate oxide layer 30, which saves process steps and reduces implementation cost.

[0112] In some embodiments, referring to Figure 4 , the at least two sub-oxide layers include a fourth sub-oxide layer 44 and a fifth sub-oxide layer 45. The fourth sub-oxide layer 44 is located on the second transistor region 12, and the density of the fourth sub-oxide layer 44 is less than that of the thin gate oxide layer 30. The fifth sub-oxide layer 45 is located on the fourth sub-oxide layer 44, and the density of the fifth sub-oxide layer 45 is the same as that of the thin gate oxide layer 30.

[0113] The following compares the conventional technology with the present application:

[0114] Taking the thickness of the voltage adjustment layer as 10 nanometers for example, after the growth of the 65 angstrom thick gate oxide layer, the voltage adjustment layer will have a consumption of about 3 nanometers, and the voltage adjustment layer will be left with 7 nanometers. Since a 1 angstrom thick SiGe layer can affect the threshold voltage of the thin gate PMOS by 1 millivolt, the consumption of 3 nanometers of SiGe layer can affect the threshold voltage of the thin gate PMOS by 30 millivolts, i.e. a threshold voltage of 0.03 volts. The difference in threshold voltage is large, which can make the threshold voltage of the thin gate PMOS reach the device requirement.

[0115] And after the growth of the 10 angstrom first sub-oxide layer, the voltage adjustment layer has a consumption of only 0.5 nanometers, and the voltage adjustment layer is left with 9.5 nanometers. After the growth of the 62 angstrom second sub-oxide layer, the voltage adjustment layer has no consumption. The overall consumption of 0.5 nanometers of SiGe layer of the voltage adjustment layer only affects the threshold voltage of the thin gate PMOS by 5 millivolts to 10 millivolts, i.e. a threshold voltage of not more than 0.01 volts. The difference in threshold voltage is small, and the threshold voltage of the thin gate PMOS can still reach the device requirement.

[0116] Therefore, the application can reduce the consumption of the voltage adjustment layer during the growth of the thick gate oxide layer, so that the threshold voltage of the thin gate PMOS meets the requirements of the device.

[0117] Based on the same inventive concept, please refer to Figure 5 The application further provides a preparation method of the semiconductor structure, which comprises the following steps:

[0118] In step 502, a substrate is provided, which comprises a first transistor region and a second transistor region.

[0119] The first transistor region is used for forming a thin gate PMOS, and the second transistor region is used for forming a thick gate NMOS and a thick gate PMOS.

[0120] Optionally, the substrate further comprises a third transistor region, which is used for forming a thin gate NMOS.

[0121] Figure 6 A cross-sectional schematic view of the structure obtained in step 502 in the preparation method of the semiconductor structure provided by the embodiment of the application is shown in FIG. 1. Figure 6 As shown in FIG. 1, the substrate 10 comprises a first transistor region 11, a second transistor region 12 and a third transistor region 13.

[0122] In step 504, a voltage adjustment layer is formed in the first transistor region.

[0123] Figure 7 A cross-sectional schematic view of the structure obtained in step 504 in the preparation method of the semiconductor structure provided by the embodiment of the application is shown in FIG. 2. Figure 7 As shown in FIG. 2, the voltage adjustment layer 20 is only formed in the first transistor region 11, and the second transistor region 12 and the third transistor region 13 are both free of the voltage adjustment layer 20.

[0124] Optionally, the voltage adjustment layer is first formed on the substrate, at this time, the voltage adjustment layer is simultaneously formed in the first transistor region, the second transistor region and the third transistor region. Then, a first photoresist is formed on the voltage adjustment layer, and the first photoresist in the second transistor region and the third transistor region is removed through a photolithography technology, and only the first photoresist in the first transistor region is left. Finally, the voltage adjustment layer in the second transistor region and the third transistor region is removed by using the shielding and protection of the first photoresist, and only the voltage adjustment layer in the first transistor region is left.

[0125] In step 506, a thick gate oxide layer is formed in the second transistor region.

[0126] Figure 8 A cross-sectional schematic view of the structure obtained in step 506 in the preparation method of the semiconductor structure provided by the embodiment of the application is shown in FIG. 3. Figure 8As shown, the thick gate oxide layer 40 is formed only in the second transistor region 12, and the first transistor region 11 and the third transistor region 13 are both free of the thick gate oxide layer 40.

[0127] Alternatively, the thick gate oxide layer is first formed in the first transistor region, the second transistor region and the third transistor region. Then the second photoresist is formed on the thick gate oxide layer, and the second photoresist in the first transistor region and the third transistor region is removed by the photolithography technique, leaving only the second photoresist in the second transistor region. Finally, the thick gate oxide layer in the first transistor region and the third transistor region is removed with the protection of the second photoresist, leaving only the thick gate oxide layer in the second transistor region.

[0128] In step 508, a thin gate oxide layer is formed on the voltage adjustment layer, and the density of the thin gate oxide layer is different from the density of at least part of the thick gate oxide layer.

[0129] Alternatively, step 508 further comprises: forming the thin gate oxide layer in the third transistor region, i.e. forming the thin gate oxide layer on the third transistor region and the voltage adjustment layer at the same time.

[0130] Figure 9 A cross-sectional view of the structure obtained in step 508 in the method for manufacturing the semiconductor structure provided by the embodiment of the present application is shown in FIG. 3. Figure 9 As shown, the thin gate oxide layer 30 is formed on the third transistor region 13 and the voltage adjustment layer 20 at the same time.

[0131] Alternatively, after the thick gate oxide layer in the first transistor region and the third transistor region is removed, the second photoresist in the third transistor region is removed first. Then the thin gate oxide layer is formed on the third transistor region, the voltage adjustment layer and the second photoresist. Finally, the second photoresist is removed, and the thin gate oxide layer on the second photoresist is removed at the same time, leaving the thin gate oxide layer on the third transistor region and the voltage adjustment layer.

[0132] Alternatively, after the thick gate oxide layer in the first transistor region and the third transistor region is removed, the second photoresist in the second transistor region and the third transistor region is removed at the same time. Then the thin gate oxide layer is formed on the second transistor region, the third transistor region and the voltage adjustment layer, and the thin gate oxide layer in the second transistor region is taken as part of the thick gate oxide layer.

[0133] The method for manufacturing the semiconductor structure includes the following steps. A substrate is provided, which includes a first transistor region and a second transistor region. A thin gate oxide layer and a thick gate oxide layer are formed in the first transistor region and the second transistor region, respectively. A voltage adjustment layer is formed in the first transistor region. A thin gate oxide layer is formed on the voltage adjustment layer. The thin gate PMOS can use the voltage adjustment layer to adjust the threshold voltage of the MOS. After the voltage adjustment layer is formed in the first transistor region, and before the thin gate oxide layer is formed on the voltage adjustment layer, the thick gate oxide layer is formed in the second transistor region. The density of the thin gate oxide layer is different from that of at least part of the thick gate oxide layer. The consumption of the voltage adjustment layer during the growth of the thick gate oxide layer is reduced by sacrificing the density of the thick gate oxide layer, so that the threshold voltage of the thin gate PMOS meets the requirements of the device.

[0134] In some embodiments, as shown in FIG. 5, step 506 includes the following steps: Figure 10

[0135] Step 1002, using the ISSG process or the regenerative thermal oxidizer (RTO) process to form a first sub-oxide layer in the second transistor region.

[0136] For example, the temperature for forming the first sub-oxide layer by the ISSG process is 900-1100°C, such as 900°C, 925°C, 950°C, 975°C, 1000°C, 1025°C, 1050°C, 1075°C, 1100°C, etc.

[0137] For example, the temperature for forming the first sub-oxide layer by the RTO process is 800-900°C, such as 800°C, 810°C, 820°C, 830°C, 840°C, 850°C, 860°C, 870°C, 880°C, 890°C, 900°C.

[0138] For example, the formation time of the first sub-oxide layer is 10-20s, such as 10s, 11s, 12s, 13s, 14s, 15s, 16s, 17s, 18s, 19s, 20s, etc.

[0139] Step 1004, using the atomic layer deposition (ALD) process to form a second sub-oxide layer on the first sub-oxide layer.

[0140] For example, the temperature for forming the second sub-oxide layer by the ALD process is 500-700°C, such as 500°C, 525°C, 550°C, 575°C, 600°C, 625°C, 650°C, 675°C, 700°C, etc.

[0141] ​In the above embodiment, the first sub-oxide layer is formed by the ISSG process or the RTO process, and the first sub-oxide layer has a high density, which is beneficial to the adhesion of the thick gate oxide layer to the second transistor region. The second sub-oxide layer is formed by the ALD process, and the second sub-oxide layer has a low density, but the second sub-oxide layer is not consumed during the formation of the second sub-oxide layer, which can reduce the consumption of the voltage adjustment layer during the growth of the thick gate oxide layer, and is beneficial to the threshold voltage of the thin gate PMOS to meet the device requirements.

[0142] In some embodiments, step 508 comprises the following step: forming a thin gate oxide layer on the voltage adjustment layer by the ISSG process.

[0143] In the above embodiment, the thin gate oxide layer is formed by the ISSG process, and the thin gate oxide layer has a high density, which is beneficial to the function of the thin gate oxide layer.

[0144] Illustratively, step 506 further comprises: when the thin gate oxide layer is formed on the voltage adjustment layer by the ISSG process, forming a third sub-oxide layer on the second sub-oxide layer by the ISSG process.

[0145] In the above embodiment, the third sub-oxide layer is formed on the second sub-oxide layer by the ISSG process at the same time when the thin gate oxide layer is formed on the voltage adjustment layer by the ISSG process, and the second transistor region is sequentially stacked with the first sub-oxide layer, the second sub-oxide layer and the third sub-oxide layer, and the first sub-oxide layer and the third sub-oxide layer have the same density as the thin gate oxide layer and are located on both sides of the thick gate oxide layer, which is beneficial to the function of the thick gate oxide layer.

[0146] In some embodiments, referring to Figure 11 The present application also provides another method for manufacturing a semiconductor structure, which comprises the following steps:

[0147] Step 1102 provides a substrate, and the substrate comprises a first transistor region and a second transistor region.

[0148] The first transistor region is used to form a thin gate PMOS, and the second transistor region is used to form a thick gate NMOS and a thick gate PMOS.

[0149] Optionally, the substrate further comprises a third transistor region, which is used to form a thin gate NMOS.

[0150] Specifically, step 1102 can be the same as step 502, and will not be described here in detail.

[0151] Step 1104 forms a voltage adjustment layer on the first transistor region.

[0152] Specifically, step 1104 can be the same as step 504, and will not be described here in detail.

[0153] In step 1106, a first sub-oxide layer is formed in the second transistor region by using an in-situ water vapor generation process, and a first thin gate oxide layer is formed on the voltage adjustment layer.

[0154] Optionally, in step 1106, a first thin gate oxide layer is formed on the voltage adjustment layer, and a first thin gate oxide layer is formed in the third transistor region by using an in-situ water vapor generation process.

[0155] In step 1108, a second sub-oxide layer is formed on the first sub-oxide layer by using an atomic layer deposition process, and a second thin gate oxide layer is formed on the first thin gate oxide layer.

[0156] Optionally, if the substrate only includes the first transistor region and the second transistor region, the second thin gate oxide layer is located in the first transistor region; if the substrate further includes the third transistor region, the second thin gate oxide layer is located in the first transistor region and the third transistor region.

[0157] In step 1110, the second thin gate oxide layer is removed by using a photo mask etching process to expose the first thin gate oxide layer to form a thin gate oxide layer.

[0158] Optionally, if the substrate only includes the first transistor region and the second transistor region, the second thin gate oxide layer in the first transistor region is removed; if the substrate further includes the third transistor region, the second thin gate oxide layers in the first transistor region and the third transistor region are removed.

[0159] In some embodiments, referring to Figure 12 The present application also provides another method for manufacturing a semiconductor structure, which comprises the following steps:

[0160] In step 1202, a substrate is provided, which includes a first transistor region and a second transistor region.

[0161] Specifically, step 1202 can be the same as step 1102, which is not described here again.

[0162] In step 1204, a voltage adjustment layer is formed in the first transistor region.

[0163] Specifically, step 1204 can be the same as step 1104, which is not described here again.

[0164] In step 1206, a first sub-oxide layer is formed in the second transistor region by using an in-situ water vapor generation process, and a first thin gate oxide layer is formed on the voltage adjustment layer.

[0165] Specifically, step 1206 can be the same as step 1106, which is not described here again.

[0166] Step 1208, a second sub-oxide layer is formed on the first sub-oxide layer by an atomic layer deposition process, and a second thin gate oxide layer is formed on the first thin gate oxide layer.

[0167] Specifically, step 1208 can be the same as step 1108, which will not be described in detail here.

[0168] Step 1210, a third sub-oxide layer is formed on the second sub-oxide layer by an in-situ water vapor generation process, and a third thin gate oxide layer is formed on the second thin gate oxide layer.

[0169] Optionally, if the substrate only includes the first transistor region and the second transistor region, the third thin gate oxide layer is located in the first transistor region; if the substrate further includes the third transistor region, the third thin gate oxide layer is located in the first transistor region and the third transistor region.

[0170] Step 1212, the third thin gate oxide layer and the second thin gate oxide layer are removed by a photomask etching process to expose the first thin gate oxide layer to form a thin gate oxide layer.

[0171] Optionally, if the substrate only includes the first transistor region and the second transistor region, the third thin gate oxide layer and the second thin gate oxide layer of the first transistor region are removed; if the substrate further includes the third transistor region, the third thin gate oxide layer and the second thin gate oxide layer of the first transistor region and the third transistor region are removed.

[0172] In some embodiments, referring to Figure 13 The preparation method further includes the following steps:

[0173] Step 1302, a thick gate oxide layer is subjected to a nitrogenization treatment by a remote plasma nitridation (RPN) process.

[0174] Illustratively, the temperature of the nitrogenization treatment is 500-700°C, such as 500°C, 525°C, 550°C, 575°C, 600°C, 625°C, 650°C, 675°C, 700°C, etc.

[0175] Illustratively, the radio frequency power of the nitrogenization treatment equipment is 4500-5500W, such as 4500W, 4600W, 4700W, 4800W, 4900W, 5000W, 5100W, 5200W, 5300W, 5400W, 5500W, etc.

[0176] Illustratively, the gas of the nitrogenization treatment is ammonia (NH3) with a concentration of 0.15-0.25, such as 0.15, 0.16, 0.17, 0.18, 0.19, 0.2, 0.21, 0.21, 0.22, 0.23, 0.24, 0.25, etc.

[0177] In step 1304, a post nitridation anneal (PNA) process is used to densify the thick gate oxide layer.

[0178] For example, the temperature of the densification process is 900-1100℃, such as 900℃, 925℃, 950℃, 975℃, 1000℃, 1025℃, 1050℃, 1075℃, 1100℃, etc.

[0179] For example, the time of the densification process is 25-35s, such as 25s, 26s, 27s, 28s, 29s, 30s, 31s, 32s, 33s, 34s, 35s, etc.

[0180] In the above embodiments, the thick gate oxide layer is first treated by the RPN process, and then treated by the PNA process, which can improve the density of the thick gate oxide layer and facilitate the function of the thick gate oxide layer.

[0181] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, all possible combinations of the technical features of the above embodiments are not described, but as long as the combinations of the technical features do not contradict, they should be considered as the scope of the present disclosure.

[0182] The above embodiments only express several implementation manners of the present application, and the description is specific and detailed, but it should not be understood as a limitation on the patent scope of the application. It should be pointed out that for ordinary skilled in the art, without departing from the concept of the present application, several modifications and improvements can be made, which are all within the protection scope of the present application. Therefore, the patent protection scope of the present application should be subject to the appended claims.

Claims

1. A semiconductor structure, characterized in that include: a substrate comprising a first transistor region and a second transistor region; a voltage adjustment layer, located in the first transistor region; a thin gate oxide layer, located on the voltage adjustment layer; a thick gate oxide layer located in the second transistor region, wherein the density of at least a portion of the thick gate oxide layer is different from the density of the thin gate oxide layer; Wherein, the density of a portion of the thick gate oxide layer is less than the density of the thin gate oxide layer.

2. The semiconductor structure according to claim 1, wherein: The thick gate oxide layer includes at least two sub-oxide layers with different densities, and the density of at least one of the sub-oxide layers is less than or equal to the density of the thin gate oxide layer.

3. The semiconductor structure according to claim 2, wherein: The at least two sub-oxide layers include: a first sub-oxide layer, located in the second transistor region, wherein the density of the first sub-oxide layer is the same as that of the thin gate oxide layer; The second sub-oxide layer is located on the first sub-oxide layer, and the density of the second sub-oxide layer is less than the density of the thin gate oxide layer.

4. The semiconductor structure according to claim 3, wherein: The at least two sub-oxide layers further include: The third sub-oxide layer is located on the second sub-oxide layer, and the density of the third sub-oxide layer is the same as the density of the thin gate oxide layer.

5. The semiconductor structure according to claim 3, wherein: The thickness of the first sub-oxide layer is 8 angstroms to 12 angstroms, and the thickness of the second sub-oxide layer is 60 angstroms to 65 angstroms.

6. The semiconductor structure according to any one of claims 1 to 5, characterized in that The voltage adjustment layer includes a silicon germanium layer.

7. The semiconductor structure according to claim 6, wherein: The thickness of the voltage adjustment layer is 8 nanometers to 12 nanometers.

8. The semiconductor structure according to claim 6, wherein: The first transistor region is a P-type transistor region, and the second transistor region includes an N-type transistor region and / or a P-type transistor region.

9. The semiconductor structure according to claim 8, wherein: The substrate further includes a third transistor region, which is an N-type transistor region. The thin gate oxide layer is also located in the third transistor region.

10. A method for preparing a semiconductor structure, characterized in that: include: providing a substrate, the substrate comprising a first transistor region and a second transistor region; forming a voltage adjustment layer in the first transistor region; forming a thick gate oxide layer in the second transistor region; forming a thin gate oxide layer on the voltage adjustment layer, wherein the density of the thin gate oxide layer is different from the density of at least a portion of the thick gate oxide layer; Wherein, the density of a portion of the thick gate oxide layer is less than the density of the thin gate oxide layer.

11. The preparation method according to claim 10, characterized in that: Forming a thick gate oxide layer in the second transistor region includes: forming a first sub-oxide layer in the second transistor region by using an in-situ water vapor generation process or a regenerative thermal oxidation process; A second sub-oxide layer is formed on the first sub-oxide layer by adopting an atomic layer deposition process.

12. The preparation method according to claim 11, characterized in that Forming a thin gate oxide layer on the voltage adjustment layer includes: A thin gate oxide layer is formed on the voltage adjustment layer by adopting an in-situ water vapor generation process.

13. The preparation method according to claim 12, characterized in that Forming a thick gate oxide layer in the second transistor region further includes: When the thin gate oxide layer is formed on the voltage adjustment layer by adopting the in-situ water vapor generation process, the third sub-oxide layer is formed on the second sub-oxide layer by adopting the in-situ water vapor generation process.

14. The preparation method according to claim 11, characterized in that Forming a thin gate oxide layer on the voltage adjustment layer includes: When forming the first sub-oxide layer in the second transistor region by adopting the in-situ water vapor generation process, forming the first thin gate oxide layer on the voltage adjustment layer by adopting the in-situ water vapor generation process; When forming the second sub-oxide layer on the first sub-oxide layer by an atomic layer deposition process, forming the second thin gate oxide layer on the first thin gate oxide layer by an atomic layer deposition process; The second thin gate oxide layer is removed by using a photomask etching process to expose the first thin gate oxide layer to form the thin gate oxide layer.

15. The preparation method according to claim 14, characterized in that Forming a thick gate oxide layer in the second transistor region further includes: forming a third sub-oxide layer on the second sub-oxide layer by using an in-situ water vapor generation process; Forming a thin gate oxide layer on the voltage adjustment layer further includes: When forming the third sub-oxide layer on the second sub-oxide layer by adopting the in-situ water vapor generation process, forming the third thin gate oxide layer on the second thin gate oxide layer by adopting the in-situ water vapor generation process; The third thin gate oxide layer is removed by using a photomask etching process.

16. The preparation method according to any one of claims 11 to 15, characterized in that: Also includes: nitriding the thick gate oxide layer using a remote plasma nitridation process; The thick gate oxide layer is densified by adopting a post-nitridation annealing process.

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