A flash memory cell structure and method of fabrication thereof

Abstract

The application provides a flash memory cell structure and a manufacturing method thereof. The method forms a stepped opening in a dielectric stack, and etches the dielectric stack, a hard mask layer and a floating gate conductive layer based on the stepped opening until a gate dielectric layer is exposed at the bottom of a first trench and the floating gate conductive layer is exposed at the bottom of a second trench. Then, an insulating layer is formed on the exposed surface of the floating gate conductive layer, and the part of the floating gate conductive layer not covered by the insulating layer is removed to obtain a floating gate, the first side surface and the top surface of the floating gate are covered by the insulating layer. Then, an isolation side wall is formed on the second side surface of the floating gate, and a word line is formed. When the number of floating gates is multiple, the multiple word lines are arranged in the horizontal direction and are located on the same side of the multiple floating gates. The formation of the stepped opening utilizes the inherent phase difference of a photolithography machine, the multiple word lines located on the same side of the multiple floating gates can reduce the complexity of circuit design, reduce the occupied area of the flash memory cell structure, and is beneficial to improving the integration of the memory device.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor device manufacturing, and relates to a flash memory cell structure and a manufacturing method thereof. BACKGROUND

[0002] Flash memory is an important device in integrated circuit products, which can keep the stored information for a long time without voltage, has high integration, fast access speed and easy erasing, and is widely used.

[0003] The commonly used design structure of the flash memory cell currently comprises two sub-structure units in each group, and the whole is left-right symmetrical. Since the adjacent word lines are distributed on different sides of the two sub-structure units, the circuit design is troublesome, and the space is large, which is not conducive to further improving the integration of the flash memory device. SUMMARY

[0004] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a flash memory cell structure and a manufacturing method thereof, which is used to solve the problems of complex circuit design and large space occupation of the flash memory cell in the prior art.

[0005] To achieve the above-mentioned purposes and other related purposes, the present application provides a manufacturing method of a flash memory cell structure, comprising the following steps:

[0006] A substrate is provided, and a gate dielectric layer, a floating gate conductive layer, a hard mask layer and a dielectric layer stack are sequentially formed on the substrate from bottom to top;

[0007] A stepped opening is formed in the dielectric layer stack, the stepped opening comprises a first trench and a second trench, the second trench extends downward from the upper surface of the dielectric layer stack, and the bottom of the second trench stays in the dielectric layer stack, the first trench extends downward from the bottom of the second trench, and the bottom of the first trench exposes the hard mask layer;

[0008] Based on the stepped opening, the dielectric layer stack, the hard mask layer and the floating gate conductive layer are etched until the bottom of the first trench exposes the gate dielectric layer and the bottom of the second trench exposes the floating gate conductive layer;

[0009] An insulating layer is formed on the surface of the floating gate conductive layer exposed by the first trench and the second trench;

[0010] The hard mask layer is removed, and the part of the floating gate conductive layer not covered by the insulating layer is removed to obtain at least one floating gate, the floating gate comprises oppositely arranged first and second side surfaces, and the first side surface and the top surface of the floating gate are covered by the insulating layer;

[0011] forming an isolation spacer on the second side of the floating gate;

[0012] forming a word line over the insulating layer, the word line further extending over the surface of the isolation spacer.

[0013] Optionally, the forming a staircase-shaped opening in the dielectric stack further comprises:

[0014] forming a photoresist layer on the dielectric stack;

[0015] using a phase difference inherent to a photoetching machine to form a photoresist opening pattern in the photoresist layer, the photoresist opening having a first sidewall and a second sidewall asymmetric to the first sidewall, an angle between the first sidewall and a bottom surface of the photoresist opening being different from an angle between the second sidewall and the bottom surface of the photoresist opening;

[0016] using the photoresist layer as an etching stop layer to etch the dielectric stack to obtain the staircase-shaped opening.

[0017] Optionally, the etching the dielectric stack, the hard mask layer and the floating gate conductive layer based on the staircase-shaped opening until the bottom of the first trench exposes the gate dielectric layer and the bottom of the second trench exposes the floating gate conductive layer further comprises:

[0018] etching the hard mask layer and the dielectric stack until the bottom surface of the first trench exposes the floating gate conductive layer and the bottom surface of the second trench exposes the hard mask layer;

[0019] etching the floating gate conductive layer and the hard mask layer until the first trench penetrates through the floating gate conductive layer and the bottom of the second trench exposes the floating gate conductive layer.

[0020] Optionally, the forming a word line over the insulating layer, the word line further extending over the surface of the isolation spacer further comprises:

[0021] forming a word line conductive layer on the substrate, the word line conductive layer covering the insulating layer and the isolation spacer;

[0022] forming a plurality of spaced-apart word line conductive layer openings in the word line conductive layer to obtain a plurality of the word lines, the word line conductive layer openings exposing the insulating layer at the portion of the first side of the floating gate but not exposing the isolation spacer.

[0023] Optionally, the step of etching the dielectric stack, the hard mask layer, and the floating gate conductive layer based on the stepped opening until the bottom of the first trench exposes the gate dielectric layer and the bottom of the second trench exposes the floating gate conductive layer further includes: further etching the gate dielectric layer until the bottom of the first trench exposes the substrate.

[0024] Optionally, the dielectric stack includes at least three dielectric layers stacked in the vertical direction, wherein in any two adjacent dielectric layers, the etching rate of the upper dielectric layer is less than the etching rate of the lower dielectric layer.

[0025] Optionally, the dielectric stack includes at least one of an undoped silicon glass layer, a borosilicate glass layer, a borosilicate phosphosilicate glass layer, and a phosphosilicate glass layer.

[0026] Optionally, the dielectric stack includes an undoped silicon oxide layer and at least two doped silicon oxide layers with different doping concentrations, or the dielectric stack includes at least three doped silicon oxide layers with different doping concentrations.

[0027] The present invention also provides a flash memory cell structure, comprising:

[0028] Substrate;

[0029] A gate dielectric layer is located on the substrate;

[0030] At least one floating gate is located on the gate dielectric layer, the floating gate including a first side surface and a second side surface disposed opposite to each other;

[0031] An insulating layer is located on the first side and top surface of the floating gate;

[0032] An isolation sidewall is located on the second side of the floating gate;

[0033] At least one line, at least a portion of which covers the surface of the isolation sidewall.

[0034] Optionally, the flash memory cell structure includes a plurality of spaced-apart floating gates and a plurality of spaced-apart word lines, wherein the plurality of word lines are located on the same side of the plurality of floating gates.

[0035] Optionally, the flash memory cell structure is fabricated using the method for fabricating a flash memory cell structure as described in any one of claims 1-8.

[0036] As described above, the flash memory cell structure and the manufacturing method thereof of the present application forms a stepped opening in the dielectric stack, and based on the stepped opening, the dielectric stack, the hard mask layer and the floating gate conductive layer are etched until the bottom of the first trench exposes the gate dielectric layer and the bottom of the second trench exposes the floating gate conductive layer, then an insulating layer is formed on the exposed surface of the floating gate conductive layer, and the part of the floating gate conductive layer not covered by the insulating layer is removed to obtain the floating gate, the first side surface and the top surface of the floating gate are covered by the insulating layer, then the isolation side wall is formed on the second side surface of the floating gate, and finally the word line is formed. In the present application, based on the photoresist plate with opening pattern and using the phase difference inherent to the photoetching machine, an asymmetric photoresist opening morphology is formed, and then combined with the etching rate control and the film layer matching of the dielectric stack, a stepped opening with inconsistent left and right depths in the dielectric stack is etched, and finally a flash memory cell structure with the word line located on the same side of the floating gate is obtained, which can reduce the complexity of circuit design and the occupied area of the flash memory cell structure, and is beneficial to improve the integration of the memory device. BRIEF DESCRIPTION OF DRAWINGS

[0037] Figure 1 A process flow chart showing the manufacturing method of the flash memory cell structure of the present application.

[0038] Figure 2 A device structure schematic diagram obtained after the step of sequentially forming the gate dielectric layer, the floating gate conductive layer, the hard mask layer and the dielectric stack on the substrate from bottom to top.

[0039] Figure 3 A device structure schematic diagram obtained after the step of forming the photoresist layer on the dielectric stack and forming at least one asymmetric photoresist opening in the photoresist layer.

[0040] Figure 4 A device structure schematic diagram showing that the fourth dielectric layer is etched completely, the third dielectric layer under the fourth dielectric layer is partially etched near one end of the first side wall, and the top surface near one end of the second side wall is just exposed.

[0041] Figure 5 A device structure schematic diagram showing that the third dielectric layer is etched completely near one end of the first side wall, and a certain thickness of the third dielectric layer near the second side wall is still not etched.

[0042] Figure 6 A device structure schematic diagram showing that the second dielectric layer is etched completely near one end of the first side wall, and the top surface near one end of the second side wall is just exposed.

[0043] Figure 7 A device structure schematic diagram showing that the first dielectric layer is etched completely near one end of the first side wall, and one end near the second side wall is still covered by the second dielectric layer.

[0044] Figure 8 A device structure schematic diagram after the step of etching the hard mask layer and the dielectric stack until the bottom surface of the first trench exposes the floating gate conductive layer and the bottom surface of the second trench exposes the hard mask layer.

[0045] Figure 9 A device structure schematic diagram after the step of etching the floating gate conductive layer and the hard mask layer until the first trench penetrates the floating gate conductive layer in the vertical direction and the bottom of the second trench exposes the floating gate conductive layer.

[0046] Figure 10 A device structure schematic diagram after the step of further removing the photoresist layer and the dielectric stack.

[0047] Figure 11 A device structure schematic diagram after the step of forming an insulating layer on the surface of the floating gate conductive layer exposed by the first trench and the second trench.

[0048] Figure 12 A device structure schematic diagram after the step of removing the hard mask layer and removing the portion of the floating gate conductive layer not shielded by the insulating layer until the gate dielectric layer is exposed to obtain at least one floating gate.

[0049] Figure 13 A device structure schematic diagram after the step of forming an isolation sidewall on the second side surface of the floating gate.

[0050] Figure 14 A device structure schematic diagram after the step of forming a word line conductive layer on the substrate.

[0051] Figure 15 A device structure schematic diagram after the step of forming a plurality of spaced-apart word line conductive layer openings in the word line conductive layer to obtain a plurality of the word lines.

[0052] Element number explanation

[0053] S1-S7 steps

[0054] 1 substrate

[0055] 2 gate dielectric layer

[0056] 3 floating gate conductive layer

[0057] 301 floating gate

[0058] 302 first side surface

[0059] 303 second side surface

[0060] 4 hard mask layer

[0061] 5 dielectric stack

[0062] 501 first dielectric layer

[0063] 502 second dielectric layer

[0064] 503 third dielectric layer

[0065] 504 fourth dielectric layer

[0066] 6 staircase opening

[0067] 601 first trench

[0068] 602 second trench

[0069] 7 photoresist layer

[0070] 701 photoresist opening

[0071] 702 first sidewall

[0072] 703 second sidewall

[0073] 8 insulating layer

[0074] 9 isolation spacer

[0075] 10 word line conductive layer

[0076] 11 word line DETAILED DESCRIPTION

[0077] The present application is herein described, by way of example only, with reference to the accompanying drawings, wherein:

[0078] Reference will now be made to the drawings, wherein: Figures 1 to 15 It is to be understood that the above-mentioned arrangement is merely an example of the basic concept of the present application, therefore, shown components in the drawings should not be construed to limit the number, shape and size of components in actual implementation, and the type, number and proportion of components in actual implementation can be arbitrarily changed, and the component layout type can also be more complex.

[0079] Embodiment 1

[0080] In this embodiment, a method for manufacturing a flash memory cell structure is provided, please refer to Figure 1, shown as a process flow diagram of the method, comprising the following steps:

[0081] S1: providing a substrate, and sequentially forming a gate dielectric layer, a floating gate conductive layer, a hard mask layer and a dielectric stack on the substrate from bottom to top;

[0082] S2: forming a stepped opening in the dielectric stack, the stepped opening comprising a first trench and a second trench, the second trench extending downward from the upper surface of the dielectric stack and the bottom of the second trench residing in the dielectric stack, the first trench extending downward from the bottom of the second trench and the bottom of the first trench exposing the hard mask layer;

[0083] S3: etching the dielectric stack, the hard mask layer and the floating gate conductive layer based on the stepped opening until the bottom of the first trench exposes the gate dielectric layer and the bottom of the second trench exposes the floating gate conductive layer;

[0084] S4: removing the hard mask layer and removing the part of the floating gate conductive layer not covered by the insulating layer to obtain at least one floating gate, the floating gate comprising oppositely arranged first and second side surfaces, and the first side surface and the top surface of the floating gate being covered by the insulating layer;

[0085] S5: removing the hard mask layer and removing the part of the floating gate conductive layer not covered by the insulating layer to obtain at least one floating gate, the floating gate comprising oppositely arranged first and second side surfaces, and the first side surface and the top surface of the floating gate being covered by the insulating layer;

[0086] S6: forming an isolation side wall on the second side surface of the floating gate;

[0087] S7: forming a word line covering the insulating layer, the word line also extending to cover the surface of the isolation side wall.

[0088] First, refer to Figure 2 , the step S1 is performed: a substrate 1 is provided, and a gate dielectric layer 2, a floating gate conductive layer 3, a hard mask layer 4 and a dielectric stack 5 are sequentially formed on the substrate 1 from bottom to top.

[0089] As an example, the substrate 1 can be a silicon substrate, a germanium substrate, a germanium-silicon substrate, a silicon carbide substrate, a III-V compound substrate or other suitable semiconductor substrate. The gate dielectric layer 2 can be silicon dioxide or other suitable material, the floating gate conductive layer 3 can be conductive polysilicon or other suitable material, and the hard mask layer 4 can be silicon nitride or other suitable material. The dielectric stack 5 comprises multiple layers of dielectric layers stacked in the vertical direction, and the material of the dielectric layers includes but is not limited to silicon oxide.

[0090] Please refer to Figures 3 to 7 , the step S2 is performed: forming a stepped opening 6 in the dielectric stack 5, the stepped opening 6 includes a first trench 601 and a second trench 602, the second trench 602 extends downward from the dielectric stack 5 upper surface, and the bottom of the second trench 602 stays in the dielectric stack 5, the first trench 601 extends downward from the bottom of the second trench 602, and the bottom of the first trench 601 exposes the hard mask layer 4.

[0091] As an example, as shown in Figure 3 , first, a photoresist layer 7 is formed on the dielectric stack 5 by spin coating or other suitable methods, then a photoresist opening pattern is prepared in the photoresist layer 7 based on a photoetching plate with an opening pattern and using the phase difference inherent to the photoetching machine during photoetching, the photoresist opening 701 has a first sidewall 702 arranged oppositely and a second sidewall 703 asymmetric to the first sidewall 702, the included angle between the first sidewall 702 and the bottom surface of the photoresist opening 701 is different from the included angle between the second sidewall 703 and the bottom surface of the photoresist opening 701.

[0092] It should be noted that the thickness of the photoresist layer 7 needs to meet the requirement that after the subsequent floating gate conductive layer etching is completed (when the bottom of the first trench 601 exposes the gate dielectric layer 2), the photoresist layer still remains on the dielectric bottom layer 5.

[0093] Specifically, the optical projection imaging system (lens system) of the photoresist machine has a kind of aberration (COMA) that can cause the inclination degree of left and right sides of the photoresist image formed is not the same, COMA can be controlled by optical design, but for the COMA of the optical system formed basically maintains constant.

[0094] Specifically, the asymmetry refers to the included angle α between the first sidewall 702 and the bottom surface of the photoresist opening 701 is greater than the included angle β between the second sidewall 703 and the bottom surface of the photoresist opening 701, for example, α is an obtuse angle, and β is a right angle. Of course, in other embodiments, α and β can also be obtuse angles.

[0095] As an example, as shown in Figures 4 to 7 , the dielectric stack 5 is etched with the photoresist layer 7 as an etching barrier layer to obtain the stepped opening 6. In this embodiment, the dry etching is used to form the stepped opening 6 in the dielectric stack 5, because the dry etching has anisotropy, which is beneficial to obtain vertical trench sidewalls, while the wet etching is generally isotropic etching, and the final trench sidewalls have a certain degree of inclination, which is not vertical.

[0096] Specifically, since the first sidewall 702 of the photoresist opening 701 has a larger inclination, the etching rate of the material close to the first sidewall 702 is faster, and the etching rate of the material close to the second sidewall 703 is slower, so that the first trench 601 and the second trench 602 with bottoms not in the same plane can be finally obtained, wherein the bottom of the first trench 601 is lower than the bottom of the second trench 602.

[0097] It should be noted that, by using an asymmetric photoresist opening morphology and a specific etching menu, although a ladder-shaped opening with different depths on both sides can be etched, the depth difference is limited for a single medium layer. In order to expand the difference to realize the final single-side etching (such as subsequent Figure 8 As shown in the figure, in the embodiment, the medium stack 5 is selected to be a multi-layer medium, and the etching rate of the medium layer in the upper layer is less than that of the medium layer in the lower layer, that is, the etching rate is from slow to fast from top to bottom. In order to obtain a stable and controllable critical dimension (CD) to obtain a sufficient process window, the number of medium layers of the medium stack 5 is at least three. In the embodiment, the medium stack 5 is taken as an example of four layers, which are a first medium layer 501, a second medium layer 502, a third medium layer 503, and a fourth medium layer 504 from bottom to top.

[0098] In the embodiment, the medium stack 5 preferably adopts silicon oxide materials, which have many types, are easy to make and remove, for example, the medium stack 5 can include at least one of an undoped silicon glass layer, a boron-silicon glass layer, a boron-phosphorus-silicon glass layer, and a phosphorus-silicon glass layer. In other embodiments, the medium stack 5 can also include non-silicon oxide materials, but the removal difficulty is higher than that of silicon oxide materials.

[0099] As an example, the medium stack 5 can include an undoped silicon oxide layer and at least two layers of doped silicon oxide layers with different doping concentrations, or the medium stack includes at least three layers of doped silicon oxide layers with different doping concentrations. For example, boron-doped or phosphorus-doped silicon oxide layers can be deposited by chemical vapor deposition, and the doping concentration is sequentially changed to obtain multiple layers of doped silicon oxide layers with different doping concentrations, so that the preparation of multiple layers of medium layers with different etching rates is realized by a simple process.

[0100] As an example, the dry etching used to form the stepped opening 6 includes a gas combination of C4F6, O2 and Ar, or a gas combination of C4F8, O2 and Ar. For this etching menu, the dielectric stack 5 includes, from top to bottom, an undoped silicon glass layer, a boron silicon glass layer, a boron phosphorus silicon glass layer and a phosphorus silicon glass layer. In other embodiments, the etching menu and the film layers of the dielectric stack 5 can also be adjusted as needed, as long as the etching rate of the upper dielectric layer is less than the etching rate of the lower dielectric layer under this etching menu. This should not be considered as limiting the scope of the present application.

[0101] As an example, Figures 4 to 7 The four stages of forming the stepped opening 6 are shown respectively, wherein, Figure 4 In the fourth stage, the fourth dielectric layer 504 is etched completely, and the third dielectric layer 503 under the fourth dielectric layer 504 is partially etched near one end of the first sidewall 402, and the top surface near one end of the second sidewall 403 is just exposed; Figure 5 In the third stage, the third dielectric layer 503 is etched completely near one end of the first sidewall 402, and a certain thickness of the third dielectric layer 503 near one end of the second sidewall 403 remains unetched; Figure 6 In the second stage, the second dielectric layer 502 is etched completely near one end of the first sidewall 402, and the top surface near one end of the second sidewall 403 is just exposed; Figure 7 In the first stage, the first dielectric layer 501 is etched completely near one end of the first sidewall 402, and one end of the second sidewall 403 is still covered by the second dielectric layer 502. As can be seen, the depth difference between the left and right sides of the trench gradually increases as the etching progresses, and finally the stepped opening 6 as shown in Figure 7 is obtained.

[0102] It should be noted that in the process of etching each dielectric layer of the dielectric stack 5, the photoresist layer 7 is also etched and thinned, but not completely etched.

[0103] Referring to Figure 8 and Figure 9 , the step S3 of etching the dielectric stack 5, the hard mask layer 4 and the floating gate conductive layer 3 based on the stepped opening 6 until the bottom of the first trench 601 exposes the gate dielectric layer 2 and the bottom of the second trench 602 exposes the floating gate conductive layer 3 is performed.

[0104] Specifically, as shown in Figure 8 , the hard mask layer 4 and the dielectric stack 5 are etched until the bottom of the first trench 601 exposes the floating gate conductive layer 3 and the bottom of the second trench 602 exposes the hard mask layer 4; as shown in Figure 9As shown, the floating gate conductive layer 3 and the hard mask layer 4 are etched until the first trench 601 penetrates the floating gate conductive layer 3 in the vertical direction, and the bottom of the second trench 602 exposes the floating gate conductive layer 3.

[0105] Specifically, the selection ratio of the etching menu, i.e., the etching rate of different materials, is adjusted so that the floating gate conductive layer 3 is etched to the gate dielectric layer 2, and the hard mask layer 4 is also etched completely. Among them, Figure 9 As shown, the bottom of the second trench 602 just exposes the floating gate conductive layer 3, but in actual etching, the surface of the floating gate conductive layer 3 in the area where the second trench 602 is located may be etched a little.

[0106] It should be noted that in the above process of etching the dielectric layer 5, the hard mask layer 4 and the floating gate conductive layer 3 until the bottom of the first trench 601 exposes the gate dielectric layer 2, and the bottom of the second trench 602 exposes the floating gate conductive layer 3, the photoresist layer 7 is also etched to reduce the thickness, but not etched completely.

[0107] Specifically, please refer to Figure 10 , the photoresist layer 6 and the dielectric layer 5 are further removed, wherein when the dielectric layer 5 adopts silicon oxide material and the gate dielectric layer 2 selects silicon oxide (such as thermal silicon oxide), by adjusting the acid ratio in the etching solution so that the etching rate of the etching solution to the gate dielectric layer 2 is less than that to the dielectric layer 5, the dielectric layer 5 on the top can be finally removed, while the gate dielectric layer 2 at the bottom is left, at this time, the bottom of the first trench 601 still exposes the gate dielectric layer 2. Of course, in other embodiments, the dielectric layer 5 can also be removed together with the part of the gate dielectric layer 2 not covered by the floating gate conductive layer 3 at the same time, at this time, the bottom of the first trench 601 exposes the substrate 1.

[0108] Please refer to Figure 11 , the step S4 of forming an insulating layer 8 on the surface of the floating gate conductive layer 3 exposed by the first trench 601 and the second trench 602 is performed.

[0109] As an example, the LOCOS (selective oxidation of silicon) process is used to form the insulating layer 8, wherein the LOCOS process realizes the selective oxidation of silicon with silicon nitride as a mask, and in this process, a layer of silicon oxide is grown on the surface of the floating gate conductive layer 3 not covered by the hard mask layer 4.

[0110] Please refer to Figure 12, the step S5 is performed: removing the hard mask layer 4, and removing the part of the floating gate conductive layer 3 not covered by the insulating layer 8 until the gate dielectric layer 2 is exposed to obtain at least one floating gate 301, the floating gate 301 comprising oppositely arranged first side surface 302 and second side surface 303, and the first side surface 302 and top surface of the floating gate 301 are covered by the insulating layer 8.

[0111] As an example, the number of the floating gates 301 is plural, and the plural floating gates 301 are arranged in horizontal direction with intervals.

[0112] Referring back to Figure 13 , the step S6 is performed: forming an isolation side wall 9 on the second side surface 303 of the floating gate 301 by thermal oxidation or other suitable process to protect the second side surface 303 of the floating gate 301.

[0113] Referring back to Figure 14 and Figure 15 , the step S7 is performed: forming a word line 11 covering the insulating layer 8, the word line 11 also extending to cover the surface of the isolation side wall 9.

[0114] Specifically, as shown in Figure 14 , a word line conductive layer 10 is formed on the substrate 1, the word line conductive layer 10 covering the insulating layer 8 and the isolation side wall 9; as shown in Figure 15 , a plurality of spaced-apart word line conductive layer openings are formed in the word line conductive layer 10 to obtain a plurality of word lines 11, the word line conductive layer openings exposing the part of the insulating layer 8 located at the first side surface 302 of the floating gate 301, but not exposing the isolation side wall 9, so that the plurality of word lines 11 are respectively located at the same side of the plurality of floating gates 301.

[0115] As an example, the two sides of the word line 11 respectively extend to the surface of the insulating layer 8 at the top of the floating gate 301 and the surface of the gate dielectric layer 2.

[0116] Thus, a flash memory cell structure is produced. The production method of the flash memory cell structure of the present embodiment is based on a photoetching plate with an opening pattern and uses the inherent phase difference of a photoetching machine to form an asymmetric photoresist opening topography in a photoresist layer. Then, in combination with etching rate control and the film layer matching of the dielectric stack, a stepped opening with inconsistent left and right depths is etched in the dielectric stack. Based on the stepped opening, the dielectric stack, the hard mask layer and the floating gate conductive layer are etched until the bottom of the first trench exposes the gate dielectric layer and the bottom of the second trench exposes the floating gate conductive layer. Then, an insulating layer is formed on the exposed surface of the floating gate conductive layer, and the part of the floating gate conductive layer that is not covered by the insulating layer is removed to obtain at least one floating gate. The first side surface and the top surface of the floating gate are covered by the insulating layer. Then, an isolation side wall is formed on the second side surface of the floating gate. Finally, a word line is formed. When the number of floating gates is multiple, multiple word lines are arranged in the horizontal direction and located on the same side of the multiple floating gates. This can reduce the complexity of circuit design and the occupied area of the flash memory cell structure, and is beneficial to improving the integration of the memory device.

[0117] Embodiment Two

[0118] In the present embodiment, a flash memory cell structure is provided. Referring to Figure 15 , which shows a schematic diagram of the flash memory cell structure, the flash memory cell structure includes a substrate 1, a gate dielectric layer 2, at least one floating gate 301, an insulating layer 8, an isolation side wall 9, and at least one word line 11. The gate dielectric layer 2 is located on the substrate 1. The floating gate 301 is located on the gate dielectric layer 2. The floating gate 301 includes a first side surface 302 and a second side surface 303 arranged opposite to each other. The insulating layer 8 is located on the first side surface 302 and the top surface of the floating gate 301. The isolation side wall 9 is located on the second side surface 303 of the floating gate 301. At least a part of the word line 11 covers the surface of the isolation side wall 9.

[0119] For example, the flash memory cell structure includes multiple floating gates 301 arranged in intervals and multiple word lines 11 arranged in intervals. The multiple word lines 11 are respectively located on the same side of the multiple floating gates 301.

[0120] For example, the flash memory cell structure is produced by the production method of the flash memory cell structure described in Embodiment One.

[0121] In summary, the flash memory cell structure and the manufacturing method thereof form a stepped opening in the dielectric stack, and based on the stepped opening, the dielectric stack, the hard mask layer and the floating gate conductive layer are etched until the bottom of the first trench exposes the gate dielectric layer and the bottom of the second trench exposes the floating gate conductive layer. Then, the insulating layer is formed on the exposed surface of the floating gate conductive layer, and the part of the floating gate conductive layer not covered by the insulating layer is removed to obtain at least one floating gate. The first side surface and the top surface of the floating gate are covered by the insulating layer. Then, the isolation side wall is formed on the second side surface of the floating gate. Finally, the word line is formed. When the number of floating gates is multiple, multiple word lines are arranged in the horizontal direction and are located on the same side of the multiple floating gates. In the present application, based on the photoresist plate with an opening pattern and the phase difference inherent in the photoetching machine, the asymmetric photoresist opening topography is formed in the photoresist layer. Then, combined with the etching rate control and the film layer matching of the dielectric stack, the stepped opening with different depths is etched in the dielectric stack. Finally, the flash memory cell structure with the word line located on the same side of the floating gate is obtained. The complexity of the circuit design is reduced, the occupied area of the flash memory cell structure is reduced, and the integration of the memory device is improved. Therefore, the present application effectively overcomes the shortcomings of the prior art and has high industrial utilization value.

[0122] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes completed by those skilled in the art without departing from the spirit and technical idea disclosed by the present application should be covered by the claims of the present application.

Claims

1. A method of fabricating a flash memory cell structure, comprising: The method comprises the following steps: providing a substrate, sequentially forming a gate dielectric layer, a floating gate conductive layer, a hard mask layer and a dielectric stack on the substrate from bottom to top; forming a stepped opening in the dielectric stack, the stepped opening comprising a first trench and a second trench, the second trench extending downward from the upper surface of the dielectric stack and the bottom of the second trench being located in the dielectric stack, the first trench extending downward from the bottom of the second trench and the bottom of the first trench exposing the hard mask layer; etching the dielectric stack, the hard mask layer and the floating gate conductive layer based on the stepped opening until the bottom of the first trench exposes the gate dielectric layer and the bottom of the second trench exposes the floating gate conductive layer; forming an insulating layer on the surface of the floating gate conductive layer exposed by the first trench and the second trench; removing the hard mask layer and removing the part of the floating gate conductive layer not covered by the insulating layer to obtain at least one floating gate, the floating gate comprising oppositely arranged first and second side surfaces, and the first side surface and the top surface of the floating gate being covered by the insulating layer; forming an isolation side wall on the second side surface of the floating gate; forming a word line covering the insulating layer, the word line also extending to cover the surface of the isolation side wall.

2. The method of claim 1, wherein The method further comprises the following steps: forming a photoresist layer on the dielectric stack; using the phase difference inherent to the photoetching machine to prepare a photoresist opening pattern in the photoresist layer, the photoresist opening having a first sidewall and a second sidewall asymmetric to the first sidewall, the angle between the first sidewall and the bottom surface of the photoresist opening being different from the angle between the second sidewall and the bottom surface of the photoresist opening; using the photoresist layer as an etching stop layer to etch the dielectric stack to obtain the stepped opening.

3. The method of claim 1, wherein The method further comprises the following steps: etching the hard mask layer and the dielectric stack until the bottom surface of the first trench exposes the floating gate conductive layer and the bottom surface of the second trench exposes the hard mask layer; etching the floating gate conductive layer and the hard mask layer until the first trench penetrates through the floating gate conductive layer and the bottom of the second trench exposes the floating gate conductive layer.

4. The method of claim 1, wherein The method further comprises the following steps: forming a word line conductive layer on the substrate, the word line conductive layer covering the insulating layer and the isolation side wall; forming a plurality of spaced-apart word line conductive layer openings in the word line conductive layer to obtain a plurality of word lines, the word line conductive layer openings exposing the part of the insulating layer located on the first side surface of the floating gate but not exposing the isolation side wall.

5. The method of claim 1, wherein The etching the dielectric layer stack, the hard mask layer and the floating gate conductive layer based on the stepped opening until the bottom of the first trench exposes the gate dielectric layer and the bottom of the second trench exposes the floating gate conductive layer further comprises: etching the gate dielectric layer further until the bottom of the first trench exposes the substrate.

6. The method of claim 1, wherein: The dielectric layer stack comprises at least three dielectric layers stacked in a vertical direction, and the etching rate of the dielectric layer in the upper layer is less than the etching rate of the dielectric layer in the lower layer.

7. The method of claim 1, wherein: The dielectric layer stack comprises at least one of an undoped silicon glass layer, a boron silicon glass layer, a boron phosphorus silicon glass layer and a phosphorus silicon glass layer.

8. The method of claim 1, wherein: The dielectric layer stack comprises an undoped silicon oxide layer and at least two doped silicon oxide layers with different doping concentrations, or the dielectric layer stack comprises at least three doped silicon oxide layers with different doping concentrations.

9. A flash memory cell structure, comprising: The method comprises: a substrate; a gate dielectric layer on the substrate; at least one floating gate on the gate dielectric layer, the floating gate comprising a first side and a second side arranged oppositely; an insulating layer on the first side and the top surface of the floating gate; an isolation side wall on the second side of the floating gate; at least one word line, at least a portion of the word line covering the surface of the isolation side wall; wherein the flash memory cell structure comprises a plurality of floating gates arranged at intervals and a plurality of word lines arranged at intervals, and the plurality of word lines are arranged on the same side of the plurality of floating gates respectively.

10. The flash memory cell structure of claim 9, wherein: The flash memory cell structure is obtained by using the method for manufacturing the flash memory cell structure according to any one of claims 1-8. The dielectric layer stack comprises at least three dielectric layers stacked in a vertical direction, and the etching rate of the dielectric layer in the upper layer is less than the etching rate of the dielectric layer in the lower layer. The dielectric layer stack comprises at least one of an undoped silicon glass layer, a boron silicon glass layer, a boron phosphorus silicon glass layer and a phosphorus silicon glass layer. The dielectric layer stack comprises an undoped silicon oxide layer and at least two doped silicon oxide layers with different doping concentrations, or the dielectric layer stack comprises at least three doped silicon oxide layers with different doping concentrations. The method comprises: a substrate; a gate dielectric layer on the substrate; at least one floating gate on the gate dielectric layer, the floating gate comprising a first side and a second side arranged oppositely; an insulating layer on the first side and the top surface of the floating gate; an isolation side wall on the second side of the floating gate; at least one word line, at least a portion of the word line covering the surface of the isolation side wall; wherein the flash memory cell structure comprises a plurality of floating gates arranged at intervals and a plurality of word lines arranged at intervals, and the plurality of word lines are arranged on the same side of the plurality of floating gates respectively. The flash memory cell structure is obtained by using the method for manufacturing the flash memory cell structure according to any one of claims 1-8.

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