Semiconductor device and manufacturing method thereof

Abstract

An embodiment of the present application discloses a semiconductor device and a manufacturing method thereof. The semiconductor device may include a substrate, a gate, a second dielectric layer, and a field plate, wherein the substrate has a first dielectric layer, the thickness of the first dielectric layer in a first region is greater than the thickness of a second region outside the first region, the gate is located on the substrate and in the first region, the gate includes a first gate structure and a second gate structure connected in a direction perpendicular to the substrate surface, the first gate structure penetrates the first dielectric layer in a direction perpendicular to the substrate surface, the second gate structure is formed on a side of the first dielectric layer away from the substrate and covers a portion of the first dielectric layer, the second dielectric layer covers the gate and the first dielectric layer, the field plate is located on the second dielectric layer and exists in the first region and the second region at the same time, so that the capacitance between the second gate structure and the drain is reduced, and the capacitance between the field plate and the channel is increased, so that the parasitic capacitance of the device is reduced and the gain characteristics of the device at high frequencies are improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor device and a manufacturing method thereof. Background Art

[0002] In some applications, RF devices require excellent gain characteristics at high frequencies. For example, third-generation compound semiconductor materials, such as gallium nitride (GaN) and silicon carbide (SiC), have attracted widespread attention due to their excellent material properties. GaN-based devices are widely used in the RF device field due to their high mobility, strong breakdown resistance, and excellent heat dissipation. However, GaN-based RF devices have high requirements for high-frequency gain characteristics.

[0003] The gain characteristics of RF devices at high frequencies primarily depend on whether their parasitic capacitance can be efficiently and quickly charged and discharged with the signal under high-frequency operating conditions. Therefore, without changing other design structures of the RF device, the gain characteristics of the RF device at high frequencies can be effectively improved by reducing the value of the parasitic capacitance. Currently, the parasitic capacitance of RF devices can be adjusted by changing the thickness or dielectric constant of the dielectric layer. However, this adjustment method is prone to other negative effects, such as electrostatic breakdown. Summary of the Invention

[0004] In view of this, an embodiment of the present application provides a semiconductor device and a method for manufacturing the same, which reduces the parasitic capacitance of the radio frequency device by adjusting the structure of the semiconductor device, thereby improving the gain characteristics of the radio frequency device at high frequencies.

[0005] According to a first aspect of an embodiment of the present application, a semiconductor device is provided, including a substrate, a gate, a second dielectric layer, and a field plate. The substrate includes a first dielectric layer, wherein the thickness of the first dielectric layer in a first region is greater than the thickness of a second region outside the first region. The gate is located on the substrate and in the first region. The gate includes a first gate structure and a second gate structure connected in a direction perpendicular to the substrate surface. The first gate structure extends through the first dielectric layer in a direction perpendicular to the substrate surface. The second gate structure is formed on a side of the first dielectric layer away from the substrate and covers a portion of the first dielectric layer. The second dielectric layer covers the gate and the first dielectric layer. The field plate is located on the second dielectric layer and exists in both the first and second regions. Thus, compared to a first dielectric layer with uniform thickness, the capacitance between the second gate structure and the drain is reduced due to the greater thickness of the first dielectric layer in the first region, while the capacitance between the field plate and the channel is increased due to the lesser thickness of the first dielectric layer in the second region. This reduces the parasitic capacitance of the semiconductor device and improves the gain characteristics of the semiconductor device at high frequencies. In addition, this design can also readjust the electric field stress within the device. Since the first dielectric layer has a greater thickness in the first region, the electric field spike at the second gate structure is weakened, thereby improving the overall robustness of the device.

[0006] In some possible embodiments, the semiconductor device further includes a source and a drain located in the substrate; the gate is located between the source and the drain, the field plate is opposite to the portion of the gate facing the drain in a direction perpendicular to the surface of the substrate and extends toward the drain, and the portion of the field plate located in the second region is electrically connected to the source.

[0007] In an embodiment of the present application, the semiconductor device may further include a source and a drain, and the field plate may be connected to the source and extend toward the drain, thereby modulating the electric field and capacitance distribution between the source and the drain, thereby achieving a specific high-frequency gain index.

[0008] In some possible implementations, the first dielectric layer includes a first sub-film layer and a second sub-film layer;

[0009] The first sub-membrane layer covers the substrate, and the second sub-membrane layer is located in a first area on the first sub-membrane layer; or, the first sub-membrane layer is located on the substrate and in a first area, and the second sub-membrane layer covers the first sub-membrane layer and the substrate in a second area outside the first sub-membrane layer.

[0010] In an embodiment of the present application, the first dielectric layer may include a multilayer structure, and the multilayer structure is thicker in the first region, so that the thickness of the first dielectric layer in the first region is greater than the thickness in the second region, thereby reducing the parasitic capacitance of the semiconductor device and improving the gain characteristics of the semiconductor device at high frequencies.

[0011] In some possible implementations, a material of at least one of the first sub-film layer and the second sub-film layer is at least one of silicon nitride, silicon oxynitride, silicon oxide, aluminum oxide, and titanium oxide.

[0012] In the embodiment of the present application, the materials of the first sub-film layer and the second sub-film layer can be set to better control the dielectric constant of the first dielectric layer.

[0013] In some possible embodiments, the substrate includes a base and an epitaxial layer, the epitaxial layer is arranged toward the gate, the material of the base is one or more of gallium nitride, aluminum nitride, silicon, silicon carbide, and sapphire, and the epitaxial layer includes one or more of gallium nitride, aluminum gallium nitride, indium aluminum nitride, aluminum nitride, and scandium aluminum nitride.

[0014] In an embodiment of the present application, the substrate may include a base and an epitaxial layer, and the epitaxial layer may serve as a functional layer to enable the semiconductor device to have personalized functions.

[0015] In some possible implementations, the gate and / or the field plate are made of at least one of nickel, titanium, aluminum, palladium, platinum, gold, titanium nitride, tantalum nitride, and copper.

[0016] In the embodiment of the present application, the materials of the gate and the field plate can be set to achieve better conductivity of the gate and the field plate.

[0017] In some possible implementations, a material of the second dielectric layer is at least one of silicon nitride, silicon oxynitride, silicon oxide, aluminum oxide, and titanium oxide.

[0018] In the embodiment of the present application, the material of the second dielectric layer can be set to achieve better insulation of the second dielectric layer.

[0019] According to a second aspect of the present application, a method for manufacturing a semiconductor device is provided, comprising:

[0020] providing a substrate;

[0021] A first dielectric layer and a gate are formed on the substrate, wherein the gate is located on the substrate and in the first region; the thickness of the first dielectric layer in the first region is greater than the thickness of the second region outside the first region; the gate includes a first gate structure and a second gate structure connected in a direction perpendicular to the substrate surface, the first gate structure penetrates the first dielectric layer in a direction perpendicular to the substrate surface, and the second gate structure is formed on a side of the first dielectric layer away from the substrate and covers a portion of the first dielectric layer;

[0022] forming a second dielectric layer covering the gate and the first dielectric layer;

[0023] A field plate is formed on the second dielectric layer; the field plate exists in both the first region and the second region.

[0024] In some possible embodiments, a source and a drain are further formed in the substrate; the gate is located between the source and the drain, the field plate is opposite to the portion of the gate facing the drain in a direction perpendicular to the substrate surface and extends toward the drain, and the portion of the field plate located in the second region is electrically connected to the source.

[0025] In some possible implementations, the first dielectric layer includes a first sub-film layer and a second sub-film layer, and forming the first dielectric layer and the gate on the substrate includes:

[0026] forming the first sub-film layer and the second sub-material layer in sequence on the substrate;

[0027] Etching the second sub-material layer and the first sub-material layer in the first region to obtain a first through hole;

[0028] forming a first gate structure located inside the first through hole, and a second gate structure connected to the first gate structure and covering a portion of the first dielectric layer;

[0029] The second sub-material layer outside the second gate structure is removed by etching using the second gate structure, and the second sub-material layer located in the first region serves as the second sub-film layer.

[0030] In the embodiment of the present application, the first sub-film layer can be used as an etch stop layer, and the second gate structure can be used as a hard self-aligned mask to etch the second sub-material layer without adding a sequential photolithography process, which can save costs.

[0031] In some possible implementations, forming a first dielectric layer and a gate on the substrate includes:

[0032] forming a first dielectric material layer on the substrate;

[0033] Etching the first dielectric material layer in the first region to obtain a second through hole;

[0034] forming a first gate structure located inside the second through hole, and a second gate structure connected to the first gate structure and covering a portion of the first dielectric layer;

[0035] The first dielectric material layer in the second area outside the first area is thinned to form a first dielectric layer.

[0036] In the embodiment of the present application, the second sub-material layer can be etched using the second gate structure as a hard self-aligned mask without adding a sequential photolithography process, which can save costs.

[0037] In some possible implementations, the first dielectric layer includes a first sub-film layer and a second sub-film layer, and forming the first dielectric layer and the gate on the substrate includes:

[0038] forming a first sub-material layer on the substrate;

[0039] removing the first sub-material layer in the second area outside the first area, and using the first sub-material layer in the first area as the first sub-film layer;

[0040] forming a second sub-film layer covering the first sub-film layer and the substrate;

[0041] Etching the second sub-film layer and the first sub-film layer in the first region to obtain a third through hole;

[0042] A first gate structure is formed inside the third through hole, and a second gate structure is formed which is connected to the first gate structure and covers a portion of the first dielectric layer.

[0043] In the embodiment of the present application, the first sub-film layer in the first area can be formed first, and then covered with the second sub-film layer, which is conducive to obtaining a flat second sub-film layer.

[0044] In some possible implementations, the first dielectric layer includes a first sub-film layer and a second sub-film layer, and forming the first dielectric layer and the gate on the substrate includes:

[0045] forming a first sub-film layer in a first area on the substrate using a double-layer photoresist patterning process;

[0046] forming a second sub-film layer covering the first sub-film layer and the substrate;

[0047] Etching the second sub-film layer and the first sub-film layer in the first region to obtain a third through hole;

[0048] A first gate structure is formed inside the third through hole, and a second gate structure is formed which is connected to the first gate structure and covers a portion of the first dielectric layer.

[0049] In the embodiment of the present application, the first sub-film layer may be formed first, and then the second sub-film layer located in the first region on the first sub-film layer may be formed, which is beneficial for obtaining the second sub-film layer accurately located under the second gate structure.

[0050] In some possible implementations, the material of the first sub-film layer and / or the second sub-film layer is at least one of silicon nitride, silicon oxynitride, silicon oxide, aluminum oxide, and titanium oxide.

[0051] In some possible embodiments, the substrate includes a base and an epitaxial layer, the material of the base is one or more of gallium nitride, aluminum nitride, silicon, silicon carbide, and sapphire, and the epitaxial layer includes one or more of gallium nitride, aluminum gallium nitride, indium aluminum nitride, aluminum nitride, and scandium aluminum nitride.

[0052] In some possible implementations, the gate and / or the field plate are made of at least one of nickel, titanium, aluminum, palladium, platinum, gold, titanium nitride, tantalum nitride, and copper.

[0053] In some possible implementations, a material of the second dielectric layer is at least one of silicon nitride, silicon oxynitride, silicon oxide, aluminum oxide, and titanium oxide.

[0054] In a third aspect of an embodiment of the present application, an electronic device is provided, comprising a circuit board, and a semiconductor device provided in the first aspect of the present application and connected to the circuit board.

[0055] It can be seen from the above technical solutions that the embodiments of the present application have the following advantages:

[0056] Embodiments of the present application provide a semiconductor device and a method for manufacturing the same. The semiconductor device may include a substrate, a gate, a second dielectric layer, and a field plate. The substrate includes a first dielectric layer, wherein the thickness of the first dielectric layer in a first region is greater than the thickness of a second region outside the first region. The gate is located on the substrate and in the first region. The gate includes a first gate structure and a second gate structure connected in a direction perpendicular to the substrate surface. The first gate structure extends through the first dielectric layer in a direction perpendicular to the substrate surface. The second gate structure is formed on a side of the first dielectric layer away from the substrate and covers a portion of the first dielectric layer. The second dielectric layer covers the gate and the first dielectric layer. The field plate is located on the second dielectric layer and exists in both the first and second regions. In this way, compared to a first dielectric layer with uniform thickness, the capacitance between the second gate structure and the drain is reduced due to the greater thickness of the first dielectric layer in the first region, while the capacitance between the field plate and the channel is increased due to the lesser thickness of the first dielectric layer in the second region. This reduces the parasitic capacitance of the semiconductor device and improves the gain characteristics of the semiconductor device at high frequencies. In addition, this design can also readjust the electric field stress within the device. Due to the greater thickness of the first dielectric layer in the first region, the electric field spike at the second gate structure is weakened, thereby improving the overall robustness of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] In order to clearly understand the specific embodiments of the present application, the following briefly describes the drawings used in describing the specific embodiments of the present application. Obviously, these drawings are only partial embodiments of the present application.

[0058] Figure 1A schematic structural diagram of a radio frequency device provided in an embodiment of the present application;

[0059] Figure 2 A schematic diagram of a transverse electric field stress distribution provided in an embodiment of the present application;

[0060] Figure 3A 、 3B 3C is a schematic structural diagram of a semiconductor device provided in an embodiment of the present application;

[0061] Figure 4 Another schematic diagram of transverse electric field stress distribution provided in an embodiment of the present application;

[0062] Figure 5 A flowchart of a method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0063] Figure 6-Figure 23 Schematic diagram of the device structure during the manufacturing process of the semiconductor device in the embodiment of the present application. DETAILED DESCRIPTION

[0064] An embodiment of the present application provides a semiconductor device and a method for manufacturing the same, which reduces the parasitic capacitance of a radio frequency device by adjusting the structure of the semiconductor device, thereby improving the gain characteristics of the radio frequency device at high frequencies.

[0065] The terms "first," "second," "third," "fourth," and the like (if any) in the specification and claims of this application and in the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or sequential sequence. It should be understood that the terms used in this manner are interchangeable where appropriate so that the embodiments described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "including" and "having," and any variations thereof, are intended to cover non-exclusive inclusions, e.g., a process, method, system, product, or apparatus comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0066] This application is described in detail with reference to schematic diagrams. When describing the embodiments of this application, for ease of explanation, cross-sectional views of device structures may be partially enlarged and not to scale. Furthermore, these schematic diagrams are merely illustrative and should not limit the scope of protection of this application. Furthermore, in actual production, three-dimensional dimensions, including length, width, and depth, should be included.

[0067] Currently, in some scenarios, RF devices are required to have good gain characteristics at high frequencies. The gain characteristics of RF devices at high frequencies mainly depend on whether the parasitic capacitance of the RF devices can efficiently and quickly replay the signal under high-frequency working conditions. Therefore, without changing other design structures of the RF devices, the gain characteristics of the RF devices at high frequencies can be effectively improved by reducing the capacitance of the parasitic capacitance.

[0068] refer to Figure 1 As shown, a structural schematic diagram of a radio frequency device provided in an embodiment of the present application includes a substrate 100, a first dielectric layer 210 on the substrate 100, a gate 220 that penetrates the first dielectric layer 210 and covers a portion of the first dielectric layer 210, a second dielectric layer 230 that covers the gate 220 and the first dielectric layer 210, and a field plate 240 located on the second dielectric layer 230. The substrate 100 includes a source 101 and a drain 102. The field plate 240 is located on the side of the gate 220 facing the drain 102 and extends above the gate 220. The field plate 240 is connected to the source 101. Factors that determine the parasitic capacitance of the RF device include the parasitic capacitance C1 between the bottom of the gate 220 and the drain 102, the parasitic capacitance C2 between the portion of the gate 220 located above the first dielectric layer 210 and the drain 102, and the capacitance C3 between the field plate 204 and the channel below the gate 220. In order to reduce the overall parasitic capacitance of the RF device, it is necessary to reduce C1 and C2 and increase C3. The parasitic capacitances C1, C2, and C3 can be adjusted by changing the thickness or dielectric constant of the dielectric layer. However, the inventors have found through research that this adjustment method is prone to produce other negative effects, such as causing electrostatic breakdown.

[0069] Specifically, increasing the thickness of the first dielectric layer 210 and lowering its dielectric constant can reduce the parasitic capacitance C2 between the portion of the gate 220 located above the first dielectric layer 210 and the drain 102, while also reducing the parasitic capacitance C3 between the field plate 240 and the channel. However, this does not reduce the overall parasitic capacitance of the device. Reducing the thickness of the second dielectric layer 230 and increasing its dielectric constant can increase the parasitic capacitance C3 between the field plate 240 and the channel, but can also degrade the withstand voltage characteristics between the gate 220 and the field plate 240.

[0070] refer to Figure 2As shown in FIG. 1 , a schematic diagram of a lateral electric field stress distribution provided in an embodiment of the present application is shown, wherein the abscissa is the position in the direction along the substrate surface, and the ordinate is the electric field stress at each position under a high-voltage reverse-bias stress state. The first electric field peak may correspond to the end of the gate bottom close to the drain 102, the second electric field peak may correspond to the end of the gate above the first dielectric layer 210 close to the drain 102, and the third electric field peak may correspond to the end of the field plate 140 close to the drain 102. As can be seen from the figure, the second electric field peak is the highest. Therefore, under continuous high electric field stress, if the thickness of the first dielectric layer 210 is small, the first dielectric layer 110 below the gate at the position corresponding to the electric field peak is prone to time-dependent dielectric breakdown (TDDB), which poses a high reliability risk. Therefore, it is necessary to reduce C2 to improve the reliability of the device.

[0071] Based on the above technical problems, embodiments of the present application provide a semiconductor device and a manufacturing method thereof. The semiconductor device may include a substrate, a gate, a second dielectric layer, and a field plate. The substrate includes a first dielectric layer, wherein the thickness of the first dielectric layer in a first region is greater than the thickness of a second region outside the first region. The gate is located on the substrate and in the first region. The gate includes a first gate structure and a second gate structure connected in a direction perpendicular to the substrate surface. The first gate structure extends through the first dielectric layer in a direction perpendicular to the substrate surface. The second gate structure is formed on a side of the first dielectric layer away from the substrate and covers a portion of the first dielectric layer. The second dielectric layer covers the gate and the first dielectric layer. The field plate is located on the second dielectric layer and exists in both the first and second regions. In this way, compared to a first dielectric layer with uniform thickness, the capacitance between the second gate structure and the drain is reduced due to the greater thickness of the first dielectric layer in the first region, while the capacitance between the field plate and the channel is increased due to the lesser thickness of the first dielectric layer in the second region. This reduces the parasitic capacitance of the semiconductor device and improves the gain characteristics of the semiconductor device at high frequencies. In addition, this design can also readjust the electric field stress within the device. Since the first dielectric layer has a greater thickness in the first region, the electric field spike at the second gate structure is weakened, thereby improving the overall robustness of the device.

[0072] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below with reference to the accompanying drawings.

[0073] refer to Figure 3A 、 3B 3C is a schematic structural diagram of a semiconductor device provided in an embodiment of the present application, wherein the semiconductor structure includes: a substrate 100 , a gate 120 , a first dielectric layer 110 , a second dielectric layer 130 , and a field plate 140 .

[0074] In the embodiment of the present application, the substrate 100 can be designed according to different device requirements. Specifically, the substrate 100 may include a base and an epitaxial layer, the epitaxial layer being formed on the surface of the base and arranged toward the gate 120. The base may be a semiconductor base, such as one or more of gallium nitride (GaN), aluminum nitride (AlN), silicon (Si), silicon carbide (SiC), and sapphire. The base may provide support for the semiconductor device or constitute a portion of the functional layer of the semiconductor device. The epitaxial layer may be a film layer obtained by epitaxial growth on the base, typically constituting a functional layer of the semiconductor device, such as one or more of gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium aluminum nitride (InAlN), aluminum nitride (AlN), and scandium aluminum nitride (ScAlN). The base and the epitaxial layer may have the same material or may have inconsistent materials. Among them, the silicon carbide substrate may be a single crystal structure and may have a variety of structural types, such as 4H-silicon carbide, 6H-silicon carbide, 3C-silicon carbide, etc.

[0075] For example, when the semiconductor device is a gallium nitride-based high-electron-mobility transistor (HEMT) device, the substrate can be a silicon carbide material, and the epitaxial layer can include gallium nitride and aluminum gallium nitride. The gallium nitride and aluminum gallium nitride form a heterostructure, thereby generating a two-dimensional electron gas. The formed semiconductor device can operate using the two-dimensional electron gas generated by the heterostructure. Of course, the semiconductor device in the embodiment of the present application can also be other radio frequency devices, and the substrate and epitaxial layer therein can also be designed accordingly.

[0076] A first dielectric layer 110 is provided on the substrate 100. The thickness of the first dielectric layer 110 in the first region is greater than the thickness of the second region outside the first region. The first region is the region on the substrate, including the substrate surface and the space defined by countless straight lines perpendicular to the substrate surface. The first region is the region for forming the gate, which can be the center region where the source and drain are located. The first region can be larger than the gate region or equal to the gate region. Figure 3A 、 3B As shown in FIG3C , the dotted line frame in the middle represents the first area 1001, and the dotted line frames on both sides of the first area 1001 represent the second area 1002. Figure 3A 、 3B 3C are cross-sectional views, so in fact the second region 1002 can be located on both sides of the first region 1001, or can form an annular region surrounding the first region 1001, such as a circular ring region or a polygonal ring region.

[0077] In the embodiment of the present application, the first dielectric layer 110 may be a stack of multiple films or an integrated structure of a single film, wherein a single film may include multiple materials or a single material.

[0078] Specifically, the first dielectric layer 110 may be an integral structure, and the first dielectric layer 110 in the second region outside the first region is thinned by etching, so as to have a thinner thickness. Figure 3A As shown, during the thinning process, the sidewalls at the junction of the first and second regions may not be strictly steep, and the sidewalls may be located in the first region. The first region may be equal to or slightly larger than the region where the gate 120 is located. The thickness of the first dielectric layer 110 in the first region may range from 40 to 1000 nm, and the thickness of the first dielectric layer 110 in the second region outside the first region may range from 20 to 500 nm. The material of the first dielectric layer 110 may be at least one of silicon nitride, silicon oxynitride, silicon oxide, aluminum oxide, and titanium oxide.

[0079] Specifically, the first dielectric layer 110 may include a first sub-film layer 112 and a second sub-film layer 113. Figure 3B As shown, the first sub-film layer 112 is located in a first region on the substrate 100, and the second sub-film layer 113 covers the first sub-film layer 112 and the second region of the substrate 100 outside the first sub-film layer 112. In this way, the difference between the thickness of the first dielectric layer 110 in the first region and the thickness of the second region outside the first region is the thickness of the first sub-film layer 112. Specifically, the portion of the second sub-film layer 113 covering the sidewalls of the first sub-film layer 112 can be located in the first region, thereby defining a larger thickness in the first region. The size of the first sub-film layer 112 along the substrate surface is smaller than the size of the first region along the substrate surface. In this case, the first region can be larger than the region where the gate is located. The thickness of the first sub-film layer 112 can range from 20 to 500 nm, and the material of the first sub-film layer 112 can be at least one of silicon nitride, silicon oxynitride, silicon oxide, aluminum oxide, and titanium oxide. The thickness of the second sub-film layer 113 can range from 20 to 500 nm, and the material of the second sub-film layer 113 can be at least one of silicon nitride, silicon oxynitride, silicon oxide, aluminum oxide, and titanium oxide.

[0080] Specifically, the first dielectric layer 110 may include a first sub-film layer 112 and a second sub-film layer 113. Figure 3CAs shown, the first sub-layer 112 covers the substrate 100, and the second sub-layer 113 is located in a first region above the first sub-layer 112. Thus, the difference between the thickness of the first dielectric layer 110 in the first region and the thickness of the second region outside the first region is the thickness of the second sub-layer 113. The second sub-layer 113 may have less steep sidewalls, in which case the sidewalls may be located in the first region. The thickness of the first sub-layer 112 may range from 20 to 500 nm, and the material of the first sub-layer 112 may be at least one of silicon nitride, silicon oxynitride, silicon oxide, aluminum oxide, and titanium oxide. The thickness of the second sub-layer 113 may range from 20 to 500 nm, and the material of the second sub-layer 113 may be at least one of silicon nitride, silicon oxynitride, silicon oxide, aluminum oxide, and titanium oxide.

[0081] The gate 120 is formed in the first region. The gate 120 includes a first gate structure and a second gate structure connected in a direction perpendicular to the substrate surface. The first gate structure penetrates the first dielectric layer 110 on the substrate 100. Since the gate 120 is located in the first region, the first gate structure penetrates the thicker portion of the first dielectric layer 110. The second gate structure is formed on the first dielectric layer 110 ( Figure 3A 、 Figure 3B 、 Figure 3C In the embodiment of the present invention, the second gate structure is formed in a direction parallel to the substrate surface (in the upward direction), that is, it is formed on the side of the first dielectric layer away from the substrate and covers a portion of the first dielectric layer. The second gate structure has a larger dimension parallel to the substrate surface than the first gate structure. In other words, the first gate structure and the second gate structure can form a T-shaped structure, with the first gate structure connected to the substrate 100 and the second gate structure facilitating balancing the electric field and capacitance within the device. In addition, a gate dielectric layer can be formed below the gate 120, and the gate dielectric layer is formed between the epitaxial layer and the first gate structure.

[0082] The substrate 100 may also include a source 101 and a drain 102, which are located on either side of the gate 120. A channel region is located between the source 101 and the drain 102, which is used to form a conductive channel when the device is in operation. The first region is located above the channel region, and the gate 120 is also located above the channel region. The gate 120 may have good conductivity and its material may be at least one of nickel (Ni), titanium (Ti), aluminum (Al), palladium (Pd), platinum (Pt), gold (Au), titanium nitride (TiN), tantalum nitride (TaN), and copper (Cu). A parasitic capacitance C1 is present between the first gate structure in the gate 120 and the drain 102, which is related to the size of the first gate structure. A parasitic capacitance C2 is present between the second gate structure in the gate 120 and the drain 102, which is related to the thickness and dielectric constant of the first dielectric layer 110 below the second gate structure.

[0083] The second dielectric layer 130 can cover the gate 120 and the first dielectric layer 110. The second dielectric layer 130 can protect the gate 120 and also serve as an isolation layer. The material of the second dielectric layer 130 can be at least one of silicon nitride, silicon oxynitride, silicon oxide, aluminum oxide, and titanium oxide, and can have a thickness ranging from 20 to 500 nm.

[0084] The field plate 140 is located on the second dielectric layer 130. The field plate 140 may face the portion of the gate facing the drain in a direction perpendicular to the substrate surface and extend toward the drain. In other words, the field plate 140 may be located on the side of the second gate structure facing the drain 102 and extend upward from the second gate structure ( Figure 3A 、 Figure 3B 、 Figure 3C The portion of the field plate 140 located in the second region is electrically connected to the source 101 (see Figure 3A 、 Figure 3B 、 Figure 3C The field plate 140 above the source 101 is an integral structure with the field plate 140 on top of the gate 120 and is used to modulate the electric field and capacitance distribution between the source and drain, thereby achieving a specific high-frequency gain index. The material of the field plate 140 is at least one of Ni, Ti, Al, Pd, Pt, Au, TiN, TaN and Cu. The material may be consistent with the material of the gate 120 or inconsistent. The thickness of the field plate 140 is in the range of 20nm-1500nm. When the device is working, there is a parasitic capacitance C3 between the field plate 140 and the conductive channel below. The parasitic capacitance affects the parasitic capacitance of the entire device and is related to the thickness and dielectric constant of the first dielectric layer 110 below the field plate 140 and the thickness and dielectric constant of the second dielectric layer 130.

[0085] In the embodiment of the present application, the first dielectric layer 110 is thicker in the first region and thinner in the second region outside the first region. That is, the thickness of the first dielectric layer 110 in the first region is greater than the thickness of the second region outside the first region. This can reduce the capacitance C2 between the second gate structure and the drain 102 without affecting the parasitic capacitance C3 between the field plate 140 and the conductive channel, thereby effectively reducing the overall parasitic capacitance of the device. In addition, since the thickness of the first dielectric layer 110 in the first region is greater, the potential and electric field distribution at the end of the gate 120 near the drain 102 can be adjusted, effectively weakening the electric field stress at the location where TDDB failure is prone to occur, thereby improving the overall robustness of the device.

[0086] refer to Figure 4As shown, this is another schematic diagram of the lateral electric field stress distribution of an embodiment of the present application, wherein the horizontal axis is the position in the direction along the substrate surface, and the vertical axis is the electric field stress at each position under the high-voltage reverse bias stress state. The first electric field peak can correspond to the end of the first gate structure close to the drain 102, the second electric field spike can correspond to the end of the second gate structure close to the drain 102, the third electric field spike can correspond to the end of the bottom layer of the field plate 140 close to the gate 120, and the fourth electric field spike can correspond to the end of the bottom layer of the field plate 140 close to the drain. It can be seen from the figure that the second electric field spike is weakened, thereby reducing the risk of TDDB failure.

[0087] An embodiment of the present application provides a semiconductor device including a substrate, a gate, a second dielectric layer, and a field plate. The substrate includes a first dielectric layer, wherein the thickness of the first dielectric layer in a first region is greater than the thickness of a second region outside the first region. The gate is located on the substrate and in the first region. The gate includes a first gate structure and a second gate structure connected in a direction perpendicular to the substrate surface. The first gate structure extends through the first dielectric layer in a direction perpendicular to the substrate surface. The second gate structure is formed on a side of the first dielectric layer away from the substrate and covers a portion of the first dielectric layer. The second dielectric layer covers the gate and the first dielectric layer. The field plate is located on the second dielectric layer and exists in both the first and second regions. Thus, compared to a first dielectric layer with uniform thickness, the capacitance between the second gate structure and the drain is reduced due to the greater thickness of the first dielectric layer in the first region, while the capacitance between the field plate and the channel is increased due to the lesser thickness of the first dielectric layer in the second region. This reduces the parasitic capacitance of the semiconductor device and improves the gain characteristics of the semiconductor device at high frequencies. Furthermore, this design can also readjust the electric field stress within the device. Due to the greater thickness of the first dielectric layer in the first region, the electric field spike at the second gate structure is weakened, thereby improving the overall robustness of the device.

[0088] Based on a semiconductor device provided in an embodiment of the present application, an embodiment of the present application also provides a method for manufacturing a semiconductor device, referring to Figure 5 FIG. 1 is a flow chart of a method for manufacturing a semiconductor device provided in an embodiment of the present application. The method may include:

[0089] S101, providing a substrate 100, reference Figure 6 shown.

[0090] In an embodiment of the present application, the substrate 100 can be designed according to different device requirements. Specifically, the substrate 100 may include a base and an epitaxial layer, and the epitaxial layer is formed on the surface of the base and is arranged toward the gate 120. The base may be a semiconductor base, such as one or more of GaN, AlN, Si, SiC, and sapphire. The base may provide support for the semiconductor device, or constitute a part of the functional layer of the semiconductor device. The epitaxial layer may be a film layer obtained by epitaxial growth on the base, which is usually a functional layer constituting the semiconductor device, for example, it may be one or more of GaN, AlGaN, InAlN, AlN, and ScAlN. The base and the epitaxial layer may have the same material or inconsistent materials. Among them, the silicon carbide substrate may be a single crystal structure and may have a variety of structural types, such as 4H-silicon carbide, 6H-silicon carbide, 3C-silicon carbide, etc.

[0091] In the gate-last process, the source and drain can be formed before the gate 120, and the substrate 100 can also have a source 101 and a drain 102. A channel region can be included between the source 101 and the drain 102. The channel region is used to form a conductive channel when the device is working. The source 101 and the drain 102 can be obtained by doping the substrate 100.

[0092] S102, forming a first dielectric layer on the substrate 100, and forming a gate 120 in a first region on the substrate 100, wherein the thickness of the first dielectric layer 110 in the first region is greater than the thickness of the second region outside the first region, and the gate 120 includes a second gate structure and a first gate structure connected in a direction perpendicular to the substrate surface, referring to Figure 7-10 、 Figure 12-15 、 Figures 17-22 shown.

[0093] In the embodiment of the present application, a first dielectric layer 110 can be formed on the substrate 100. The thickness of the first dielectric layer 110 in a first region is greater than the thickness of a second region outside the first region. The first region can be a region for forming a gate, or can be the center region where the source and drain electrodes are located. The first region can be larger than or equal to the region where the gate is located. The first dielectric layer 110 can be formed before or during the formation of the gate 120.

[0094] In the embodiment of the present application, the gate 120 is formed in the first region. The gate 120 includes a first gate structure and a second gate structure connected in a direction perpendicular to the substrate surface. The first gate structure penetrates the first dielectric layer 110 on the substrate 100. Since the gate 120 is located in the first region, the first gate structure penetrates the thicker portion of the first dielectric layer 110. The second gate structure is formed on the first dielectric layer 110 ( Figure 3A 、 Figure 3B 、 Figure 3C In the upward direction), the size of the second gate structure in the direction parallel to the substrate surface is greater than the size of the first gate structure in the direction parallel to the substrate surface, that is, the first gate structure and the second gate structure can form a T-shaped structure. A gate dielectric layer can also be formed under the gate 120, and the gate dielectric layer is formed between the epitaxial layer and the first gate structure. The gate 120 can have good conductivity, and its material can be at least one of Ni, Ti, Al, Pd, Pt, Au, TiN, TaN and Cu. There is a parasitic capacitance between the first gate structure of the gate 120 and the drain 102, which is related to the size of the first gate structure. There is a parasitic capacitance C2 between the second gate structure of the gate 120 and the drain 102, which is related to the thickness and dielectric constant of the first dielectric layer 110 under the second gate structure.

[0095] In the embodiment of the present application, the first dielectric layer 110 is thicker in the first region, while the thickness of the second region outside the first region is thinner. That is, the thickness of the first dielectric layer 110 in the first region is greater than the thickness of the second region outside the first region. This can reduce the capacitance between the second gate structure and the drain 102 without affecting the parasitic capacitance at other locations, thereby effectively reducing the parasitic capacitance of the entire device. In addition, since the thickness of the first dielectric layer 110 in the first region is greater, the potential and electric field distribution at the end of the gate 120 near the drain 102 can be adjusted, effectively weakening the electric field stress at the location where TDDB failure is prone to occur, thereby improving the overall robustness of the device.

[0096] In the embodiment of the present application, the first dielectric layer 110 may be a stack of multiple films or an integrated structure of a single film, wherein a single film may include multiple materials or a single material.

[0097] As a possible method of forming the first dielectric layer 110 and the gate 120, the first dielectric layer 110 may include a first sub-film layer 112 and a second sub-film layer 113. The first sub-film layer 112 and the second sub-material layer 113' may be deposited on the substrate 100 in sequence. Figure 7As shown, the thickness of the first sub-film layer 112 can range from 20 to 500 nm, and the material of the first sub-film layer 112 can be at least one of silicon nitride, silicon oxynitride, silicon oxide, aluminum oxide, and titanium oxide. The thickness of the second sub-material layer 113' can range from 20 to 500 nm, and the material of the second sub-material layer 113' can be at least one of silicon nitride, silicon oxynitride, silicon oxide, aluminum oxide, and titanium oxide. The first sub-film layer 112 and the second sub-material layer 113' can have different refractive indices, densities, and etching resistances. The first sub-film layer 112 and the second sub-material layer 113' can have the same material or different materials. When the first sub-film layer 112 and the second sub-material layer 113' have the same material layer, they can have different deposition temperatures, thereby having different refractive indices, densities, and etching resistances.

[0098] Then, the second sub-material layer 113' and the first sub-film layer 112 can be etched in the first region to obtain the first through hole 119. Figure 8 As shown. The second sub-material layer 113' and the first sub-membrane layer 112 can be etched using a photolithography process, using anisotropic dry or wet etching. The first through-hole 119 is located in the first region, exposing the substrate 100 in the first region. When a gate dielectric layer is formed on the substrate 100, the first through-hole 119 can expose the gate dielectric layer.

[0099] Then, a first gate structure located inside the first through hole 119 and a second gate structure connected to the first gate structure and covering a portion of the first dielectric layer can be formed to obtain a gate 120. Figure 9 As shown. The first and second gate structures can be formed by deposition and etching. Specifically, a conductive material can be deposited to fill the first through-hole 119 and cover the first through-hole 119. The thickness of the conductive material can range from 20 to 1500 nm. The conductive material can be at least one of Ni, Ti, Al, Pd, Pt, Au, TiN, TaN, and Cu. The conductive material outside the first region can then be removed to form the gate 120 located in the conductive region.

[0100] Then, the second gate structure can be used as a mask to etch away the second sub-material layer 113′ outside the first region, and the second sub-material layer 113′ located in the first region serves as the second sub-film layer 113. Figure 10As shown, since there is a difference in etching resistance between the first sub-film layer 112 and the second sub-material layer, the first sub-film layer 112 can be used as an etching stop layer, and the second gate structure can be used as a hard self-aligned mask to etch the second sub-material layer 113' to obtain the second sub-film layer 113. The etched surface stays at the interface position of the first sub-film layer 112 and the second sub-material layer 113'. The etching thickness is the thickness of the second sub-material layer 113'. The etching method can be anisotropic dry etching or wet etching. Since the second gate structure can be used as a mask, there is no need to add a sequential photolithography process, which can save costs. Of course, the etching of the second sub-material layer 113' can also be performed by a photolithography process before forming the first gate structure and the second gate structure, which will not be described in detail here.

[0101] That is, the first dielectric layer 110 may include a first sub-layer 112 and a second sub-layer 113. The first sub-layer 112 covers the substrate 100, and the second sub-layer 113 is located in a first region above the first sub-layer 112. Thus, the difference between the thickness of the first dielectric layer 110 in the first region and the thickness of the second region outside the first region is the thickness of the second sub-layer 113. The material of the first sub-layer 112 and / or the second sub-layer 113 is at least one of silicon nitride, silicon oxynitride, silicon oxide, aluminum oxide, and titanium oxide.

[0102] As another possible method of forming the first dielectric layer 110 and the gate 120, a first dielectric material layer 115 may be deposited on the substrate 100. Figure 12 As shown, the thickness of the first dielectric material layer 115 may be in the range of 40-1000 nm, and the material of the first dielectric material layer 115 may be at least one of silicon nitride, silicon oxynitride, silicon oxide, aluminum oxide, and titanium oxide.

[0103] Then, the first dielectric material layer 115 can be etched in the first region to obtain the second through hole 116. Figure 13 As shown. The first dielectric material layer 115 can be etched using a photolithography process, using anisotropic dry or wet etching. The second through hole 116 is located in the first region, exposing the substrate 100 in the first region. When a gate dielectric layer is formed on the substrate 100, the second through hole 116 can expose the gate dielectric layer.

[0104] Then, a first gate structure located inside the second through hole 116 and a second gate structure connected to the first gate structure and covering a portion of the first dielectric layer can be formed to form a gate 120. Figure 14As shown. The first gate structure and the second gate structure can be formed by deposition and etching. Specifically, a conductive material can be deposited to fill the second through-hole 116 and cover the second through-hole 116. The thickness of the conductive material can range from 20 to 1500 nm. The conductive material can be at least one of Ni, Ti, Al, Pd, Pt, Au, TiN, TaN, and Cu. The conductive material outside the first region can then be removed to form the gate 120 located in the conductive region.

[0105] Then, the first dielectric material layer 115 outside the first region can be etched to remove a portion of the first dielectric material layer 115 in the second region outside the first region, that is, the first dielectric material layer 115 in the second region is thinned to form the first dielectric layer 110. Figure 15 As shown, during the etching process, the second gate structure is used as a hard self-aligned mask. The etching thickness can be controlled by the etching rate and etching time. The thickness range can be 20-500nm, and the etching method can be anisotropic dry etching or wet etching. Since the first dielectric layer 110 in the second area outside the first area is etched and thinned, it has a thinner thickness. Specifically, the thickness of the first dielectric layer 110 in the first area is the deposition thickness of the first dielectric material layer 115, and its thickness range can be 40-1000nm. The thickness range of the first dielectric layer 110 in the second area outside the first area can be 20-500nm. Since the second gate structure can be used as a mask, there is no need to add a sequential photolithography process, which can save costs. Of course, the etching of the first dielectric material layer 115 in the second area outside the first area can also be performed by a photolithography process before forming the first gate structure and the second gate structure. It will not be described in detail here.

[0106] As another possible way to form the first dielectric layer 110 and the gate 120, the first dielectric layer includes a first sub-film layer 112 and a second sub-film layer 113, and the first sub-material layer 111 can be deposited on the substrate 100, referring to Figure 17 As shown, the third sub-material layer 111 in the second region outside the first region is removed, and the third sub-material layer 111 in the first region is used as the first sub-film layer 112. Figure 19 As shown. The thickness of the first sub-material layer 111 can range from 20 to 500 nm, and the material of the first sub-material layer 111 can be at least one of silicon nitride, silicon oxynitride, silicon oxide, aluminum oxide, and titanium oxide. The first sub-material layer 111 can be etched using a photolithography process, and the etching method can be anisotropic dry etching or wet etching.

[0107] Then, a second sub-film layer 113 covering the first sub-film layer 112 and the substrate 100 may be formed. Figure 20 As shown, the second sub-membrane layer 113 can be formed by deposition. The thickness of the second sub-membrane layer 113 can range from 20 to 500 nm. The material of the second sub-membrane layer 113 can be at least one of silicon nitride, silicon oxynitride, silicon oxide, aluminum oxide, and titanium oxide. The second sub-membrane layer 113 can cover the upper surface and sidewalls of the first sub-membrane layer 112, as well as the substrate 100 outside the first sub-membrane layer 112.

[0108] Then, the second sub-film layer 113 and the first sub-film layer 112 can be etched in the first region to obtain the third through hole 114. Figure 21 As shown. The second sub-membrane layer 113 and the first sub-membrane layer 112 can be etched using a photolithography process, using anisotropic dry etching or wet etching. The third through hole 114 can be provided in the first region to expose the substrate 100 in the first region. When a gate dielectric layer is formed on the substrate 100, the third through hole 114 can expose the gate dielectric layer.

[0109] Then, a first gate structure located inside the third through hole 114 and a second gate structure connected to the first gate structure and covering a portion of the first dielectric layer can be formed to form a gate 120. Figure 22 As shown. The first and second gate structures can be formed by deposition and etching. Specifically, a conductive material can be deposited to fill and cover the third through-hole 114. The thickness of the conductive material can range from 20 to 1500 nm. The conductive material can be at least one of Ni, Ti, Al, Pd, Pt, Au, TiN, TaN, and Cu. The conductive material outside the first region can then be removed to form the gate 120 located in the conductive region.

[0110] As another possible way to form the first dielectric layer 110 and the gate 120, the first dielectric layer includes a first sub-film layer 112 and a second sub-film layer 113. The first sub-film layer 112 can be formed in the first region on the substrate 100 using a double-layer photoresist patterning process. The double-layer photoresist pattern includes a first photoresist 103 with a larger opening in the lower layer and a second photoresist 104 with a smaller opening in the upper layer. In this way, the opening in the double-layer photoresist is used to define the position of the first sub-film layer 112. Figure 18 As shown. Then, a deposition process can be used to form a first sub-film layer 112 in the opening. Of course, a dielectric material is also formed on the photoresist layer during the deposition process. Figure 18As shown, the thickness of the first sub-film layer 112 can be in the range of 20-500nm, and the material of the first sub-film layer 112 can be at least one of silicon nitride, silicon oxynitride, silicon oxide, aluminum oxide, and titanium oxide. Then, the double-layer photoresist 103 / 104 and the dielectric material on the double-layer photoresist 103 / 104 can be removed by dry etching or wet etching. Figure 19 As shown, the first sub-layer 112 may then be cleaned using a dry process and / or a wet process.

[0111] Then, a second sub-film layer 113 covering the first sub-film layer 112 and the substrate 100 can be formed, and the second sub-film layer 113 and the first sub-film layer 112 are etched in the first region to obtain a third through-hole 114, thereby forming a first gate structure located inside the third through-hole 114 and a second gate structure connected to the first gate structure and covering a portion of the first dielectric layer. The formation of the second sub-film layer 113, the formation of the third through-hole, and the formation of the first gate structure and the second gate structure can refer to the aforementioned method, and Figure 20 、 Figure 21 、 Figure 22 As shown, no further details are given here.

[0112] That is to say, the first dielectric layer 110 may include a first sub-membrane layer 112 and a second sub-membrane layer 113, the first sub-membrane layer 112 is located in the first area on the substrate 100, and the second sub-membrane layer 113 covers the first sub-membrane layer 112 and the substrate 100 in the second area outside the first sub-membrane layer 112, so that the difference between the thickness of the first dielectric layer 110 in the first area and the thickness of the second area outside the first area is the thickness of the first sub-membrane layer 112.

[0113] S103, forming a second dielectric layer 130 covering the gate 120 and the first dielectric layer 110, referring to Figure 11 、 Figure 16 、 Figure 23 shown.

[0114] After forming the gate 120, a second dielectric layer 130 can be formed to cover the gate 120 and the first dielectric layer 110. The second dielectric layer 130 can protect the gate 120 and also serve as an isolation layer. The second dielectric layer 130 can be formed by deposition. The material of the second dielectric layer 130 can be at least one of silicon nitride, silicon oxynitride, silicon oxide, aluminum oxide, and titanium oxide, and can have a thickness ranging from 20 to 500 nm.

[0115] In the gate-first process, after forming the second dielectric layer 130 , the second dielectric layer 130 and the first dielectric layer 110 may be etched to expose the source and drain regions of the substrate 100 , thereby forming the source 101 and the drain 102 .

[0116] S104, forming a field plate 140 on the second dielectric layer 130, referring to Figure 1 、 Figures 3A-3C 、 Figure 4 shown.

[0117] After forming the second dielectric layer 130, a field plate 140 may be formed on the second dielectric layer 130. The field plate 140 may face the portion of the gate facing the drain in a direction perpendicular to the substrate surface and extend toward the drain. In other words, the field plate 140 may be located on the side of the second gate structure facing the drain 102 and extend upward from the second gate structure ( Figure 3A 、 Figure 3B 、 Figure 3C The portion of the field plate 140 located in the second region is electrically connected to the source 101 (see Figure 3A 、 Figure 3B 、 Figure 3C The field plate 140 above the source 101 is an integral structure with the field plate 140 on top of the gate 120 and is used to modulate the electric field and capacitance distribution between the source and drain, thereby achieving a specific high-frequency gain index. The material of the field plate 140 is at least one of Ni, Ti, Al, Pd, Pt, Au, TiN, TaN and Cu. The material may be consistent with the material of the gate 120 or inconsistent. The thickness of the field plate 140 ranges from 20nm to 1500nm. When the device is working, there is a parasitic capacitance C3 between the field plate 140 and the conductive channel below. The parasitic capacitance affects the parasitic capacitance of the entire device, which is related to the thickness and dielectric constant of the first dielectric layer 110 below the field plate 140 and the thickness and dielectric constant of the second dielectric layer 130.

[0118] Since the thickness of the first dielectric layer 110 in the area under the second gate structure is greater than the thickness of the second area outside the second gate structure, the capacitance between the second gate structure and the drain 102 can be reduced without affecting the parasitic capacitance between the field plate 140 and the channel, thereby effectively reducing the parasitic capacitance of the entire device.

[0119] An embodiment of the present application provides a method for manufacturing a semiconductor device, comprising providing a substrate, forming a first dielectric layer and a gate on the substrate, wherein the thickness of the first dielectric layer in a first region is greater than the thickness of a second region outside the first region, the gate being located on the substrate and located in the first region, the gate including a second gate structure and a first gate structure connected in a direction perpendicular to the substrate surface, the first gate structure extending perpendicular to the substrate surface through the first dielectric layer, the second gate structure being formed on a side of the first dielectric layer away from the substrate and covering a portion of the first dielectric layer, and then forming a second dielectric layer covering the gate and the first dielectric layer, and forming a field plate on the second dielectric layer, the field plate being present in both the first region and the second region. Thus, compared to a first dielectric layer with uniform thickness, the capacitance between the second gate structure and the drain is reduced due to the greater thickness of the first dielectric layer in the first region, while the capacitance between the field plate and the channel is increased due to the lesser thickness of the first dielectric layer in the second region, thereby reducing the parasitic capacitance of the semiconductor device and improving the gain characteristics of the semiconductor device at high frequencies. Furthermore, this design can also readjust the electric field stress within the device. Due to the greater thickness of the first dielectric layer in the first region, the electric field spike at the second gate structure is weakened, thereby improving the overall robustness of the device.

[0120] Based on a semiconductor device provided in an embodiment of the present application, an embodiment of the present application further provides an electronic device, the electronic device including a circuit board and a semiconductor device connected to the circuit board, the semiconductor device can be any of the semiconductor devices provided above. The circuit board can be a printed circuit board (PCB), and of course the circuit board can also be a flexible circuit board (FPC), etc. This embodiment does not limit the circuit board. Optionally, the electronic device is a different type of user device or terminal device such as a computer, a mobile phone, a tablet computer, a wearable device, and an in-vehicle device; the electronic device can also be a network device such as a base station.

[0121] Optionally, the electronic device further includes a packaging substrate, the packaging substrate is fixed on the printed circuit board PCB via solder balls, and the semiconductor device is fixed on the packaging substrate via solder balls.

[0122] In another aspect of the present application, a non-transitory computer-readable storage medium for use with a computer having software for creating an integrated circuit is provided, wherein the computer-readable storage medium has one or more computer-readable data structures stored thereon, the one or more computer-readable data structures having photomask data for manufacturing the integrated circuit provided in any of the diagrams provided above.

[0123] The various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on the differences from other embodiments.

[0124] The above is a specific implementation of the present application. It should be understood that the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them. Although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A semiconductor device, characterized in that: include: a substrate having a first dielectric layer thereon, wherein the thickness of the first dielectric layer in a first region is greater than the thickness of the first dielectric layer in a second region outside the first region; The first dielectric layer includes a first sub-film layer and a second sub-film layer, the first sub-film layer covers the substrate, and the second sub-film layer is located in a first area on the first sub-film layer, the non-perpendicular sidewall of the second sub-film layer is located in the first area, and the sidewall of the second sub-film layer is in a straight line with the sidewall of the second gate structure included in the gate; or, the first sub-film layer is located on the substrate and in the first area, the second sub-film layer covers the first sub-film layer and the substrate in a second area outside the first sub-film layer, the part of the sidewall of the first sub-film layer covered by the second sub-film layer is located in the first area, the size of the projection of the first sub-film layer along the substrate surface direction is smaller than the size of the projection of the first area along the substrate surface direction, and the first sub-film layer is located below the coverage of the second gate structure included in the gate along the substrate surface direction; a gate, the gate being located on the substrate and in the first region, the first region being a region for forming the gate, the gate comprising a first gate structure and a second gate structure connected in a direction perpendicular to the substrate surface, the first gate structure penetrating the first dielectric layer in a direction perpendicular to the substrate surface, and the second gate structure being formed on a side of the first dielectric layer away from the substrate and covering a portion of the first dielectric layer; a second dielectric layer covering the gate and the first dielectric layer; A field plate is located on the second dielectric layer; the field plate exists in both the first region and the second region.

2. The semiconductor device according to claim 1, wherein It also includes a source and a drain located in the substrate; the gate is located between the source and the drain, the field plate is opposite to the portion of the gate facing the drain in a direction perpendicular to the surface of the substrate and extends toward the drain, and the portion of the field plate located in the second region is electrically connected to the source.

3. The semiconductor device according to claim 1, wherein The material of at least one of the first sub-film layer and the second sub-film layer is at least one of silicon nitride, silicon oxynitride, silicon oxide, aluminum oxide, and titanium oxide.

4. The semiconductor device according to any one of claims 1 to 3, wherein: The substrate includes a base and an epitaxial layer, the epitaxial layer is arranged toward the gate, the material of the base is one or more of gallium nitride, aluminum nitride, silicon, silicon carbide, and sapphire, and the epitaxial layer includes one or more of gallium nitride, aluminum gallium nitride, indium aluminum nitride, aluminum nitride, and scandium aluminum nitride.

5. The semiconductor device according to any one of claims 1 to 3, wherein: The gate and / or the field plate may be made of at least one of nickel, titanium, aluminum, palladium, platinum, gold, titanium nitride, tantalum nitride and copper.

6. The semiconductor device according to any one of claims 1 to 3, wherein: The material of the second dielectric layer is at least one of silicon nitride, silicon oxynitride, silicon oxide, aluminum oxide, and titanium oxide.

7. A method for manufacturing a semiconductor device, characterized in that: include: providing a substrate; forming a first dielectric layer and a gate on the substrate; The gate is located on the substrate and in a first region, where the first region is a region for forming the gate; The thickness of the first dielectric layer in the first region is greater than the thickness in the second region outside the first region; the gate includes a first gate structure and a second gate structure connected in a direction perpendicular to the substrate surface, the first gate structure penetrates the first dielectric layer in a direction perpendicular to the substrate surface, and the second gate structure is formed on a side of the first dielectric layer away from the substrate and covers a portion of the first dielectric layer; the first dielectric layer includes a first sub-film layer and a second sub-film layer, the first sub-film layer covers the substrate, and the second sub-film layer is located in a first region on the first sub-film layer, the non-perpendicular sidewalls of the second sub-film layer are located in the first region, and the sidewalls of the second sub-film layer are aligned with the sidewalls of the second gate structure included in the gate; or, the first sub-film layer is located on the substrate and in the first region, the second sub-film layer covers the first sub-film layer and the substrate in the second region outside the first sub-film layer, the portion of the sidewalls of the first sub-film layer covered by the second sub-film layer is located in the first region, the projection size of the first sub-film layer along the substrate surface is smaller than the projection size of the first region along the substrate surface, and the first sub-film layer is located below the coverage of the second gate structure included in the gate along the substrate surface; forming a second dielectric layer covering the gate and the first dielectric layer; A field plate is formed on the second dielectric layer; the field plate exists in both the first region and the second region.

8. The method according to claim 7, characterized in that A source and a drain are also formed in the substrate; the gate is located between the source and the drain, the field plate is opposite to the portion of the gate facing the drain in a direction perpendicular to the substrate surface and extends toward the drain, and the portion of the field plate located in the second region is electrically connected to the source.

9. The method according to claim 7 or 8, characterized in that The first dielectric layer includes a first sub-film layer and a second sub-film layer. Forming the first dielectric layer and the gate on the substrate includes: forming a first sub-material layer and a second sub-material layer in sequence on the substrate; Etching the second sub-material layer and the first sub-material layer in the first region to obtain a first through hole; forming a first gate structure located inside the first through hole, and a second gate structure connected to the first gate structure and covering a portion of the first dielectric layer; The second sub-material layer outside the second gate structure is removed by etching using the second gate structure, and the second sub-material layer located in the first region serves as the second sub-film layer.

10. The method according to claim 7 or 8, characterized in that Forming a first dielectric layer and a gate on the substrate, comprising: forming a first dielectric material layer on the substrate; Etching the first dielectric material layer in the first region to obtain a second through hole; forming a first gate structure located inside the second through hole, and a second gate structure connected to the first gate structure and covering a portion of the first dielectric layer; The first dielectric material layer in the second area outside the first area is thinned to form a first dielectric layer.

11. The method according to claim 7 or 8, characterized in that The first dielectric layer includes a first sub-film layer and a second sub-film layer. Forming the first dielectric layer and the gate on the substrate includes: forming a first sub-material layer on the substrate; removing the first sub-material layer in the second area outside the first area, and using the first sub-material layer in the first area as the first sub-film layer; forming a second sub-film layer covering the first sub-film layer and the substrate; Etching the second sub-film layer and the first sub-film layer in the first region to obtain a third through hole; A first gate structure is formed inside the third through hole, and a second gate structure is formed which is connected to the first gate structure and covers a portion of the first dielectric layer.

12. The method according to claim 7 or 8, characterized in that The first dielectric layer includes a first sub-film layer and a second sub-film layer. Forming the first dielectric layer and the gate on the substrate includes: forming a first sub-film layer in a first area on the substrate using a double-layer photoresist patterning process; forming a second sub-film layer covering the first sub-film layer and the substrate; Etching the second sub-film layer and the first sub-film layer in the first region to obtain a third through hole; A first gate structure is formed inside the third through hole, and a second gate structure is formed which is connected to the first gate structure and covers a portion of the first dielectric layer.

13. The method according to claim 7 or 8, characterized in that The material of the first sub-film layer and / or the second sub-film layer is at least one of silicon nitride, silicon oxynitride, silicon oxide, aluminum oxide, and titanium oxide.

14. The method according to claim 7 or 8, characterized in that The substrate includes a base and an epitaxial layer, the material of the base is one or more of gallium nitride, aluminum nitride, silicon, silicon carbide, and sapphire, and the epitaxial layer includes one or more of gallium nitride, aluminum gallium nitride, indium aluminum nitride, aluminum nitride, and scandium aluminum nitride.

15. The method according to claim 7 or 8, characterized in that The gate and / or the field plate may be made of at least one of nickel, titanium, aluminum, palladium, platinum, gold, titanium nitride, tantalum nitride and copper.

16. The method according to any one of claims 7 or 8, characterized in that The material of the second dielectric layer is at least one of silicon nitride, silicon oxynitride, silicon oxide, aluminum oxide, and titanium oxide.

17. An electronic device, characterized in that: The invention comprises a circuit board and a semiconductor device according to any one of claims 1 to 6, connected to the circuit board.

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