Digital closed loop control and measurement circuit for a quartz flexible accelerometer

Abstract

This invention discloses a digital closed-loop control and measurement circuit for a quartz flexible accelerometer. It includes a differential capacitor carrier demodulation and detection circuit, a low-pass filter amplifier circuit, a first A / D converter, an FPGA, a D / A converter, and a power amplifier circuit connected in sequence to achieve low-noise digital closed-loop control. The set value of the D / A converter reflects the current acceleration measurement. It also includes a sampling resistor, a zero-drift amplifier circuit, a second A / D converter, and an FPGA connected in sequence to form a zero-drift current measurement circuit driving the meter's torque coil. The measurement value of the second A / D converter also reflects the current acceleration measurement. The FPGA simultaneously obtains the set value of the D / A converter and the measurement value of the second A / D converter, digitally outputting a low-noise, zero-drift acceleration characterization value. This invention effectively solves the problems of poor temperature drift characteristics, large zero-point error, and large scale factor error in ordinary digital closed-loop quartz accelerometers, significantly improving the accuracy of digital quartz accelerometers.

Description

Technical Field

[0001] This invention belongs to the field of measurement sensors, and relates to an acceleration sensor circuit, and more particularly to a digital closed-loop control and measurement circuit for a quartz flexible accelerometer. Background Technology

[0002] Quartz flexural accelerometers are crucial components in inertial navigation, control, and detection equipment, and their performance directly impacts the accuracy and efficiency of these devices. Due to their lightweight, small size, high sensitivity, and good stability, quartz flexural accelerometers are currently the most widely used medium-to-high precision accelerometer sensor.

[0003] Traditional quartz flexural accelerometers integrate an analog current feedback circuit with the sensor head. The magnitude of the analog current output by the servo circuit is proportional to the input acceleration, thus forming the characteristic. In modern navigation computing and digital control systems, the analog current must generally be converted into a digital value through a digital conversion circuit for further processing. However, for a medium-to-high precision sensor like a quartz accelerometer, this digital conversion introduces additional accuracy losses, even obscuring the original high-precision characteristics of the sensor head. Moreover, the introduction of the digital conversion circuit significantly increases the size, weight, and power consumption of the inertial measurement unit.

[0004] To overcome the shortcomings of sensors from the non-digital era, many research teams have proposed the concept of digital quartz flexural accelerometers. These accelerometers employ fully digital servo circuits for closed-loop feedback, introducing digital differential capacitance measurement and digital servo current drive, and incorporating a digital processor. The digital drive control quantity, after certain digital processing, can characterize the input acceleration. However, existing accelerometers using digital closed-loop servo circuits essentially digitize the control system based on the original analog closed-loop circuit principle. If the servo control quantity is directly output as the acceleration characterization quantity, its accuracy will be affected by multiple components in the closed-loop system, making it difficult to achieve the original accuracy, and even less accurate than the original analog quartz flexural accelerometers combined with I / F or A / D conversion modules. Specifically, this manifests as a large temperature drift coefficient, large zero-point error, and large scale factor error. Alternatively, it may essentially still be an analog servo combined with A / F conversion. / A D converter cannot fully utilize the advantages of a fully digitized quartz flexural accelerometer.

[0005] Therefore, a quartz accelerometer and its circuitry that truly possess medium-to-high precision characteristics and the advantage of full digitalization is a reasonable demand for technological development. Summary of the Invention

[0006] The purpose of this invention is to address the shortcomings of existing technologies by providing a digital closed-loop control and measurement circuit for a quartz flexible accelerometer, overcoming the problem that ordinary digital closed-loop quartz accelerometers use closed-loop control quantities to characterize acceleration, making it difficult to achieve high precision in digital measurement.

[0007] To achieve the above objectives, the specific technical solution of the present invention is as follows:

[0008] A digital closed-loop control and measurement circuit for a quartz flexural accelerometer includes a differential capacitor carrier demodulation detection circuit, a low-pass filter amplifier circuit, a first A / D converter, an FPGA, a D / A converter, a power amplifier circuit, a sampling resistor, a zero-drift amplifier circuit, and a second A / D converter, and also includes a digital output interface circuit.

[0009] The differential capacitor carrier demodulation detection circuit, low-pass filter amplifier circuit, first A / D converter, FPGA, D / A converter, and power amplifier circuit are connected in sequence to realize low-noise digital closed-loop control. The setting value of the D / A converter can reflect the current acceleration measurement. The sampling resistor, zero-drift amplifier circuit, second A / D converter, and FPGA are connected in sequence to form a zero-drift current measurement circuit for driving the meter torque coil. The measurement value of the second A / D converter can also reflect the current acceleration measurement.

[0010] The FPGA simultaneously obtains the setting value of the D / A converter and the measurement value of the second A / D converter, and digitally outputs a low-noise, zero-drift acceleration characterization value.

[0011] Furthermore, the differential capacitor carrier demodulation detection circuit, the low-pass filter amplifier circuit, and the first A / D converter constitute a differential capacitor measurement circuit;

[0012] The differential capacitor carrier demodulation detection circuit includes a capacitor readout front-end circuit and an analog switch sample-and-hold circuit connected in sequence.

[0013] The input terminal of the first A / D converter is connected to the output terminal of the low-pass filter amplifier circuit. The low-pass filter amplifier circuit identifies the phase of the carrier amplitude-modulated wave through the analog switch sample-and-hold circuit. The low-pass filter amplifier circuit is a second-order voltage-controlled voltage source type low-pass filter that filters out the carrier signal.

[0014] The FPGA is connected to the analog switch in the analog switch sample-and-hold circuit and the first A / D converter, providing analog switch drive signals and digital conversion.

[0015] Furthermore, the capacitance reading front-end circuit is used to perform modulation and subtraction functions on the changes in a pair of differential capacitors, converting the change in the measured capacitance into a voltage change; the differential capacitor C x0 +ΔC and differential capacitance Cx0 -One end of ΔC is connected to the differential capacitor C. x0 The other end of +ΔC is connected to the inverting input of operational amplifier A1, and the differential capacitor C... x0 The other end of -ΔC is connected to the inverting input of operational amplifier A2; the non-inverting inputs of operational amplifiers A1 and A2 are grounded; a feedback capacitor C is connected in parallel between the inverting input and output of operational amplifiers A1 and A2. f Feedback resistor R f Parallel connection to feedback capacitor C f Two ends; operational amplifier A1, feedback capacitor C f Feedback resistor R f This constitutes the first charge amplifier, operational amplifier A2, and feedback capacitor C. f Feedback resistor R f This forms a second charge amplifier; the output of the first charge amplifier is connected to the non-inverting input of the differential amplifier A3, and the output of the second charge amplifier is connected to the inverting input of the differential amplifier A3.

[0016] The operational amplifiers A1, A2, and differential amplifier A3 are all low-noise amplifiers.

[0017] Furthermore, the power amplifier circuit includes a reference voltage source, a D / A converter, resistors R3 and R4, and a power operational amplifier A4;

[0018] The D / A converter is connected to the FPGA;

[0019] One end of resistor R3 is connected to the reference voltage source, and the other end is connected to the negative input terminal of the power operational amplifier A4. One end of resistor R4 is connected to the negative input terminal of the power operational amplifier A4, and the other end is connected to one end of the meter torque coil and the output terminal of the power operational amplifier A4. The positive input terminal of the power operational amplifier A4 is connected to the output terminal of the D / A converter, and the other end of the meter torque coil is grounded. The reference voltage source provides a reference voltage to the D / A converter and also serves as the negative input of the power operational amplifier A4. Resistors R3 and R4 are equal in resistance as matching resistors for the power operational amplifier A4. Both the D / A converter and the power operational amplifier A4 are low-noise types.

[0020] Furthermore, the zero-drift amplifier circuit includes a zero-drift follower A5, resistors R5, R6, R7, R8, and a fully differential amplifier A6. The sampling resistor is connected to the positive input of the zero-drift follower A5, the output of the zero-drift follower A5 is connected to one end of resistor R5, and the other end of resistor R5 is connected to the positive input of the fully differential amplifier A6 and one end of resistor R7. The positive output of the fully differential amplifier A6 is connected to the positive input of the second A / D converter and the other end of resistor R7, and the negative output of the fully differential amplifier A6 is connected to one end of resistor R8 and the negative input of the second A / D converter. One end of resistor R6 is grounded, and the other end is connected to the other end of resistor R8 and the negative input of the fully differential amplifier A6. The output of the second A / D converter is connected to the FPGA.

[0021] The resistance values ​​of resistors R5, R6, R7, and R8 are equal.

[0022] Furthermore, the second A / D converter is a differential precision A / D converter.

[0023] The beneficial effects of this invention are:

[0024] This invention organically combines digital closed-loop control and servo current measurement into a single circuit. It distributes the required characteristics for acceleration measurement, such as low drift, high repeatability, low noise, and large bandwidth, to different functional modules. For example, low noise is primarily required for the drive stage, while low drift is required for the detection stage. These characteristics, represented by two integrated systems, fully leverage the advantages of digital resources to achieve high-precision acceleration measurements. This makes the digital quartz flexural accelerometer truly useful and further enhances its advantages in easily implementing temperature compensation and long-term characteristic compensation, thus improving the performance of the quartz flexural accelerometer head. Attached Figure Description

[0025] Figure 1 This is a block diagram of a digital closed-loop control and measurement circuit for a quartz flexible accelerometer according to an embodiment of the present invention.

[0026] Figure 2 This is a schematic diagram of a differential capacitance measurement circuit.

[0027] Figure 3 This is a schematic diagram of the capacitor reading front-end circuit.

[0028] Figure 4 This is a schematic diagram of a power amplifier circuit driven by a torque coil.

[0029] Figure 5 This is a schematic diagram of a zero-drift amplifier circuit. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described are only some, not all, of the embodiments of the present invention. Other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are all within the protection scope of the present invention.

[0031] like Figure 1 As shown, the present invention discloses a digital closed-loop control and measurement circuit for a quartz flexural accelerometer, comprising a differential capacitor carrier demodulation and detection circuit, a low-pass filter amplifier circuit, a first A / D converter, an FPGA, a D / A converter, a power amplifier circuit, a sampling resistor, a zero-drift amplifier circuit, and a second A / D converter. It also includes a digital output interface circuit (typically connected to an RS485 transceiver via UART communication to achieve data interaction with an external system). This circuit, combined with the quartz flexural accelerometer head, forms a compact, integrated digital quartz accelerometer. The differential capacitor carrier demodulation and detection circuit... A digital closed-loop control circuit is constructed, consisting of a low-pass filter amplifier circuit, a first A / D converter, an FPGA, a D / A converter, and a power amplifier circuit, prioritizing low noise. The D / A converter's setting value reflects the current acceleration measurement. Furthermore, a driving torque current measurement circuit is formed by a sampling resistor, a zero-drift amplifier circuit, a second A / D converter, and the FPGA, achieving high-precision measurement with low drift and high repeatability. The selected components are designed for low drift, the measurement circuit structure is kept as simple as possible, and the sampling speed can be relatively slow, with higher accuracy achieved through digital filtering. The measurement value from the second A / D converter also reflects the current acceleration measurement.

[0032] The digital output interface circuit is used to output the acceleration measurement values ​​obtained by the FPGA.

[0033] The differential capacitance measurement and DA drive digital closed-loop control circuit designed in this embodiment mainly pursues low noise, and strives to ensure that all selected components have low noise performance. The capacitance detection circuit should have high gain and a high carrier frequency, and the A / D conversion and D / A conversion should have high sampling rates.

[0034] The differential capacitance carrier demodulation detection circuit, the low-pass filter amplifier circuit, and the first A / D converter constitute the differential capacitance measurement circuit, such as... Figure 2As shown in the diagram, the differential capacitor carrier demodulation detection circuit includes a capacitor readout front-end circuit and an analog switch sample-and-hold circuit. The input of the first A / D converter is connected to the output of the low-pass filter amplifier circuit. The low-pass filter amplifier circuit uses the analog switch sample-and-hold circuit to identify the phase of the carrier amplitude-modulated wave. The low-pass filter amplifier circuit is designed as a second-order voltage-controlled source type low-pass filter to filter out the carrier signal. Additionally, the FPGA is connected to the analog switch in the analog switch sample-and-hold circuit and the first A / D converter to provide analog switch drive signals and digital conversion.

[0035] The analog switch sample-and-hold circuit includes an analog switch S and a sampling capacitor C. H The input terminal of the analog switch S is the output terminal of the capacitor reading front-end circuit, and the sampling time of the analog switch is at the peak value of the amplitude modulation wave; the sampling capacitor C H One end is grounded, and the other end is connected to the output terminal of analog switch S.

[0036] The low-pass filter amplifier circuit includes a first resistor R1, a second resistor R2, a first capacitor C1, a second capacitor C2, and an operational amplifier. One end of the first resistor R1 is connected to the output terminal of the analog switch S, and the other end is connected to one end of the second resistor R2. The other end of the second resistor R2 is connected to the non-inverting input terminal of the operational amplifier. One end of the first capacitor C1 is connected to the non-inverting input terminal of the operational amplifier, and the other end is grounded. One end of the second capacitor C2 is connected to the junction of the first resistor R1 and the second resistor R2, and the other end is connected to the output terminal of the operational amplifier. A low-noise operational amplifier is selected here.

[0037] Design of the capacitor reading front-end circuit, such as Figure 3 As shown, this mainly performs modulation and subtraction functions on the changes in a pair of differential capacitors, converting the change in the measured capacitance into a voltage change. A high-frequency sinusoidal carrier wave is applied to the differential capacitor C. x0 +ΔC and differential capacitance C x0 At the common terminal of -ΔC, the differential capacitor C x0 The other end of +ΔC is connected to the inverting input of operational amplifier A1, and the differential capacitor C... x0 The other end of -ΔC is connected to the inverting input of operational amplifier A2, and the non-inverting inputs of operational amplifiers A1 and A2 are grounded; a feedback capacitor C is connected in parallel between the inverting input and output of operational amplifiers A1 and A2. f Feedback resistor R f Parallel connection to feedback capacitor C f Two ends; operational amplifier A1, feedback capacitor C f Feedback resistor R f This constitutes the first charge amplifier, operational amplifier A2, and feedback capacitor C. f Feedback resistor R fThis forms a second charge amplifier; the output of the first charge amplifier is connected to the non-inverting input of the differential amplifier A3, and the output of the second charge amplifier is connected to the inverting input of the differential amplifier A3.

[0038] The capacitance of the differential capacitor pair is modulated onto the amplitude of a high-frequency carrier wave through two charge amplifiers. The two amplitude-modulated signals, 180° out of phase, are amplified by differential amplifier A3, eliminating the common-mode component and only amplifying the capacitance change. The charge amplifiers and differential amplifiers here should have low noise specifications and, to match the higher carrier frequency and amplification factor, must have a large broadband gain product. Operational amplifiers A1 and A2, and differential amplifier A3 are all low-noise amplifiers.

[0039] The power amplifier circuit for the driving torque coil designed in this example is as follows: Figure 4 The diagram illustrates how the closed-loop control signal from the meter drives the torque coil via a DA converter and a power operational amplifier. Since the output capability of a typical DA converter is insufficient to support the torque current, and DA converters usually employ a unidirectional voltage output, a power operational amplifier with a negative input mode is used, as shown in the diagram. Combined with the negative boosting effect of the reference voltage, this allows the coil drive voltage to be controlled within the range of positive and negative reference voltages.

[0040] The power amplifier circuit includes a reference voltage source, a D / A converter, resistors R3 and R4, and a power operational amplifier A4. The D / A converter is connected to the FPGA. One end of resistor R3 is connected to the reference voltage source, and the other end is connected to the negative input terminal of the power operational amplifier A4. One end of resistor R4 is connected to the negative input terminal of the power operational amplifier A4, and the other end is connected to one end of the meter torque coil and the output terminal of the power operational amplifier A4. The positive input terminal of the power operational amplifier A4 is connected to the output terminal of the D / A converter, and the other end of the meter torque coil is grounded. The reference voltage source provides a reference voltage to the D / A converter and also serves as the negative input of the power operational amplifier A4. Resistors R3 and R4 are matching resistors for the power operational amplifier A4, and their resistance values ​​are equal. Both the D / A converter and the power operational amplifier A4 must be low-noise types.

[0041] The zero-drift amplifier circuit designed in this example is as follows: Figure 5As shown, the voltage across the sampling resistor is sampled and digitally converted with high precision, allowing the torque current to be calculated. To achieve high accuracy, a differential precision A / D converter is required for the second A / D converter. To convert the single-ended signal from the sampling resistor to a differential form, a fully differential amplifier is used, with a fully symmetrical resistor ratio to achieve amplification. Between the high end of the sampling resistor and the fully differential amplifier, a follower circuit consisting of a low-noise, low-drift operational amplifier is designed. This serves two purposes: firstly, the high impedance at the positive input of the follower isolates the measurement circuit from the closed-loop control circuit; secondly, the follower design better ensures the accuracy characteristics of the measurement circuit.

[0042] The zero-drift amplifier circuit includes a zero-drift follower A5, resistors R5, R6, R7, and R8, and a fully differential amplifier A6. The sampling resistor is connected to the positive input of the zero-drift follower A5. The output of the zero-drift follower A5 is connected to one end of resistor R5, and the other end of resistor R5 is connected to the positive input of the fully differential amplifier A6 and one end of resistor R7. The positive output of the fully differential amplifier A6 is connected to the positive input of the second A / D converter and the other end of resistor R7. The negative output of the fully differential amplifier A6 is connected to one end of resistor R8 and the negative input of the second A / D converter. One end of resistor R6 is grounded, and the other end is connected to the other end of resistor R8 and the negative input of the fully differential amplifier A6. The output of the second A / D converter is connected to the FPGA.

[0043] The resistance values ​​of resistors R5, R6, R7, and R8 are equal.

[0044] This example provides two sets of acceleration parameters simultaneously: one is the DA setpoint after closed-loop control, which, through calibration, corresponds to the measured acceleration value; the other is the A / D output value obtained from the sampling resistor current measurement circuit, which, through appropriate scaling factor conversion, corresponds to the same measured acceleration value. Since both quantities are synchronously acquired in the FPGA, a fusion algorithm can be further introduced to produce low-noise, low-drift acceleration parameters in the final output. Because this example primarily demonstrates the circuit design, specific data processing methods are not detailed here.

[0045] Those skilled in the art can readily make various changes and modifications based on the provided textual description, drawings, and claims, without departing from the spirit and scope of the invention as defined by the claims. Any modifications or equivalent variations made to the above embodiments based on the technical concept and essence of the invention fall within the protection scope defined by the claims of this invention.

Claims

1. A digital closed-loop control and measurement circuit for a quartz flexible accelerometer, characterized in that, It includes a differential capacitor carrier demodulation detection circuit, a low-pass filter amplifier circuit and a first A / D converter, an FPGA, a D / A converter, a power amplifier circuit, a sampling resistor, a zero-drift amplifier circuit and a second A / D converter, and also includes a digital output interface circuit; The differential capacitor carrier demodulation detection circuit, low-pass filter amplifier circuit, first A / D converter, FPGA, D / A converter, and power amplifier circuit are connected in sequence to realize low-noise digital closed-loop control. The setting value of the D / A converter can reflect the current acceleration measurement. The sampling resistor, zero-drift amplifier circuit, second A / D converter, and FPGA are connected in sequence to form a zero-drift current measurement circuit for driving the meter torque coil. The measurement value of the second A / D converter can also reflect the current acceleration measurement. The FPGA simultaneously obtains the setting value of the D / A converter and the measurement value of the second A / D converter, calibrates the setting value of the D / A converter to obtain the corresponding acceleration measurement value, and converts the measurement value of the second A / D converter through scaling factor transformation to obtain the same acceleration measurement value. The FPGA incorporates a fusion algorithm to fuse two acceleration measurements and output a low-noise, zero-drift acceleration characterization value. The zero-drift amplifier circuit includes a zero-drift follower A5, resistors R5, R6, R7, and R8, and a fully differential amplifier A6. The sampling resistor is connected to the positive input of the zero-drift follower A5. The output of the zero-drift follower A5 is connected to one end of resistor R5, and the other end of resistor R5 is connected to the positive input of the fully differential amplifier A6 and one end of resistor R7. The positive output of the fully differential amplifier A6 is connected to the positive input of the second A / D converter and the other end of resistor R7. The negative output of the fully differential amplifier A6 is connected to one end of resistor R8 and the negative input of the second A / D converter. One end of resistor R6 is grounded, and the other end is connected to the other end of resistor R8 and the negative input of the fully differential amplifier A6. The output of the second A / D converter is connected to the FPGA. The resistance values ​​of resistors R5, R6, R7, and R8 are equal.

2. The digital closed-loop control and measurement circuit for the quartz flexible accelerometer as described in claim 1, characterized in that, The differential capacitor carrier demodulation detection circuit, the low-pass filter amplifier circuit, and the first A / D converter constitute the differential capacitor measurement circuit. The differential capacitor carrier demodulation detection circuit includes a capacitor readout front-end circuit and an analog switch sample-and-hold circuit connected in sequence. The input terminal of the first A / D converter is connected to the output terminal of the low-pass filter amplifier circuit. The low-pass filter amplifier circuit identifies the phase of the carrier amplitude-modulated wave through the analog switch sample-and-hold circuit. The low-pass filter amplifier circuit is a second-order voltage-controlled voltage source type low-pass filter that filters out the carrier signal. The FPGA is connected to the analog switch in the analog switch sample-and-hold circuit and the first A / D converter, providing analog switch drive signals and digital conversion.

3. The digital closed-loop control and measurement circuit for the quartz flexible accelerometer as described in claim 2, characterized in that, The capacitance reading front-end circuit is used to perform modulation and subtraction of the changes in a pair of differential capacitors, converting the change in the measured capacitance into a voltage change; the differential capacitor With differential capacitor One end is connected to the differential capacitor. The other end is connected to an operational amplifier The inverting input terminal, differential capacitor The other end is connected to an operational amplifier Inverting input terminal; operational amplifier , The non-inverting input terminal of the operational amplifier is grounded; , A feedback capacitor is connected in parallel between the inverting input and the output. Feedback resistor Parallel connection to the feedback capacitor Two ends; operational amplifier Feedback capacitor Feedback resistor Constructing the first charge amplifier, operational amplifier Feedback capacitor Feedback resistor This forms the second charge amplifier; the output of the first charge amplifier is connected to the differential amplifier. The non-inverting input terminal of the first amplifier and the output terminal of the second charge amplifier are connected to the differential amplifier. The inverting input terminal; operational amplifier , Differential amplifier All are low-noise amplifiers.

4. The digital closed-loop control and measurement circuit for the quartz flexible accelerometer as described in claim 1, characterized in that, The power amplifier circuit includes a reference voltage source, a D / A converter, resistors R3 and R4, and a power operational amplifier A4; The D / A converter is connected to the FPGA; One end of resistor R3 is connected to the reference voltage source, and the other end is connected to the negative input terminal of the power operational amplifier A4. One end of resistor R4 is connected to the negative input terminal of the power operational amplifier A4, and the other end is connected to one end of the meter torque coil and the output terminal of the power operational amplifier A4. The positive input terminal of the power operational amplifier A4 is connected to the output terminal of the D / A converter, and the other end of the meter torque coil is grounded. The reference voltage source provides a reference voltage to the D / A converter and also serves as the negative input of the power operational amplifier A4. Resistors R3 and R4 are equal in resistance as matching resistors for the power operational amplifier A4. Both the D / A converter and the power operational amplifier A4 are low-noise types.

5. The digital closed-loop control and measurement circuit for a quartz flexible accelerometer as described in claim 1, characterized in that, The second A / D converter is a differential precision A / D converter.

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