Systems and methods for testing non-volatile memory storage device backplanes

Abstract

The present application discloses a system and method for testing a non-volatile memory storage device backplane, which generates a first signal through a test control device and transmits the first signal to a simulation device through a circuit board (a non-volatile memory storage device backplane) under test, a signal processing element in the simulation device receives the first signal and generates a second signal identical to the first signal, and the signal processing element transmits the second signal to the test control device through the circuit board under test, so that the test control device determines the bit error rate of the second signal. The technical means can use the existing loopback test architecture to test the high-frequency signal of the circuit board and achieve the technical effect of improving the test coverage.

Description

TECHNICAL FIELD

[0001] The present application relates to a test system and method thereof, in particular, to a test system and method thereof for testing a backplane of a non-volatile memory storage device. BACKGROUND

[0002] Industry 4.0, also known as the fourth industrial revolution, is not simply about creating new industrial technologies, but rather about integrating existing industrial technologies, sales processes, and product experiences. Through artificial intelligence technology, it establishes an intelligent factory with adaptability, resource efficiency, and human factors engineering. It integrates customers and business partners in business processes and value streams to provide perfect after-sales service, thus building a new intelligent industrial world with sensory awareness.

[0003] With the wave of Industry 4.0 sweeping the world, manufacturers are transforming production to optimize production and improve competitiveness through intelligent manufacturing. Intelligent manufacturing is based on sensing technology, network technology, automation technology, and artificial intelligence. Through the processes of perception, human-computer interaction, decision-making, execution, and feedback, it realizes the intelligentization of product design and manufacturing, enterprise management and service.

[0004] The characteristics of low profit and fierce competition in the electronic assembly industry make manufacturers pursue more effective control and optimization of raw materials and production tools to maximize the benefits of factory production resources. In the production line of the electronic assembly industry, there must be various circuit board testing links, including testing of circuit boards connected to multiple high-speed storage media.

[0005] Currently, there are two ways to test circuit boards connected to multiple high-speed storage media. One is to connect the circuit board to the real high-speed storage medium and perform actual testing. The other is to use a loopback device containing a loopback circuit to perform signal loopback testing on the circuit board. The first method is the most original way, with the disadvantage of high cost. The second method can greatly reduce costs under certain test coverage, however, as circuit boards gradually need to support PCIe Gen4 / Gen5 specifications, the frequency of signals transmitted on the circuit board increases. However, the architecture of the second method using a loopback device cannot perform high-frequency testing on the circuit board.

[0006] In more detail, in the Gen4 / Gen5 specification, because the loss requirement of the signal is higher, the length of the working circuit on the current circuit board is adjusted to adjust the signal strength during the design of the circuit board, so that the signal passing through the working circuit of the circuit board can meet the Gen4 / Gen5 specification. Therefore, when the second method is used to test the high-frequency signal of the circuit board, the high-frequency signal will be directly sent back to the circuit board by the return circuit when entering the return device. Therefore, the high-frequency signal will pass through the working circuit of the circuit board once, which will increase the length of the circuit through which the high-frequency signal passes by one time, which will increase the loss of the high-frequency signal. Therefore, the high-frequency signal sent into the circuit board again by the return device cannot be correctly identified, and thus the test of the high-frequency signal of the circuit board cannot be completed, which reduces the test coverage rate of the circuit board.

[0007] In summary, it can be seen that the problem of using the return device to test the high-frequency signal of the circuit board has existed for a long time in the prior art. Therefore, it is necessary to propose an improved technical means to solve this problem. SUMMARY

[0008] In view of the problem of using the return device to test the high-frequency signal of the circuit board in the prior art, the present application discloses a system and method for testing the backplane of a non-volatile memory storage device, wherein:

[0009] The system for testing the backplane of a non-volatile memory storage device disclosed by the present application at least comprises: a circuit board to be tested; a test control device connected to the circuit board to be tested, configured to generate a first signal and transmit the first signal to the circuit board to be tested, so that the first signal passes through the circuit board to be tested; an analog device connected to the circuit board to be tested, comprising a signal processing element, the signal processing element being configured to receive the first signal passing through the circuit board to be tested and generate a second signal identical to the first signal, and transmit the second signal to the circuit board to be tested, so that the second signal passes through the circuit board to be tested and is transmitted to the test control device, and the test control device is further configured to receive the second signal and judge the bit error rate (BER) of the second signal to generate a test result of the circuit board to be tested.

[0010] The method for testing the backplane of a non-volatile memory storage device comprises the following steps: connecting a test control device to a circuit board under test and connecting the circuit board under test to a simulation device, the simulation device comprising a signal processing element; the test control device generates a first signal and transmits the first signal to the circuit board under test, so that the first signal is transmitted to the simulation device through the circuit board under test; the signal processing element receives the first signal and generates a second signal identical to the first signal; the signal processing element transmits the second signal to the circuit board under test, so that the second signal is transmitted to the test control device through the circuit board under test; and the test control device receives the second signal and determines the bit error rate of the second signal to generate a test result of the circuit board under test.

[0011] The system and method of the present application differ from the prior art in that the present application generates a first signal by a test control device and transmits the first signal to a simulation device through a circuit board under test, a signal processing element in the simulation device receives the first signal and generates a second signal identical to the first signal, and the signal processing element transmits the second signal to the test control device through the circuit board under test, so that the test control device determines the bit error rate of the second signal, thereby solving the problems existing in the prior art and achieving the technical effect of improving the test coverage. BRIEF DESCRIPTION OF DRAWINGS

[0012] Figure 1 The system architecture diagram for testing the backplane of a non-volatile memory storage device is provided.

[0013] Figure 2A The method flow chart for testing the backplane of a non-volatile memory storage device is provided.

[0014] Figure 2B The method flow chart for testing the continuity of a pin is provided.

[0015] BRIEF DESCRIPTION OF DRAWINGS

[0016] 110 circuit board under test

[0017] 112 connection interface

[0018] 113 connection interface

[0019] 120 simulation device

[0020] 121 signal processing element

[0021] 123 connection interface

[0022] 130 test control device

[0023] 131 signal generating element

[0024] 132 connection interface Detailed Implementation

[0025] The features and implementation methods of the present invention will be described in detail below with reference to the accompanying drawings and embodiments. The content is sufficient to enable any person skilled in the art to easily and fully understand the technical means used by the present invention to solve the technical problem and to implement it accordingly, thereby achieving the effects that the present invention can achieve.

[0026] This invention can replace the existing feedback device with a simulation device and use the simulation device to complete the testing of the circuit board under test. The circuit board under test is usually a non-volatile memory storage device (NVMe). In addition, the testing of the circuit board under test can include all the tests that the feedback device can perform, as well as high-frequency signal testing.

[0027] The following is a preliminary step. Figure 1 The system architecture diagram for testing the backplane of a non-volatile memory storage device proposed in this invention is used to illustrate the system operation of this invention. For example... Figure 1 As shown, the system of the present invention includes a circuit board under test 110, a simulation device 120, and a test control device 130.

[0028] The circuit board under test 110 can be connected to the test control device 130 or the simulation device 120. More specifically, the circuit board under test 110 can be connected to the test control device 130 through the connection interface 112, and the circuit board under test 110 can also be connected to the simulation device 120 through the connection interface 113.

[0029] The circuit board under test 110 contains the operating circuitry to be tested (not shown). Through this operating circuitry, electrical signals can be transmitted between the test control device 130 and the analog device 120. It should be noted that noise and / or signal strength reduction may occur during the transmission of electrical signals through the operating circuitry. Therefore, the operating circuitry must be designed to account for electrical signal loss, ensuring that the electrical signals remain at a correctly identifiable strength when transmitted from the test control device 130 to the analog device 120 or vice versa. In most embodiments, considering cost factors, the electrical signals transmitted from the test control device 130 to the analog device 120 or vice versa typically meet or slightly exceed the minimum specified strength.

[0030] The simulation device 120 can be connected to the circuit board 110 under test, and the simulation device 120 comprises a signal processing element 121. In more detail, the simulation device 120 comprises a connecting circuit (not shown in the figure), which can connect the signal processing element 121 to a connecting interface 123, so that the electrical signal passing through the circuit board 110 under test can reach the signal processing element 121 through the connecting circuit via the connecting interface 113.

[0031] The signal processing element 121 is responsible for receiving a first signal passing through the circuit board 110 under test, and is responsible for generating a second signal identical to the received first signal. The signal processing element 121 can increase the intensity of the first signal to generate the second signal, or can generate the second signal with the same waveform as the first signal according to the waveform of the first signal, but the way the signal processing element 121 generates the second signal is not limited to the above.

[0032] The signal processing element 121 is also responsible for transmitting the generated second signal to the circuit board 130 under test, so that the second signal passes through the circuit board 110 under test and is transmitted to the test control device 130. In more detail, the second signal can be transmitted to the connecting interface 113 of the circuit board 110 under test through the connecting circuit and the connecting interface 123, and can reach the test control device 130 through the working circuit of the circuit board 110 under test and the connecting interface 112.

[0033] The signal processing element 121 can also send the received first signal or the generated second signal back to itself through a loopback circuit, that is, send the first signal or the second signal back to the signal processing element 121. Generally, the length of the loopback circuit is similar to that of the loopback circuit in the loopback device of the prior art, but the present application is not limited thereto.

[0034] The simulation device 120 can also be connected to the test control device 130, and the simulation device 120 can also receive the control signal generated by the test control device 130. For example, the simulation device 120 can be connected to the test control device 130 through a JTAG interface (not shown in the figure), and the JTAG interface can be connected to the signal processing element 121 through a connecting circuit, so that the signal processing element 121 can obtain the control signal generated by the test control device 130, wherein the control signal comprises a receiving control signal and a sending control signal.

[0035] In more detail, the signal processing element 121 can also receive a receiving control signal generated by the test control device 130 through the JTAG interface, and can receive the third signal through the DUT 110 according to the received receiving control signal. The signal processing element 121 can also receive a transmitting control signal generated by the test control device 130 through the JTAG interface, and can transmit the fourth signal generated by the signal processing element 121 to the DUT 110, so that the fourth signal is transmitted to the test control device 130 through the DUT 110.

[0036] The test control device 130 is connected to the DUT 110, and is responsible for generating the first signal and transmitting the first signal to the DUT 110, so that the first signal is transmitted to the test control device 130 through the DUT 110. In more detail, the test control device 130 can be connected to the DUT 110 through the connection interface 132, and can transmit the first signal generated by the test control device 130 to the DUT 110 through the connection interface 132.

[0037] The test control device 130 can include a signal generating element 131, and the signal generating element 131 can generate the first signal. Generally, the first signal generated by the signal generating element 131 is a differential signal. For example, the signal generating element 131 can be an SAS controller or a PCIe controller, but the present application is not limited thereto. In some embodiments, the signal generating element 131 can also include a clock detection logic circuit.

[0038] The test control device 130 is also responsible for receiving the second signal generated by the simulation device 120 and determining the bit error rate (BER) of the second signal at the corresponding characteristic frequency to generate the test result of the DUT 110.

[0039] In some embodiments, the test control device 130 is not limited to determining the bit error rate, and can also select a corresponding detection mode according to the test program being executed, and can generate a corresponding detection result according to the test signal transmitted to the simulation device 120 and the response signal returned by the simulation device 120, and generate a test result including various detection results. For example, the test control device 130 can also determine the continuity of each pin connected to the test control device 130 of the DUT 110, and can generate a corresponding detection result according to the continuity of each pin determined, that is, the test result generated by the test control device 130 can include the detection result of whether each pin connected to the test control device 130 of the DUT 110 is actually connected, in addition to the bit error rate.

[0040] In more detail, the test control device 130 can be connected with the simulation device 120 through the JTAG interface, and can transmit the generated control signal to the simulation device 120 through the JTAG interface. Meanwhile, the test control device 130 can also generate a third signal, and can transmit the generated third signal to the circuit board under test 110, so that the third signal reaches the simulation device 120 through the circuit board under test 110. The test control device 130 can also receive a generated fourth signal, and can determine the open-closed state of each pin of the circuit board under test 110 connected with the test control device 130 according to the received fourth signal to generate a corresponding detection result.

[0041] Next, the operation system and method of the present application are illustrated with an embodiment, and reference is made to Figure 2A The method for testing the backplane of a non-volatile memory storage device according to the present application is shown in a flow chart.

[0042] First, the tester can connect the test control device 130 with the circuit board under test 110 and connect the circuit board under test 110 with the simulation device 120 (step 211). In this embodiment, it is assumed that the test control device 130 and the circuit board under test 110 can be connected through the connection interface 132 of the test control device 130 and the connection interface 112 of the circuit board under test 110, and the circuit board under test 110 and the simulation device 120 can be connected by plugging the simulation device 120 into the connection interface 113 of the circuit board under test 110.

[0043] After connecting the test control device 130 with the circuit board under test 110 and connecting the circuit board under test 110 with the simulation device 120 (step 211), the test control device 130 can generate a first signal and transmit the first signal to the simulation device 120 through the circuit board under test 110, that is, transmit the generated first signal to the circuit board under test 110, so that the first signal is transmitted to the simulation device 120 through the circuit board under test 110 (step 230). In this embodiment, it is assumed that the test control device 130 includes a signal generating element 131, which can generate a PRBS test sequence (first signal) in the form of a high-frequency differential signal after the tester starts the test control device 130, and can transmit the first signal through the connection interface 132 of the test control device 130, so that the first signal sequentially passes through the connection interface 132, the connection interface 112 of the circuit board under test 110, the working circuit, and the connection interface 113 to reach the simulation device 120.

[0044] After the first signal generated by the test control device 130 reaches the analog device 120, the signal processing element 121 of the analog device 120 can receive the first signal and can generate a second signal identical to the received first signal (step 250). In this embodiment, it is assumed that the signal processing element 121 can receive the first signal reaching the analog device 120 through the connection circuit of the analog device 120 and can enhance the signal strength of the received first signal to generate the second signal, redrive the second signal identical to the first signal, or retimer the first signal through a clock checker signal to generate the second signal.

[0045] In practice, the signal processing element 121 of the analog device 120 can transmit the first signal to a loopback circuit connected to the signal processing element 121 of the analog device 120 before receiving the first signal and generating the second signal, so that the first signal is looped back to itself (the signal processing element 121), or can transmit the second signal to the loopback circuit after generating the second signal, so that the second signal is looped back to itself.

[0046] After the signal processing element 121 of the analog device 120 generates the second signal, the signal processing element 121 can transmit the generated second signal to the test control device 130 through the circuit board under test 110, that is, transmit the generated second signal to the circuit board under test 110, so that the second signal is transmitted to the test control device 130 through the circuit board under test 110 (step 260). In this embodiment, it is assumed that the signal processing element 121 can transmit the second signal to the connection interface 123 through the connection circuit of the analog device 120, so that the second signal reaches the test control device 130 in sequence through the connection interface 123, the connection interface 113 and the working circuit of the circuit board under test 110, and the connection interface 112.

[0047] After the second signal generated by the signal processing element 121 of the analog device 120 reaches the test control device 130, the test control device 130 can receive the second signal and can determine the bit error rate of the received second signal, thereby generating a test result corresponding to the circuit board under test 110 (step 270). In this embodiment, it is assumed that the test control device 130 can compare the data represented by the received second signal with the data corresponding to the first signal sent out and can determine the bit error rate of the second signal according to the comparison result, and can generate a test result including the determined bit error rate.

[0048] In this way, through the analog device 130 of the present application, the high-frequency differential signal test that cannot be performed by the loopback device of the prior art can be completed for the circuit board under test 120.

[0049] In the above embodiment, after connecting the test control device 130 with the circuit board under test 110 and connecting the circuit board under test 110 with the simulation device 120 (step 211), before the signal processing element 121 of the simulation device 120 receives the first signal and generates the second signal identical to the received first signal (step 250), the test control device 130 can be connected with the simulation device 120 (step 215) as shown in the flowchart, for example, by connecting the test control device 130 with the JTAG connection interface of the simulation device 120 through a cable. Figure 2B

[0050] After connecting the test control device 130 with the simulation device 120 (step 215), the test control device 130 can execute the corresponding test program according to the current test stage, and select the corresponding detection type according to the executed test program (step 221). When the detection type represents the high-frequency transmission detection (PRBS mode), the test control device 130 can determine the bit error rate of the PRBS test sequence as described above (steps 211-270). When the detection mode represents the pin open-circuit detection (1149.6 mode), the test control device 130 can first generate a receiving control signal, and can transmit the generated receiving control signal to the simulation device 120 through the JTAG connection interface, and can transmit a third signal for testing a specific pin to the circuit board under test 110 through the connection interface 132, so that the third signal reaches the simulation device 120 through the circuit board under test 110. After the signal processing element 121 of the simulation device 120 receives the third signal, it can generate a corresponding fourth signal according to the received third signal (step 225). Then, the test control device 130 can continue to generate a sending control signal, and can transmit the generated sending control signal to the simulation device 120 through the JTAG connection interface. After the signal processing element 121 of the simulation device 120 receives the sending control signal generated by the test control device 130 through the JTAG connection interface, it can generate a fourth signal associated with the third signal according to the received sending control signal, and can transmit the generated fourth signal to the circuit board under test 110 through the connection interface 123, so that the fourth signal reaches the test control device 130 through the circuit board under test 110, or can transmit the fourth signal to the test control device 130 through the JTAG connection interface (step 227).

[0051]

[0052] ​​The test control device 130 can generate a detection result corresponding to the tested pin according to the received fourth signal after receiving the fourth signal. The test control device 130 can repeatedly the above process until the third signal corresponding to all pins is sent and the on-off detection result corresponding to each pin is generated (step 229). Thus, when the test control device 130 generates the test result corresponding to the tested circuit board 110 (step 270), the test control device 130 can generate the test result containing the on-off detection result and the bit error rate.

[0053] In summary, the difference between the present application and the prior art is that the test control device generates the first signal and transmits the first signal to the analog device through the tested circuit board, the signal processing element in the analog device receives the first signal and generates the second signal identical to the first signal, and the signal processing element transmits the second signal to the test control device through the tested circuit board, so that the test control device judges the bit error rate of the second signal. By means of this technical means, the problem that the existing technology cannot test the high-frequency signal of the circuit board using the loopback device can be solved, and the technical effect of improving the test coverage rate is achieved.

[0054] In addition, the method for testing the circuit board using the analog device to generate the same signal according to the present application can be realized in hardware, software or a combination of hardware and software, and can be realized in a centralized manner in a computer system or in a distributed manner with different elements distributed in a plurality of interconnected computer systems.

[0055] Although the embodiments of the present application are disclosed as above, the content described is not used to directly limit the patent protection scope of the present application. Any person skilled in the art of the present application can make some changes and decorations in the form and details of the implementation of the present application without departing from the spirit and scope of the present application. The patent protection scope of the present application shall be subject to the scope defined by the appended claims.

Claims

1. A method for testing a non-volatile memory storage backplane, the method comprising: The connection test control device is connected with the circuit board under test and the simulation device, and the simulation device comprises signal processing elements, wherein, the test control device generating a first signal and transmitting the first signal to the DUT, such that the first signal is transmitted through the DUT; the signal processing element receiving the first signal and generating a second signal identical to the first signal; the signal processing element transmitting the second signal to the DUT, such that the second signal is transmitted through the DUT; and the test control device receiving the second signal and determining a bit error rate of the second signal to generate a test result of the DUT. the signal processing element generating the second signal identical to the first signal further comprises the signal processing element looping the first signal or the second signal back to the signal processing element. the method further comprises the test control device transmitting a receive control signal to the signal processing element and transmitting a third signal through the DUT to the signal processing element, such that the signal processing element receives the third signal according to the receive control signal, and the test control device transmitting a transmit control signal to the signal processing element, such that the signal processing element transmits a fourth signal through the DUT to the test control device according to the transmit control signal, and the test control device generating a continuity test result of all pins of the DUT connected to the test control device according to the fourth signal. the test control device generating the first signal comprises a signal generating element included in the test control device generating the first signal as a differential signal.

2. The method of testing a backplane of a non-volatile memory storage device of claim 1, wherein, the test control device generating the test result of the DUT further comprises the test control device selecting a test mode and generating a corresponding test signal according to the test mode and transmitting the test signal to the analog device, and generating the test result according to a response signal generated by the analog device.

3. The method of testing a backplane of a non-volatile memory storage device of claim 1, wherein, 6. A system for testing a non-volatile memory storage backplane, the system comprising:

4. The method of testing a backplane of a non-volatile memory storage device of claim 1, wherein, the test control device generating a first signal and transmitting the first signal to the DUT, such that the first signal is transmitted through the DUT; the signal processing element receiving the first signal and generating a second signal identical to the first signal; 5. The method of testing a backplane of a non-volatile memory storage device of claim 1, wherein, the signal processing element transmitting the second signal to the DUT, such that the second signal is transmitted through the DUT; and the test control device receiving the second signal and determining a bit error rate of the second signal to generate a test result of the DUT. the signal processing element further loops the first signal or the second signal back to the signal processing element. ​ ​ 7. The system for testing a backplane of a non-volatile memory storage device of claim 6, wherein, ​ 8. The system for testing a backplane of a non-volatile memory storage device of claim 6, wherein, The simulation device is also connected to the test control device, which is also used to transmit a receiving control signal to the signal processing element and transmit a third signal to the signal processing element through the circuit board under test. The signal processing element is also used to receive the receiving control signal transmitted by the test control device, receive the third signal according to the receiving control signal, and receive a transmitting control signal transmitted by the test control device, and transmit a fourth signal to the test control device according to the transmitting control signal, so that the test control device generates the continuity detection result of all pins of the circuit board under test connected to the test control device according to the fourth signal.

9. The system for testing a backplane of a non-volatile memory storage device of claim 6, wherein, The test control device also includes a signal generating element, which is used to generate the first signal of the differential signal.

10. The system for testing a backplane of a non-volatile memory storage device of claim 6, wherein, The test control device is also used to select a detection mode, generate a corresponding test signal according to the detection mode, and transmit the test signal to the simulation device, and generate the test result according to the response signal generated by the simulation device.

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