Data processing method, device, equipment, system and medium for display device

Abstract

The present application discloses a data processing method, device, equipment, system and medium for a display device, the method comprising: receiving a video signal; processing the video signal in a first data delay mode; wherein the processing of the video signal in the first data delay mode comprises: writing the video signal into a memory according to a source timing signal of the video signal; reading the video signal from the memory and sending it to a display panel according to a first output timing signal; for the same frame of video signal, the first output timing signal has a first delay time relative to the source timing signal, and the first delay time is less than the time of a clock cycle of a frame of video signal. This solution can control the first delay time of the output timing signal relative to the source timing signal to be less than the time of a clock cycle of a frame of video signal, effectively reducing the writing delay of the image on the FPGA side and further improving the user experience.

Description

Technical Field

[0001] The present invention generally relates to the field of information processing technology, and in particular to a data processing method, device, equipment, system and medium for a display device. Background Art

[0002] With the continuous development of internet information technology, the demand for remote work has surged, and with it, the demand for electronic whiteboards. Electronic whiteboards are high-tech products developed using cutting-edge electronics, software, and other advanced technologies. By applying the principle of electromagnetic induction and combining computers and projectors, they enable various functions, including paperless office and teaching. However, when using electronic whiteboards based on system-on-chips (SOCs) and field-programmable gate arrays (FPGAs), writing delays can occur. This delay is primarily due to image delays on the SOC and FPGA sides.

[0003] At present, the image processing method on the FPGA side in related technologies is to input a frame of image into the memory before reading it from the memory to output the frame of image. This solution causes the output end to have a timing delay of inputting a frame of image output, that is, the input and output will not operate in the address space of the same frame, resulting in a large writing positioning delay and a poor user experience. Summary of the Invention

[0004] In view of the above-mentioned defects or deficiencies in the prior art, it is desirable to provide a data processing method, device, equipment, system and medium for a display device.

[0005] In a first aspect, an embodiment of the present application provides a data processing method for a display device, the method comprising:

[0006] receiving a video signal;

[0007] processing the video signal in a first data delay mode;

[0008] The step of processing the video signal in the first data delay mode includes:

[0009] Writing the video signal into the memory according to the source timing signal of the video signal;

[0010] Reading the video signal from the memory and sending it to the display panel according to the first output terminal timing signal;

[0011] For the same frame of video signal, the first output end timing signal has a first delay time relative to the source end timing signal, and the first delay time is less than the clock cycle time of one frame of video signal.

[0012] In a second aspect, the present application provides a data processing device for a display device, the device comprising:

[0013] A receiving module, configured to receive a video signal;

[0014] a processing module, configured to process the video signal in a first data delay mode;

[0015] The processing module includes:

[0016] A writing unit, configured to write the video signal into the memory according to a timing signal from a source end of the video signal;

[0017] a reading unit, configured to read the video signal from the memory and send the video signal to the display panel according to the first output terminal timing signal;

[0018] For the same frame of video data, the first output end timing signal has a first delay time relative to the source end timing signal, and the first delay time is less than the clock cycle time of one frame of video signal.

[0019] In a third aspect, an embodiment of the present application provides an electronic device comprising a processor and a memory, wherein the processor is configured to execute the data processing method for the display device according to the first aspect.

[0020] In a fourth aspect, an embodiment of the present application provides a data processing system for a display device, the system comprising a first processor, a second processor, and a display panel, wherein the first processor is connected to the second processor and the display panel respectively;

[0021] The second processor is used to send a video signal to the first processor;

[0022] The first processor is configured to receive a video signal and process the video signal in a first data delay mode. The processing of the video signal in the first data delay mode includes: writing the video signal into a memory according to a source timing signal of the video signal; reading the video signal from the memory and sending the video signal to a display panel according to a first output timing signal. For a same frame of the video signal, the first output timing signal has a first delay time relative to the source timing signal, and the first delay time is less than a clock period of one frame of the video signal.

[0023] The display panel is used to receive the video signal sent by the first processor and process the video signal to display a corresponding video image.

[0024] In a fifth aspect, an embodiment of the present application provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program is used to implement the data processing method for the display device according to the first aspect above.

[0025] The data processing method, apparatus, device, system, and medium for a display device provided in the embodiments of the present application receive a video signal, process the video signal in a first data delay mode, write the video signal to a memory according to a source timing signal of the video signal, and read the video signal from the memory and send it to a display panel according to a first output timing signal. For the same frame of video signal, the first output timing signal has a first delay time relative to the source timing signal, and the first delay time is less than the time of a clock cycle of a frame of video signal. This technical solution can control the first delay time of the output timing signal relative to the source timing signal to be less than the time of a clock cycle of a frame of video signal, thereby effectively reducing the image writing delay on the FPGA side and further improving the user experience. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Other features, objects and advantages of the present application will become more apparent upon reading the detailed description of non-limiting embodiments made with reference to the following drawings:

[0027] Figure 1 A schematic diagram of the structure of a data processing system for a display device provided in an embodiment of the present application;

[0028] Figure 2 A schematic diagram of the structure of a data processing system for a display device provided in an embodiment of the present application;

[0029] Figure 3 A schematic diagram of the structure of a data processing system for a display device provided in an embodiment of the present application;

[0030] Figure 4 A schematic flow chart of a data processing method for a display device provided in an embodiment of the present application;

[0031] Figure 5 A schematic diagram of the organizational structure of the video signal provided in an embodiment of the present application;

[0032] Figure 6 A schematic flow chart of a data processing method for a display device provided in an embodiment of the present application;

[0033] Figure 7 A timing diagram of the comparison between the source data valid signal and the output data valid signal provided in an embodiment of the present application;

[0034] Figure 8 A timing diagram of the comparison between the valid signal of the source data and the valid data of the output end provided in an embodiment of the present application;

[0035] Figure 9 A schematic flow chart of a data processing method for a display device provided in an embodiment of the present application;

[0036] Figure 10 A timing diagram for comparing the embodiment of the present application with a conventional solution;

[0037] Figure 11 A timing diagram of the source data valid signal, the output data valid signal, and the backlight timing signal provided in an embodiment of the present application;

[0038] Figure 12 A schematic structural diagram of a data processing device for a display device provided in an embodiment of the present application;

[0039] Figure 13 A schematic diagram of the structure of a computer system shown in an embodiment of the present application. DETAILED DESCRIPTION

[0040] The present application will be further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely for the purpose of explaining the relevant invention and are not intended to limit the invention. It should also be noted that, for ease of description, only portions relevant to the invention are shown in the accompanying drawings.

[0041] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments in this application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0042] It is understandable that with the rapid development of Internet information technology, display devices such as smart interactive tablets are being used in a variety of information interaction fields, such as education and teaching, video conferencing, multi-person discussions, and other scenarios. Smart interactive tablets generally refer to display devices with touch interaction functions, such as electronic whiteboards and smart blackboards. They are high-tech products that integrate electronic, software, and communication technologies. According to the different touch technology principles, they can be divided into infrared touch, capacitive touch, electromagnetic, etc. With the development of technology and the diverse needs of users, the integration of dynamic backlight adjustment technology in smart interactive tablets can achieve the advantages of high contrast, reduced power consumption, and reduced light radiation.

[0043] However, in order to achieve regional adjustment of the backlight, the smart interactive tablet needs to add a programmable logic device FPGA on the basis of the system-on-chip SOC, and realize backlight control and pixel compensation through the FPGA. However, since the FPGA needs to store a frame of image during the backlight control and pixel compensation process to complete the backlight statistics and pixel compensation, that is to say, when adding an FPGA to the smart interactive tablet product to adjust the backlight area, the output of the image will be delayed by at least one frame, which will cause additional writing delays when using the electronic whiteboard. Since the FPGA side needs to continuously maintain the link status with the VBO of the external logic board (Timer Control Register, TCON), it needs to use the local clock signal, and the FPGA side image needs to enter the memory to isolate the error caused by the source clock and the local clock. Therefore, how to reduce the operation delay of the electronic whiteboard is an urgent problem to be solved.

[0044] The writing delay of the smart interactive tablet is mainly reflected in the delay of the image on the SOC side and the delay of the image on the FPGA side. As mentioned in the relevant technology, the image is processed on the FPGA side by writing a frame of image to the memory before reading it from the memory to output the frame of image. This solution causes the output end to input a frame of image output with a timing delay, that is, the input and output will not operate in the address space of the same frame, resulting in a large writing positioning delay and a poor user experience.

[0045] Based on the above-mentioned defects, the present application provides a data processing method, device, equipment, system and medium for a display device. Compared with the related art, this method can control the first delay time of the output end timing signal relative to the source end timing signal to be less than the clock cycle time of one frame of video signal, thereby effectively reducing the image writing delay on the FPGA end and further improving the user experience.

[0046] The data processing method for a display device provided in the embodiment of the present application can be used in Figure 1 The data processing system of the display device is shown.

[0047] like Figure 1 As shown, the data processing system of the display device includes a first processor 10, a second processor 20 and a display panel 30, wherein the first processor 10 is connected to the second processor 20 and the display panel 30 respectively.

[0048] The first processor 10 is configured to receive a video signal transmitted by the second processor 20, perform backlight zone adjustment, and then transmit the signal to the display panel 30. The first processor 10 may include an FPGA chip. Upon receiving the video signal, the backlight zone adjustment process may include processing the video signal in a first data delay mode, including: writing the video signal to a memory based on a source timing signal of the video signal; and reading the video signal from the memory based on a first output timing signal and transmitting the signal to the display panel. For the same frame of the video signal, the first output timing signal has a first delay relative to the source timing signal.

[0049] The second processor 20 is configured to send a video signal to the first processor 10 , wherein the second processor may include a SOC system chip.

[0050] The display panel 30 is configured to receive the video signal sent by the first processor 10 and process the video signal to display a corresponding video image.

[0051] Further, see Figure 2 As shown, Figure 2 This is a structural diagram of a data processing system for a display device provided in another embodiment of the present application. The above-mentioned system may include an FPGA chip 100, a THINE module 300, a display panel 30, and a SOC system chip 200, wherein the THINE module 300 is respectively connected to a first end of the FPGA chip 100 and one end of the SOC system chip 200, the second end of the FPGA chip 100 is connected to the other end of the SOC system chip 200, and the third end of the FPGA chip 100 is connected to the display panel 30.

[0052] The SOC system chip 200 is a product formed by combining multiple integrated circuits with specific functions on a single chip. It is used to generate a first format signal through data processing. The first format signal can be a V-By-One (VBO) signal. In high-definition display products, due to bandwidth issues, the video signal needs to be divided into multiple signals for separate transmission. Moreover, due to wiring reasons, etc., the signal delay of each video signal may be different. Therefore, the clock domain of each video signal is not exactly the same. Through SOC processing, independent multiple VBO signals can be obtained, and each VBO signal is sent to the THINE module 300. VBO is a standard digital interface technology for image information transmission that can support 4.0Gbps high-speed signal transmission and is widely used in the field of ultra-high-definition liquid crystal displays.

[0053] The above-mentioned SOC system chip 200 is also used to send control instructions to the FPGA chip 100. The control instructions may include a first control instruction and a second control instruction. It should be noted that the first control instruction is a control instruction for setting the display device to writing mode, and the second control instruction is a control instruction for setting the display device to normal mode.

[0054] The above-mentioned THINE module 300 is an interface chip, which may include multiple THINE chips, for example, four THINE chips, namely THINE_1, THINE_2, THINE_3, and THINE_4. Each THINE chip is used to receive each first format signal sent by the SOC system chip 200, and convert and process each received first format signal into a corresponding second format signal, and then send each second format signal to the FPGA chip 100. Among them, the first format signal can be a VBO signal, and the second format signal is a low voltage differential (LVDS) signal. For example, when four VBO signals are received, each VBO signal can be converted into an LVDS signal by chips such as THINE_1, THINE_2, THINE_3, and THINE_4, and sent to the FPGA chip.

[0055] The FPGA chip 100 is used to synchronously process the received second format signals into a single video signal and write the video signal into a memory according to the source timing signal of the video signal, and then read the video signal from the memory according to the first output timing signal and send it to the display panel, wherein, for the same frame of video signal, the first output timing signal has a first delay time relative to the source timing signal, and the first delay time is less than the clock cycle time of one frame of video signal. It should be noted that the source timing signal refers to the signal corresponding to the video signal in the clock domain, which may include a frame synchronization signal, a field synchronization signal, and a data valid signal, etc. The clock cycle time of one frame of video signal refers to the time length from the first rising edge to the next rising edge of the frame synchronization signal, or the time length from the first falling edge to the next falling edge of the frame synchronization signal.

[0056] Please continue to see Figure 2As shown, the data processing system of the display device further includes a memory 40 and a system clock signal source 50. The memory 40 is connected to the fourth terminal 100 of the FPGA chip, and the system clock signal source 50 is connected to the fifth terminal of the FPGA chip 100. The memory can be DDR (Double Data Rate Synchronous Dynamic Random Access Memory), such as DDR3, for reading and writing video signals. It can be made of semiconductor devices and can transmit data twice within one clock cycle, characterized by a fast data reading rate. The system clock signal source is typically composed of a positive feedback oscillation circuit consisting of a quartz crystal oscillator and a NAND gate, and is used to provide a first output timing signal to the FPGA chip. The first output timing signal is, for example, OSC_CLK, which is a corresponding local clock signal generated by the system clock signal source at the local end.

[0057] Further, see Figure 3 As shown, Figure 3 This is a system structure diagram of a data processing system for a display device according to another embodiment of the present application. The FPGA chip may include virtual modules such as LVDS_RX, SYNC, WDMA, RDMA, AXI_INTERCONNECT, VS_DET, DLY, VTG, CLK_DET, VBO_TX, IIC, and COM_DET. Among them, one end of each LVDS_RX is respectively connected to one end of each THINE, the other end of each LVDS_RX is connected to one end of SYNC, the other end of SYNC is respectively connected to one end of WDMA, one end of VS_DET, and the first end of CLK_DET, the second and third ends of CLK_DET are respectively connected to the first end of DLY and one end of OSC_CLK, the other end of OSC_CLK is connected to the first end of VTG, the second and third ends of DLY are respectively connected to the second end of VTG and the other end of VS_DET, the other end of WDMA is connected to the first end of AXI_INTERCONNECT, the second and third ends of AXI_INTERCONNECT are respectively connected to the memory DDR3 and the first end of RDMA, the second and third ends of RDMA are respectively connected to the third end of VTG and one end of VBO_TX, the other end of VBO_TX is connected to the display panel PANEL, one end of the IIC module is connected to the SOC, the other end of the IIC module is connected to one end of the COM_DET module, and the other end of the COM_DET module is connected to the fourth end of the DLY module.

[0058] Among them, the above-mentioned LVDS_RX is an LVDS signal receiving module, which is used to receive the LVDS signal sent by the THINE module. The LVDS_RX module may include LVDS_RX_1, LVDS_RX_2, LVDS_RX_3, and LVDS_RX_4, which are used to receive the corresponding LVDS signal of each channel and send each LVDS signal to the SYNC module; the above-mentioned SYNC module is used to synchronize the LVDS signals of each channel to obtain a video signal, and send the video signal to the WDMA module; the above-mentioned WDMA module is used to write the video signal into the memory DDR3; the above-mentioned RDMA module is used to read the video signal from the memory DDR3; the above-mentioned AXI_INTERCONNECT module is an AXI bus arbitration module, which is used to determine the execution direction when a read request or a write request to the memory DDR3 arrives at the same time, and coordinate the write control request and the read control request to avoid data reading and writing confusion. The VS_DET module is used to detect the frame synchronization signal corresponding to the video signal after synchronization processing from the SYNC module; the CLK_DET module is a clock detection module, which is used to obtain the video signal after synchronization processing from the SYNC module, and obtain the output timing signal through the OSC_CLK module, and detect the difference between the source timing signal and the output timing signal, determine the delay parameter and send it to the DLY module; the IIC module is used to receive the control instruction sent by the SOC and send the control instruction to the COM_DET module, and the control instruction carries scene mode information; the COM_DET module is used to parse the received control instruction and determine the scene mode information, which includes writing mode information and normal mode information;

[0059] The above-mentioned DLY module is a delay module, which is used to determine the delay parameter and send it to the VTG module according to the scene mode information. The delay parameters corresponding to the writing mode and the normal mode are different. When the scene mode information is the writing mode, the delay parameter may include the first delay time of the first output end timing signal relative to the source end timing signal. When the scene mode information is the normal mode, the delay parameter may include the third delay time of the second output end timing signal relative to the source end timing signal, wherein the first delay time is less than the clock cycle time of one frame of video signal, and the third delay time is greater than or equal to the clock cycle time of one frame of video signal; the above-mentioned VTG module is used to send the delay parameter to the RDMA module to read the video signal from the memory through the RDMA module according to the delay parameter; the RDMA module is also used to send the read video signal to the VBO_TX module; the VBO_TX module is a v-by-one sending module, which is used to convert the read video signal into a VBO signal and send it to the display panel PANEL.

[0060] For ease of understanding and explanation, the following Figures 4 to 13The data processing method, device, equipment, system and medium of the display device provided in the embodiments of the present application are described in detail.

[0061] Figure 4 The figure shows a flow chart of a data processing method for a display device according to an embodiment of the present application. The method can be applied to a data processing device for an electronic whiteboard, and can be implemented as part or all of a processing device for a display device through software, hardware, or a combination of software and hardware. Figure 4 As shown, the method includes:

[0062] S101: Receive a video signal.

[0063] S102: Process the video signal in a first data delay mode.

[0064] The step of processing the video signal in the first data delay mode includes:

[0065] S1021. Write the video signal into the memory according to the source timing signal of the video signal.

[0066] In this step, the system chip can obtain scene mode information of the display device by detecting whether a touch screen operation is performed on the display panel. When a touch screen operation is detected, the scene mode information is determined to be writing mode. If no touch screen operation is detected, the scene mode information is determined to be normal mode, which is a non-writing mode, such as movie viewing mode or TV mode. For example, when using a display device such as a smart interactive whiteboard, the user can click on the writing software icon to launch the writing software, thereby determining that the scene mode information is writing mode.

[0067] After acquiring the scene mode information, the SOC chip sends a first control instruction to the FPGA chip, causing the FPGA chip to perform a corresponding operation according to the first control instruction. The first control instruction is a control instruction for setting the display device to writing mode. After receiving the first control instruction, the FPGA chip parses the first control instruction to obtain a parsing result. If the parsing result indicates that the scene mode information is writing mode, the FPGA chip determines to process the video signal in the first data delay mode.

[0068] Specifically, the SOC system chip generates each first-format signal and sends it to the THINE module. After receiving each first-format signal, the THINE module can convert the received first-format signals into corresponding second-format signals. Each second-format signal is then sent to the FPGA chip, which synchronizes the source timing signals of each second-format signal to obtain a single-channel video signal and writes the video signal to the memory. The first-format signal can be a VBO (V-By-One) signal, and the second-format signal can be an LVDS signal. The above-mentioned VBO signals can be three or four channels.

[0069] It should be noted that the above-mentioned LVDS is a low-voltage, differential signal transmission solution and a low-swing differential signal technology. It can also be understood as a transmission protocol that enables signals to be transmitted at a rate of several hundred Mbps on differential PCB line pairs or balanced cables.

[0070] Among them, when receiving four-way VBO signals sent by SOC, the four-way VBO signals can be converted into four corresponding LVDS signals, and then the source timing signals of the four-way LVDS signals are synchronized to obtain a single-way video signal. Since the four-way LVDS signals are independent timing signals, the LVDS signal is a video signal transmitted based on the LVDS transmission protocol, which may include a data valid signal (Data Enable, DE), a frame synchronization signal and a field synchronization signal. Different LVDS signals may have timing errors due to wiring reasons. By synchronizing the four-way LVDS signals, the resolution of each LVDS signal is 960*2160, and a single-way video signal can be obtained. The organization form of the single-way video signal can be seen in Figure 5 As shown, its resolution can be 3840*2160. For example, when there is a timing error in the received LVDS signal, such as when the first LVDS signal is input half a line ahead of the second LVDS signal, during the synchronization process, in order to strictly align the timing of the output signals, it is necessary to delay the output of the first LVDS signal by half a line, thereby ensuring that all four signals can be received by the SYNC synchronization module, and then output a single video signal with the same timing. After the video signal is obtained, the video signal can be written to the memory, which can be, for example, DDR.

[0071] While writing the source video signal into the memory, backlight data can also be counted. The backlight data is used to light up the display panel. The backlight data may include brightness, light-emitting position, etc.

[0072] S1022: Read the video signal from the memory and send it to the display panel according to the first output-end timing signal. For the same frame of the video signal, the first output-end timing signal has a first delay time relative to the source-end timing signal, and the first delay time is less than a clock period of one frame of the video signal.

[0073] As an implementable manner, the above-mentioned source end timing signal includes: a source end data valid signal, the source end data valid signal includes a first valid time t1; the first output end timing signal includes: an output end data valid signal, the output end data valid signal includes a second valid time t3.

[0074] When the first effective time t1 is greater than the second effective time t3, the first delay time t 4-1 The value range of is:

[0075] t1–t3≤t 4-1 ≤t0–t3;

[0076] Wherein, t0 is the clock cycle time of the valid signal of the data at the source end of an input frame, t1 is the first valid time of the valid signal of the data at the source end, and t3 is the second valid time of the valid signal of the data at the output end.

[0077] It should be noted that the first valid time is the time corresponding to when the source data valid signal is at a high level, and the second valid time is the time corresponding to when the output data valid signal is at a high level. The source data valid signal may include a first valid time and a first blanking time. The first blanking time is the time corresponding to when the source data valid signal is at a low level. The FPGA chip may transfer data to the memory during the first valid time, i.e., it may write data to the memory, and may not transfer data to the memory during the first blanking time.

[0078] When the first effective time t1 is less than or equal to the second effective time t3, the first delay time t 4-1 The value range of is:

[0079] 0 <t 4-1 ≤t0–t3;

[0080] Wherein, t0 is the time of a clock cycle of a valid data signal at the input frame source end, and t3 is the second valid time of the valid data signal at the output end.

[0081] It should be noted that the above-mentioned first delay time can be determined by counting and comparing the source data valid signal with the output data valid signal within the input frame period after the product is powered on. It can be determined by counting once after power-on. Of course, multiple delay times can also be determined after counting the source data valid signal and the output data valid signal multiple times, and the multiple delay times are averaged to determine the delay time. This embodiment does not limit the number of counts. Optionally, in actual application, the above-mentioned first delay time can be pre-set in the product according to relevant parameters, and the relevant parameters include the first count value of the source data valid signal, the second count value of the output data valid signal, and the effective count value of the source data valid signal and the output data valid signal. When the display device is in writing mode, the video signal can be directly read from the memory according to the first delay time to effectively reduce the writing delay.

[0082] Optionally, as an implementable method, based on the above embodiment, as Figure 6 As shown, the above-mentioned counting and comparing of the source end data valid signal and the output end data valid signal to determine the first delay time may include the following steps:

[0083] S201: Count pixel clocks of a valid source data signal to obtain a first count value.

[0084] S202: Count the pixel clocks of the output-end data valid signal to obtain a second count value.

[0085] S203: Compare the first count value and the second count value to obtain a comparison result.

[0086] S204: Determine a first delay time, a first number of delayed rows, or a second number of delayed rows according to the comparison result.

[0087] Specifically, by counting the source data valid signal and the output data valid signal, the first count value, the second count value, the valid count value and the time of the clock cycle of the input frame data valid signal can be obtained, wherein the time of the clock cycle of the input frame data valid signal is recorded as t0, the first count value is recorded as vtt1, the second count value is recorded as vtt2, and the valid count values ​​corresponding to the source data valid signal and the output data valid signal are both vact. And the first valid time of the source data valid signal can be recorded as t1, the first blanking time of the source data valid signal can be recorded as t2, the second valid time of the output data valid signal can be recorded as t3, and the second blanking time of the output data valid signal can be recorded as t4. Among them, the second blanking time t4 can be composed of two parts, one part is the first delay time t 4-1 , the other part is the delay time t 4-2 ,t4=t 4-1 +t4-2 , and at the same time satisfying t0=t1+t2=t3+t4.

[0088] It should be noted that because the source timing signal and the output timing signal are essentially clocks from different sources, an error between the pixel clocks is unavoidable, resulting in a difference between the first count value and the second count value. Furthermore, because the output timing signal is triggered by the source timing signal, it is generally necessary to ensure that the cycle time of the source timing signal is equal to the cycle time of the output timing signal, that is, t0 = t1 + t2 = t3 + t4 must be satisfied.

[0089] In this embodiment, the first count value is the number of pixel clocks corresponding to the source data valid signal, and the second count value is the number of pixel clocks corresponding to the output data valid signal. The effective count value is the number of pixel clocks corresponding to the valid time of the source data valid signal and the output data valid signal. The valid time corresponds to the time when the source data valid signal and the output data valid signal are at a high level. The first blanking time is the time when the source data valid signal is at a low level. The second blanking time is the time when the output data valid signal is at a low level.

[0090] In this step, the first effective time, the second effective time, the first blanking time, and the second blanking time can be expressed by the following formulas respectively:

[0091] t1=t0*(vact / vtt1);

[0092] t2 = t0 – t1;

[0093] t3 = t0 * (vact / vtt2);

[0094] t4 = t0 – t3;

[0095] Where t1 is the first valid time of the source data valid signal; t2 is the first blanking time of the source data valid signal; t3 is the second valid time of the output data valid signal; t4 is the second blanking time of the output data valid signal; t0 is the clock cycle of the source data valid signal in one input frame; vtt1 is the first count value; vtt2 is the second count value; and vact is the valid count value of the source data valid signal and the output data valid signal. It should be noted that since the source and output transmit the same data but differ only in the clock domain, the valid count values ​​of the source data valid signal and the output data valid signal are the same.

[0096] After determining the first count value and the second count value, a comparison result of the first count value and the second count value can be determined, and a valid count value can be obtained. Then, a first delay time can be determined based on the valid count value, the first count value, the second count value, and the comparison result. The comparison result is determined by determining whether the first count value is less than the second count value. When the comparison result indicates that the first count value is less than the second count value, the first delay time is calculated based on the first count value, the second count value, and the valid count value.

[0097] For details, see Figure 7 As shown, Source Dat represents the valid signal of the source data, and Sink Dat represents the valid signal of the output data. When Source Dat is high, it means that the video signal is being written into the memory; when Sink Dat is high, it means that the video signal is being read from the memory. When the first count value vtt1 is less than the second count value vtt2, since t1 = t0 * (vact / vtt1), t3 = t0 * (vact / vtt2), the first valid time is greater than the second valid time. In order to ensure that the valid data of the output data valid signal is delayed after the valid data of the source data valid signal, the first delay time t can be determined. 4-1 The value range is t1–t3≤t 4-1 ≤t0–t3, e.g. Figure 7 The left side of the figure shows the first delay time t 4-1 The minimum value indicates that the falling edge of Source Dat should be aligned with the falling edge of Sink Dat. The first delay time t is shown in the figure on the right. 4-1 The maximum value indicates that Sink Dat needs to be aligned with the rising edge of the next Source Dat, so that the minimum value of the first delay time and the maximum value of the first delay time corresponding to the clock cycle of a frame of video signal can be determined. The minimum value of the first delay time can be expressed by the following formula:

[0098] t 4-1 =t1–t3=t0*(vact / vtt1)-t0*(vact / vtt2)

[0099] =t0*(vact / vtt1–vact / vtt2)

[0100] The maximum value of the first delay time corresponding to the clock cycle of one frame of video signal can be expressed by the following formula:

[0101] t 4-1 =t0–t3=t0*(1–vact / vtt2);

[0102] Among them, t 4-1is the first delay time; t0 is the clock cycle time of the valid data signal at the input frame source; vtt1 is the first count value of the valid data signal at the source; vtt2 is the second count value of the valid data signal at the output; and vact is the valid count value. It is understood that the maximum value of the first delay time can be infinite.

[0103] Optional, see Figure 8 As shown, when the comparison result indicates that the first count value is greater than the second count value, the first delay time is calculated based on the first count value, the second count value, the effective count value and the time of the clock cycle of the valid signal of the data at the source end of the input frame. That is, when the first count value vtt1 is greater than or equal to the second count value vtt2, the first effective time t1 is less than or equal to the second effective time t3. In order to ensure that the effective data of the output end data valid signal is delayed after the effective data of the source end data valid signal, the first delay time t 4-1 The value range is 0 <t 4-1 ≤t0–t3, in Figure 8 The left diagram shows the first delay time t 4-1 The minimum value indicates that the rising edge of Sink Dat should be aligned with the rising edge of Source Dat. The first delay time t is determined in the figure on the right. 4-1 The maximum value indicates that Sink Dat needs to be aligned with the rising edge of the next Source Dat. Thus, the first delay time t can be determined. 4-1 The minimum value of is 0. The first delay time t corresponding to the clock cycle of a frame of video signal 4-1 The maximum value can be expressed by the following formula:

[0104] t 4-1 =t0–t3=t0*(1–vact / vtt2);

[0105] Among them, t 4-1 is the first delay time; t0 is the clock cycle time of the valid data signal at the input frame source; vtt1 is the first count value of the valid data signal at the source; vtt2 is the second count value of the valid data signal at the output; and vact is the valid count value. It is understood that the maximum value of the first delay time can be infinite.

[0106] Furthermore, since the video signal is read from the memory in units of lines, it is necessary to determine a first number of delayed lines. Based on the first number of delayed lines, the video signal can be read from the memory and sent to the display panel. For the same frame of video signal, the first number of delayed lines is the number of lines delayed in reading the video signal from the memory relative to storing the video signal in the memory.

[0107] When the first count value vtt1 is less than the second count value vtt2, that is, the first effective time t1 is greater than the second effective time t3, assuming that the value of the delayed pixel clock is vtt and the value of the pixel clock of each row is htt, the following formula can be obtained:

[0108] L0=vtt / htt;

[0109] Then, based on the mapping relationship between time and the number of pixel clock values, the following formula can be obtained:

[0110] t 4-1 / t0=vtt / vtt1;

[0111] Since t1–t3≤t 4-1 ≤t0–t3, so the range of the first delay line number L0 can be obtained as:

[0112] {[(t1-t3)*vtt1] / (t0*htt)}+L1≤L0≤[(t0–t3)*vtt1] / (t0*htt);

[0113] Among them, htt is the value of the pixel clock per row, vtt1 is the first count value of the source data valid signal, L1 is the margin added to the number of rows, t0 is the clock cycle time of the source data valid signal of an input frame, t1 is the first valid time of the source data valid signal, and t3 is the second valid time of the output data valid signal.

[0114] It should be noted that, in the actual application process of reading the video signal from the memory, the value of the first delayed line number L0 needs to be rounded up. For example, when the calculated first delayed line number is 7.3, the actual delayed line number is 8.

[0115] It is understandable that, considering that when actually reading and writing in the memory DDR, it is necessary to pass through a cache, and then read and write to the DDR from the cache, because the actual reading and writing rate to the DDR is much higher than the reading and writing rate in the cache, the actual reading and writing of video data to the DDR is in units of lines, and in the actual reading and writing process, reading and writing are performed in units of n lines, so it is necessary to increase the number of lines to add margin. The number of lines to add margin L1 = n, n can be customized according to actual conditions, for example, n can be 4, for example, video data is stored in the cache according to the frame synchronization signal, and after 4 lines are stored in the cache, the 4 lines of data are written to the DDR, and the rate of writing the 4 lines to the DDR is much higher than the rate of storing data in the above-mentioned cache. Therefore, when calculating the number of delayed lines, in order to ensure that the reading of data in the DDR is later than the writing of data, the number of lines to add margin must be increased. The number of lines to add margin is equal to the number of lines of data read and written from the cache to the DDR each time.

[0116] Therefore, the minimum value for determining the first delayed number of lines for reading the video signal from memory is:

[0117] L0={[(t1-t3)*vtt1] / (t0*htt)}+L1;

[0118] Among them, vtt1 is the first count value of the source data valid signal, L1 is the row number plus margin, t0 is the time of the clock cycle of the source data valid signal of an input frame, t1 is the first valid time of the source data valid signal, and t3 is the second valid time of the output data valid signal.

[0119] Specifically, 4-1 / t0=vtt / vtt1=vact / vtt1–vact / vtt2;

[0120] We further obtain: vtt = vtt1*(vact / vtt1–vact / vtt2);

[0121] Therefore, the minimum value of the first delay line number L0 can be expressed by the following formula:

[0122] L0={[(t1-t3)*vtt1] / (t0*htt)}+L1

[0123] =(vtt1 / htt)*(vact / vtt1–vact / vtt2)+L1;

[0124] The maximum value of the first delayed row number L0 is expressed by the following formula:

[0125] L0=[(t0–t3)*vtt1] / (t0*htt);

[0126] =(vtt1 / htt)*(1–vact / vtt2)

[0127] Among them, vtt1 is the first count value of the valid signal of the source data, L1 is the margin added to the number of rows, htt is the number of pixel clocks per row, vtt2 is the second count value of the valid signal of the output data, and vact is the valid count value.

[0128] Optionally, the video signal can be read from the memory and sent to the display panel according to the second delayed line number; wherein, for the same frame of video signal, the second delayed line number is the number of lines delayed in reading the video signal from the memory relative to storing the video signal in the memory.

[0129] When the first count value vtt1 is greater than or equal to the second count value vtt2, that is, the first effective time t1 is less than or equal to the second effective time t3, it should be noted that in actual application, since the source-end timing signal and the output-end timing signal are essentially non-isochronous clocks, an error between the pixel clocks is inevitably generated, and the first count value and the second count value are not equal, that is, the first effective time and the second effective time are also not equal.

[0130] Assuming that the number of delayed pixel clocks is vtt, the number of pixel clocks per row is htt, and based on the mapping relationship between time and the number of pixel clocks, the following formula can be obtained:

[0131] t 4-1 / t0=vtt / vtt1;

[0132] L0=vtt / htt;

[0133] Due to 0 <t 4-1 ≤t0–t3, so we can get

[0134] The range of the second delay line number L2 is:

[0135] 0+L1 <L2≤[(t0–t3)*vtt1] / (t0*htt);

[0136] Among them, t0 is the time of the clock cycle of the valid signal of the data at the source end of an input frame, t3 is the second valid time of the valid signal of the data at the output end, htt is the value of the pixel clock per row, vtt1 is the first count value of the valid signal of the data at the source end, and L1 is the margin added for the number of rows.

[0137] From the above formula, we can know that the minimum value of the second delay line number L2 is L1, and the maximum value of the second delay line number L2 can be expressed by the following formula:

[0138] L2=[(t0–t3)*vtt1] / (t0*htt);

[0139] =(vtt1 / htt)*(1–vact / vtt2);

[0140] Among them, vtt1 is the first count value of the valid signal of the source data, L1 is the margin added to the number of rows, htt is the number of pixel clocks per row, vtt2 is the second count value of the valid signal of the output data, and vact is the valid count value.

[0141] Specifically, after determining the first or second number of delayed lines, the first or second number of delayed lines can be used as the value of the lines to be delayed. The frame synchronization signal of the detected video signal is then counted by detecting the rising edge. After delaying the lines corresponding to the first or second number of delayed lines, the video signal is read from the memory and processed to obtain a first format signal to be transmitted. The first format signal to be transmitted is then sent to the display panel, so that the display panel processes the first format signal to display the corresponding video image. The video signal read from the memory can be an LVDS format signal, and the first format signal can be a VBO signal.

[0142] For example, see Figure 9 As shown, the THINE_1 module, THINE_2 module, THINE_3 module, and THINE_4 module can receive each VBO signal sent by the SOC, and convert each VBO signal into a corresponding LVDS signal and send it to the corresponding LVDS_RX_1 module, LVDS_RX_2 module, LVDS_RX_3 module, and LVDS_RX_4 module. The LVDS_RX module receives each LVDS signal and sends it to the SYNC module. The SYNC module synchronizes each LVDS signal to obtain a single video signal and sends it to the WDMA module. The WDMA module writes the video signal into the memory. Then, the source timing signal of the video signal is determined, and the source timing signal includes a source data valid signal. The first output timing signal includes an output data valid signal, and the source data valid signal is compared with the output data valid signal within an input frame period. According to the difference between the source data valid signal and the output data valid signal, the delay parameter is calculated and sent to the DLY module.

[0143] Among them, the OSC_CLK module can first count the source - side data valid signal and the output - side data valid signal within an input frame period to determine the first count value, the second count value, the valid count value, and the time of the clock period of the source - side data valid signal of an input frame. Then, based on the first count value, the second count value, the valid count value, and the time of the clock period of the source - side data valid signal of an input frame, the DLY module calculates the first delay time. By judging whether the first count value is less than the second count value, when the first count value is less than the second count value, that is, when the first valid time is greater than the second valid time, the first delay time and the first delay line number are calculated through the first delay calculation scheme and sent to the VTG module. When the first count value is greater than or equal to the second count value, that is, when the first valid time is less than or equal to the second valid time, the first delay time and the second delay line number are calculated through the second delay calculation scheme and sent to the VTG module. Then, taking the first delay line number or the second delay line number as the line value to be delayed, the VS_DET module detects the frame synchronization signal corresponding to the video signal, counts the lines according to the frame synchronization signal, delays the line corresponding to the line value to be delayed, and then the VTG module sends the first delay line number or the second delay line number to the RDMA module. The RDMA module reads the video signal from the memory based on the first delay line number or the second delay line number, then processes the read video signal to obtain the VBO signal to be sent, and sends the VBO signal to be sent to the VBO_TX module, so that the VBO_TX module sends the VBO signal to the display panel to display the corresponding video image.

[0144] Further, when the first count value is less than the second count value, that is, when the first valid time is greater than the second valid time, the first delay time and the first delay line number are calculated through the first delay calculation scheme. Among them, the range of the first delay time is t1–t3≤t 4-1 ≤t0–t3, and the range of the first delay line number L0 is {[(t1–t3)*vtt1] / (t0*htt)}+L1≤L0≤[(t0–t3)*vtt1] / (t0*htt), that is, the minimum value of the first delay line number is determined to be {[(t1–t3)*vtt1] / (t0*htt)}+L1.

[0145] When the first count value is greater than or equal to the second count value, that is, when the first valid time is less than or equal to the second valid time, the first delay time and the second delay line number are calculated through the second delay calculation scheme. Among them, the range of the first delay time is 0<t 4-1 ≤t0–t3, and the range of the second delay line number L2 is: L1<L2≤[(t0–t3)*vtt1] / (t0*htt), so as to determine that the minimum value of the second delay line number is L1.

[0146] This embodiment calculates the difference between the valid data signal of the source end and the valid data signal of the output end, uses the inter-frame synchronization to eliminate the error periodically, and accurately calculates the actual minimum delay time and the minimum number of delayed lines. Compared with the traditional image delay within one frame, this application can control the image delay within the range of one frame. Figure 10 The timing diagram shown.

[0147] Furthermore, in the process of writing the video signal into the memory, the backlight data can be counted, that is, the backlight data can be counted during the first valid time of the source data valid signal, and then the backlight data is sent to the backlight module according to the backlight timing signal, so that the display panel is in a lit state through the backlight module, wherein, for the same frame of video signal, the backlight timing signal has a second delay time relative to the source timing signal.

[0148] See Figure 11 As shown, the above-mentioned source timing signal includes a source frame synchronization signal, source vs represents the source frame synchronization signal of the source timing signal, local vs represents the output frame synchronization signal of the output timing signal, source DE represents the source data valid signal, and local DE represents the output data valid signal. Since the backlight data must be transmitted to the backlight unit at one time, the backlight data needs to be transmitted after the statistics of all backlights of one frame are completed after the source valid signal ends, and the transmission is completed before the next frame source valid signal arrives. Therefore, it can be determined that the backlight timing signal has a second delay time relative to the source timing signal, and the second delay time is greater than the first delay time. The range of the second delay time of the backlight timing signal relative to the source timing signal is:

[0149] t 1-2 +t 1-3 +t1 <T X <t 1-2 +t 1-3 +t0+t1-1+t 1-2 +t 1-3 -T;

[0150] That is to say, we can further obtain: 1-2 +t 1-3 +t1 <T X <2t 1-2 +2t 1-3 +t1+t 1-1 -T;

[0151] Among them, t 1-2 is the effective time of the source frame synchronization signal, t 1-3 is the back-end time of the source frame synchronization signal, t 1-1 T is the leading time of the source frame synchronization signal. Xis the second delay time, t1 is the data valid time of the source data valid signal, T is the transmission time of the backlight timing signal, t 1-3 +t 1-1 +t1 is the blanking time of the source frame synchronization signal. It can be understood that the blanking time of the source frame synchronization signal refers to the time corresponding to the source frame synchronization signal being at a low level, that is, the time elapsed from the start time of the falling edge of the source frame synchronization signal to the start time of the rising edge; the valid time of the source frame synchronization signal refers to the time corresponding to the source frame synchronization signal being at a high level, that is, the time elapsed from the start time of the rising edge of the source frame synchronization signal to the start time of the falling edge; the transmission time of the backlight timing signal refers to the output time of the backlight data; the trailing time of the source frame synchronization signal refers to the time elapsed from the start time of the falling edge of the source frame synchronization signal to the start time of the rising edge of the source data valid signal; and the leading time of the source frame synchronization signal refers to the time elapsed from the start time of the falling edge of the source data valid signal to the start time of the next rising edge of the source frame synchronization signal.

[0152] It should be noted that for a frame of display image, the transmission delay of the backlight timing signal is later than the source timing signal, that is, the transmission of the backlight data is later than the transmission of the display image data. The second delay time range generated is as shown in the above formula. The transmission delay of the backlight timing signal is longer than the output timing signal, that is, at the moment when the output data is generated, the backlight data does not have the corresponding backlight brightness. Such a display solution is unacceptable for general display products, and will cause color difference and other problems in the picture. However, it has advantages in the writing scene of the electronic whiteboard. Since only part of the pixel data is updated for each frame of the picture, the currently updated small number of pixels can be illuminated by the diffuse light of the adjacent backlight partitions, so that the writing follow-up is better; and the user is not likely to notice the color difference of the small number of updated pixels.

[0153] In addition, the SOC system chip can send a second control instruction to the FPGA chip, where the second control instruction is a control instruction for setting the display device to normal mode. After receiving the second control instruction, the FPGA chip responds to the second control instruction to perform parsing processing to obtain a parsing result. When the parsing result indicates that the scene mode information is normal mode, the normal mode can be, for example, a movie viewing mode or a TV mode. Then, in response to the control instruction carrying the normal mode information, the video signal is processed in the second data delay mode. Processing the display data in the second data delay mode includes:

[0154] The video signal is written into the memory according to the source timing signal of the video signal; the video signal is read from the memory and sent to the display panel according to the second output timing signal; wherein, for the same frame of video data, the second output timing signal has a third delay time relative to the source timing signal, and the third delay time is greater than or equal to the clock cycle time of one frame of video signal.

[0155] Specifically, after receiving each first-format signal, each first-format signal can be synchronously processed into a video signal based on the source-end timing signal of each first-format signal and written into the memory. Then, based on the output-end timing signal, the range of the third delay time is determined to be greater than or equal to t0. After delaying the third delay time, the video signal is read from the memory and sent to the display panel. Optionally, when reading the video signal from the memory after the third delay time, the read video signal can be processed to obtain the first-format signal to be sent, and the first-format signal to be sent can be sent to the display panel, so that the display panel processes the first-format signal to display the corresponding video image.

[0156] The data processing method for a display device provided in an embodiment of the present application receives a video signal and processes the video signal in a first data delay mode. The video signal is written to a memory according to a source timing signal of the video signal, and the video signal is read from the memory according to a first output timing signal and sent to a display panel. For the same frame of video signal, the first output timing signal has a first delay time relative to the source timing signal, and the first delay time is less than the clock cycle time of one frame of video signal. This technical solution can control the first delay time of the output timing signal relative to the source timing signal to be less than the clock cycle time of one frame of video signal, thereby effectively reducing the image writing delay on the FPGA side and further improving the user experience.

[0157] It should be noted that although the operations of the present method are described in a particular order in the accompanying drawings, this does not require or imply that the operations must be performed in that particular order, or that all of the illustrated operations must be performed to achieve the desired results. Rather, the steps depicted in the flowcharts may be performed in a different order. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into a single step, and / or a single step may be broken down into multiple steps.

[0158] on the other hand, Figure 12 This is a schematic diagram of the structure of a data processing device for a display device provided in an embodiment of the present application. The device may be a device in a terminal or a server, such as Figure 11 As shown, the device includes:

[0159] A receiving module 60, configured to receive a video signal;

[0160] a processing module 70, configured to process the video signal in a first data delay mode;

[0161] The processing module 70 includes:

[0162] The writing unit 710 is used to write the video signal into the memory according to the source timing signal of the video signal;

[0163] a reading unit 720, configured to read the video signal from the memory according to the first output terminal timing signal and send the video signal to the display panel;

[0164] For the same frame of video data, the first output end timing signal has a first delay time relative to the source end timing signal, and the first delay time is less than the clock cycle time of one frame of video signal.

[0165] Optionally, the above device is further used for:

[0166] receiving a first control instruction;

[0167] In response to the first control instruction, it is determined to process the video signal in a first data delay mode.

[0168] Optionally, the first control instruction is a control instruction for setting the display device to a writing mode.

[0169] Optionally, the source end timing signal includes: a source end data valid signal, the source end data valid signal includes a first valid time t1; the first output end timing signal includes: an output end data valid signal, the output end data valid signal includes a second valid time t3;

[0170] The first effective time is greater than the second effective time;

[0171] First delay time t 4-1 The value range of is:

[0172] t1–t3≤t 4-1 ≤t0–t3;

[0173] Wherein, t0 is the clock cycle time of the valid signal of the data at the source end of an input frame, t1 is the first valid time of the valid signal of the data at the source end, and t3 is the second valid time of the valid signal of the data at the output end.

[0174] Optionally, the first delay time t 4-1 The value range of is as follows:

[0175] t0*(vact / vtt1–vact / vtt2)≤t 4-1 ≤t0*(1–vact / vtt2);

[0176] Among them, vtt1 is the first count value of the valid signal of the source data, vtt2 is the second count value of the valid signal of the output data, and vact is the valid count value of the valid signal of the source data and the valid signal of the output data. The valid count value is the number of pixel clocks corresponding to the valid time of the valid signal of the source data and the valid signal of the output data.

[0177] Optionally, the source end timing signal includes: a source end data valid signal, the source end data valid signal includes a first valid time t1; the first output end timing signal includes: an output end data valid signal, the output end data valid signal includes a second valid time t3;

[0178] The first effective time is less than or equal to the second effective time;

[0179] First delay time t 4-1 The value range of is:

[0180] 0 <t 4-1 ≤t0–t3;

[0181] Wherein, t0 is the time of a clock cycle of a valid data signal at the input frame source end, and t3 is the second valid time of the valid data signal at the output end.

[0182] Optionally, reading the video signal from the memory and sending it to the display panel according to the first output terminal timing signal includes:

[0183] Reading the video signal from the memory and sending it to the display panel according to the first number of delayed lines;

[0184] Wherein, for the same frame of video signal, the first delayed line number is the number of lines delayed between reading the video signal from the memory and storing the video signal into the memory;

[0185] The range of the first delay line number L0 is:

[0186] (vtt1 / htt)*(vact / vtt1–vact / vtt2)+L1≤L0≤(vtt1 / htt)*(1–vact / vtt2);

[0187] Wherein, htt is the number of pixel clocks per row, vtt1 is the first count value of the valid signal of the source data, and L1 is the margin added to the number of rows.

[0188] Optionally, the reading unit 720 is further configured to:

[0189] Reading the video signal from the memory and sending it to the display panel according to the second number of delayed lines;

[0190] Wherein, for the same frame of video signal, the second delayed line number is the number of lines delayed between reading the video signal from the memory and storing the video signal into the memory;

[0191] The range of the second delay line number L2 is:

[0192] L1 <L2≤(vtt1 / htt)*(1–vact / vtt2);

[0193] Among them, htt is the value of the pixel clock per row, vtt1 is the first count value of the valid signal of the source data, vtt2 is the second count value of the valid signal of the output data, vact is the valid count value of the valid signal of the source data and the valid signal of the output data, and L1 is the margin added for the number of rows.

[0194] Optionally, the above device is further used for:

[0195] Counting pixel clocks of a valid signal of source data to obtain a first count value;

[0196] Counting pixel clocks of the output-end data valid signal to obtain a second count value;

[0197] Comparing the first count value and the second count value to obtain a comparison result;

[0198] A first delay time, a first delay line number, or a second delay line number is determined according to the comparison result.

[0199] Optionally, the above device is further used for:

[0200] Obtain the clock cycle time and valid count value of a valid signal of the source end data of an input frame;

[0201] The first delay time is determined according to the valid count value, the time of a clock cycle of a valid signal of data at the source end of an input frame, the first count value, the second count value and the comparison result.

[0202] Optionally, the above device is further used for:

[0203] Counting the lines according to the source-end frame synchronization signal of the source-end timing signal, delaying the lines corresponding to the first delayed number of lines, and reading the video signal from the memory;

[0204] Processing the read video signal to obtain a first format signal to be sent;

[0205] The first format signal to be sent is sent to the display panel.

[0206] Optionally, the above device is further used for:

[0207] Converting received signals in the first format into corresponding signals in the second format;

[0208] Synchronously processing the source end timing signals of the second format signals of each channel to obtain a video signal;

[0209] Write the video signal into memory;

[0210] The first format signal is a VBO format signal;

[0211] The second format signal is an LVDS format signal.

[0212] Optionally, the above device is further used for:

[0213] Sending backlight data to the backlight module according to the backlight timing signal, so as to light up the display panel through the backlight module;

[0214] For the same frame of video signal, the backlight timing signal has a second delay time relative to the source timing signal, and the second delay time is greater than the first delay time.

[0215] Optionally, the source end timing signal includes a source end data valid signal and a source end frame synchronization signal, and the device is further configured to:

[0216] Counting backlight data at the first valid time of the valid data signal of the source end;

[0217] The range of the second delay time is:

[0218] t 1-2 +t 1-3 +t1 <T X <2t 1-2 +2t 1-3 +t1+t 1-1 -T;

[0219] Among them, t 1-2 is the effective time of the source frame synchronization signal, t 1-3 is the back-end time of the source frame synchronization signal, t 1-1 T is the leading time of the source frame synchronization signal. X is the second delay time, t1 is the first valid time of the source data valid signal, T is the transmission time of the backlight timing signal, t 1-3 +t 1-1 +t1 is the blanking time of the source frame synchronization signal.

[0220] Optionally, the above device is further used for:

[0221] processing the video signal in a second data delay mode in response to a control instruction carrying normal mode information;

[0222] The processing of the display data in the second data delay mode includes:

[0223] Writing the video signal into the memory according to the source timing signal of the video signal;

[0224] Reading the video signal from the memory and sending it to the display panel according to the second output terminal timing signal;

[0225] For the same frame of video data, the second output end timing signal has a third delay time relative to the source end timing signal, and the third delay time is greater than or equal to the clock cycle time of one frame of video signal.

[0226] It can be understood that the functions of the various functional modules of the data processing device of the display device of this embodiment can be specifically implemented according to the method in the above method embodiment. The specific implementation process can refer to the relevant description of the above method embodiment and will not be repeated here.

[0227] On the other hand, an electronic device provided in an embodiment of the present application includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, the data processing method for the display device as described above is implemented.

[0228] Reference below Figure 13 , Figure 13 A schematic diagram of the structure of the computer system of the FPGA chip of the embodiment of the present application.

[0229] like Figure 13 As shown, the computer system 300 includes a central processing unit (CPU) 301, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 302 or a program loaded from a storage unit 303 to a random access memory (RAM) 303. Various programs and data required for the operation of the system 300 are also stored in the RAM 303. The CPU 301, ROM 302, and RAM 303 are connected to each other via a bus 304. An input / output (I / O) interface 305 is also connected to the bus 304.

[0230] The following components are connected to the I / O interface 305: an input section 306 including a keyboard, a mouse, and the like; an output section 307 including devices such as a cathode ray tube (CRT), a liquid crystal display (LCD), and a speaker; a storage section 308 including a hard disk; and a communication section 309 including a network interface card such as a LAN card or a modem. The communication section 309 performs communication processing via a network such as the Internet. A drive 310 is also connected to the I / O interface 305 as needed. Removable media 311, such as a magnetic disk, an optical disk, a magneto-optical disk, or a semiconductor memory, is installed in the drive 310 as needed, so that computer programs read therefrom can be installed into the storage section 308 as needed.

[0231] In particular, according to an embodiment of the present application, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present application includes a computer program product, which includes a computer program carried on a machine-readable medium, and the computer program includes program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network via the communication section 303, and / or installed from a removable medium 311. When the computer program is executed by the central processing unit (CPU) 301, the above-mentioned functions defined in the system of the present application are executed.

[0232] It should be noted that the computer-readable medium shown in this application can be a computer-readable signal medium or a computer-readable storage medium, or any combination of the two. The computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or device, or any combination of the above. More specific examples of computer-readable storage media can include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In this application, a computer-readable storage medium can be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, device, or device. In this application, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, which carries computer-readable program code. This propagated data signal can take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium that can transmit, propagate, or transport a program for use by or in conjunction with an instruction execution system, apparatus, or device. Program code embodied on a computer-readable medium may be transmitted using any suitable medium, including but not limited to wireless, wireline, optical fiber cable, RF, or any suitable combination thereof.

[0233] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, program segment, or a part of code, and the aforementioned module, program segment, or a part of code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order than that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of the boxes in the block diagram and / or flowchart, can be implemented by a dedicated hardware-based system that performs the specified function or operation, or can be implemented by a combination of dedicated hardware and computer instructions.

[0234] The units or modules involved in the embodiments described in this application may be implemented by software or hardware. The units or modules described may also be provided in a processor. For example, they may be described as: a processor comprising: a receiving module and a processing module, wherein the processing module comprises a writing unit and a reading unit. The names of these units or modules do not, in certain circumstances, constitute limitations on the units or modules themselves. For example, the receiving module may also be described as "receiving a video signal."

[0235] As another aspect, the present application further provides a computer-readable storage medium, which may be included in the electronic device described in the above embodiments; or may exist independently and not be incorporated into the electronic device. The computer-readable storage medium stores one or more programs, and when the aforementioned programs are used by one or more processors to execute the data processing method for the display device described in the present application:

[0236] receiving a video signal;

[0237] processing the video signal in a first data delay mode;

[0238] The step of processing the video signal in the first data delay mode includes:

[0239] Writing the video signal into a memory according to a source timing signal of the video signal;

[0240] Reading the video signal from the memory and sending it to the display panel according to the first output terminal timing signal;

[0241] For the same frame of video signal, the first output-end timing signal has a first delay time relative to the source-end timing signal, and the first delay time is less than a clock cycle time of one frame of video signal.

[0242] In summary, the data processing method, device, equipment, system, and medium for the display device provided in the embodiments of the present application receive a video signal, process the video signal in a first data delay mode, write the video signal into a memory according to the source timing signal of the video signal, and read the video signal from the memory according to the first output timing signal and send it to the display panel. For the same frame of video signal, the first output timing signal has a first delay time relative to the source timing signal, and the first delay time is less than the time of the clock cycle of one frame of video signal. This technical solution can control the first delay time of the output timing signal relative to the source timing signal to be less than the time of the clock cycle of one frame of video signal, thereby effectively reducing the writing delay of the image on the FPGA side and further improving the user experience.

[0243] The above description is merely a preferred embodiment of the present application and an illustration of the technical principles employed. Those skilled in the art should understand that the scope of the invention herein is not limited to the technical solutions formed by the specific combination of the above-mentioned technical features, but also encompasses other technical solutions formed by any combination of the above-mentioned technical features or their equivalents without departing from the inventive concept. For example, a technical solution formed by replacing the above-mentioned features with (but not limited to) technical features having similar functions disclosed in this application.

Claims

1. A data processing method for a display device, characterized in that: The method comprises: receiving a video signal; processing the video signal in a first data delay mode; The step of processing the video signal in the first data delay mode includes: Writing the video signal into a memory according to a source timing signal of the video signal; Reading the video signal from the memory and sending it to the display panel according to the first output terminal timing signal; Wherein, for the same frame of video signal, the first output-end timing signal has a first delay time relative to the source-end timing signal, and the first delay time is less than the time of a clock cycle of one frame of video signal; the source-end timing signal includes: a source-end data valid signal, and the source-end data valid signal includes a first valid time t1; the first output-end timing signal includes: an output-end data valid signal, and the output-end data valid signal includes a second valid time t3; When the first effective time is greater than the second effective time, the value range of the first delay time is: t1–t3≤t 4-1 ≤t0–t3; or, when the first effective time is less than or equal to the second effective time, the value range of the first delay time is: 0 <t 4-1 ≤t0–t3; Among them, t0 is the clock cycle time of the valid signal of the data at the source end of an input frame, t1 is the first valid time of the valid signal of the data at the source end, t3 is the second valid time of the valid signal of the data at the output end, t 4-1 is the first delay time.

2. The method according to claim 1, characterized in that The method further comprises: receiving a first control instruction; In response to the first control instruction, it is determined to process the video signal in a first data delay mode.

3. The method according to claim 2, characterized in that The first control instruction is a control instruction for setting the display device to a writing mode.

4. The method according to claim 1, wherein The first delay time t 4-1 The value range of is as follows: t0 * ( vact / vtt1–vact / vtt2 )≤t 4-1≤t0 *(1–vact / vtt2 ); Among them, vtt1 is the first count value of the source data valid signal, vtt2 is the second count value of the output data valid signal, and vact is the valid count value of the source data valid signal and the output data valid signal, and the valid count value is the number of pixel clocks corresponding to the valid time period of the source data valid signal and the output data valid signal.

5. The method according to claim 4, characterized in that The step of reading the video signal from the memory and sending the video signal to the display panel according to the first output terminal timing signal includes: Reading the video signal from the memory according to a first number of delayed lines and sending the video signal to a display panel; Wherein, for the same frame of video signal, the first delayed line number is the number of lines delayed between reading the video signal from the memory and storing the video signal into the memory; The range of the first delay line number L0 is: (vtt1 / htt) * ( vact / vtt1–vact / vtt2) +L1 ≤L0≤(vtt1 / htt)*(1–vact / vtt2); Wherein, htt is the number of pixel clocks per row, vtt1 is the first count value of the valid signal of the source data, and L1 is the margin added to the number of rows.

6. The method according to claim 5, characterized in that The step of reading the video signal from the memory and sending the video signal to the display panel according to the first output terminal timing signal includes: Reading the video signal from the memory and sending it to a display panel according to a second number of delayed lines; Wherein, for the same frame of video signal, the second delayed line number is the number of lines delayed between reading the video signal from the memory and storing the video signal into the memory; The range of the second delay line number L2 is: L1 <L2≤(vtt1 / htt)*(1–vact / vtt2); Among them, htt is the value of the pixel clock per row, vtt1 is the first count value of the valid signal of the source data, vtt2 is the second count value of the valid signal of the output data, vact is the valid count value of the valid signal of the source data and the valid signal of the output data, and L1 is the margin added for the number of rows.

7. The method according to claim 6, characterized in that The method further comprises: Counting pixel clocks of a valid signal of source data to obtain a first count value; Counting pixel clocks of the output-end data valid signal to obtain a second count value; Comparing the first count value and the second count value to obtain a comparison result; The first delay time, the first delayed row number, or the second delayed row number is determined according to the comparison result.

8. The method according to claim 5, characterized in that Reading the video signal from the memory and sending it to the display panel includes: Counting rows according to a source-end frame synchronization signal of the source-end timing signal, delaying rows corresponding to the first number of delayed rows, and reading the video signal from the memory; Processing the read video signal to obtain a first format signal to be sent; The first format signal to be sent is sent to the display panel.

9. The method according to claim 1, characterized in that Writing the video signal into a memory according to a source clock signal of the video signal comprises: Converting received signals in the first format into corresponding signals in the second format; Synchronously processing the source end timing signals of the respective second format signals to obtain the video signals; Writing the video signal into a memory; The first format signal is a VBO format signal; The second format signal is an LVDS format signal.

10. The method according to any one of claims 1-4, 6, 8-9, characterized in that: The method further comprises: Sending backlight data to the backlight module according to the backlight timing signal, so as to make the display panel in a lighting state through the backlight module; For the same frame of video signal, the backlight timing signal has a second delay time relative to the source timing signal, and the second delay time is greater than the first delay time.

11. The method according to claim 10, characterized in that The source end timing signal includes a source end data valid signal and a source end frame synchronization signal, and the method further includes: Counting backlight data during a first valid time of the source-end data valid signal; The range of the second delay time is: Among them, t 1-2 is the effective time of the source frame synchronization signal, t 1-3 is the back-end time of the source frame synchronization signal, t 1-1 T is the leading time of the source frame synchronization signal. X is the second delay time, t1 is the first valid time of the source data valid signal, T is the transmission time of the backlight timing signal, t 1-3 +t 1-1 +t1 is the blanking time of the source frame synchronization signal.

12. The method according to claim 1, characterized in that The method further comprises: processing the video signal in a second data delay mode in response to a control instruction carrying normal mode information; The processing of the display data in the second data delay mode includes: Writing the video signal into a memory according to a source timing signal of the video signal; Reading the video signal from the memory and sending it to the display panel according to the second output terminal timing signal; For the same frame of video data, the second output-end timing signal has a third delay time relative to the source-end timing signal, and the third delay time is greater than or equal to the clock cycle time of one frame of video signal.

13. A data processing device for a display device, characterized in that: The device comprises: A receiving module, configured to receive a video signal; a processing module, configured to process the video signal in a first data delay mode; Wherein, the processing module includes: a writing unit, configured to write the video signal into a memory according to a source timing signal of the video signal; a reading unit, configured to read the video signal from the memory and send the video signal to the display panel according to the first output terminal timing signal; Wherein, for the same frame of video data, the first output-end timing signal has a first delay time relative to the source-end timing signal, and the first delay time is less than the time of a clock cycle of a frame of video signal; the source-end timing signal includes: a source-end data valid signal, and the source-end data valid signal includes a first valid time t1; the first output-end timing signal includes: an output-end data valid signal, and the output-end data valid signal includes a second valid time t3; When the first effective time is greater than the second effective time, the value range of the first delay time is: t1–t3≤t 4-1 ≤t0–t3; or, when the first effective time is less than or equal to the second effective time, the value range of the first delay time is: 0 <t 4-1 ≤t0–t3; Among them, t0 is the clock cycle time of the valid signal of the data at the source end of an input frame, t1 is the first valid time of the valid signal of the data at the source end, t3 is the second valid time of the valid signal of the data at the output end, t 4-1 is the first delay time.

14. An electronic device comprising a processor and a memory, characterized in that: The processor is used to execute the data processing method for the display device according to any one of claims 1 to 12.

15. The electronic device according to claim 14, characterized in that The processor includes an FPGA chip.

16. A data processing system for a display device, characterized in that: The system includes a first processor, a second processor and a display panel, wherein the first processor is connected to the second processor and the display panel respectively; The second processor is used to send a video signal to the first processor; The first processor is used to receive a video signal; Processing a video signal in a first data delay mode; wherein processing the video signal in the first data delay mode includes: writing the video signal into a memory according to a source timing signal of the video signal; reading the video signal from the memory and sending it to a display panel according to a first output timing signal; wherein, for the same frame of video signal, the first output timing signal has a first delay time relative to the source timing signal, and the first delay time is less than the time of a clock cycle of a frame of video signal; the source timing signal includes: a source data valid signal, the source data valid signal includes a first valid time t1; the first output timing signal includes: an output data valid signal, the output data valid signal includes a second valid time t3; When the first effective time is greater than the second effective time, the value range of the first delay time is: t1–t3≤t 4-1 ≤t0–t3; or, when the first effective time is less than or equal to the second effective time, the value range of the first delay time is: 0 <t 4-1 ≤t0–t3; Among them, t0 is the clock cycle time of the valid signal of the data at the source end of an input frame, t1 is the first valid time of the valid signal of the data at the source end, t3 is the second valid time of the valid signal of the data at the output end, t 4-1 is the first delay time; The display panel is used to receive the video signal sent by the first processor and process the video signal to display a corresponding video image. 17 . A computer-readable storage medium storing a computer program, wherein the computer program is used to implement the data processing method for a display device according to claim 1 .

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