Semiconductor substrate and semiconductor device

Abstract

The disclosed embodiment discloses a semiconductor substrate and a semiconductor device, wherein the array area includes a main memory unit; the peripheral area includes an anti-fuse memory unit; and the structure of the anti-fuse memory unit can be formed by using the manufacturing process of the main memory unit. In the disclosed embodiment, the manufacturing process of the main memory unit is used to form a transistor and a capacitor structure in the main memory unit with a smaller size to realize the anti-fuse function, which can reduce the size of the device in the anti-fuse memory unit, thereby significantly reducing the proportion of the anti-fuse circuit area in the peripheral area.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor substrate and a semiconductor device. Background Art

[0002] With the continuous development of semiconductor technology and storage technology, electronic devices are constantly moving towards miniaturization and integration. Dynamic random access memory (DRAM) is widely used in various electronic devices due to its high storage density and fast read and write speed. Dynamic random access memory is generally composed of multiple storage cells, each of which usually includes a transistor structure and a capacitor. The capacitor stores data information, and the transistor structure controls the reading and writing of data information in the capacitor. Summary of the invention

[0003] According to some embodiments, the present disclosure provides, in a first aspect: a semiconductor substrate, comprising:

[0004] A semiconductor substrate including an array region and a peripheral region;

[0005] Wherein, the array area includes a main storage unit;

[0006] The peripheral region includes an anti-fuse memory cell;

[0007] The structure of the anti-fuse memory unit is formed by adopting the manufacturing process of the main memory unit.

[0008] Exemplarily, by making the anti-fuse memory cell and the main memory cell have the same structure, when there is a damaged cell in the main memory cell, the anti-fuse memory cell can be used to replace the damaged main memory cell. In addition, the anti-fuse memory cell and the main memory cell can be formed using the same preparation process. In other words, the preparation process for forming the device in the main memory cell in the array area can be used to form the device in the anti-fuse memory cell in the peripheral area. This can not only reduce the difficulty of process preparation, but also reduce the size of the device in the anti-fuse memory cell, thereby reducing the occupied area of ​​the peripheral area.

[0009] In some examples, the film layers with the same functions in the same functional devices in the anti-fuse memory unit and the main memory unit are formed by a single patterning process.

[0010] In some examples, the main memory cell includes a main control transistor; the anti-fuse memory cell includes an anti-fuse control transistor;

[0011] Wherein, in the main control transistor and the anti-fuse control transistor, film layers having the same function are formed by using the same mask.

[0012] In some examples, the gate of the main control transistor and the gate of the anti-fuse control transistor are formed with the same pattern using the same mask;

[0013] The active area of ​​the main control transistor and the active area of ​​the anti-fuse control transistor are formed with the same pattern using the same mask;

[0014] The source of the main control transistor and the source of the anti-fuse control transistor are formed with the same pattern using the same mask;

[0015] The drain of the main control transistor and the drain of the anti-fuse control transistor are formed with the same pattern using the same mask.

[0016] In some examples, the main storage unit further includes a main storage capacitor; the anti-fuse storage unit further includes an anti-fuse storage capacitor;

[0017] A first isolation layer is provided between the layer where the main storage capacitor and the anti-fuse storage capacitor are located and the layer where the main control transistor and the anti-fuse control transistor are located; wherein the first isolation layer has a main via and a secondary via; the main storage capacitor is electrically connected to the main control transistor through the main via, and the anti-fuse storage capacitor is electrically connected to the anti-fuse control transistor through the secondary via;

[0018] Furthermore, in the main storage capacitor and the anti-fuse storage capacitor, film layers having the same function are formed using the same mask.

[0019] In some examples, the main storage capacitor includes a main first electrode plate and a main second electrode plate; wherein the main first electrode plate is electrically connected to the main control transistor through the main via;

[0020] The anti-fuse storage capacitor comprises a secondary first electrode plate and a secondary second electrode plate; wherein the secondary first electrode plate is electrically connected to the anti-fuse control transistor through the secondary via hole;

[0021] The main first electrode plate and the auxiliary first electrode plate are formed with the same pattern using the same mask.

[0022] In some examples, the main storage capacitor and the anti-fuse storage capacitor are pillar capacitors.

[0023] In some examples, the main via and the auxiliary via are formed with the same pattern using the same mask.

[0024] In some examples, the semiconductor substrate further includes: a primary contact pad located in the primary via hole, and a secondary contact pad located in the secondary via hole;

[0025] The main first electrode plate is electrically connected to the main control transistor through the main contact pad;

[0026] The auxiliary first electrode plate is electrically connected to the anti-fuse control transistor through the auxiliary contact pad.

[0027] In some examples, the primary contact pad and the secondary contact pad are formed using the same manufacturing process.

[0028] In some examples, the array region includes a plurality of primary bit lines, and the peripheral region includes a plurality of secondary bit lines;

[0029] The plurality of main bit lines and the plurality of sub bit lines are formed by adopting the same manufacturing process.

[0030] In some examples, the plurality of main bit lines and the plurality of sub bit lines are formed with the same pattern using the same mask.

[0031] In some examples, the peripheral region further includes secondary storage capacitors; wherein one secondary storage capacitor is electrically connected to one of the anti-fuse memory cells;

[0032] The structure of the sub-storage capacitor is the same as that of the main storage capacitor.

[0033] In some examples, the peripheral region further includes repair control circuitry;

[0034] The repair control circuit is connected to the anti-fuse storage unit, and the repair control circuit is connected to the auxiliary storage capacitor through the anti-fuse storage unit;

[0035] The repair control circuit is configured to control the corresponding anti-fuse memory cell to operate, so as to replace the damaged main memory cell with an electrically connected auxiliary storage capacitor, when determining that a damaged main memory cell exists in the array area.

[0036] According to some embodiments, a second aspect of the present disclosure provides: a semiconductor device, comprising the above-mentioned semiconductor substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 A schematic diagram of a top view of a semiconductor substrate provided in an embodiment of the present disclosure;

[0038] Figure 2 is a schematic diagram of a partial top view of the semiconductor substrate in an embodiment of the present disclosure;

[0039] Figure 3 for Figure 2 The schematic cross-sectional structure diagram of the semiconductor substrate along the AA' direction shown;

[0040] Figure 4a for Figure 2 The schematic cross-sectional structure diagram of the semiconductor substrate along the BB' direction shown;

[0041] Figure 4b for Figure 2 The schematic cross-sectional structure diagram of the semiconductor substrate along the CC' direction shown;

[0042] Figure 5a Some equivalent circuit diagrams of the semiconductor substrate in the peripheral area in the embodiments of the present disclosure;

[0043] Figure 5b Schematic diagrams of other equivalent circuits of the semiconductor substrate in the peripheral region in the embodiments of the present disclosure. DETAILED DESCRIPTION

[0044] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. And in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present disclosure.

[0045] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. "First", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0046] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual proportions, and are only intended to illustrate the present disclosure. The same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions.

[0047] With the continuous development and progress of integrated circuit technology, the performance requirements for the yield and service life of semiconductor storage devices are getting higher and higher. Although the manufacturing process of semiconductor storage devices is constantly improving, some inevitable defects will still occur during the manufacturing of semiconductor storage devices, resulting in the inability to correctly store and read storage cells in the array area of ​​the semiconductor storage device. Therefore, some redundant storage cells can be reserved during the design stage of the semiconductor storage device. In this way, when the semiconductor storage device is tested, if it is determined that the storage cells in the array area are damaged, the reserved storage cells can be used to replace the damaged storage cells in the array area, so that the bad storage cells in the array area can be repaired.

[0048] However, the transistors in the reserved memory cells are usually N-type metal oxide semiconductor field effect transistors (MOSFETs) with thick oxide, and their size is generally 700*101nm. 2 , its pitch (i.e. the distance between two adjacent MOS tubes) is generally 204nm. Then the area occupied by the thick-oxide N-type MOS tube is the sum of its size and its pitch.

[0049] In practical applications, the gate plays a "switching role" of turning off and on. Normally, the spacing between the source and drain of the thick-oxygen N-type MOS tube cannot be too small. If it is too small, the channel distance will be too short, and the "switching effect" of the gate will be weakened, causing the source and drain to be connected, resulting in a short-channel effect (Short-channel Effects). Therefore, if the length of the conductive channel of the thick-oxygen N-type MOS tube is reduced to a dozen nanometers or even a few nanometers, the thick-oxygen N-type MOS tube will experience a short-channel effect. Therefore, based on the reliability and performance considerations of the thick-oxygen N-type MOS tube, the device size of the thick-oxygen N-type MOS tube cannot be further reduced.

[0050] In the embodiments of the present disclosure, reference Figure 1 , Figure 2 , Figure 4a and Figure 4b As shown, the semiconductor substrate may include a semiconductor substrate 10. For example, the material of the semiconductor substrate 10 may include silicon, germanium or a semiconductor of silicon on insulator (SOI), or may include germanium silicon compounds, silicon carbide or other known materials, such as III and V group compounds such as gallium arsenide. Certain doping ions may also be implanted into the semiconductor substrate 10 according to design requirements to change electrical parameters. For example, the semiconductor substrate 10 may be a silicon substrate.

[0051] In the embodiments of the present disclosure, reference Figures 1 to 3, the semiconductor substrate 10 may include an array area AA and a peripheral area BB. The array area AA may include a plurality of storage areas aa, and the storage area aa may have a main storage unit, a main word line A130, and a main bit line A120. Exemplarily, the main word line A130 may be a buried word line buried in the semiconductor substrate 10. For example, a word line groove is etched in the semiconductor substrate 10, the main word line A130 is disposed in the word line groove, and the upper surface of the main word line A130 is lower than the upper surface of the semiconductor substrate 10. Thereafter, a second isolation layer 150 is filled on the main word line A130, so that the upper surface of the second isolation layer 150 is flush with the upper surface of the semiconductor substrate 10. Exemplarily, the material of the main word line A130 includes one of tungsten, titanium, nickel, aluminum, platinum, titanium nitride, N-type polysilicon, and P-type polysilicon.

[0052] In the embodiments of the present disclosure, reference Figures 1 to 5b , the peripheral area BB may have a repair area bb, and the repair area bb includes a plurality of antifuse storage cells BX, a plurality of sub-storage capacitors, a sub-word line B130, and a sub-bit line B120. Exemplarily, the sub-word line B130 may be a buried word line buried in the semiconductor substrate 10. For example, a word line groove is etched in the semiconductor substrate 10, the sub-word line B130 is disposed in the word line groove, and the upper surface of the sub-word line B130 is lower than the upper surface of the semiconductor substrate 10. Thereafter, a second isolation layer 150 is filled on the sub-word line B130, so that the upper surface of the second isolation layer 150 is flush with the upper surface of the semiconductor substrate 10. Exemplarily, the material of the sub-word line B130 includes one of tungsten, titanium, nickel, aluminum, platinum, titanium nitride, N-type polysilicon, and P-type polysilicon.

[0053] In the embodiment of the present disclosure, one anti-fuse storage unit BX can be connected to one sub-storage capacitor. For example, the sub-storage capacitor is electrically connected to the sub-bit line B120 through the corresponding anti-fuse storage unit BX. Exemplarily, other circuits may be set between the anti-fuse storage unit BX and the electrically connected sub-storage capacitor, or no circuit may be set but directly connected. When other circuits are set between the anti-fuse storage unit BX and the electrically connected sub-storage capacitor, the circuits set may have the same structure and working principle as the circuits that implement the same function in the related art, and will not be described in detail here.

[0054] In the embodiment of the present disclosure, the structure of the anti-fuse memory cell can be formed by using the manufacturing process of the main memory cell. Since the size of the transistor and capacitor in the main memory cell formed by the manufacturing process of the main memory cell is small, in the embodiment of the present disclosure, the size of the transistor and capacitor in the structure of the anti-fuse memory cell formed by the manufacturing process of the main memory cell is also small, which can reduce the size of the device in the anti-fuse memory cell, thereby reducing the occupied area of ​​the peripheral area BB.

[0055] In the disclosed embodiment, the film layer with the same function in the functional device in the anti-fuse memory unit and the main memory unit can be formed by a single patterning process. That is, the device in the anti-fuse memory unit in the peripheral area BB can be formed while the device in the main memory unit in the array area AA is formed, so that there is no need to perform additional process steps for preparing the device in the anti-fuse memory unit, saving process preparation time and improving preparation efficiency. In addition, the size of the device in the anti-fuse memory unit can be reduced by forming the device in the main memory unit in the array area AA while forming the device in the anti-fuse memory unit in the peripheral area BB, thereby reducing the occupied area of ​​the peripheral area BB.

[0056] In some embodiments, the main storage unit may include a main control transistor and a main storage capacitor A210 electrically connected to the main control transistor. The anti-fuse storage unit may include an anti-fuse control transistor BT and an anti-fuse storage capacitor electrically connected to the anti-fuse control transistor. Among them, the main control transistor and the anti-fuse control transistor are transistor devices, and the main storage capacitor A210 has the function of data storage. The anti-fuse storage capacitor B210 has anti-fuse device characteristics. For example, the array area AA has a main bit line and a main word line, the gate of the main control transistor is electrically connected to the main word line, the drain is electrically connected to the main bit line, and the source is electrically connected to the main storage capacitor A210. The voltage signal on the main word line can control the opening or closing of the main control transistor, and then read the data information stored in the main storage capacitor A210 through the main bit line, or write the data information into the main storage capacitor A210 through the main bit line for storage. Furthermore, the peripheral area BB has a sub-bit line and a sub-word line, the gate of the anti-fuse control transistor is electrically connected to the sub-word line, the drain is electrically connected to the sub-bit line, and the source is electrically connected to the anti-fuse storage capacitor B210. The voltage signal on the sub-word line can control the opening or closing of the anti-fuse control transistor, and then read the data information stored in the anti-fuse storage capacitor B210 through the sub-bit line, or write the data information into the anti-fuse storage capacitor B210 through the sub-bit line for storage.

[0057] In the embodiments of the present disclosure, reference Figures 1 to 3, the structure of the secondary storage capacitor can be made the same as that of the main storage capacitor A210, so that when there is a damaged cell in the main storage cell, the secondary storage capacitor can be used to replace the main storage capacitor A210 in the damaged main storage cell. In addition, the secondary storage capacitor and the main storage capacitor A210 can be formed using the same preparation process. In other words, the preparation process for forming the main storage capacitor A210 in the array area AA can be used to form the secondary storage capacitor in the peripheral area BB. This can not only reduce the difficulty of process preparation, but also reduce the size of the secondary storage capacitor, thereby reducing the occupied area of ​​the peripheral area BB.

[0058] In the embodiments of the present disclosure, reference Figure 2 , there is a first isolation layer 300 between the layer where the main storage capacitor A210 and the anti-fuse storage capacitor B210 are located and the layer where the main control transistor and the anti-fuse control transistor are located. A main via and a secondary via are formed in the first isolation layer 300. A main contact pad A220 is provided in the main via, so that the main storage capacitor A210 is electrically connected to the main control transistor through the main contact pad A220 provided in the main via. In addition, a secondary contact pad B220 is provided in the secondary via, so that the anti-fuse storage capacitor B210 is electrically connected to the anti-fuse control transistor through the secondary contact pad B220 provided in the secondary via. Exemplarily, the structures of the main control transistor and the anti-fuse control transistor can be made the same, and the structures of the main storage capacitor A210 and the anti-fuse storage capacitor B210 can be made the same. For example, in order to reduce the occupied area of ​​the capacitor, the main storage capacitor A210 and the anti-fuse storage capacitor B210 can be set as columnar capacitors.

[0059] In the embodiments of the present disclosure, reference Figure 2 , the main via and the auxiliary via can be formed with the same pattern using the same mask. This can keep the main via and the auxiliary via as uniform as possible, reducing the difficulty of manufacturing design.

[0060] In the embodiments of the present disclosure, reference Figure 2 , the main contact pad A220 and the auxiliary contact pad B220 can be formed using the same preparation process.

[0061] That is to say, in this way, the auxiliary contact pad B220 in the peripheral area BB can be formed while the main contact pad A220 in the array area AA is formed. Therefore, not only can the difficulty of process preparation be reduced, but the auxiliary contact pad B220 can also be prepared by the process of preparing the main contact pad A220, so that the size of the formed auxiliary contact pad B220 is roughly the same as the size of the main contact pad A220, and the pitch of the auxiliary contact pad B220 is roughly the same as the pitch of the main contact pad A220, so that the area occupied by the auxiliary contact pad B220 is roughly the same as the area occupied by the main contact pad A220, reducing the size of the auxiliary contact pad B220, and then reducing the occupied area of ​​the peripheral area BB.

[0062] In some examples, active areas A110 and B110 defined by shallow trench isolation regions are formed in the array region and the peripheral region of the semiconductor substrate, respectively, and silicon oxide is filled in the shallow trench isolation region. Then, word line grooves passing through the silicon oxide in the active region and the shallow trench isolation region are etched in the semiconductor substrate. Afterwards, the main word line A130 and the auxiliary word line B130 can be prepared and formed using the same patterning process. For example, a gate insulating layer 140 is covered on the sidewalls of the word line grooves in the array region and the peripheral region. Exemplarily, the gate insulating layer 140 may include one or more of silicon oxide, silicon nitride, oxynitride, silicon nitride, oxide / nitride / oxide, and a high dielectric material. For example, atomic layer deposition may be used to cover the sidewalls of the word line grooves with silicon oxide to form a gate insulating layer 140. Afterwards, using the same mask, a deposition process can be selected from chemical vapor deposition, physical vapor deposition, atomic layer deposition, high-density plasma chemical vapor deposition, metal organic chemical vapor deposition, plasma enhanced chemical vapor deposition or other suitable deposition processes to form a pattern of the main word line A130 in the word line groove of the array area, and a pattern of the sub-word line B130 in the word line groove of the peripheral area BB. Afterwards, a second isolation layer 150 is filled on the buried word line in each word line groove, and the top surface of the formed second isolation layer 150 is flush with the top surface of the semiconductor substrate 10.

[0063] It should be noted that the word line can be used as the gate of the transistor, and the source / drain region of the transistor can be located in the active region on both sides of the word line. For example, one of the source / drain regions, such as the source / drain region between two word lines, can be used as the source of the corresponding transistor, and another source / drain region, such as the source / drain region between the word line and the shallow trench isolation region, can be used as the drain of the corresponding transistor. Exemplarily, the main word line A130 can be used as the gate of the main control transistor, the source / drain region A111 located between the two main word lines A130 (such as the area covered by the main bit line A120) can be used as the source of the main control transistor, and the source / drain region A112 located between the main word line A130 and the shallow trench isolation region can be used as the drain of the main control transistor. The sub-word line B130 can serve as the gate of the anti-fuse control transistor, the source / drain region B111 located between the two sub-word lines B130 (for example, the area covered by the sub-bit line B120) can serve as the source of the anti-fuse control transistor, and the source / drain region B112 located between the sub-word line B130 and the shallow trench isolation region can serve as the drain of the anti-fuse control transistor.

[0064] The size of the main control transistor formed in the general array area AA is about: 116*62 / 2nm 2 , its pitch (i.e., the distance between two adjacent main control transistors) is about 55nm, then the area occupied by the main control transistor is the sum of its size plus its pitch. In the embodiment of the present disclosure, by forming the film layer with the same function in the main control transistor and the anti-fuse control transistor using a single patterning process, the anti-fuse control transistor in the peripheral area BB can be formed while the main control transistor in the array area AA is formed. Thus, not only can the difficulty of process preparation be reduced, but the anti-fuse control transistor can also be prepared using the process for preparing the main control transistor, so that the size of the formed anti-fuse control transistor is roughly the same as the size of the main control transistor, and the pitch of the anti-fuse control transistor is roughly the same as the pitch of the main control transistor, so that the area occupied by the anti-fuse control transistor is roughly the same as the area occupied by the main control transistor, reducing the size of the anti-fuse control transistor, and further reducing the occupied area of ​​the peripheral area BB.

[0065] In the process of manufacturing semiconductor substrates, the production of film layers in transistors and storage capacitors usually requires corresponding masks to form the circuit patterns required for the film layers in transistors and storage capacitors. For example, in the process of manufacturing semiconductor substrates, it is first necessary to form a mask pattern corresponding to the required circuit pattern on the mask. Afterwards, the mask pattern can be used as a blocking structure, and the film layer not blocked by the mask pattern can be etched away through an etching process to form the required circuit pattern. In the embodiment of the present disclosure, the film layer with the same function in the anti-fuse control transistor and the main control transistor can be formed using the same mask. In this way, the same mask can be used to form the pattern of the same functional film layer in the anti-fuse control transistor and the main control transistor, reducing the number of masks used, thereby reducing production costs.

[0066] In some examples, the film layers with the same functions in the anti-fuse control transistor and the main control transistor can be formed with the same pattern using the same mask. Since the process for preparing the mask is relatively uniform, the size of the mask pattern formed on the mask is also relatively uniform. After using the mask, a circuit pattern with a relatively uniform size can be obtained. In addition, since the process for preparing the pattern of the mask for the main storage unit is relatively mature, by directly using the pattern of the mask for preparing the main storage unit to prepare the anti-fuse storage unit, there is no need to design a new mask, thereby reducing the difficulty of designing a new mask and reducing the preparation cost.

[0067] A general transistor includes a gate, an active area, a source, and a drain. In the disclosed embodiment, the gate of the main control transistor and the gate in the anti-fuse control transistor can be formed with the same pattern using the same mask. Also, the active area of ​​the main control transistor and the active area in the anti-fuse control transistor can be formed with the same mask. Also, the source of the main control transistor and the source in the anti-fuse control transistor can be formed with the same mask. Also, the drain of the main control transistor and the drain in the anti-fuse control transistor can be formed with the same mask. In this way, the structures of the main control transistor and the anti-fuse control transistor can be kept uniform as much as possible, so that the sizes of the main control transistor and the anti-fuse control transistor can be kept uniform, and when controlling data reading and storage, the transistor characteristics of the main control transistor and the anti-fuse control transistor can be kept uniform as much as possible, and then after the anti-fuse control transistor replaces the main control transistor, the error rate of data reading and storage can be reduced, and the stability of data reading and storage can be improved.

[0068] In the disclosed embodiment, multiple main bit lines and multiple sub-bit lines can be formed by the same preparation process. For example, the main bit line A120 and the sub-bit line B120 can be formed by a single patterning process. For example, the main bit line A120 and the sub-bit line B120 can be formed by the same mask to form the same pattern. For example, the material of the main bit line A120 and the sub-bit line B120 includes tungsten.

[0069] In the embodiment of the present disclosure, the film layers with the same functions in the main storage capacitor A210 and the anti-fuse storage capacitor B210 can be formed by a single patterning process. That is, in this way, the anti-fuse storage capacitor B210 in the peripheral area BB can be formed while the main storage capacitor A210 in the array area AA is formed. Thus, not only can the difficulty of process preparation be reduced, but the anti-fuse storage capacitor B210 can also be prepared by the process of preparing the main storage capacitor A210, so that the size of the formed anti-fuse storage capacitor B210 is substantially the same as the size of the main storage capacitor A210, and the pitch of the anti-fuse storage capacitor B210 is substantially the same as the pitch of the main storage capacitor A210, so that the area occupied by the anti-fuse storage capacitor B210 is substantially the same as the area occupied by the main storage capacitor A210, reducing the size of the anti-fuse storage capacitor B210, and further reducing the occupied area of ​​the peripheral area BB.

[0070] In the embodiment of the present disclosure, the film layers with the same function in the main storage capacitor A210 and the anti-fuse storage capacitor B210 can be formed using the same mask. In this way, the same mask can be used to form the pattern of the film layers with the same function in the anti-fuse storage capacitor B210 and the main storage capacitor A210, thereby reducing the number of masks used and thus reducing production costs.

[0071] Typically, the capacitor may have two electrode plates disposed opposite to each other and a dielectric layer between the two electrode plates. In some examples, the main storage capacitor A210 includes a main first electrode plate AC1 and a main second electrode plate AC2, and a dielectric layer between the main first electrode plate AC1 and the main second electrode plate AC2. The main first electrode plate AC1 is electrically connected to the main control transistor through a main via. In an application, the voltage signal on the main word line can control the opening or closing of the main control transistor, thereby reading the data information stored in the main storage capacitor A210 through the main bit line, or writing the data information into the main storage capacitor A210 through the main bit line for storage.

[0072] In some examples, the anti-fuse storage capacitor B210 includes a secondary first electrode plate BC1 and a secondary second electrode plate BC2, and a dielectric layer between the secondary first electrode plate BC1 and the secondary second electrode plate BC2, wherein the secondary first electrode plate BC1 is electrically connected to the anti-fuse control transistor through a secondary via.

[0073] Combination Figure 5a and Figure 5b If the anti-fuse memory cell is burned during programming, the anti-fuse memory cell can be changed from a non-storage state to a storage state, thereby reducing the path resistance to a smaller value (e.g., tens of kilohms to hundreds of kilohms). When the anti-fuse memory cell is selected, the path current flows through the equivalent resistance in the storage state, generating a lower voltage on the node N1, making the output signal D_O of the logic gate 12 a high level. On the contrary, if the anti-fuse memory cell is not burned during programming, the equivalent resistance of the anti-fuse memory cell in the path will be relatively large (e.g., several megohms to hundreds of megohms), and the voltage drop generated by the fixed circuit on the path will exceed the flip point of the logic gate 12, making the output signal D_O of the logic gate 12 a low level.

[0074] In some examples, combined Figure 5a and Figure 5b When writing or storing data in the secondary storage capacitor connected to the anti-fuse storage capacitor B210: a voltage can be applied to the gate of the anti-fuse control transistor BT to turn on the anti-fuse control transistor B210, and a high voltage is applied to the secondary bit line B120 electrically connected to the turned-on anti-fuse control transistor B210. The secondary second electrode plate BC2 is connected to the secondary storage capacitor, and a high voltage exists between the secondary first electrode plate BC1 and the secondary second electrode plate BC2 of the anti-fuse storage capacitor B210. If the high voltage is large enough, the dielectric layer (such as silicon oxide layer) between the secondary first electrode plate BC1 and the secondary second electrode plate BC2 can be broken down, so that the resistance of the channel becomes very small. For example, if the signal defined as stored is 0, it can be known that the secondary storage capacitor will store 0. If the high voltage is not enough to break down the dielectric layer (such as silicon oxide layer), the channel resistance becomes very large. For example, if the signal defined as stored is 1, it can be known that the secondary storage capacitor will store 1. It should be noted that the specific value of the high voltage in this paragraph can be basically the same as that in the relevant technology and is not limited here.

[0075] And, when reading data in the secondary storage capacitor connected to the anti-fuse storage capacitor B210: a voltage can be applied to the gate of the anti-fuse control transistor to turn on the anti-fuse control transistor, and a voltage of 1V to 1.2V is applied to the secondary bit line B120 electrically connected to the turned-on anti-fuse control transistor, and the secondary second electrode plate BC2 is connected to the secondary storage capacitor. If the dielectric layer (e.g., silicon oxide layer) has been broken down before, the channel resistance becomes very small (e.g., 1kΩ), and the circuit for measuring voltage in the channel also has a resistor voltage divider, and the voltage of the measured voltage divider resistor (e.g., 10kΩ) is very large, and it can be known that the secondary storage capacitor connected to the anti-fuse storage capacitor B210 stores 0. On the contrary, if the dielectric layer (e.g., silicon oxide layer) has not been broken down, the channel resistance becomes very large (e.g., 100kΩ), and the circuit for measuring voltage in the channel also has a resistor voltage divider, and the voltage of the measured voltage divider resistor is very small, and it can be known that the secondary storage capacitor connected to the anti-fuse storage capacitor B210 stores 1.

[0076] It should be noted that Figure 5a In the figure, n represents the number of rows, and m represents the number of columns. Moreover, the specific values ​​of n and m can be designed and determined according to the requirements of actual applications, and are not limited here.

[0077] In some examples, the dielectric layer of the anti-fuse storage capacitor B210 and the dielectric layer of the main storage capacitor A210 may be a film layer disposed as a whole layer.

[0078] In some examples, after forming the main bit line A120 and the sub-bit line B120, a deposition process may be selected from chemical vapor deposition, physical vapor deposition, atomic layer deposition, high-density plasma chemical vapor deposition, metal organic chemical vapor deposition, plasma enhanced chemical vapor deposition or other suitable deposition processes to form a first isolation layer 300 in the array region and the peripheral region. Afterwards, an etching process is used to form a main via and a sub-via in the first isolation layer 300. Afterwards, a deposition process may be selected from chemical vapor deposition, physical vapor deposition, atomic layer deposition, high-density plasma chemical vapor deposition, metal organic chemical vapor deposition, plasma enhanced chemical vapor deposition or other suitable deposition processes to form a main contact pad A220 in the main via and a sub-contact pad B220 in the sub-via.

[0079] Afterwards, a deposition process may be selected from chemical vapor deposition, physical vapor deposition, atomic layer deposition, high-density plasma chemical vapor deposition, metal organic chemical vapor deposition, plasma enhanced chemical vapor deposition or other suitable deposition processes to form the first electrode plate film layer. Afterwards, the first electrode plate film layer is etched using an etching process to form the main first electrode plate AC1 and the auxiliary first electrode plate AC2.

[0080] Afterwards, a deposition process can be selected from chemical vapor deposition, physical vapor deposition, atomic layer deposition, high-density plasma chemical vapor deposition, metal organic chemical vapor deposition, plasma enhanced chemical vapor deposition or other suitable deposition processes to form a dielectric layer on the main first electrode plate AC1 and the auxiliary first electrode plate AC2.

[0081] Afterwards, a deposition process may be selected from chemical vapor deposition, physical vapor deposition, atomic layer deposition, high-density plasma chemical vapor deposition, metal organic chemical vapor deposition, plasma enhanced chemical vapor deposition or other suitable deposition processes to form a main second electrode plate AC2 and a secondary second electrode plate AC2 on the dielectric layer. Exemplarily, the main second electrode plate AC2 may be a film layer provided as a whole layer. The secondary second electrode plate BC2 may also be a film layer provided as a whole layer.

[0082] Afterwards, a deposition process can be selected from chemical vapor deposition, physical vapor deposition, atomic layer deposition, high-density plasma chemical vapor deposition, metal organic chemical vapor deposition, plasma enhanced chemical vapor deposition or other suitable deposition processes to form a second isolation layer 400 on the main second electrode plate AC2 and the auxiliary second electrode plate AC2.

[0083] In the disclosed embodiment, the peripheral area BB may further include a repair control circuit. The repair control circuit is connected to the anti-fuse memory cell. And, the repair control circuit is connected to the secondary storage capacitor through the anti-fuse memory cell. And, the repair control circuit is configured to control the corresponding anti-fuse memory cell to work when it is determined that there is a damaged main memory cell in the array area AA, so as to replace the damaged main memory cell with the electrically connected secondary storage capacitor. Exemplarily, when it is determined that there is a damaged main memory cell in the array area AA, the specific position of the damaged main memory cell (for example, which row and which column in the array area AA) can be determined, so that the repair control circuit can be programmed to control the anti-fuse memory cell to form a path, so as to replace the damaged main memory cell at the position with the secondary storage capacitor electrically connected to the anti-fuse memory cell forming the path.

[0084] The embodiments of the present disclosure also provide some semiconductor devices. The semiconductor device may include the semiconductor substrate provided in the embodiments of the present disclosure. The principle of solving the problem by the semiconductor device is similar to that of the aforementioned semiconductor substrate, so the implementation of the semiconductor device can refer to the implementation of the aforementioned semiconductor substrate, and the repeated parts will not be repeated here.

[0085] In specific implementation, in the embodiments of the present disclosure, the semiconductor substrate may be applied to a semiconductor device (e.g., DRAM). The semiconductor device may include a semiconductor device. Moreover, the semiconductor device may be a product or component with a storage function. Other essential components of the semiconductor device are understood by those of ordinary skill in the art, and are not described in detail herein, nor should they be used as limitations to the present disclosure.

[0086] Obviously, those skilled in the art can make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to include these modifications and variations.

Claims

1. A semiconductor substrate, It is characterized in that include: A semiconductor substrate including an array region and a peripheral region; Wherein, the array area includes a main storage unit; The peripheral region includes an anti-fuse memory cell; The structure of the anti-fuse memory unit is formed by adopting the manufacturing process of the main memory unit; The peripheral region also includes a secondary storage capacitor; One of the secondary storage capacitors is electrically connected to one of the anti-fuse storage cells; The peripheral region also includes a repair control circuit; The repair control circuit is connected to the anti-fuse storage unit, and the repair control circuit is connected to the auxiliary storage capacitor through the anti-fuse storage unit; The repair control circuit is configured to control the corresponding anti-fuse memory cell to operate, so as to replace the damaged main memory cell with an electrically connected auxiliary storage capacitor, when determining that a damaged main memory cell exists in the array area.

2. The semiconductor substrate according to claim 1, It is characterized in that The film layers with the same functions in the functional devices in the anti-fuse memory unit and the main memory unit are formed by a single patterning process.

3. The semiconductor substrate according to claim 2, It is characterized in that The main storage unit includes a main control transistor; the anti-fuse storage unit includes an anti-fuse control transistor; Wherein, in the main control transistor and the anti-fuse control transistor, film layers having the same function are formed by using the same mask.

4. The semiconductor substrate according to claim 3, It is characterized in that The gate of the main control transistor and the gate of the anti-fuse control transistor are formed with the same pattern using the same mask; The active area of ​​the main control transistor and the active area of ​​the anti-fuse control transistor are formed with the same pattern using the same mask; The source of the main control transistor and the source of the anti-fuse control transistor are formed with the same pattern using the same mask; The drain of the main control transistor and the drain of the anti-fuse control transistor are formed with the same pattern using the same mask.

5. The semiconductor substrate according to claim 3, It is characterized in that The main storage unit further comprises a main storage capacitor; the anti-fuse storage unit further comprises an anti-fuse storage capacitor; A first isolation layer is provided between the layer where the main storage capacitor and the anti-fuse storage capacitor are located and the layer where the main control transistor and the anti-fuse control transistor are located; wherein the first isolation layer has a main via and a secondary via; the main storage capacitor is electrically connected to the main control transistor through the main via, and the anti-fuse storage capacitor is electrically connected to the anti-fuse control transistor through the secondary via; Furthermore, in the main storage capacitor and the anti-fuse storage capacitor, film layers having the same function are formed using the same mask.

6. The semiconductor substrate according to claim 5, It is characterized in that The main storage capacitor comprises a main first electrode plate and a main second electrode plate; wherein the main first electrode plate is electrically connected to the main control transistor through the main via hole; The anti-fuse storage capacitor comprises a secondary first electrode plate and a secondary second electrode plate; wherein the secondary first electrode plate is electrically connected to the anti-fuse control transistor through the secondary via hole; The main first electrode plate and the auxiliary first electrode plate are formed with the same pattern using the same mask.

7. The semiconductor substrate according to claim 6, It is characterized in that The main storage capacitor and the anti-fuse storage capacitor are pillar capacitors.

8. The semiconductor substrate according to claim 6, It is characterized in that The main via hole and the auxiliary via hole are formed with the same pattern by using the same mask.

9. The semiconductor substrate according to claim 6, It is characterized in that The semiconductor substrate further includes: a main contact pad located in the main via hole, and a secondary contact pad located in the secondary via hole; The main first electrode plate is electrically connected to the main control transistor through the main contact pad; The auxiliary first electrode plate is electrically connected to the anti-fuse control transistor through the auxiliary contact pad.

10. The semiconductor substrate according to claim 9, It is characterized in that The main contact pad and the auxiliary contact pad are formed by adopting the same preparation process.

11. The semiconductor substrate according to claim 5, It is characterized in that The array region includes a plurality of main bit lines, and the peripheral region includes a plurality of sub bit lines; The plurality of main bit lines and the plurality of sub bit lines are formed by adopting the same manufacturing process.

12. The semiconductor substrate according to claim 11, It is characterized in that The plurality of main bit lines and the plurality of sub bit lines are formed with the same pattern by using the same mask.

13. The semiconductor substrate according to any one of claims 1 to 12, It is characterized in that The structure of the sub-storage capacitor is the same as that of the main storage capacitor.

14. A semiconductor device, It is characterized in that Comprising the semiconductor substrate as described in any one of claims 1-13.

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