Radiation resistant self-biased low dropout voltage regulator circuit based on cafvf

Abstract

The application discloses a kind of anti-radiation self-biased low-dropout voltage regulator circuits based on CAFVF, which includes power tube, first negative feedback circuit, second negative feedback circuit, positive voltage feedback circuit, voltage feedback circuit, current source bias circuit and starting circuit.The circuit presented in the application does not need reference circuit and error amplifier, effectively avoids the situation that the output end of error amplifier is affected by SET.In addition, the circuit of the application establishes a voltage balance point through multiple feedback loops and determines the output voltage value.Finally, the circuit can output a stable voltage in a radiation environment.The anti-radiation ability of the low-dropout voltage regulator is significantly improved by the circuit of the application, which has SET robustness and can work stably in a radiation environment such as aviation and aerospace.The application can be widely applied in the field of voltage regulator circuit.

Description

Technical Field

[0001] This invention relates to the field of voltage regulator circuits, and more particularly to a radiation-resistant self-biased low-dropout voltage regulator circuit based on CAFVF. Background Technology

[0002] With the rapid development of integrated circuits, low-dropout regulators, as important power management modules, are widely used in SoC chip design. A typical CAFVF-based low-dropout regulator structure includes a reference voltage VREF (usually implemented by a bandgap reference circuit), an error amplifier MEA, a power transistor, and a bias voltage VCN. The stability of the power supply has a significant impact on the performance of the circuit. However, with the rapid development of applications in aerospace, aviation, and nuclear energy, more and more functional circuits need to operate in radiated environments. Under the influence of single-event transients, the circuit will experience output voltage jumps, deviating from the normal output level for extended periods. Summary of the Invention

[0003] To address the aforementioned problems, the present invention aims to provide a radiation-resistant self-biased low-dropout voltage regulator circuit based on CAFVF, which can output a stable voltage under radiation conditions.

[0004] The technical solution adopted in this invention is: a radiation-resistant self-biased low-dropout regulator circuit based on CAFVF, comprising the following steps:

[0005] It includes a power transistor, a first negative feedback circuit, a second negative feedback circuit, a positive voltage feedback circuit, a voltage feedback circuit, a current source bias circuit, and a startup circuit. The power transistor is connected to the first negative feedback circuit, the positive voltage feedback circuit, and the voltage feedback circuit. The first negative feedback circuit is also connected to the second negative feedback circuit, the voltage feedback circuit, and the startup circuit. The negative feedback circuit is also connected to the positive voltage feedback circuit, the voltage feedback circuit, the current source bias circuit, and the startup circuit. The positive voltage feedback circuit is also connected to the voltage feedback circuit and the current source bias circuit.

[0006] Furthermore, the first negative feedback circuit includes a first transistor, a second transistor, and a third transistor, and the second negative feedback circuit includes a third transistor and a fourth transistor. The source of the first transistor is connected to the power supply, and the drain, gate, second gate, third drain, and fourth gate of the first transistor are connected together. The source of the second transistor is connected to the power supply, and the drain, fourth drain, gate of the power transistor, and startup circuit are connected together. The source of the third transistor is grounded, and the gate of the third transistor is connected to the voltage feedback circuit. The source of the fourth transistor is connected to the positive feedback circuit and the current source bias circuit.

[0007] Furthermore, the positive voltage feedback circuit includes a fifth transistor, a sixth transistor, and a seventh transistor. The source of the fifth transistor, the drain of the power transistor, the gate of the sixth transistor, and the voltage feedback circuit are connected. The drain of the fifth transistor, the source of the fourth transistor, and the current source bias circuit are connected. The gate of the fifth transistor, the source of the sixth transistor, the drain of the seventh transistor, and the gate of the seventh transistor are connected. The drain of the sixth transistor is connected to the power supply, and the source of the seventh transistor is grounded.

[0008] Furthermore, the voltage feedback circuit includes an eighth transistor and a ninth transistor. The source of the eighth transistor, the gate of the sixth transistor, the drain of the power transistor, and the source of the fifth transistor are connected. The drain of the eighth transistor, the gate of the eighth transistor, the drain of the ninth transistor, the gate of the ninth transistor, and the gate of the third transistor are connected. The source of the ninth transistor is grounded.

[0009] Furthermore, the current source bias circuit includes a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor. The drain of the tenth transistor, the source of the fourth transistor, and the drain of the fifth transistor are connected. The gate of the tenth transistor, the drain of the thirteenth transistor, the gate of the thirteenth transistor, the gate of the twelfth transistor, and the drain of the twelfth transistor are connected. The source of the thirteenth transistor is grounded. The source of the twelfth transistor, the drain of the eleventh transistor, and the gate of the eleventh transistor are connected. The source of the eleventh transistor is connected to a power supply.

[0010] Furthermore, the startup circuit includes a fourteenth transistor, a fifteenth transistor, and a first resistor. The drain of the fourteenth transistor, the gate of the power transistor, the drain of the second transistor, and the drain of the fourth transistor are connected together. The source of the fourteenth transistor, the drain of the fifteenth transistor, and the gate of the fifteenth transistor are connected together. The source of the fifteenth transistor is grounded. The gate of the fourteenth transistor is connected to the first end of the first resistor, and the second end of the first resistor is connected to the power supply.

[0011] Furthermore, the working principle is as follows:

[0012] When the circuit is powered on, current is injected into the gate of the power transistor to establish the DC operating point of the circuit.

[0013] The output voltage of the circuit is converted into the first negative feedback current at the drain terminal of the second transistor after passing through the voltage feedback circuit, the third transistor which serves as the current source, and the PMOS current mirror composed of the first and second transistors.

[0014] The output voltage of the circuit passes through the voltage feedback circuit, the third transistor and the fourth transistor which act as current sources, and generates a second negative feedback current at the drain terminal of the fourth transistor.

[0015] The second and fourth transistors form a push-pull output at the gate of the power transistor, which improves the switching rate of the power transistor gate.

[0016] The first negative feedback current and the second negative feedback current charge the capacitance of the power transistor's gate, forming the gate voltage of the power transistor.

[0017] The gate voltage of the power transistor is converted into a negative feedback voltage through the power transistor;

[0018] The circuit's output voltage passes through a source follower consisting of a sixth transistor and a seventh transistor connected to a diode, then through a fifth transistor and a fourth transistor, ultimately forming a positive feedback voltage at the drain of the power transistor.

[0019] The beneficial effects of the circuit in this invention are as follows: Traditional low-dropout regulator circuits contain a reference circuit and an error amplifier. The reference circuit often includes an error amplifier, and the output of the error amplifier is easily affected by settling voltage (SET), leading to unstable output voltage. The circuit proposed in this invention eliminates the need for a reference circuit and an error amplifier, effectively avoiding the SET effect on the error amplifier output. Furthermore, the circuit in this invention establishes a voltage balance point and determines the output voltage value through multiple feedback loops. Ultimately, the circuit can output a stable voltage in a radiation environment. The circuit in this invention significantly improves the radiation resistance of low-dropout regulators, exhibits SET robustness, and can operate stably in radiation environments such as aviation and aerospace. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the structure of a radiation-resistant self-biased low-dropout regulator circuit based on CAFVF according to the present invention.

[0021] Figure 2 This is a schematic diagram of a small-signal circuit model according to a specific embodiment of the present invention;

[0022] Figure 3 This is a transient response waveform diagram of the circuit in a specific embodiment of the present invention without SET.

[0023] Figure 4 This is a waveform diagram of the SET response of the circuit in a specific embodiment of the present invention when the load steps upward;

[0024] Figure 5 This is a waveform diagram of the SET response of the circuit in a specific embodiment of the present invention when the load steps downward;

[0025] Figure 6 This is a waveform diagram of the SET response of the circuit in a specific embodiment of the present invention under light load;

[0026] Figure 7 This is a waveform diagram of the SET response of circuit one in a specific embodiment of the present invention under heavy load;

[0027] Reference numerals: Mp, power transistor; M1, first transistor; M2, second transistor; M3, third transistor; M4, fourth transistor; M5, fifth transistor; M6, sixth transistor; M7, seventh transistor; M8, eighth transistor; M9, ninth transistor; M10, tenth transistor; M11, eleventh transistor; M12, twelfth transistor; M13, thirteenth transistor; M14, fourteenth transistor; M15, fifteenth transistor; Rs, first resistor; VDD, power supply. Detailed Implementation

[0028] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments. The step numbers in the following embodiments are only for ease of explanation and do not limit the order of the steps. The execution order of each step in the embodiments can be adapted according to the understanding of those skilled in the art.

[0029] like Figure 1 As shown, the present invention provides a radiation-resistant self-biased low-dropout regulator circuit based on CAFVF, including a power transistor Mp, a first negative feedback circuit, a second negative feedback circuit, a positive voltage feedback circuit, a voltage feedback circuit, a current source bias circuit, and a startup circuit.

[0030] Specifically, the first and second negative feedback loops in the circuit play a major role, while the positive feedback loop plays an auxiliary role. The positive and negative feedback loops work together to regulate and form a stable output voltage at the drain of the power transistor.

[0031] Further, as a preferred embodiment of the present invention, the first negative feedback circuit includes a first transistor M1, a second transistor M2, and a third transistor M3; the second negative feedback circuit includes a third transistor M3 and a fourth transistor M4; the positive voltage feedback circuit includes a fifth transistor M5, a sixth transistor M6, and a seventh transistor M7; the voltage feedback circuit includes an eighth transistor M8 and a ninth transistor M9; the current source bias circuit includes a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, and a thirteenth transistor M13; and the startup circuit includes a fourteenth transistor M14, a fifteenth transistor M15, and a first transistor M6. The drain and gate of the first transistor M1, the gate of the second transistor M2, the drain of the third transistor M3, and the gate of the fourth transistor M4 are connected. The source of the second transistor M2 is connected to the power supply. The drain of the second transistor M2, the drain of the fourth transistor M4, the gate of the power transistor Mp, and the drain of the fourteenth transistor M14 are connected. The source of the third transistor M3 is grounded. The gate of the third transistor M3, the gate of the ninth transistor M9, the drain of the ninth transistor M9, the gate of the eighth transistor M8, and the drain of the eighth transistor M8 are connected. The source of the fourth transistor M4 and the fifth transistor... The drain of transistor M5 is connected to the drain of the tenth transistor M10. The source of the fifth transistor M5, the drain of power transistor Mp, the gate of the sixth transistor M6, and the source of the eighth transistor M8 are connected. The gate of the fifth transistor M5, the source of the sixth transistor M6, the drain of the seventh transistor M7, and the gate of the seventh transistor M7 are connected. The drain of the sixth transistor M6 is connected to the power supply VDD. The source of the seventh transistor M7 is grounded. The source of the ninth transistor M9 is grounded. The source of the tenth transistor M10 is grounded. The gate of the tenth transistor M10, the drain of the thirteenth transistor M13, and the gate of the thirteenth transistor M13 are connected. The source of the thirteenth transistor M13 is grounded, the source of the twelfth transistor M12, the drain of the eleventh transistor M11, and the gate of the eleventh transistor M11 are connected, and the source of the eleventh transistor M11 is connected to the power supply VDD. The source of the fourteenth transistor M14, the drain of the fifteenth transistor M15, and the gate of the fifteenth transistor M15 are connected, and the source of the fifteenth transistor M15 is grounded. The gate of the fourteenth transistor M14 is connected to the first terminal of the first resistor Rs, and the second terminal of the first resistor Rs is connected to the power supply VDD.

[0032] Specifically, the power transistor Mp, the first transistor M1, the second transistor M2, the fifth transistor M5, the eighth transistor M8, the eleventh transistor M11, and the twelfth transistor M12 are all PMOS transistors, while the third transistor M3, the fourth transistor M4, the sixth transistor M6, the seventh transistor M7, the ninth transistor M9, the tenth transistor M10, the thirteenth transistor M13, the fourteenth transistor M14, and the fifteenth transistor M15 are all NMOS transistors.

[0033] Furthermore, as a preferred embodiment of the present invention, a load circuit is also included, the load circuit consisting of a load capacitor C. L and load resistance R L They are connected in parallel, with one end connected to the drain of the power transistor and the other end grounded.

[0034] Since the self-biased low-dropout regulator circuit based on CAFVF proposed in this patent does not use analog circuits such as bandgap references and operational amplifiers, but is implemented using multiple feedback loops, it can greatly reduce the impact of single-event effects on the circuit, making it possible to output stable voltage under radiation environments and meet the requirements for stable power supply under radiation environments.

[0035] This invention patent corresponds to Figure 1 Small signal circuit models such as Figure 2 As shown, its open-loop transfer function and closed-loop transfer function expressions are as follows:

[0036]

[0037]

[0038] Where C int This is the capacitance of the power transistor's gate.

[0039] Figure 3 This is a transient response waveform diagram of the circuit of the present invention without SET (Set-Off). At 10 μs, when the load current steps from 10 μA to 10 mA with a step time of 100 ns, the circuit's output voltage changes by 6.5 mV, and the settling time is 1.1 μs. At 40 μs, when the load current steps from 10 mA to 100 μA with a step time of 100 ns, the circuit's output voltage changes by 5.3 mV, and the settling time is 1.6 μs. The circuit exhibits fast response speed and good transient response performance.

[0040] Figure 4This is the SET response waveform of the circuit of this invention when the load steps upward. The circuit was subjected to a SET test at 10μs when the load current steps upward to measure the worst-case SET reliability. At 10μs, the output voltage of the circuit was 1.603V, a decrease of 5mV due to the upward load step; the overshoot voltage at the drains of M11 and M13 was 3.5mV.

[0041] Figure 5 This is the SET response waveform of the circuit of this invention under a downward step load. The circuit was subjected to a SET test at 40μs when the load stepped downward. At 40μs, the output voltage of the circuit was 1.598V, an increase of 5mV due to the downward step load. The overshoot voltages at the drains of M11 and M13 were 3.3mV, those at the drains of M2 and M10 were 1.9mV, those at the drain of M1 were 1.6mV, those at the drain of M15 were 1.3mV, and those at the drain of M9 were 0.6mV. Figure 4 and Figure 5 The voltage change of the circuit described herein under load step stress and SET bombardment is less than 0.22% of the output voltage. The circuit can still operate normally under radiation and has good circuit performance, demonstrating SET robustness.

[0042] Figure 6 This is the SET response waveform of the circuit of this invention under light load. At 2μs, the circuit operating under light load was subjected to a SET attack. The drains of M11 and M13 were most affected, followed by the drains of M2, M10, M1, and M15. The effect of the SET attack on other nodes of the circuit was negligible. The voltage change of the drains of M11 and M13 was 6.8mV, the drain voltage change of M2 was 2.6mV, the drain voltage change of M10 was 1.1mV, the drain voltage change of M1 was 2.8mV, and the drain voltage change of M15 was 1.6mV. The circuit exhibits SET robustness under light load.

[0043] Figure 7This is the SET response waveform of the circuit of this invention under heavy load. When the circuit operating under heavy load was subjected to a SET attack at 2μs, the drains of M11 and M13 were most affected, followed by the drains of M8, M3, M2, M4 and M10, M1, M15, and M9. The effect of the SET attack on other nodes of the circuit was negligible. The drain voltage changes of M11 and M13 were 4.2mV, M8 was 4.0mV, M3 was 3.9mV, M2 was 3.5mV, M4 and M10 were 2.7mV, M1 was 2.3mV, M15 was 2.0mV, and M9 was 1.1mV. The circuit also exhibits SET robustness under heavy load.

[0044] The working principle of the self-biased low-dropout regulator circuit based on CAFVF with anti-SET radiation proposed in this patent is as follows:

[0045] When the circuit is powered on, current is injected into the gate of the power transistor to establish the DC operating point of the circuit.

[0046] The output voltage of the circuit is converted into the first negative feedback current at the drain terminal of the second transistor M2 through the voltage feedback circuit, the third transistor M3 which serves as the current source, the PMOS current mirror composed of the first transistor M1 and the second transistor M2.

[0047] The output voltage of the circuit passes through the voltage feedback circuit, the third transistor M3 and the fourth transistor M4 which act as current sources, and generates a second negative feedback current at the drain terminal of the fourth transistor M4.

[0048] The second transistor M2 and the fourth transistor M4 form a push-pull output at the gate of the power transistor, thereby increasing the switching rate of the gate of the power transistor Mp.

[0049] The first negative feedback current and the second negative feedback current charge the capacitance of the power transistor gate, forming the gate voltage of the power transistor Mp.

[0050] The gate voltage of the power transistor Mp is converted into a negative feedback voltage through the power transistor Mp;

[0051] The output voltage of the circuit passes through the source follower formed by the sixth transistor M6, the seventh transistor M7 connected by a diode, and then through the fifth transistor M5 and the fourth transistor M4, forming a positive feedback voltage at the drain of the power transistor Mp.

[0052] The above is a detailed description of the preferred embodiments of the present invention. However, the present invention is not limited to the embodiments described. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention. All such equivalent modifications or substitutions are included within the scope defined by the claims of this application.

Claims

1. A radiation-resistant self-biased low-dropout voltage regulator circuit based on CAFVF, characterized in that, It includes a power transistor, a first negative feedback circuit, a second negative feedback circuit, a positive voltage feedback circuit, a voltage feedback circuit, a current source bias circuit, and a startup circuit. The power transistor is connected to the first negative feedback circuit, the positive voltage feedback circuit, and the voltage feedback circuit. The first negative feedback circuit is also connected to the second negative feedback circuit, the voltage feedback circuit, and the startup circuit. The negative feedback circuit is also connected to the positive voltage feedback circuit, the voltage feedback circuit, the current source bias circuit, and the startup circuit. The positive voltage feedback circuit is also connected to the voltage feedback circuit and the current source bias circuit. The first negative feedback circuit includes a first transistor, a second transistor, and a third transistor. The second negative feedback circuit includes a third transistor and a fourth transistor. The source of the first transistor is connected to the power supply. The drain, gate, second, third, and fourth transistors of the first transistor are connected together. The source of the second transistor is connected to the power supply. The drain, fourth, and power transistors of the second transistor are connected together and the gate of the power transistor are connected to the startup circuit. The source of the third transistor is grounded. The gate of the third transistor is connected to the voltage feedback circuit. The source of the fourth transistor is connected to the positive feedback circuit and the current source bias circuit. The positive voltage feedback circuit includes a fifth transistor, a sixth transistor, and a seventh transistor. The source of the fifth transistor, the drain of the power transistor, the gate of the sixth transistor, and the voltage feedback circuit are connected. The drain of the fifth transistor, the source of the fourth transistor, and the current source bias circuit are connected. The gate of the fifth transistor, the source of the sixth transistor, the drain of the seventh transistor, and the gate of the seventh transistor are connected. The drain of the sixth transistor is connected to the power supply, and the source of the seventh transistor is grounded. The voltage feedback circuit includes an eighth transistor and a ninth transistor. The source of the eighth transistor, the gate of the sixth transistor, the drain of the power transistor, and the source of the fifth transistor are connected. The drain of the eighth transistor, the gate of the eighth transistor, the drain of the ninth transistor, the gate of the ninth transistor, and the gate of the third transistor are connected. The source of the ninth transistor is grounded. The current source bias circuit includes a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor. The drain of the tenth transistor, the source of the fourth transistor, and the drain of the fifth transistor are connected. The gate of the tenth transistor, the drain of the thirteenth transistor, the gate of the thirteenth transistor, the gate of the twelfth transistor, and the drain of the twelfth transistor are connected. The source of the thirteenth transistor is grounded. The source of the twelfth transistor, the drain of the eleventh transistor, and the gate of the eleventh transistor are connected. The source of the eleventh transistor is connected to a power supply. The startup circuit includes a fourteenth transistor, a fifteenth transistor, and a first resistor. The drain of the fourteenth transistor, the gate of the power transistor, the drain of the second transistor, and the drain of the fourth transistor are connected together. The source of the fourteenth transistor, the drain of the fifteenth transistor, and the gate of the fifteenth transistor are connected together. The source of the fifteenth transistor is grounded. The gate of the fourteenth transistor is connected to the first end of the first resistor, and the second end of the first resistor is connected to the power supply.

2. The radiation-resistant self-biased low-dropout regulator circuit based on CAFVF according to claim 1, characterized in that, The working principle is as follows: When the circuit is powered on, current is injected into the gate of the power transistor to establish the DC operating point of the circuit. The output voltage of the circuit is converted into the first negative feedback current at the drain terminal of the second transistor through the voltage feedback circuit, the third transistor which serves as the current source, and the PMOS current mirror composed of the first and second transistors. The output voltage of the circuit passes through the voltage feedback circuit, the third transistor and the fourth transistor which act as current sources, and generates a second negative feedback current at the drain terminal of the fourth transistor. The second and fourth transistors form a push-pull output at the gate of the power transistor, which improves the switching rate of the power transistor gate. The first negative feedback current and the second negative feedback current charge the capacitance of the power transistor's gate, forming the gate voltage of the power transistor. The gate voltage of the power transistor is converted into a negative feedback voltage through the power transistor; The circuit's output voltage passes through a source follower consisting of a sixth transistor and a seventh transistor connected to a diode, then through a fifth transistor and a fourth transistor, ultimately forming a positive feedback voltage at the drain of the power transistor.

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