Splicing display method, device, LED splicing controller, storage medium and system

Abstract

The present application provides a splicing display method, device, LED splicing controller, storage medium and system, which relates to the field of display technology. The method includes: obtaining a preset resolution and a preset frame rate corresponding to each display component; determining a target candidate clock that satisfies that the quotient obtained by dividing by the preset frame rate of any one display component is greater than or equal to the product of the preset effective width and the preset effective height of any one display component according to the preset frame rate of each display component; determining the smallest one of the target candidate clocks as the target clock; determining a target resolution corresponding to each display component based on the target clock; and sending a sub-video image to each display component according to the target resolution corresponding to each display component, so that each display component displays the sub-video image according to the corresponding target resolution. This method is applicable to the splicing display process and is used to solve the problem of weak flexibility in splicing display.

Description

Technical Field

[0001] This application relates to the field of display technologies, and particularly to a splicing display method, apparatus, LED splicing controller, storage medium, and system. Background Art

[0002] A light emitting diode (LED) splicing display system includes a video source, a splicing controller, and one or more LED display components. The video source can output multiple video images. The splicing controller can splice multiple video images output by the video source into one video image and then divide it into multiple video images, and send the divided multiple video images to one or more LED display components respectively. Each LED display component can display its corresponding video image respectively, and the video images displayed by one or more LED display components are combined together to form the video image spliced by the above splicing controller.

[0003] In order to ensure that the video images displayed by one or more LED display components are normal and smooth without phenomena such as tearing and asynchronous video images between seams, the splicing controller also needs to nest the video image in the standard resolution after splicing and dividing the video image, and ensure that the clock phases output to each LED display component are synchronized, and then display the video image on the LED display component according to the standard resolution.

[0004] However, the clock of the divided video image is usually smaller than the clock of the corresponding nested standard resolution. The larger the clock, the higher the requirement for the data transmission link. Nesting the divided video image in the standard resolution increases the clock, which also improves the requirement for the data transmission link. And after the LED display component receives the video image nested in the standard resolution, it also needs to crop and divide the parts outside the video image in the effective width and effective height of the standard resolution, that is, the video image nested in the standard resolution requires the LED display component to have the function of cropping and dividing. Therefore, the solution of nesting the video image in the standard resolution has relatively high requirements for the data transmission link and the LED display component, and the flexibility of the solution is weak. Summary of the Invention

[0005] Based on the above technical problems, this application provides a splicing display method, apparatus, LED splicing controller, storage medium, and system, which can generate a set of custom resolutions (detailed timings) for each potential display width, height, frame rate (W*H P / I FPS), and the clock in the generated custom resolution is smaller, so as to achieve synchronous output of one or more display components, reduce the requirements for the data transmission link and the display component, and improve the flexibility of the splicing display solution.

[0006] In a first aspect, the present application provides a splicing display method, which is applied to a splicing controller. The splicing controller is connected to one or more light-emitting diode display components. The method includes: obtaining a preset resolution and a preset frame rate corresponding to each display component; wherein the preset resolution includes a preset effective width and a preset effective height; determining one or more target candidate clocks according to the preset frame rate of each display component; the target candidate clock is a clock that satisfies the following first condition: the quotient obtained by dividing it by the preset frame rate of any one display component is greater than or equal to the product of the preset effective width and the preset effective height of any one display component; determining the smallest one of the one or more target candidate clocks as the target clock of the one or more display components; based on the target clock, determining a target resolution corresponding to each display component; sending sub-video images to each display component according to the target resolution corresponding to each display component, so that each display component displays the sub-video images according to the corresponding target resolution; wherein the sub-video images are obtained by the splicing controller splitting the video image, and the sub-video images displayed by each display component are spliced together to obtain the video image.

[0007] The splicing display method provided by the embodiments of the present application can generate a target resolution corresponding to each display component according to the preset effective width, the preset effective height, and the preset frame rate required to be displayed by each display component. For display components with different preset effective widths, different preset effective heights, and different preset frame rates, the splicing controller first determines the target candidate clocks that meet the requirements of each display component, and selects the smallest one from the target candidate clocks as the target clock, and generates the target resolution corresponding to each display component based on the smallest target clock. Since the target clock is smaller, and the smaller the clock, the lower the requirement for the data transmission link, the requirement for the data transmission link is reduced, and the flexibility of the splicing display solution is improved. Moreover, since the target clock is smaller, the product of the effective width and the effective height in the target resolution determined based on the target clock is also smaller, and the area of the effective display area corresponding to the target resolution is also smaller, which is more in line with the area of the effective display area corresponding to the preset resolution. After the splicing controller transmits the video image to the display component according to the target resolution, the display component (or the sending card in the display component) does not need to crop and split the received video image, which reduces the requirement for the function of the display component and improves the flexibility of the splicing display solution.

[0008] In addition, the target clocks in the target resolutions corresponding to multiple display components are the same, and the clocks of the splicing controller at any resolution are consistent, and frame out-of-sync between the video images displayed by multiple display components will not occur due to clock (or pixel frequency) deviation (frequency offset).

[0009] In a possible implementation manner, one or more candidate clocks are determined according to the preset frame rate of each display component, including: determining a plurality of initial clocks from a plurality of clocks between the minimum clock and the maximum clock according to the preset clock step accuracy; the preset clock step accuracy is used to indicate the clock interval between adjacent initial clocks; determining one or more initial candidate clocks that meet the second condition from the plurality of initial clocks according to the number of factors of the quotient obtained by dividing each initial clock by the preset frame rate of any one display component and the second condition; the second condition is that the number of factors of the quotient obtained by dividing the preset frame rate of any one display component is greater than the number threshold; determining one or more target candidate clocks from the one or more initial candidate clocks based on the initial resolutions corresponding to the one or more initial candidate clocks, and each initial candidate clock corresponds to one or more initial resolutions.

[0010] Optionally, determining one or more initial candidate clocks that meet the second condition from the plurality of initial clocks according to the number of factors of the quotient obtained by dividing each initial clock by the preset frame rate of any one display component and the second condition includes: obtaining one or more first initial clocks from the plurality of initial clocks whose number of factors of the quotient obtained by dividing the preset frame rate of any one display component is greater than the number threshold, and determining initial candidate clocks from the one or more first initial clocks; determining one or more target candidate clocks from the one or more initial candidate clocks based on the initial resolutions corresponding to the one or more initial candidate clocks includes: if there are initial candidate clocks that meet the first condition among the one or more initial candidate clocks, determining one or more target candidate clocks from the one or more initial candidate clocks based on the initial resolutions corresponding to the one or more initial candidate clocks.

[0011] Optionally, the method further includes: if there are no initial candidate clocks that meet the first condition among the one or more initial candidate clocks, obtaining one or more second initial clocks from the plurality of initial clocks whose number of factors of the quotient obtained by dividing the preset frame rate of any one display component is less than or equal to the number threshold; determining one or more initial candidate clocks from the one or more second initial clocks.

[0012] Optionally, determining one or more initial candidate clocks from the one or more first initial clocks includes: using the first initial clocks that are the same as the standard clock among the one or more first initial clocks as the initial candidate clocks; determining one or more initial candidate clocks from the one or more second initial clocks includes: using the first initial clocks that are the same as the standard clock among the one or more first initial clocks as the initial candidate clocks.

[0013] Optionally, one or more initial candidate clocks include a first clock, and a preset frame rate of one or more display components is a first frame rate; before determining one or more target candidate clocks from one or more initial candidate clocks based on the initial resolutions corresponding to the one or more initial candidate clocks, the method further includes: performing one or more factorizations on a first area obtained by dividing the first clock by the first frame rate, each time decomposing the first area into two factors; for each factorization, taking one of the two factors obtained by the factorization as a maximum width and taking the other of the two factors obtained by the factorization as a maximum height; determining an effective width according to the maximum width and determining an effective height according to the maximum height; generating one of a plurality of initial resolutions based on the maximum width, the maximum height, the effective width, and the effective height.

[0014] Optionally, one or more display components include a display component of M rows and N columns, both M and N being integers greater than or equal to 1. When N is greater than or equal to 2, the method further includes: adjusting a horizontal front porch HFP in a target resolution corresponding to each row of display components in the M rows, so that the horizontal blanking sizes of the display components in each row of the M rows decrease sequentially from left to right.

[0015] It should be understood that when each row of display components in the M rows includes multiple ones, reducing the horizontal blanking of the display components in that row can reduce the out-of-sync between adjacent display components in the same row caused by the scanning sequence.

[0016] In a second aspect, the present application provides a splicing display device, and the device includes each module for the method described in the first aspect above.

[0017] In a third aspect, the present application provides an LED splicing controller, and the LED splicing controller includes a processor and a memory; the memory stores instructions executable by the processor; when the processor is configured to execute the instructions, the LED splicing controller implements the method described in the first aspect above.

[0018] In a fourth aspect, the present application provides a computer program product, and when the computer program product runs on a splicing controller, the splicing controller is enabled to execute the steps of the related method described in the first aspect or the third aspect above to implement the method described in the first aspect above.

[0019] In a fifth aspect, the present application provides a readable storage medium, and the readable storage medium includes: software instructions; when the software instructions run in a splicing controller, the splicing controller is enabled to implement the method described in the first aspect above.

[0020] In a sixth aspect, the present application provides a splicing display system, and the system includes a splicing controller and one or more display components connected to the splicing controller; the splicing controller and the one or more display components are used to cooperate with each other to implement the method described in the first aspect above.

[0021] The beneficial effects of the second to sixth aspects described above can be referred to those described in the first aspect and will not be elaborated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0023] Figure 1 It is a schematic diagram of the splicing control display;

[0024] Figure 2 It is a schematic diagram of cutting;

[0025] Figure 3 It is a schematic diagram of the composition of the LED splicing display system provided by the embodiment of the present application;

[0026] Figure 4 It is a schematic diagram of the composition of the splicing controller provided by the embodiment of the present application;

[0027] Figure 5 It is a schematic flowchart of the splicing display method provided by the embodiment of the present application;

[0028] Figure 6 It is another schematic flowchart of the splicing display method provided by the embodiment of the present application;

[0029] Figure 7 It is yet another schematic flowchart of the splicing display method provided by the embodiment of the present application;

[0030] Figure 8 It is a schematic diagram of the simulation algorithm provided by the embodiment of the present application;

[0031] Figure 9 It is a display effect diagram of the custom resolution provided by the embodiment of the present application;

[0032] Figure 10 It is another schematic diagram of the composition of the splicing controller provided by the embodiment of the present application;

[0033] Figure 11 It is a functional schematic diagram of the timing control module provided by the embodiment of the present application;

[0034] Figure 12 It is a structural schematic diagram of the synchronization constraint provided by the embodiment of the present application;

[0035] Figure 13 It is a structural schematic diagram of other constraints provided by the embodiment of the present application;

[0036] Figure 14 It is a schematic diagram of the composition of the splicing control display device provided by the embodiment of the present application. Specific embodiments

[0037] Hereinafter, terms such as "first", "second", and "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first", "second", or "third", etc. may explicitly or implicitly include one or more of such features.

[0038] First, the terms related to the embodiments of the present application are introduced.

[0039] 1. Resolution (or it can also be called detailed timing): A property of digital video, including a combination of a set of data information describing the pixel transmission and display process. Part of the parameters of the resolution are the (effective) width of a single-frame digital image and the (effective) height of a single-frame digital image. This part of the parameters is generally described by width (W) * height (H) and progressive (P) / interlaced (I) refresh. Among them, the width is represented by the number of effective pixel points included in a row of a single-frame digital image, and the height is represented by the number of effective pixel points (or the number of rows) included in a column of the digital image. For example, 1920*1080P means that the digital image is composed of 1920 effective pixel points per row and 1080 effective rows, and progressive refresh is adopted. Another part of the parameters of the resolution are the relevant parameters of the blanking part. For example, horizontal front porch (HFP), horizontal back porch (HBP), horizontal synchronization (HSYNC) period, vertical front porch (VFP), vertical back porch (VBP), and vertical synchronization (VSYNC) period, etc.

[0040] 2. Standard resolution: Resolutions standardized by the Video Electronics Standards Association (VESA) and the Consumer Technology Association (CTA), etc. Multiple standard resolutions are given in their standard documents. For example, the relevant parameters of 640*350P85 and its blanking part, the relevant parameters of 720*400P85 and its blanking part, the relevant parameters of 800*600P100 and its blanking part, the relevant parameters of 1600*1200P60 and its blanking part, and the relevant parameters of 1920*1400P60 and its blanking part, etc.

[0041] 3. Aspect ratio: (Effective) width of a single-frame digital image in the resolution / (Effective) height of a single-frame digital image in the resolution. The aspect ratios of standard resolutions are generally 4:3, 5:4, 16:9, or 16:10, etc.

[0042] 4. Clock (which can be called pixel clock or pixel frequency): Used to represent the total number of pixels contained in a video image (digital image) per unit time, and can be calculated according to the total width of a single-frame digital image (effective width + blanking width) * the total height of a single-frame digital image (effective height + blanking height) * frame rate.

[0043] The LED splicing display system includes a video source, a splicing controller, and one or more LED display components. The video source can output multiple high-resolution video images (i.e., the above-mentioned digital images). The splicing controller can splice multiple video images output by the video source into one video image and then divide it into multiple video images, and send the divided multiple video images to one or more LED display components respectively. Each LED display component can display its corresponding video image respectively, and the video images displayed by one or more LED display components are combined together to form one video image spliced by the splicing controller.

[0044] Exemplarily, Figure 1 is a schematic diagram of splicing display. As Figure 1As shown, taking the example that the user needs to display a video image of 9920×1440, the video source can output 4 high-resolution video images of 2480×1440. The video wall controller can splice the 4 high-resolution video images of 2480×1440 output by the video source into 1 video image of 9920×1440, and divide the video image of 9920×1440 into 4 video images of 1920×900, 2 video images of 3840×540, 1 video image of 2240×900, and 1 video image of 2240×540 respectively, and send the divided video images to their respective corresponding LED display components. The video images displayed by multiple LED display components are combined together to form the video image of 9920×1440 spliced by the video wall controller.

[0045] In order for the video images displayed by one or more LED display components to be normal and smooth without tearing or other phenomena, after the video wall controller divides the source video image into multiple video images of different resolutions (or called original video images), it needs to nest the divided video images in the standard resolution. It can be understood that nesting the video image in the standard resolution can mean: transmitting the video image according to the standard resolution.

[0046] However, the solution of nesting the video image in the standard resolution timing sequence (which can be called the nesting solution) has high requirements for the data transmission link and the LED display component, and the versatility of the solution is not strong.

[0047] For example, for the data transmission link, if the picture area of the video image is small, but the aspect ratio is large or small, the current solution requires a larger standard resolution for nesting, and thus requires a higher transmission link standard and bandwidth.

[0048] Taking the video image of 3840*540P60 as an example, the picture area of this video image is small, but the aspect ratio is large. This video image needs to be nested in the standard 4K (3840*2160P60) resolution, and the video wall controller transmits the nested video image to the LED display component.

[0049] The clock / pixel frequency calculated according to the VESA - coordinated video timings (VESA - CVT) standard for 3840*540P60 is 134.5 megahertz (Mhz). The maximum supported transmission clock in the high definition multimedia interface (HDMI) 1.4 standard is 340Mhz for video images. That is, a transmission link using the HDMI 1.4 standard can transmit video images of 3840*540P60. For the standard 4K (3840*2160P60) resolution, the calculated clock according to the CTA - 861 - G standard is 594Mhz, which is greater than the maximum transmission capacity of 340Mhz of the transmission link using the HDMI 1.4 standard. That is, after nesting the 3840*540P60 video image within the standard 4K (3840*2160P60) resolution, a transmission link using the HDMI2.0 standard with a larger bandwidth is required to transmit the video image.

[0050] For another example, for an LED display component, after receiving the nested video image sent by the video wall controller, it is also necessary to crop and segment the nested video image to obtain the original video image, and then display the original video image.

[0051] Exemplarily, Figure 2 is a cropping schematic diagram. As Figure 2 shown in (a), the total width of the standard 4K resolution is 4400, the total height is 2250, the effective width is 3840, and the effective height is 2160. There is also a blanking area outside the effective area. As Figure 2 shown in (b), taking the example of nesting the 3840*540P60 video image into the standard 4K resolution timing of 3840*2160P60 as above, after nesting the 3840*540P60 video image into the standard 4K resolution timing of 3840*2160P60, the extra area is filled with black data ( Figure 2 shown with hatching in the figure). After the LED display component receives the nested video image, it is necessary to crop and segment the invalid black data to display the effective 3840*540 video image.

[0052] However, not all LED display components support the cropping and segmentation function. The current scheme of nesting video images in the standard resolution has relatively high requirements for LED display components.

[0053] Based on this, the embodiments of the present application provide a splicing display method, device, LED splicing controller, storage medium and system, which can generate a set of custom resolutions with smaller clocks for each potential effective width, effective height, and frame rate (W*H P / I FPS), thereby reducing the requirements for the data transmission link and the LED display component, and improving the versatility of the splicing display solution.

[0054] It should be noted that, for the following introduction, LED is uniformly used as an example. The splicing display method provided by the embodiments of the present application can also be applied to other types of display devices. That is to say, the LED in the following embodiments can also be replaced by a liquid crystal display (LCD) or other types of display devices, etc. The embodiments of the present application do not limit this.

[0055] The following is an introduction in combination with the accompanying drawings.

[0056] Figure 3 It is a schematic diagram of the composition of the LED splicing display system provided by the embodiments of the present application. As Figure 3 shown, the splicing display system includes: a video source 100, an LED splicing controller 200, and one or more LED display components 300. The video source 100, the LED splicing controller 200, and one or more LED display components 300 can be connected through a wired network or a wireless network.

[0057] Among them, the video source 100 can be a computing device with computing and processing functions such as a computer or a server. Among them, the server can be a single server, or, alternatively, it can also be a server cluster composed of multiple servers. In some implementation manners, the server cluster can also be a distributed cluster. The video source 100 can also be implemented on a cloud platform. For example, the cloud platform can include a private cloud, a public cloud, a hybrid cloud, a community cloud, a distributed cloud, an inter-cloud, or a multi-cloud, etc., or any combination thereof.

[0058] For example, the video source 100 can be an ultra-high resolution server / super high resolution server.

[0059] The video source 100 is used to obtain video images. For example, the video source 100 can be connected to an image acquisition device, and the video source 100 can receive the video images sent by the image acquisition device.

[0060] In some embodiments, the video source 100 is also used to send video images to the LED splicing controller 200.

[0061] As described above, the video source 100, the LED controller 200, and one or more LED display components 300 can be connected via a wired network or a wireless network. The wired network or the wireless network may include one or more media or devices capable of transmitting video images from the video source 100 to the LED controller 200.

[0062] In some embodiments, the wired network or the wireless network may include one or more communication media that enable the video source 100 to directly transmit video images to the LED controller 200 in real time. In this embodiment, the video source 100 may modulate the video images according to a communication standard (such as a wireless communication protocol) and transmit the modulated video images to the LED controller 200. The one or more communication media may include wireless, and / or, wired communication media, such as the radiofrequency (RF) spectrum or one or more physical transmission lines. Optionally, the one or more communication media may form part of a packet-based network, which may be, for example, a local area network, a wide area network, or a global network (such as the Internet). Optionally, the one or more communication media may include routers, switches, base stations, or other devices that facilitate communication from the video source 100 to the LED controller 200.

[0063] The LED controller 200 may also be referred to as an LED splicing controller, and its specific form may be referred to the related art and will not be elaborated here.

[0064] The LED controller 200 can be used to receive multiple video images sent by the video source 100, splice the multiple video images sent by the video source 100 into one video image, segment the spliced one video image to obtain the video images corresponding to each LED display component, obtain the target resolution corresponding to each LED display component, and send the video images to each LED display component respectively according to the target resolution corresponding to each LED display component. Among them, the detailed process of obtaining the resolution corresponding to each LED display component can be referred to the following splicing display method and will not be elaborated here.

[0065] There may be multiple LED display components 300, and each LED display component 300 may include a sending card, multiple receiving cards, and multiple LED bead modules.

[0066] The sending card is a video protocol conversion system. The sending card can strip out the video data sent by the controller, process it internally, and send it to the receiving card. The receiving card can control the LED bead modules to emit light and display images according to the internally processed video data sent by the sending card.

[0067] The data transmission between the LED controller 200 and the transmitting card in the LED display component 300 may refer to the data transmission between the video source 100 and the LED controller 200 described above, which will not be elaborated here.

[0068] The execution subject of the splicing display method provided by the embodiments of the present application may be the above-mentioned LED controller 200, or an application (APP) installed in the LED controller 200 that provides the function of obtaining resolution; or, a processor (such as a central processing unit (CPU)) in the LED controller 200; or, a functional module in the LED controller 200 for executing the splicing display method, etc. The embodiments of the present application do not limit this.

[0069] For the convenience of description, hereinafter, the LED controller will be uniformly used as an example of the execution subject of the splicing display method provided by the embodiments of the present application for introduction.

[0070] Figure 4 It is a schematic diagram of the composition of the LED controller provided by the embodiments of the present application. As Figure 4 shown, the LED controller may include: a processor 10, a memory 20, a communication line 30, a communication interface 40, and an input / output interface 50.

[0071] Among them, the processor 10, the memory 20, the communication interface 40, and the input / output interface 50 may be connected through the communication line 30.

[0072] The processor 10 is configured to execute the instructions stored in the memory 20 to implement the splicing display method provided by the following embodiments of the present application. The processor 10 may be a CPU, a general-purpose processor, a network processor (NP), a digital signal processor (DSP), a microprocessor, a microcontroller, a programmable logic device (PLD), or any combination thereof. The processor 10 may also be any other device with processing functions, such as a circuit, a device, or a software module. The embodiments of the present application do not limit this. In one example, the processor 10 may include one or more CPUs, such as Figure 4 the CPU0 and CPU1 in. As an alternative implementation, the electronic device may include multiple processors. For example, in addition to the processor 10, it may also include a processor 60 ( Figure 4 shown by a dotted line in).

[0073] A memory 20 for storing instructions. For example, the instructions can be a computer program. Optionally, the memory 20 can be a read-only memory (ROM) or other type of static storage device that can store static information and / or instructions, or it can be a random access memory (RAM) or other type of dynamic storage device that can store information and / or instructions. It can also be an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM), or other optical disc storage, optical disc storage (including compact discs, laser discs, optical discs, digital versatile discs, Blu-ray discs, etc.), magnetic disk storage media, or other magnetic storage devices. The embodiments of the present application do not limit this.

[0074] It should be noted that the memory 20 can exist independently of the processor 10 or can be integrated with the processor 10. The memory 20 can be located inside the LED controller or outside the LED controller. The embodiments of the present application do not limit this.

[0075] A communication line 30 for transmitting information between the various components included in the LED controller. The communication line 30 can be an industry standard architecture (ISA) line, a peripheral component interconnect (PCI) line, or an extended industry standard architecture (EISA) line, etc. The communication line 30 can be divided into an address line, a data line, a control line, etc. For the sake of simplicity of representation, Figure 4 only a solid line is used to represent it in the figure, but it does not mean that there is only one line or one type of line.

[0076] A communication interface 40 for communicating with other devices (such as the above-mentioned video source 100, or the LED display component 300, etc.) or other communication networks. For example, the communication interface 40 can be a digital visual interface (DVI) or a video interface such as HDMI.

[0077] Optionally, other communication networks communicating with the communication interface 40 may be Ethernet, radio access network (RAN), wireless local area networks (WLAN), etc. The communication interface 40 may be a module, a circuit, a transceiver, or any device capable of implementing communication.

[0078] The input / output interface 50 is used to implement human-computer interaction between the user and the LED controller. For example, it can implement action interaction, text interaction, or voice interaction between the user and the LED controller.

[0079] Exemplarily, the input / output interface 50 may be a mouse, a keyboard, a display screen, or a touch display screen, etc. Through the keyboard, mouse, display screen, or touch display screen, etc., the work interaction or text interaction between the user and the LED controller can be realized.

[0080] It should be noted that Figure 4 the structure shown in Figure 4 does not constitute a limitation on the LED controller. In addition to

[0081] the components shown, the LED controller may include more or fewer components than those shown in the figure, or a combination of certain components, or a different component arrangement.

[0081] Next, the splicing display method provided by the embodiments of the present application will be introduced with reference to the accompanying drawings.

[0082] Figure 5 It is a schematic flowchart of the splicing display method provided by the embodiments of the present application. Optionally, this method can be executed by an LED controller having the above Figure 3 shown hardware structure. As Figure 5 shown, this method includes S101 to S105.

[0083] S101. The LED controller obtains the preset resolution and preset frame rate corresponding to each LED display component.

[0084] Wherein, each LED display component is also each display component in the above one or more LED display components. One or more LED display components may include M rows and N columns of LED display components. Both M and N are integers greater than or equal to 1. As described above, one LED display component may include one sending card, multiple receiving cards, and multiple LED bead modules. M rows and N columns of LED display components can also be understood as M rows and N columns of sending cards. One sending card may correspond to multiple receiving cards and multiple LED bead modules. The specific number of receiving cards and LED bead modules corresponding to one sending card in the embodiments of the present application is not limited. The preset resolution may include a preset effective width and a preset effective height, etc.

[0085] As described above, the LED controller can include an input / output interface, which can be a mouse, a keyboard, or a touch display screen, etc. The LED controller can receive, through a mouse, a keyboard, or a touch display screen, etc., the preset effective width, the preset effective height, and the preset frame rate required to be displayed by one or more LED display components input by a user.

[0086] S102. The LED controller determines one or more target candidate clocks according to the preset frame rate of each LED display component.

[0087] Among them, the target candidate clock is a clock that satisfies the following first condition: the quotient obtained by dividing it by the preset frame rate of any one LED display component is greater than or equal to the product of the preset effective width and the preset effective height corresponding to any one LED display component.

[0088] Optionally, the LED controller can determine a plurality of initial clocks from a plurality of clocks between the minimum clock supported by the LED controller and the maximum clock supported by the LED controller according to the preset clock step accuracy, and determine one or more initial candidate clocks that satisfy the second condition from the plurality of initial clocks according to the number of factors of the quotient obtained by dividing each initial clock by the preset frame rate of any one LED display component and the second condition, and determine one or more target candidate clocks from the one or more initial candidate clocks based on the initial resolution corresponding to the one or more initial candidate clocks.

[0089] Among them, the clock step accuracy can be preset by a manager in the LED controller, and the clock step accuracy is used to indicate the clock interval between adjacent initial clocks. For example, the clock step accuracy can be 1 kilohertz (kHz), or 1 MHz, etc. The specific value of the clock step accuracy in the embodiments of the present application is not limited. The minimum clock can also be preset by a manager in the LED controller, and the specific value of the minimum clock in the embodiments of the present application is not limited. The maximum clock can also be preset by a manager in the LED controller, or the LED controller can first determine the maximum limit bandwidth of the current scene according to the maximum limit bandwidth input by the user, and then the LED controller can determine the maximum limit clock corresponding to the maximum limit bandwidth of the current scene as the above-mentioned maximum clock according to the maximum limit bandwidth and the corresponding relationship between the maximum limit bandwidth and the maximum limit clock preset. The specific value of the maximum clock in the embodiments of the present application is not limited. The second condition is that the number of factors of the quotient obtained by dividing it by the preset frame rate of any one LED display component is greater than the number threshold.

[0090] Optionally, the LED controller can determine a plurality of initial clocks from a plurality of clocks between the minimum clock and the maximum clock in a preset order.

[0091] For example, the LED controller can start from the minimum clock, select an initial clock every clock step precision until it traverses from the minimum clock to the maximum clock.

[0092] The clock step precision is used to indicate the minimum interval for selecting candidate clocks among multiple clocks from the minimum clock to the maximum clock.

[0093] For example, if the minimum clock is 100Mhz, the clock step precision is 1Mhz, and the maximum limit bandwidth of the current scenario is 10.2 gigabits per second (Gbps) (that is, the video image data is transmitted using the transmission link of the HDMI 1.4 standard in the current scenario), the LED controller can determine the maximum limit clock 340Mhz corresponding to 10.2 (Gbps) as the maximum clock according to the corresponding relationship between the maximum limit bandwidth and the maximum limit clock, and traverse the minimum clock 100Mhz and the maximum clock 340Mhz with 1Mhz as the step precision to obtain multiple clocks 101Mhz, 102Mhz, 103Mhz,..., 339Mhz, and 340Mhz, and determine multiple initial clocks from these multiple clocks.

[0094] Exemplarily, the initial resolutions corresponding to one or more initial candidate clocks can be as shown in Table 1 below.

[0095] Table 1

[0096] Resolution ID Initial candidate clock Total width Total height Effective width Effective height Frame rate Resolution 1 Clock 1 Total width 1 Total height 1 Effective width 1 Effective height 1 Frame rate 1 Resolution 2 Clock 1 Total width 2 Total height 2 Effective width 2 Effective height 2 Frame rate 2 Resolution 3 Clock 2 Total width 3 Total height 3 Effective width 3 Effective height 3 Frame rate 3

[0097] As shown in Table 1, the initial resolutions corresponding to one or more initial candidate clocks can include a resolution ID item, an initial candidate clock item, a total width item, a total height item, an effective width item, an effective height item, and a frame rate item. Among them, the resolution ID item can include Resolution 1, Resolution 2, and Resolution 3. The initial candidate clock item can include Clock 1 and Clock 2. The total width item can include Total Width 1, Total Width 2, and Total Width 3. The total height item can include Total Height 1, Total Height 2, and Total Height 3. The effective width item can include Effective Width 1, Effective Width 2, and Effective Width 3. The effective height item can include Effective Height 1, Effective Height 2, and Effective Height 3. The frame rate item can include Frame Rate 1, Frame Rate 2, and Frame Rate 3. There is a corresponding relationship among Resolution 1, Clock 1, Total Width 1, Total Height 1, Effective Width 1, Effective Height 1, and Frame Rate 1. There is a corresponding relationship among Resolution 2, Clock 1, Total Width 2, Total Height 2, Effective Width 2, Effective Height 2, and Frame Rate 2. There is a corresponding relationship among Resolution 3, Clock 2, Total Width 3, Total Height 3, Effective Width 3, Effective Height 3, and Frame Rate 3.

[0098] Optionally, taking the example that one or more initial candidate clocks include the first clock and the preset frame rates corresponding to one or more LED display components are all the first frame rate, before the LED controller determines one or more target candidate clocks from one or more initial candidate clocks based on the initial resolutions corresponding to the one or more initial candidate clocks, the LED controller may also generate an initial resolution based on the one or more initial candidate clocks.

[0099] Optionally, the LED controller generating an initial resolution based on one or more initial candidate clocks may include the following four steps:

[0100] Step 1: The LED controller performs one or more factorizations on the first area obtained by dividing the first clock by the first frame rate, and each time decomposes the first area into two factors.

[0101] Step 2: For each factorization, the LED controller takes one of the two factors obtained by the factorization (for example, the larger one) as the maximum width and the other of the two factors obtained by the factorization (for example, the smaller one) as the maximum height.

[0102] Step 3: The LED controller determines the effective width according to the maximum width and determines the effective height according to the maximum height.

[0103] For example, the LED controller may subtract 80 from the maximum width to obtain the effective width. Also taking the above first frame rate and first area as an example, the LED controller may calculate a first value according to the VESA-CVT standard with the first clock, the first frame rate, and the first area, etc., and subtract the first value from the maximum height to obtain the effective height.

[0104] Step 4: The LED controller generates one of a variety of initial resolutions based on the maximum width, the maximum height, the effective width, and the effective height.

[0105] In a possible implementation, the LED controller determining one or more initial candidate clocks from multiple initial clocks according to the number of factors of the quotient obtained by dividing each initial clock by the target frame rate of any one LED display component and a second condition may include: The LED controller obtains from the multiple initial clocks one or more first initial clocks for which the number of factors of the quotient obtained by dividing by the target frame rate of any one LED display component is greater than a number threshold, and determines the initial candidate clocks from the one or more first initial clocks.

[0106] Among them, the quantity threshold can be preset by the administrator. For example, the quantity threshold can be 8, 10, or 12, etc. The embodiments of the present application do not limit the specific value of the quantity threshold. In this possible implementation, the second condition can be understood as when the number of factors of the quotient obtained by dividing any target frame rate of the LED display component is greater than the quantity threshold, the initial clock is determined as the first initial clock.

[0107] Optionally, in this possible implementation, the above-mentioned LED controller determines one or more target candidate clocks from one or more initial candidate clocks based on the initial resolutions corresponding to one or more initial candidate clocks, which may include: if one or more initial candidate clocks include an initial candidate clock that meets the first condition, the LED controller determines one or more target candidate clocks from one or more initial candidate clocks based on the initial resolutions corresponding to one or more initial candidate clocks.

[0108] In another possible implementation, the LED controller can screen out initial candidate clocks of different gradient queues from the initial clocks according to different granularities. In this case, the method may further include: if one or more first initial clocks do not include an initial candidate clock that meets the first condition, obtaining one or more second initial clocks in the multiple initial clocks, where the number of factors of the quotient obtained by dividing any preset frame rate of the LED display component is less than or equal to the quantity threshold, and determining one or more initial candidate clocks from one or more second initial clocks.

[0109] Optionally, the LED controller can also obtain a standard clock instruction. After determining one or more initial candidate clocks, the LED controller can also delete the clocks other than the standard clock in the initial candidate clocks, so that the LED controller only retains the standard clock in the initial candidate clocks.

[0110] Among them, the standard clock refers to the clock in the standard protocol. The acquisition method of the standard clock instruction can refer to the description of obtaining the preset resolutions of one or more LED display components through the input / output interface in the above S101, which will not be elaborated here.

[0111] Optionally, the LED controller can also default to screen one or more initial candidate clocks according to the standard clock. In this case, determining one or more initial candidate clocks from one or more first initial clocks includes: using the first initial clock that is the same as the standard clock in one or more first initial clocks as the initial candidate clock; determining one or more initial candidate clocks from one or more second initial clocks includes: using the first initial clock that is the same as the standard clock in one or more first initial clocks as the initial candidate clock.

[0112] Optionally, the LED controller can also obtain the capability information of one or more LED display components, and determine the clocks supported by any one LED display component and the clocks supported by the LED controller based on the capability information of one or more LED display components and the capability information of the LED controller. After determining one or more initial candidate clocks, the LED controller can also delete the clocks outside the union of the clocks supported by one or more LED display components and the clocks supported by the LED controller among the initial candidate clocks.

[0113] Among them, the capability information of the LED display component is used to indicate the clocks supported by the sending card and the receiving card in the LED display component.

[0114] In a possible implementation, taking the first initial candidate clock as an example, the above-mentioned LED controller can determine one or more target candidate clocks from one or more initial candidate clocks based on the initial resolutions corresponding to one or more initial candidate clocks, which may include: for each initial resolution among the one or more initial resolutions corresponding to the first initial candidate clock, the LED controller determines whether the initial resolution supports any one LED display component; if there is an initial resolution among the one or more initial resolutions corresponding to the first initial candidate clock that supports any one LED display component, the first initial candidate clock is determined as the target candidate clock.

[0115] For example, the LED controller can compare the effective width and effective height in the initial resolution with the preset effective width and preset effective height of a certain LED display component. When the effective width in the initial resolution is greater than or equal to the preset effective width of the LED display component and the effective height in the initial resolution is greater than or equal to the preset effective height of the LED display component, the LED controller can determine that the initial resolution supports the LED display component.

[0116] S103. The LED controller determines the smallest one of the one or more target candidate clocks as the target clock of the one or more LED display components.

[0117] For example, the LED controller can sort the one or more target candidate clocks in ascending order to obtain a second sorting result, and determine the first target candidate clock in the second sorting result as the target clock.

[0118] S104. The LED controller determines the target resolution corresponding to each LED display component based on the target clock.

[0119] Among them, the target resolution includes the target effective width, the target effective height, and the target frame rate, etc.

[0120] Optionally, as described above, the LED controller can generate an initial resolution based on one or more initial candidate clocks. After determining the target clock, the LED controller can also use the target clock as an index to traverse the generated initial resolutions, determine one or more initial resolutions corresponding to the target clock as candidate resolutions, and determine the target resolution corresponding to each LED display component from the one or more candidate resolutions based on the preset effective width and preset effective height in the preset resolution corresponding to each LED display component.

[0121] Optionally, the LED controller can sort one or more candidate resolutions in ascending order of the effective width to obtain a first sorting result, and select the target resolution according to the first sorting result. Figure 6 Another flowchart of the splicing display method provided by the embodiment of the present application. As Figure 6 shown, taking the first LED display component as an example, the above S104 may specifically include S201 to S211.

[0122] S201. The LED controller obtains the preset effective width and preset effective height of the first LED display component.

[0123] S201 can refer to S101 described above and will not be elaborated here.

[0124] S202. The LED controller sorts one or more candidate resolutions in ascending order of the effective width to obtain a first sorting result.

[0125] S203. The LED controller determines whether the number of times of currently selecting candidate resolutions is greater than or equal to the number of candidate resolutions in the first sorting result.

[0126] If so, execute S204; if not, execute S205.

[0127] S204. The LED controller sends a first message.

[0128] Wherein, the first message is used to indicate the end of the process of screening the target resolution from the initial candidate resolutions.

[0129] As described above, the LED controller may include an input / output interface, and the input / output interface may be a touch display screen. The LED controller may display a first interface on the touch display screen, and the first interface includes the above first message.

[0130] S205. The LED controller determines whether the effective width of the currently selected candidate resolution is greater than or equal to the preset effective width corresponding to the first LED display component, and whether the effective height of the currently selected candidate resolution is greater than or equal to the preset effective height corresponding to the first LED display component.

[0131] If so, execute S206; if not, execute S207.

[0132] S206. The LED controller determines the currently selected candidate resolution as the target resolution corresponding to the first LED display component.

[0133] S207. The LED controller determines whether the effective width of the currently selected candidate resolution is greater than or equal to the preset effective width of the first LED display component, and whether the effective height of the currently selected candidate resolution is less than the preset effective height of the first LED display component.

[0134] If so, execute S208 and S209 and then return to S203; if not, execute S210.

[0135] S208. The LED controller selects the candidate resolution before the currently selected candidate resolution in the first sorting result for judgment.

[0136] S209. The LED controller increments the number of times of the currently selected candidate resolution by 1.

[0137] S210. The LED controller determines whether the effective width of the currently selected candidate resolution is less than the preset effective width of the first LED display component, and whether the effective height of the currently selected candidate resolution is greater than or equal to the preset effective height of the first LED display component.

[0138] If so, execute S211 and S209 and then return to S203; if not, execute S204.

[0139] S211. The LED controller selects the candidate resolution after the currently selected candidate resolution in the first sorting result for judgment.

[0140] It should be noted that in S201 to S211, taking the LED controller to judge by obtaining the preset effective width and preset effective height of one LED display component each time and selecting the target resolution corresponding to the LED display component as an example, the LED controller can judge one or more LED display components according to the steps of S201 to S211 and select the target resolution corresponding to each LED display component.

[0141] Optionally, after determining the target resolution corresponding to each LED display component, the LED controller can also correct the target resolution according to the resolution standard. For example, correct the target resolution according to the VESA-CVT standard or the VESA-graphics interchange format (GIF) standard, so that the target resolution meets the resolution standard and ensures the compatibility between the LED controller and the LED display component.

[0142] Optionally, after determining the target resolution corresponding to each LED display component, the LED controller can also correct the target resolution according to the hardware bit width limit of the transmission link, so that when the LED controller sends the target resolution to the LED display component, the bit width of each parameter in the sent target resolution is less than the hardware bit width limit of the transmission link. In this case, taking the clock in the target resolution as an example, the method can further include: the LED controller obtains the bit width information of each LED display component; the LED controller modifies the target clock in the target resolution corresponding to each LED display component according to the bit width information sent by each LED display component and the bit width information of the LED controller, so that the bit width of the target clock in the target resolution corresponding to one or more LED display components is less than or equal to the minimum value of the maximum bit width of the transmission clock of the transmission link indicated by the bit width information sent by each LED display component and the maximum bit width of the transmission clock of the LED controller indicated by the bit width information of the LED controller.

[0143] Among them, the bit width information of the LED controller can be preset in the LED controller. For example, preset in the memory of the LED controller. The specific content of the bit width information of the LED controller and the value of the indicated maximum bit width are not limited in the embodiments of the present application.

[0144] Optionally, the LED controller can first correct the target resolution according to the resolution standard, and then correct the target resolution according to the hardware bit width limit of the transmission link. In this case, Figure 7 Another schematic flow chart of the splicing display method provided by the embodiments of the present application. As Figure 7 shown, after S104, the method can further include S301 to S305.

[0145] S301. The LED controller obtains the bit width information of each LED display component.

[0146] Among them, the bit width information of the LED display component is used to indicate the maximum bit width of the transmission clock of the transmission link between the LED controller and the LED display component. For example, the LED controller can obtain it by receiving the bit width information sent by each LED display component.

[0147] S302. The LED controller corrects the target resolution corresponding to each LED display component according to the resolution standard.

[0148] Among them, the specific correction process can be referred to the related technology of the resolution standard and will not be elaborated here.

[0149] S303. The LED controller determines whether the bit width of the target clock in the target resolution corresponding to each LED display component is less than or equal to the minimum value of the maximum bit width of the transmission link transmission clock indicated by the bit width information sent by each LED display component and the maximum bit width of the LED controller transmission clock indicated by the bit width information of the LED controller.

[0150] If so, execute S304; if not, execute S305 and then execute S304.

[0151] S304. The LED controller outputs the target resolution.

[0152] S305. The LED controller adjusts the target resolution corresponding to each LED display component so that the bit width of the target clock in the target resolution corresponding to each LED display component is less than or equal to the minimum value of the maximum bit width of the transmission link transmission clock indicated by the bit width information sent by each LED display component and the maximum bit width of the LED controller transmission clock indicated by the bit width information of the LED controller.

[0153] It should be noted that the above introduces the correction process taking the clock in the target resolution as an example. The correction processes of other parameters in the target resolution, such as the maximum width, maximum height, effective width, effective height, etc., can also be referred to the above S301 to S305 and will not be elaborated here.

[0154] Optionally, refer to Figure 8 , Figure 8 which is the schematic diagram of the simulation algorithm provided by the embodiment of the present application. As shown in Figure 8 , before S104, the LED controller can also determine the maximum bandwidth M0 of the output interface based on the interface standard of the current LED controller output interface, and through an offline computer simulation algorithm, screen out the globally optimal pixel clock solution that matches this maximum bandwidth, and output the database of the total width, total height, and frame rate at this pixel clock as the basis for determining the target resolution of each LED display component in the above S104. For downward compatibility, the database of the total width, total height, and frame rate that matches the globally optimal pixel clock solution under other bandwidths can also be output simultaneously.

[0155] Optionally, as described above, one or more LED display components may include an LED display component of M rows and N columns. When N is greater than or equal to 2, the method may further include: the LED controller adjusts the size of the horizontal front porch (HFP) in the target resolution corresponding to each row of the M rows of LED display components, so that the horizontal blanking size of each row of the M rows of LED display components decreases sequentially from left to right.

[0156] For example, the LED controller may obtain the number of rows and columns of one or more LED display components. When the number of columns is greater than 2, that is, each row includes one or more LED display components, and at this time, the LED display components in each row need to be synchronously displayed. At this time, the LED controller (or the timing control module in the following LED controller) may turn on the internal row synchronization flag, and (or the output module in the following LED controller) in response to the internal row synchronization flag, adjusts the size of the horizontal front porch (HFP) in the target resolution corresponding to each row of the M rows of LED display components, so that the horizontal blanking size of each row of the M rows of LED display components decreases sequentially from left to right.

[0157] It should be understood that when each row of the M rows of LED display components includes multiple components, reducing the horizontal blanking of the LED display components in that row can reduce the out-of-synchronization between adjacent LED display components in a row due to the scanning sequence.

[0158] Optionally, as described above, one or more LED display components may include an LED display component of M rows and N columns. Both M and N are integers greater than or equal to 1. When both M and N are greater than or equal to 2, that is, one or more LED display components include multiple rows and multiple columns, each frame of video image of the LED display components of multiple rows and multiple columns needs to be synchronously displayed. At this time, the LED controller may turn on the internal frame synchronization flag, and in response to the internal frame synchronization flag, obtain the target resolution according to the steps described in S101 to S104 above. When one or more LED display components include 1 row and 1 column, that is, 1 LED display component, the LED controller may turn off the internal frame synchronization flag and only obtain the target resolution corresponding to the 1 LED display component. The specific process may also refer to S101 to S104 above and will not be elaborated here.

[0159] S105. The LED controller sends sub-video images to each LED display component according to the target resolution corresponding to each LED display component, so that each LED display component displays the sub-video images according to the corresponding target resolution.

[0160] Among them, the sub-video image is obtained by the LED controller splicing and controlling the video image (that is, the video image obtained after splicing multiple video images output by the aforementioned LED controller from the video source), and the sub-video images displayed by each LED display component are spliced together to obtain the video image.

[0161] Exemplarily, Figure 9 is the display effect diagram of the custom resolution provided by the embodiment of the present application. As Figure 9 shown, taking the target effective width and target effective height corresponding to the LED display component as 2240×540, 2240×900, 1920×900, and 3840×540 as examples, assuming that the solid line area shown above Figure 2 represents the effective display area and the dotted line area represents the total width and height area, then after generating the custom resolution for the target effective width and target effective height corresponding to each LED display component by using the splicing display method provided by the embodiment of the present application, the area of the total width and height area is smaller, the corresponding clock is also smaller, and the contour of the total width and height area fits the contour of the effective display area, without the need for the sending card that receives the video image to crop and divide the video image again.

[0162] The splicing display method provided by the embodiment of the present application can generate the target resolution corresponding to each LED display component according to the preset effective width, preset effective height, and preset frame rate required to be displayed by each LED display component. For LED display components with different preset effective widths, different preset effective heights, and different preset frame rates, the LED controller first determines the target candidate clocks that meet each LED display component, and selects the smallest one from the target candidate clocks as the target clock, and generates the target resolution corresponding to each LED display component based on the smallest target clock. Since the target clock is smaller, and the smaller the clock, the lower the requirement for the data transmission link, so the requirement for the data transmission link is reduced, and the flexibility of the splicing display solution is improved. Moreover, since the target clock is smaller, the product of the effective width and the effective height in the target resolution determined based on the target clock is also smaller, and the area of the effective display area corresponding to the target resolution is also smaller, which is more consistent with the area of the effective display area corresponding to the preset resolution. After the LED controller transmits the video image to the LED display component according to the target resolution, the LED display component (or the sending card in the LED display component) does not need to crop and divide the received video image, which reduces the requirement for the function of the LED display component and improves the flexibility of the splicing display solution.

[0163] In addition, the target clocks in the target resolutions corresponding to multiple LED display components are the same, and the clocks of the LED splicing controller are consistent at any resolution, so that frame out-of-sync between the video images displayed by multiple LED display components will not be caused by clock (or pixel frequency) deviation (frequency offset).

[0164] It should be noted that the above introduces the splicing display method provided in the embodiments of the present application by taking LED as an example. As described above, this method can also be applied to LCD or other types of display devices. When this method is applied to LCD, the corresponding LCD splicing controller can perform splicing display according to the standard resolution, or generate a custom resolution for display according to the above splicing display method. The embodiments of the present application do not limit this.

[0165] In an exemplary embodiment, the present application provides another composition structure of the LED splicing controller. Figure 10 It is another composition schematic diagram of the LED splicing controller provided in the embodiments of the present application. As Figure 10 shown, the LED splicing controller may include an input subsystem and K output sub-systems, where K is an integer greater than or equal to 1, and each output sub-system may include a clock synchronization module, a timing control module, and an output module.

[0166] The input subsystem can receive multiple video images input by the video source, splice the multiple video images input by the video source into one video image, and segment the spliced video image, and send the K segmented video images to the K output sub-systems through the internal / external bus respectively.

[0167] The output sub-system can ensure the clock phase synchronization between the K output sub-systems through the clock synchronization module, and ensure the synchronization of the K picture contents output by the K output sub-systems through the internal logic of the output module. Specifically, it can refer to the related technology and will not be elaborated here.

[0168] The timing control module can be used to execute the steps in the above splicing display method. Exemplarily, Figure 11 It is a function schematic diagram of the timing control module provided in the embodiments of the present application. As Figure 11 shown, the timing control module has a database generation (generating according to constraint conditions) function, a database screening (screening according to constraint conditions) function, a resolution screening (screening according to the target effective width and target effective height of one or more LED display components) function, and a resolution generation (generating according to constraint conditions) function.

[0169] Among them, the database generation function can be referred to the description of generating the initial resolution corresponding to the initial candidate clock in S102 above, which will not be elaborated here. The database screening function can be referred to the description of screening the target candidate clock from the initial candidate clock in S102 above, which will not be elaborated here. The resolution screening function can be referred to the description of S201 to S211 above, which will not be elaborated here. The resolution generation function can be referred to the description of S301 to S305 above, which will not be elaborated here.

[0170] As can be seen from the above splicing display method, the design constraints of this application mainly include two aspects: synchronization constraints and other constraints.

[0171] Figure 12 It is a schematic structural diagram of the synchronization constraint provided by the embodiment of this application. As Figure 12 shown, for the LED splicing control display system, the synchronization constraint can include constraints related to the LED splicing controller and constraints related to the LED display component, etc. Among them, the constraints related to the LED splicing controller can include synchronization constraints of the transmission link and synchronization constraints of the image content, etc. The synchronization constraints of the transmission link can include frame synchronization constraints, line synchronization constraints, and clock source synchronization constraints, etc.

[0172] Figure 13 It is a schematic structural diagram of the other constraints provided by the embodiment of this application. As Figure 13 shown, the other constraints involved in this application refer to various constraints in the actual user demand scenario, including clock compatibility constraints, output scale scenario constraints, data transmission link constraints, etc.

[0173] The clock compatibility constraint means that the sending cards of some brands only support or prefer to support the clocks specified in the standard resolution on the receiving clock. Therefore, in the splicing display method of this application, two modes of "global clock coverage" and "standard clock coverage" can be selected. When the standard clock coverage is selected, the clock on which the generated resolution depends will only be selected from the standard clocks (that is, the target clocks of the above standard sequence). When the global clock coverage is selected, the clock on which the generated resolution depends can be selected from clocks other than the standard clocks (that is, the initial candidate clocks determined from the first clock and the second clock above).

[0174] The output scale scenario constraint mainly adjusts the resolution generation strategy according to the actual splicing form. For example, in the output splicing scenario of 1×1, the LED controller will directly skip all synchronization constraints. In the output splicing scenario of M×N (M≥2), the LED controller will execute the line synchronization constraint link (i.e., turn on the line synchronization flag). Or in the output splicing scenario of M×N (M = 1, N≥2), the LED controller will skip the line synchronization constraint mitigation. In the output splicing scenario of M×N (M≥2, N≥2), the LED controller will execute all synchronization constraint links (i.e., turn on the line synchronization flag and turn on the frame synchronization flag).

[0175] The data transmission link constraint mainly constraints the maximum limit bandwidth, hardware bit length, and clock holes on the data transmission link.

[0176] In the limitations of the maximum limit bandwidth, for example, some sending cards use DVI interfaces and support a maximum clock of 170Mhz, some sending cards use HDMI 1.4 interfaces and support a maximum clock of 340Mhz, and some sending cards use HDMI2.0 interfaces and support a maximum clock of 600Mhz, etc.

[0177] The limitation in terms of hardware bit length means that the resolutions in the sending card and the receiving card are obtained or configured through the corresponding registers inside the chip, and the bit lengths of these registers limit the generation and acquisition of the resolution.

[0178] The limitation in terms of clock holes means that the chip manufacturer may have some clock holes in the hardware or software design. Clock holes are also clocks that are not supported. Therefore, when screening the target clock from the candidate clocks, this part of the candidate clocks that are not supported can also be excluded.

[0179] The above mainly introduces the solution provided by the embodiments of the present application from the perspective of methods. To implement the above functions, it includes the corresponding hardware structures and / or software modules for executing each function. Those skilled in the art should easily realize that, combining the units and algorithm steps of each example described in the embodiments disclosed in this article, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a certain function is executed in the way of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Skilled professionals can use different methods for each specific application to implement the described functions, but such implementation should not be considered to exceed the scope of the present application.

[0180] In an exemplary embodiment, the embodiments of the present application further provide a controller display device, and this device can apply the above LED controller. Figure 14 It is a schematic diagram of the composition of the controller display device provided by the embodiments of the present application. AsFigure 14 As shown, the device includes an acquisition module 1401, a processing module 1402, and a transmission module 1403.

[0181] The acquisition module 1401 is configured to acquire a preset resolution and a preset frame rate corresponding to each LED display component; wherein, the preset resolution includes a preset effective width and a preset effective height;

[0182] The processing module 1402 is configured to determine one or more target candidate clocks according to the preset frame rate of each LED display component; the target candidate clock is a clock that satisfies the following first condition: the quotient obtained by dividing it by the preset frame rate of any one LED display component is greater than or equal to the product of the preset effective width and the preset effective height of any one LED display component; determine the smallest one of the one or more target candidate clocks as the target clock of the one or more LED display components; based on the target clock, determine the target resolution corresponding to each LED display component;

[0183] The transmission module 1403 is configured to send sub-video images to each LED display component according to the target resolution corresponding to each LED display component, so that each LED display component displays the sub-video images according to the corresponding target resolution; wherein, the sub-video images are obtained by the video wall controller splitting the video image, and the sub-video images displayed by each LED display component are spliced together to obtain the video image.

[0184] In some possible embodiments, the processing module 1402 is specifically configured to determine a plurality of initial clocks from a plurality of clocks between the minimum clock and the maximum clock according to a preset clock step accuracy; the preset clock step accuracy is used to indicate the clock interval between adjacent initial clocks; determine one or more initial candidate clocks that satisfy the second condition from the plurality of initial clocks according to the number of factors of the quotient obtained by dividing each initial clock by the preset frame rate of any one LED display component, and the second condition; the second condition is: the number of factors of the quotient obtained by dividing it by the preset frame rate of any one LED display component is greater than a number threshold; determine one or more target candidate clocks from the one or more initial candidate clocks based on the initial resolutions corresponding to the one or more initial candidate clocks, and each initial candidate clock corresponds to one or more initial resolutions;

[0185] In some other possible embodiments, the processing module 1402 is specifically configured to obtain, from multiple initial clocks, one or more first initial clocks whose number of factors of the quotient obtained by dividing any preset frame rate of an LED display component is greater than a number threshold, and determine an initial candidate clock from the one or more first initial clocks; if the one or more initial candidate clocks include an initial candidate clock that meets the first condition, then determine one or more target candidate clocks from the one or more initial candidate clocks based on the initial resolutions corresponding to the one or more initial candidate clocks;

[0186] In some other possible embodiments, the processing module 1402 is further configured to, if the one or more initial candidate clocks do not include an initial candidate clock that meets the first condition, obtain one or more second initial clocks in the multiple initial clocks whose number of factors of the quotient obtained by dividing any preset frame rate of an LED display component is less than or equal to the number threshold; determine one or more initial candidate clocks from the one or more second initial clocks;

[0187] In some other possible embodiments, the processing module 1402 is specifically configured to use the first initial clock that is the same as the standard clock among the one or more first initial clocks as the initial candidate clock; use the first initial clock that is the same as the standard clock among the one or more first initial clocks as the initial candidate clock;

[0188] In some other possible embodiments, the one or more initial candidate clocks include a first clock, and the preset frame rate of the one or more LED display components is a first frame rate; before determining one or more target candidate clocks from the one or more initial candidate clocks based on the initial resolutions corresponding to the one or more initial candidate clocks, the processing module 1402 is further configured to perform one or more factorizations on the first area obtained by dividing the first clock by the first frame rate, and each time decompose the first area into two factors; for each factorization, use one of the two factors obtained by the factorization as the maximum width and the other of the two factors obtained by the factorization as the maximum height; determine the effective width according to the maximum width and determine the effective height according to the maximum height; generate one of the multiple initial resolutions based on the maximum width, the maximum height, the effective width, and the effective height;

[0189] In some other possible embodiments, the one or more LED display components include an LED display component with M rows and N columns, where both M and N are integers greater than or equal to 1. When N is greater than or equal to 2, the processing module 1402 is further configured to adjust the horizontal front porch HFP in the target resolution corresponding to each row of the M rows of LED display components, so that the horizontal blanking size of each row of the M rows of LED display components decreases sequentially from left to right.

[0190] It should be noted that Figure 14The division of modules herein is illustrative and is merely a logical function division. In actual implementation, there may be other division methods. For example, two or more functions may also be integrated into one processing module. The above integrated module may be implemented in the form of hardware or in the form of a software function module.

[0191] In an exemplary embodiment, the embodiment of the present application further provides a readable storage medium, including execution instructions, which when running on a video wall controller, cause the video wall controller to execute any one of the methods provided in the above embodiments.

[0192] In an exemplary embodiment, the embodiment of the present application further provides a computer program product including computer execution instructions, which when running on a video wall controller, cause the video wall controller to execute any one of the methods provided in the above embodiments.

[0193] In an exemplary embodiment, the embodiment of the present application further provides a chip, including: a processor and an interface. The processor is coupled to a memory through the interface. When the processor executes a computer program in the memory or the video wall controller executes instructions, any one of the methods provided in the above embodiments is executed.

[0194] In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using a software program, it may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer execution instructions. When the computer execution instructions are loaded and executed on a computer, the processes or functions according to the embodiments of the present application are generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer execution instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer execution instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center in a wired manner (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or a wireless manner (such as infrared, wireless, microwave, etc.). The computer-readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server or a data center that includes one or more integrated media. The available medium may be a magnetic medium (such as a floppy disk, a hard disk, a magnetic tape), an optical medium (such as a DVD), or a semiconductor medium (such as a solid state disk (SSD)), etc.

[0195] Although the present application has been described in connection with various embodiments, those skilled in the art will understand and realize other variations of the disclosed embodiments by referring to the drawings, the disclosure, and the appended claims when implementing the claimed application. In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude a plurality. A single processor or other unit may implement several functions recited in the claims. Certain measures are recited in mutually different dependent claims, but this does not mean that these measures cannot be combined to achieve good results.

[0196] Although the present application has been described in connection with specific features and their embodiments, it is obvious that various modifications and combinations can be made without departing from the spirit and scope of the present application. Accordingly, the present specification and the drawings are merely exemplary illustrations of the present application as defined by the appended claims, and are considered to cover any and all modifications, variations, combinations, or equivalents within the scope of the present application. Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application is also intended to include these changes and modifications.

[0197] As described above, the foregoing are only specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present application should be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be determined by the protection scope of the claims.

Claims

1. A splicing display method, characterized in that, The method is applied to a video wall controller, which is connected to one or more display components. The method includes: Obtaining a preset resolution and a preset frame rate corresponding to each display component; wherein, the preset resolution includes a preset effective width and a preset effective height; Determining one or more target candidate clocks according to the preset frame rate of each display component; the target candidate clock is a clock that satisfies the following first condition: the quotient obtained by dividing it by the preset frame rate of any one display component is greater than or equal to the product of the preset effective width and the preset effective height of any one display component; Determining the smallest one of the one or more target candidate clocks as the target clock of the one or more display components; Determining a target resolution corresponding to each display component based on the target clock; Sending a sub-video image to each display component according to the target resolution corresponding to each display component, so that each display component displays the sub-video image according to the corresponding target resolution; wherein, the sub-video image is obtained by the video wall controller splitting the video image, and the sub-video images displayed by each display component are spliced together to obtain the video image.

2. The method according to claim 1, characterized in that The determining one or more target candidate clocks according to the preset frame rate of each display component includes: Determining a plurality of initial clocks from a plurality of clocks between the minimum clock and the maximum clock according to a preset clock step accuracy; the preset clock step accuracy is used to indicate the clock interval between adjacent initial clocks; Determining one or more initial candidate clocks that satisfy the second condition from the plurality of initial clocks according to the number of factors of the quotient obtained by dividing each initial clock by the preset frame rate of any one display component and the second condition; the second condition is: the number of factors of the quotient obtained by dividing it by the preset frame rate of any one display component is greater than a number threshold; Determining the one or more target candidate clocks from the one or more initial candidate clocks based on the initial resolutions corresponding to the one or more initial candidate clocks, and each initial candidate clock corresponds to one or more initial resolutions.

3. The method according to claim 2, wherein The determining one or more initial candidate clocks that satisfy the second condition from the plurality of initial clocks according to the number of factors of the quotient obtained by dividing each initial clock by the preset frame rate of any one display component and the second condition includes: Obtaining one or more first initial clocks from the plurality of initial clocks, where the number of factors of the quotient obtained by dividing any one of the first initial clocks by the preset frame rate of any one display component is greater than the number threshold, and determining initial candidate clocks from the one or more first initial clocks; The determining the one or more target candidate clocks from the one or more initial candidate clocks based on the initial resolutions corresponding to the one or more initial candidate clocks includes: If there are initial candidate clocks that satisfy the first condition among the one or more initial candidate clocks, then determining the one or more target candidate clocks from the one or more initial candidate clocks based on the initial resolutions corresponding to the one or more initial candidate clocks.

4. The method according to claim 3, wherein The method further includes: If none of the one or more initial candidate clocks satisfies the first condition, obtain one or more second initial clocks from the multiple initial clocks, where the number of factors of the quotient obtained by dividing any one of the preset frame rates of the display components is less than or equal to the number threshold; Determine the one or more initial candidate clocks from the one or more second initial clocks.

5. The method according to claim 4, wherein Determining the one or more initial candidate clocks from the one or more first initial clocks includes: using the first initial clock that is the same as the standard clock among the one or more first initial clocks as the initial candidate clock; Determining the one or more initial candidate clocks from the one or more second initial clocks includes: using the second initial clock that is the same as the standard clock among the one or more second initial clocks as the initial candidate clock.

6. The method according to any one of claims 2 to 4, characterized in that The one or more initial candidate clocks include a first clock, and the preset frame rate of the one or more display components is a first frame rate; before determining the one or more target candidate clocks from the one or more initial candidate clocks based on the initial resolutions corresponding to the one or more initial candidate clocks, the method further includes: Performing one or more factorizations on the first area obtained by dividing the first clock by the first frame rate, and each time decomposing the first area into two factors; For each factorization, using one of the two factors obtained by the factorization as the maximum width and the other of the two factors obtained by the factorization as the maximum height; Determining the effective width according to the maximum width and determining the effective height according to the maximum height; Generating one of the multiple initial resolutions based on the maximum width, the maximum height, the effective width, and the effective height.

7. The method according to claim 1, wherein The one or more display components include a display component of M rows and N columns, where both M and N are integers greater than or equal to 1. When N is greater than or equal to 2, the method further includes: Adjusting the horizontal front porch HFP in the target resolution corresponding to each row of the M rows of display components so that the horizontal blanking sizes of the M rows of display components decrease sequentially from left to right.

8. A control and display device, characterized in that, The device is applied to a video wall controller, the video wall controller is connected to one or more display components, and the device includes: an acquisition module, a processing module, and a sending module; The acquisition module is configured to acquire the preset resolution and the preset frame rate corresponding to each display component; where the preset resolution includes a preset effective width and a preset effective height; The processing module is configured to determine one or more target candidate clocks according to the preset frame rate of each display component; the target candidate clock is a clock that satisfies the following first condition: the quotient obtained by dividing it by the preset frame rate of any one display component is greater than or equal to the product of the preset effective width and the preset effective height of any one display component; determine the smallest one of the one or more target candidate clocks as the target clock of the one or more display components; and determine the target resolution corresponding to each display component based on the target clock. The sending module is configured to send sub-video images to each display component according to the target resolution corresponding to each display component, so that each display component displays the sub-video images according to the corresponding target resolution; wherein, the sub-video images are obtained by the video wall controller splitting the video image, and the sub-video images displayed by each display component are spliced together to obtain the video image.

9. The apparatus according to claim 8, wherein The processing module is specifically configured to determine a plurality of initial clocks from among a plurality of clocks between the minimum clock and the maximum clock according to a preset clock step accuracy; the preset clock step accuracy is used to indicate the clock interval between adjacent initial clocks. Determine one or more initial candidate clocks that satisfy the second condition from the plurality of initial clocks according to the number of factors of the quotient obtained by dividing each initial clock by the preset frame rate of any one display component, and the second condition: the number of factors of the quotient obtained by dividing it by the preset frame rate of any one display component is greater than a number threshold. Determine the one or more target candidate clocks from the one or more initial candidate clocks based on the initial resolutions corresponding to the one or more initial candidate clocks, and each initial candidate clock corresponds to one or more initial resolutions.

10. The apparatus according to claim 9, wherein The processing module is specifically configured to obtain, from the plurality of initial clocks, one or more first initial clocks whose number of factors of the quotient obtained by dividing them by the preset frame rate of any one display component is greater than the number threshold, and determine the initial candidate clocks from the one or more first initial clocks. If the one or more initial candidate clocks include an initial candidate clock that satisfies the first condition, then determine the one or more target candidate clocks from the one or more initial candidate clocks based on the initial resolutions corresponding to the one or more initial candidate clocks.

11. The apparatus according to claim 10, wherein The processing module is further configured to, if the one or more initial candidate clocks do not include an initial candidate clock that satisfies the first condition, obtain one or more second initial clocks among the plurality of initial clocks whose number of factors of the quotient obtained by dividing them by the preset frame rate of any one display component is less than or equal to the number threshold. Determine the one or more initial candidate clocks from the one or more second initial clocks.

12. The apparatus according to claim 11, wherein The processing module is specifically configured to use, as the initial candidate clock, the first initial clock among the one or more first initial clocks that is the same as the standard clock; and use, as the initial candidate clock, the second initial clock among the one or more second initial clocks that is the same as the standard clock.

13. The apparatus according to any one of claims 9 to 11, wherein the one or more initial candidate clocks include a first clock, and a preset frame rate of the one or more display components is a first frame rate; before determining the one or more target candidate clocks from the one or more initial candidate clocks based on the initial resolutions corresponding to the one or more initial candidate clocks, the processing module is further configured to perform one or more factorizations on a first area obtained by dividing the first clock by the first frame rate, and each time decompose the first area into two factors; for each factorization, use one of the two factors obtained by the factorization as the maximum width and use the other of the two factors obtained by the factorization as the maximum height; determine an effective width according to the maximum width and determine an effective height according to the maximum height; and generate one of the multiple initial resolutions based on the maximum width, the maximum height, the effective width, and the effective height.

14. The apparatus according to claim 8, wherein the one or more display components include display components arranged in M rows and N columns, both M and N are integers greater than or equal to 1, and when N is greater than or equal to 2, the processing module is further configured to adjust a horizontal front porch HFP in a target resolution corresponding to each row of display components in the M rows, so that a horizontal blanking size of each row of display components in the M rows decreases sequentially from left to right.

15. An LED controller, characterized in that, The LED controller includes: a processor and a memory; the memory stores instructions executable by the processor; when the processor is configured to execute the instructions, the LED controller implements the method according to any one of claims 1 to 7.

16. A readable storage medium, characterized in that, The readable storage medium includes: software instructions; when the software instructions run in the controller, the controller implements the method according to any one of claims 1 to 7.

17. A control panel display system, characterized in that, The system includes a controller and one or more display components connected to the controller; the controller is configured to obtain a preset resolution and a preset frame rate corresponding to each display component; wherein the preset resolution includes a preset effective width and a preset effective height; determine one or more target candidate clocks according to the preset frame rate of each display component; the target candidate clock is a clock that satisfies the following first condition: the quotient of dividing by the preset frame rate of any one of the display components is greater than or equal to the product of the preset effective width and the preset effective height of any one of the display components; determine the smallest one of the one or more target candidate clocks as the target clock; Based on the target clock, determine the target resolution corresponding to each display component; send the sub-video images to each display component according to the target resolution corresponding to each display component; wherein, the sub-video images are obtained by the video wall controller splitting the video image. The one or more display components are configured to display the sub-video images sent by the video wall controller according to their respective corresponding target resolutions, and the sub-video images displayed by each display component are spliced together to obtain the video image.

Images