Signal transmission method and device, source driver and electronic equipment

Abstract

The present disclosure relates to a signal transmission method, a device, a source driver and an electronic device. The signal transmission method is applied to a source driver, the source driver is connected with a controller in a low-voltage differential signal interface mode, and the method comprises the following steps: obtaining a clock signal and a correction signal provided by the controller; determining a timing offset value between the clock signal and the correction signal according to the clock signal and the correction signal; and adjusting a timing relationship between the clock signal and the correction signal based on the timing offset value by using a delay unit, wherein the delay unit is arranged in a clock path of the clock signal or in a data path of the correction signal. The signal transmission method can alleviate the delay between the clock signal and the data signal in the process of transmitting the data signal between the controller and the source driver, ensure the accurate transmission of the data signal, and be beneficial to improving the communication frequency between the source driver and the controller.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to a signal transmission method, a signal transmission apparatus, a source driver and an electronic device. BACKGROUND

[0002] In the field of display technology, a pixel array of a display panel such as a liquid crystal display panel or an organic light emitting diode (OLED) display panel usually includes a plurality of gate lines and a plurality of data lines arranged in a cross manner with the gate lines. A timing controller (T-con) of the display panel needs to provide gate signals and data signals to the plurality of gate lines and the plurality of data lines respectively through a gate driving circuit and a source driving circuit, so as to form a gray voltage required by each gray level in each row of pixel units in a manner such as row-by-row scanning, and then display a frame of image. SUMMARY

[0003] At least one embodiment of the present disclosure provides a signal transmission method applied to a source driver, the source driver being communicatively connected to a controller in a low-voltage differential signal interface manner, the method comprising: obtaining a clock signal and a correction signal provided by the controller; determining a timing offset value between the clock signal and the correction signal according to the clock signal and the correction signal; and adjusting a timing relationship between the clock signal and the correction signal based on the timing offset value by using a delay unit, wherein the delay unit is arranged in a clock path of the clock signal or in a data path of the correction signal.

[0004] At least one embodiment of the present disclosure provides a signal transmission apparatus for a source driver and a controller to be communicatively connected in a low-voltage differential signal interface manner, the signal transmission apparatus comprising: an obtaining unit configured to obtain a clock signal and a correction signal provided by the controller; a determining unit configured to determine a timing offset value between the clock signal and the correction signal according to the clock signal and the correction signal; and an adjusting unit configured to adjust a timing relationship between the clock signal and the correction signal based on the timing offset value by using a delay unit, wherein the delay unit is arranged in a clock path of the clock signal or in a data path of the correction signal.

[0005] The source driver is connected with the controller in a low-voltage differential signal interface mode, and the source driver comprises: a processing circuit configured to acquire a clock signal and a correction signal provided by the controller, and determine a timing offset value between the clock signal and the correction signal according to the clock signal and the correction signal; and a delay circuit arranged in a clock path of the clock signal or a data path of the correction signal, and configured to adjust a timing relationship between the clock signal and the correction signal based on the timing offset value.

[0006] The electronic device comprises the source driver, the controller and the display panel provided in any of the embodiments of the present disclosure. The controller is configured to provide a display signal to the source driver; and the display panel is connected with the source driver to receive a driving signal provided by the source driver, and the driving signal is generated based on the display signal. BRIEF DESCRIPTION OF DRAWINGS

[0007] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings described below only relate to some of the embodiments of the present disclosure, but not limit the present disclosure.

[0008] Figure 1A A circuit driving system architecture schematic diagram of a display panel is shown;

[0009] Figure 1B A system architecture diagram of a timing controller TCON and a source driver is shown;

[0010] Figure 1C A schematic diagram of a source driver acquiring a data signal through a mini-LVDS interface is shown;

[0011] Figure 1D A timing relationship diagram of a data signal and a clock signal is shown;

[0012] Figure 2A A flowchart of a signal transmission method provided by at least one embodiment of the present disclosure is shown;

[0013] Figure 2B A schematic diagram of another source driver acquiring a data signal through a mini-LVDS interface is shown;

[0014] Figure 3A A flowchart of a signal transmission method provided by at least one embodiment of the present disclosure is shown; Figure 2A A method flowchart of step S20 is shown;

[0015] Figure 3BA timing diagram between a clock signal and a correction signal is shown according to an embodiment of the present disclosure;

[0016] Figure 4A A timing diagram between a clock signal and a correction signal is shown according to an embodiment of the present disclosure; Figure 2A A method flowchart of step S30 is shown;

[0017] Figure 4B Another schematic diagram of a source driver obtaining a data signal through a mini-LVDS interface is shown according to an embodiment of the present disclosure;

[0018] Figure 5A And 5B A signal format diagram of a display signal provided by a controller to a source driver is shown according to an embodiment of the present disclosure;

[0019] Figure 6A A timing diagram of a trigger signal PSI is shown according to an embodiment of the present disclosure;

[0020] Figure 6B A timing diagram of a single mode indication signal is shown according to an embodiment of the present disclosure;

[0021] Figure 7 A timing relationship diagram of a display sub-signal transmitted in a correction configuration mode is shown according to an embodiment of the present disclosure;

[0022] Figure 8 A schematic block diagram of a signal transmission device is shown according to an embodiment of the present disclosure;

[0023] Figure 9 A schematic block diagram of a source driver is shown according to an embodiment of the present disclosure; and

[0024] Figure 10 A schematic block diagram of an electronic device is shown according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0025] In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments of the present disclosure. Based on the described embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without any creative work fall within the scope of protection of the present disclosure.

[0026] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the ordinary meaning as understood by a person of ordinary skill in the art to which the present disclosure pertains. The terms "first", "second", and similar terms used in the present disclosure do not denote any order, quantity, or importance, but are used to distinguish different components. Also, the terms "one", "a", or "the" and similar terms used in the present disclosure do not denote the quantity of mentioned objects, but mean that there is at least one of the objects. The terms "comprises", "comprising", "includes", "including" and the like used in the present disclosure specify the presence of stated elements or objects but do not preclude the presence or addition of other elements or objects. The terms "connected", "coupled", and the like used in the present disclosure do not necessarily denote a direct or mechanical connection or coupling, but can include an electrical connection or coupling, whether direct or indirect. The terms "upper", "lower", "left", "right", and the like are used only to indicate relative positions, and when the absolute positions of the described objects are changed, the relative positions can also be changed accordingly.

[0027] Various driving circuits for display panels generally include scan driving integrated circuits (also referred to as gate drivers or G-ICs), data driving integrated circuits (also referred to as source drivers or SD-ICs), controllers, and the like. The controllers are mainly used to convert image data signals, control signals, clock signals, and the like received from the outside (such as signal sources of storage devices, network modems, and the like) into image data signals, gate signals, control signals, clock signals, and the like suitable for source drivers and gate drivers, for implementing image display driving of display panels. For example, the controller can be a timing controller (TCON). The source drivers are mainly used to receive digital signals (display signals or image signals) and control signals, and the like provided by the aforementioned controllers, convert the digital signals into corresponding analog gray scale voltage signals through digital-to-analog conversion, and input the analog gray scale voltage signals into each column of pixel units of a pixel array of a display panel. The gate drivers are mainly used to implement opening of each row of pixel units of the pixel array, for example, row by row (or interlaced), and under the action of control signals, cooperate with the source drivers to input required image data signals into corresponding pixel units for the opened row of pixel units, so that the pixel units can display according to the image data signals.

[0028] In the display process of a display panel, a video and an animation are composed of a large number of pictures displayed in time sequence (for example, a frame rate of 60 Hz or 120 Hz, etc.), each picture is a frame, that is, a frame of image refers to a complete picture displayed by the display panel. In the display process of a frame of image, the gate driver sequentially turns on each row of pixel units in the pixel array from the first row to the last row for scanning, and in the scanning process, the source driver inputs the required image data signal of each row of pixel units into the turned-on pixel units, thereby completing the scanning and display required for a frame of picture. For example, due to the process of the pixel units of the display panel and other reasons, in order to obtain a clear and complete display effect with good quality, the display picture needs to be continuously refreshed, and each refresh needs to display a frame of image, and a plurality of frames of continuously displayed images form a static picture or a dynamic picture in visual effect.

[0029] Figure 1A A schematic diagram of a circuit driving system architecture of a display panel is shown. As shown in the figure, the circuit driving system architecture includes a timing controller TCON, a gate driver G-IC, a source driver SD-IC, and a display panel. The circuit driving system architecture further includes a power management integrated circuit PMIC, a gamma (Gamma) circuit, a common electrode voltage (Vcom) circuit, etc. Figure 1A

[0030] The input voltage Vin of the power management integrated circuit is, for example, 5V or 12V, and the output voltage includes a digital operating voltage DVDD provided to each IC, an analog voltage AVDD provided to the Gamma circuit and the Vcom circuit, a gate turn-on voltage VGH and a gate turn-off voltage VGL provided to the gate driver G-IC, etc. The common electrode voltage (Vcom) circuit is used to provide a common voltage for the pixel array.

[0031] The control signals output by the timing controller TCON include control signals provided to the gate driver G-IC and control signals provided to the source driver SD-IC. For example, the control signals provided to the source driver SD-IC include a row start signal (Start Horizontal, STH) for starting the transmission of row data, a row clock pulse signal (Clock Pulse Horizontal, CPH), a data transmission control signal Load, and a data polarity inversion signal POL. For example, the control signals provided to the gate driver G-IC include a frame start signal (Start Vertical, STV) representing the start of scanning of a frame of picture, a scanning clock pulse signal (Clock Pulse Vertical, CPV), an enable signal (Enable), etc.

[0032] ​For example, the input digital interface type of the timing controller TCON can be Low-Voltage Differential Signaling (LVDS), Embedded Display Port (eDP) interface, V-by-One (Vx1) interface, etc. The output digital interface type of the timing controller TCON can be mini-LVDS, for example, for communication with the source driver SD-IC.

[0033] The LVDS interface transmits signals in the form of wire pairs, including a clock wire pair and several signal wire pairs. For example, the LVDS signal wire pair includes three control signals: field synchronization signal, row synchronization signal, and enable signal. The mini-LVDS interface is similar to the LVDS interface, and also transmits signals by differential signal wire pairs. Unlike the LVDS signal wire pair, the mini-LVDS signal wire pair of the mini-LVDS interface does not transmit control signals, and these control signals are transmitted by signal wires or signal differential pairs independent of the mini-LVDS signal wire pair.

[0034] In this disclosure, the communication between the source driver and the controller through the mini-LVDS interface is taken as an example to illustrate the embodiments.

[0035] Figure 1B A system architecture diagram showing the connection between the timing controller TCON and the source driver is shown.

[0036] As shown in Figure 1B The system architecture includes the timing controller TCON and a plurality of source drivers. The plurality of source drivers includes source driver SD#1, source driver SD#2, etc., and the number of source drivers is related to the physical resolution of the display panel. For one display panel, there can be tens or even hundreds of source drivers. For example, each source driver is connected by a clock signal wire pair for transmitting a clock signal, a mini-LVDS signal wire pair for transmitting an image data signal, and a control signal wire for transmitting a plurality of control signals. The mini-LVDS signal wire pair can be 3 pairs of signal wires or 6 pairs of signal wires. The control signal wire can or can not be a signal differential pair. The mini-LVDS signal wire and the plurality of control signal wires are independent of each other.

[0037] For example, the timing controller TCON and each source driver (e.g., source driver SD#1, source driver SD#2, etc.) are connected by the mini-LVDS signal wire pair in addition to the LOAD control signal wire for transmitting a data transmission control signal LOAD, the POL control signal wire for transmitting a control signal POL, the POL2 control signal wire for transmitting a control signal POL2, etc.

[0038] Other control signal lines can also be included between each source driver and the TCON, such as a horizontal dot inversion (H2DOT) control signal line, a bias voltage (PWRC) control signal line, a POLC control signal line, etc.

[0039] Figure 1C A diagram showing a source driver obtaining data signals through a mini-LVDS interface is shown.

[0040] As shown in Figure 1C , the source driver 110 includes a mini-LVDS interface 111. The mini-LVDS interface 111 is connected with a mini-LVDS interface (not shown) of a controller through a plurality of low-voltage differential signal line pairs to receive data signals provided by the controller. In embodiments of the present disclosure, the data signals are any signals transmitted through the low-voltage differential signal line pairs. For example, the data signals can be image data signals or configuration data signals.

[0041] For example, as shown in Figure 1C , the mini-LVDS interface 111 is connected with the mini-LVDS interface (not shown) of the controller through 3 low-voltage differential signal line pairs, which include a low-voltage differential signal line pair LV0, a low-voltage differential signal line pair LV1 and a low-voltage differential signal line pair LV2, respectively.

[0042] As shown in Figure 1C , the source driver 110 includes a clock signal interface 112 in addition to the mini-LVDS interface 111. The clock signal interface 112 may, for example, also transmit a clock signal through a low-voltage differential signal line, such as the clock signal interface 112 transmitting a clock signal through a clock signal line pair CLK.

[0043] As shown in Figure 1C , the source driver 110 further includes a plurality of samplers, such as a sampler 0, a sampler 1 and a sampler 2. The clock signal interface 112 is connected with the plurality of samplers one by one through a plurality of clock signal lines. For example, a clock signal line iCLK0 is connected with the sampler 0 to provide a clock signal to the sampler 0, a clock signal line iCLK1 is connected with the sampler 1 to provide a clock signal to the sampler 1, and a clock signal line iCLK2 is connected with the sampler 2 to provide a clock signal to the sampler 2.

[0044] As shown in Figure 1CAs shown, the mini-LVDS interface 111 includes a plurality of data channels, which are connected to a plurality of samplers one by one. For example, the data channel iLV0, the data channel iLV1 and the data channel iLV2 are connected to the sampler 0, the sampler 1 and the sampler 2 respectively. Each data channel corresponds to a low-voltage differential signal line pair to output a data signal on the low-voltage differential signal line pair to the sampler.

[0045] Each sampler samples the data signal in each data channel according to a clock signal. After sampling the data channel, each sampler outputs a data signal. For example, the sampler 0 samples the data channel iLV0 according to the clock signal iCLK0 and outputs the data signal iData0[n:0], the sampler 1 samples the data channel iLV1 according to the clock signal iCLK1 and outputs the data signal iData1[n:0], and the sampler 2 samples the data channel iLV2 according to the clock signal iCLK2 and outputs the data signal iData2[n:0].

[0046] As shown in Figure 1C , a resistance, for example, a line resistance, is further included in the transmission path of each clock signal. For example, the resistance R1 is included in the transmission path of the clock signal iCLK0, the resistance R2 is included in the transmission path of the clock signal iCLK1, and the resistance R3 is included in the transmission path of the clock signal iCLK2. In the present disclosure, iCLK0, iCLK1 and iCLK2 represent not only clock signal lines but also clock signals transmitted by the clock signal lines.

[0047] As shown in Figure 1C , each sampler is connected to the same clock signal interface 112. Due to the different positions of the samplers and the like in the circuit, the lengths of the clock signal lines iCLK0, iCLK1 and iCLK2 are different, which leads to different time delays of the clock signals reaching each sampler.

[0048] Figure 1D A timing relationship diagram of a data signal and a clock signal is shown.

[0049] It is assumed that the lengths of the signal lines of the respective data channels are the same, i.e., the lengths of the signal lines of the data channel iLV0, the data channel iLV1 and the data channel iLV2 are the same. In this case, the time delays of the data signals transmitted by the respective channels to reach the respective samplers are the same, and thus the timings of the data signals obtained by the respective samplers sampling the respective data channels are the same. In Figure 1D , iLVx is used to uniformly represent the timings of the data signals obtained by sampling the data channel iLV0, the data channel iLV1 and the data channel iLV2 respectively.

[0050] In Figure 1C and Figure 1DIn the example, the length of the clock signal line iCLK0 is less than the length of the clock signal line iCLK1, and the length of the clock signal line iCLK1 is less than the length of the clock signal line iCLK2. Therefore, relative to the data signal iLVx normally transmitted by each data, the delay of the clock signal iCLK0 received by the sampler 0 is less than the delay of the clock signal iCLK1 received by the sampler 1, and the delay of the clock signal iCLK1 received by the sampler 1 is less than the delay of the clock signal iCLK2 received by the sampler 2.

[0051] It should be noted that although the disclosure takes 3 low-voltage differential signal line pairs, 3 data channels and 3 samplers as an example, the disclosure does not limit the number of low-voltage differential signal line pairs, the number of data channels and the number of samplers, for example, it can also be 6 low-voltage differential signal line pairs, 6 data channels and 6 samplers.

[0052] As shown in Figure 1D , there is a timing delay between the clock signal and the data signal, which causes the transmission of the image data signal or the configuration data signal to be unstable, and the transmission frequency of the low-voltage differential signal interface is difficult to improve.

[0053] To this end, an embodiment of the disclosure provides a signal transmission method applied to a source driver, the source driver being communicatively connected to a controller through a low-voltage differential signal interface, and the method comprises: obtaining a clock signal and a correction signal provided by the controller; determining a timing offset value between the clock signal and the correction signal according to the clock signal and the correction signal; and adjusting the timing relationship between the clock signal and the correction signal based on the timing offset value, the delay unit being arranged in a clock path of the clock signal or in a data path of the correction signal. The signal transmission method adjusts the timing relationship between the clock signal and the correction signal through the delay unit, alleviates the delay between the clock signal and the data signal in the process of transmitting the data signal (for example, an image data signal) between the controller and the source driver, ensures the accurate transmission of the data signal, and is conducive to improving the communication frequency between the source driver and the controller. The correction signal is, for example, a configuration data signal used to correct the clock signal and the data signal.

[0054] Figure 2A A flowchart of a signal transmission method provided by at least one embodiment of the disclosure is shown.

[0055] As shown in Figure 2A , the signal transmission method comprises steps S10-S30. The signal transmission method is performed by, for example, the source driver 110 shown in Figure 1C .

[0056] Step S10: Obtain a clock signal and a correction signal provided by the controller.

[0057] Step S20: determining a timing offset value between the clock signal and the correction signal according to the clock signal and the correction signal.

[0058] Step S30: adjusting the timing relationship between the clock signal and the correction signal by a delay unit based on the timing offset value, wherein the delay unit is disposed in a clock path of the clock signal or in a data path of the correction signal.

[0059] In the display device, the signal transmission method can be performed, for example, before the controller provides the image data signal for display to the source driver. The signal transmission method corrects the timing relationship between the clock signal and the correction signal in advance, so that the data signal is stably transmitted between the controller and the source driver and is advantageous to improve the frequency of the data signal transmission between the controller and the source driver.

[0060] For step S10, for example, in the example of Figure 1C The respective samplers in the source driver 110 acquire the clock signal and the correction signal, respectively.

[0061] The clock signal is, for example, a clock signal provided by a clock source to the clock signal interface 112 of the source driver 110 through clock signal lines, and is provided by the clock signal interface 112 to the respective samplers through the respective clock signal lines (clock signal line iCLK0, clock signal line iCLK1, and clock signal line iCLK2). Due to the delay of the clock signal on the clock signal line iCLK0, the clock signal line iCLK1, and the clock signal line iCLK2, the sampler 0, the sampler 1, and the sampler 2 obtain the clock signal iCLK0, the clock signal iCLK1, and the clock signal iCLK2, respectively, as shown. Figure 1D

[0062] The correction signal is a signal for correcting the delay of the clock signal, and the correction signal can be in any form. For example, the correction signal can be a signal different from the image data. The correction signal can be, for example, a signal of 0 and 1 alternately. “0” is, for example, a signal representing a low level, and “1” is, for example, a signal representing a high level.

[0063] For example, in the example of Figure 1C ​In the example of FIG. 1, the iLVx is a correction signal. For example, the mini-LVDS interface 111 receives a correction signal of 0 and 1 alternately provided by the controller, and the mini-LVDS interface 111 provides the correction signal to the respective samplers through, for example, 3 data channels. The respective samplers sample the respective data channels to obtain the correction signal, which can be any one of a signal obtained by sampler 0 sampling the data channel iLV0, a signal obtained by sampler 1 sampling the data channel iLV1, and a signal obtained by sampler 2 sampling the data channel iLV2. For step S20, the timing offset value is, for example, a relative concept. For example, the timing offset value can be a delay of the clock signal relative to the correction signal, or a delay of the correction signal relative to the clock signal.

[0064] For example, the timing offset value is an offset value between a sampling time of the clock signal and a reference time of the correction signal during the first signal.

[0065] For example, the correction signal is a signal of the first signal and the second signal alternately, the first signal can be, for example, a high-level signal to represent a digital signal "1", and the second signal can be, for example, a low-level signal to represent a digital signal "0". The first signal period is, for example, a period during which the correction signal is high.

[0066] The sampling time of the clock signal can be a rising edge or a falling edge of the clock signal. In the present disclosure, the sampling time is taken as the rising edge of the clock signal to illustrate the embodiments.

[0067] The reference time can be any time during the first signal. For example, the reference time is a middle time during the first signal. Taking the middle time of the first signal as the reference time makes the sampling time (for example, the rising edge) of the clock signal align with the time, which can ensure sufficient setup time and hold time, thereby ensuring the stability of sampling.

[0068] In step S20, in some embodiments of the present disclosure, for example, a time length of a time corresponding to the rising edge of the clock signal from the reference time can be calculated, and the time length is taken as the timing offset value multiplied by 2.

[0069] For example, in Figure 1D In the timing diagram shown in FIG. 2, taking the middle time of the first signal as the reference time, the delays between the respective times corresponding to the rising edges of the clock signal iCLK0, the clock signal iCLK1, and the clock signal iCLK2 and the reference time T are time length Δt1, time length Δt2, and time length Δt3, respectively, and then the time length Δt1 / 2, the time length Δt2 / 2, and the time length Δt3 / 2 are taken as the timing offset values of the clock signal iCLK0, the clock signal iCLK1, and the clock signal iCLK2, respectively, relative to the correction signal. In Figure 1DIn the example of FIG. 1, the time length Δtl is equal to 0.

[0070] The rising edge of the clock signal can correspond to a time earlier than the reference time or a time later than the reference time. In the present disclosure, if the rising edge of the clock signal corresponds to a time earlier than the reference time, the delay is positive, i.e., the timing offset value is positive; if the rising edge of the clock signal corresponds to a time later than the reference time, the delay is negative, i.e., the timing offset value is negative.

[0071] The following Figure 3A and Figure 3B Another embodiment of determining the timing offset value is shown in the following Figure 3A and Figure 3B The description.

[0072] For step S30, the delay between the clock signal and the correction signal is reduced by using a delay unit based on the timing offset value.

[0073] In an embodiment of the present disclosure, a delay unit is arranged in the clock path of the source driver to adjust the timing of the clock signal relative to the correction signal, thereby alleviating the delay of the clock signal relative to the correction signal. For example, a delay unit is arranged in the data path of the source driver to adjust the timing of the clock signal relative to the correction signal, thereby alleviating the delay between the clock signal and the correction signal.

[0074] In some embodiments of the present disclosure, the delay unit can be a delay circuit designed by those skilled in the art to delay a signal for a period of time. For example, the delay circuit includes capacitors, resistors, buffers, etc.

[0075] For example, P (P is an integer greater than 0) delay units are arranged in each clock path in advance. If the timing offset value is negative, indicating that the rising edge of the clock signal corresponds to a time later than the reference time, the number of delay units is appropriately reduced, for example, to P-1 (here, for example, P is an integer greater than 1). If the timing offset value is positive, indicating that the rising edge of the clock signal corresponds to a time earlier than the reference time, the number of delay units is appropriately increased, for example, to P+1.

[0076] Those skilled in the art can determine the number of delay units to be increased or reduced according to the delay effect of the delay unit and the timing offset value.

[0077] For example, the delay time length of a single delay unit is determined, and the ratio of the timing offset value to the delay time length is used as the number of delay units.

[0078] For example, the number of delay units is increased or reduced one by one until the number of delay units that minimizes the timing offset value is found.

[0079] Figure 2B A schematic diagram of a source driver obtaining a data signal through a mini-LVDS interface is shown.

[0080] As shown in Figure 2B , the source driver 120 includes a plurality of delay units, for example, 2 or more delay units, on each clock path. The number of delay units used in each clock path is adjusted according to the timing offset value, so as to adjust the timing relationship between the clock signal and the correction signal.

[0081] In Figure 2B , in addition to the plurality of delay units added in each clock path, other structures are similar to those of Figure 1C , and will not be described again. In some embodiments of the present disclosure, the number of delay units in the plurality of clock paths can be the same or different.

[0082] Figure 3A A method flowchart of step S20 in Figure 2A is shown.

[0083] As shown in Figure 3A , the method includes steps S21-S22.

[0084] Step S21: Obtain a first time length from a sampling moment to a first transition edge of the correction signal and a second time length to a second transition edge.

[0085] Step S22: Determine a timing offset value between the clock signal and the correction signal based on the first time length and the second time length.

[0086] In this embodiment, the first transition edge is the transition edge of the correction signal from the second signal to the first signal, and the second transition edge is the transition edge of the correction signal from the first signal to the second signal.

[0087] The method takes the first transition edge and the second transition edge as the reference to obtain the timing offset value, which can improve the accuracy of the timing offset value.

[0088] The method described above will be described below in combination with Figure 3B . Figure 3A Figure 3B A timing diagram between a clock signal and a correction signal is shown.

[0089] As shown in Figure 3B , the timing diagram includes a clock signal iCLK0 and a correction signal iLV0. For example, the correction signal iLV0 is at the middle moment of the digital signal "1" as a reference moment. ​

[0090] The transition edge Y1 is an example of a first transition edge, which is the transition edge of the correction signal from "0" to "1"; the transition edge Y2 is an example of a second transition edge, which is the transition edge of the correction signal from "1" to "0". That is, the transition edge Y1 is the rising edge of the correction signal, and the transition edge Y2 is the falling edge of the correction signal.

[0091] For step S21, the sampling time point is, for example, the time point corresponding to the rising edge Y3 of the clock signal iCLK0. The first time length between the time point corresponding to the rising edge Y3 and the transition edge Y1 and the second time length between the time point corresponding to the rising edge Y3 and the transition edge Y2 are obtained.

[0092] In some embodiments of the present disclosure, the correction signal is counted positively from the sampling time point to the second transition edge, and the second time length is represented by the positive count; the correction signal is counted inversely from the sampling time point to the first transition edge, and the first time length is represented by the inverse count. The method for obtaining the first time length and the second time length provided by this embodiment is easy to implement, efficient, and has high accuracy.

[0093] For example, in the example of Figure 3B , the correction signal is counted positively from the rising edge Y3 to the transition edge Y2, and the positive count +3 represents the second time length; the correction signal is counted inversely from the rising edge Y3 to the transition edge Y1, and the inverse count -5 represents the first time length.

[0094] In this embodiment, step S22 takes, for example, the average of the positive count and the inverse count as the timing offset value. For example, [+3+(-5)] / 2=-1, and thus -1 is taken as the timing offset value between the reference time point of the clock signal iCLK0 and the correction signal iLV0.

[0095] In other embodiments of the present disclosure, one skilled in the art can assign corresponding weights to the positive count and the inverse count as needed, and take the weighted average of the positive count and the inverse count as the timing offset value.

[0096] Figure 4A A method flowchart of step S30 in one Figure 2A of the present disclosure is shown.

[0097] As shown in Figure 4A , the method can include steps S31-S32.

[0098] Step S31: determining the number of delay units according to the timing offset value.

[0099] Step S32: adjusting the number of delay units in the clock path or adjusting the number of delay units in the data path.

[0100] For step S31, the number of delay units is determined, for example, by looking up a correspondence table between the timing offset value and the number of delay units.

[0101] In some embodiments of the present disclosure, the number of delay units can be increased or decreased according to a preset gradient based on the currently used delay units according to the timing offset value, so as to determine the number of delay units.

[0102] For example, when the clock path includes 5 delay units and the timing offset value between the clock signal and the correction signal is negative, the number of delay units is appropriately reduced. For example, if the preset gradient is 1 delay unit and the timing offset value is -1, the number of delay units is reduced by 1, so the number of delay units is adjusted to 4. Similarly, if the timing offset value between the clock signal and the correction signal is positive, the number of delay units is appropriately increased.

[0103] For step S32, for example, if the number of delay units is adjusted to 4, 4 delay units are selected from the 5 delay units for use in the clock path.

[0104] In some embodiments of the present disclosure, the delay time lengths of the plurality of delay units can be the same or different. If the delay time lengths of the plurality of delay units are different, appropriate delay units can be selected for use in the clock path according to the timing offset value. For example, if the timing offset value is large, delay units with a longer delay time length can be selected for use in the clock path, and if the timing offset value is small, delay units with a shorter delay time length can be selected for use in the clock path. Furthermore, the plurality of delay units with different delay time lengths can be freely combined to minimize the timing offset value.

[0105] This embodiment flexibly and conveniently compensates for the timing offset by adjusting the number of delay units, so as to obtain the optimal sampling time.

[0106] In some other embodiments of the present disclosure, delay units can be arranged in the data path.

[0107] Figure 4B Another schematic diagram of another source driver provided by at least one embodiment of the present disclosure is shown, which acquires data signals through a mini-LVDS interface.

[0108] As shown in FIG. 13, the source driver 130 is the same as the source driver 120 in FIG. 12 except that a plurality of delay units are arranged in the data path instead of the clock path, and the rest is the same as the source driver 120, which will not be described again. Figure 4B Figure 2B As shown in FIG. 13, the source driver 130 is the same as the source driver 120 in FIG. 12 except that a plurality of delay units are arranged in the data path instead of the clock path, and the rest is the same as the source driver 120, which will not be described again.

[0109] As shown in FIG. 13, the source driver 130 is the same as the source driver 120 in FIG. 12 except that a plurality of delay units are arranged in the data path instead of the clock path, and the rest is the same as the source driver 120, which will not be described again. Figure 4B ​As shown, multiple delay units are respectively disposed in each data path. For example, multiple delay units are respectively disposed in the data channel between each low-voltage differential signal pair and each sampler. For example, multiple delay units 401 are disposed in the data channel iLV0 between the low-voltage differential signal pair LV0 and sampler 0.

[0110] The number of multiple delay units 401, multiple delay units 402 and multiple delay units 403 can be the same or different.

[0111] For example, the number of delay units in the data path is determined based on the timing offset value. For instance, if the timing offset value is positive, the number of delay units in the data path is reduced; if the timing offset value is negative, the number of delay units is increased. For example, if the timing offset values ​​of the correction signal iLV1 and clock signal iCLK1 on data channel iLV1 are positive, the number of delay units in multiple delay units 402 is reduced. If the timing offset values ​​of the correction signal and clock signal iCLK2 on data path iLV2 are positive, the number of delay units in multiple delay units 403 is reduced.

[0112] The method for determining the number of delay units in each data path is similar to the method for determining the number of delay units in the clock path, and will not be described in detail here.

[0113] In some other embodiments of this disclosure, delay units can be set in both the data path and the clock path, and the number of delay units in the data path or the number of delay units in the clock path can be adjusted according to the timing offset value.

[0114] like Figure 1B As shown, the mini-LVDS signal pairs are only used to transmit image data signals and not to transmit control signals such as polarity inversion configuration information or data transmission control information. Therefore, there are multiple signal lines and multiple signal line interfaces between the timing controller and the source drivers, resulting in a large amount of signal routing space occupied in the display panel, especially when the number of source drivers is large. If the available signal routing space in the display panel is insufficient to accommodate these multiple data lines, then some commonly used control functions cannot be flexibly embedded into the source drivers.

[0115] In another system architecture of the present disclosure, the timing controller TCON and the source driver can be connected only through a pair of mini-LVDS signal lines, a pair of clock signal lines, a LOAD control signal line, and a POL control signal line. In this system architecture, the mini-LVDS transmits not only image data signals but also configuration data signals for controlling the source driver, such as the control signal POL2, a horizontal dot inversion control signal, a bias voltage control signal, and the like. This system architecture can multiplex the low-voltage differential signal interface, so that it is used not only to provide image data to the source driver but also to provide configuration data, thereby reducing the number of interfaces for signal transmission, saving costs, and ensuring that various control functions can be flexibly embedded into the source driver. The image data signals are signals for image display, such as including RGB (red, green, and blue) data. The configuration data signals are used to configure the source driver. In this system architecture, the controller and the source driver can transmit display signals in at least two modes.

[0116] In some embodiments of the present disclosure, the controller provides display signals in at least two modes, the display signals including a plurality of display sub-signals, the at least two modes respectively providing the plurality of display sub-signals, and each display sub-signal including a mode identification signal. In this embodiment, Figure 2A The step S20 includes: in response to the mode identification signal being the correction mode signal, determining that the controller provides the display sub-signals in the correction configuration mode and that the display sub-signals include correction signals; and determining a timing offset value between the clock signal and the correction signals according to the clock signal and the correction signals.

[0117] In embodiments of the present disclosure, the above-mentioned controller can be a timing controller (TCON). This embodiment is applied to the system architecture in which the timing controller TCON and the source driver can be connected only through a pair of mini-LVDS signal lines, a pair of clock signal lines, a LOAD control signal line, and a POL control signal line. That is, the mini-LVDS transmits not only image data signals but also configuration data signals for controlling the source driver, such as the control signal POL2, a horizontal dot inversion control signal, a bias voltage control signal, and the like. This system architecture can multiplex the low-voltage differential signal interface, so that it is used not only to provide image data signals to the source driver but also to provide configuration data signals, thereby reducing the number of interfaces for signal transmission, saving costs, and ensuring that various control functions can be flexibly embedded into the source driver.

[0118] In some embodiments of the present disclosure, the at least two modes include a correction configuration mode. The at least two modes can further include a row configuration mode or a frame configuration mode in addition to the correction configuration mode. Each mode provides at least one display sub-signal. Each display sub-signal includes a mode identification signal to indicate the mode to which the display sub-signal belongs. The mode identification signal is used to distinguish whether the display sub-signal is provided by the controller in the row configuration mode, in the frame configuration mode, or in the correction configuration mode. For example, the mode identification signal of the row configuration mode is mode identification signal A, the mode identification signal of the frame configuration mode is mode identification signal B, and the mode identification signal of the correction configuration mode is mode identification signal C (i.e., correction mode signal).

[0119] The display sub-signal provided by the correction configuration mode includes the correction mode signal in addition to the correction signal. The correction signal is, for example, the signal in which "0" and "1" are alternated.

[0120] For example, the source driver first receives the mode identification signal. If the mode identification signal is mode identification signal C, it is determined that the controller provides the display sub-signal in the correction configuration mode, and it is determined that the signal received after the correction mode signal is the correction signal.

[0121] The display signal can include, for example, an image data signal and a configuration data signal. The configuration data signal can be generated by a timing control module in the timing controller, for example. The configuration data signal is used to configure the source driver so that the source driver processes the image data signal according to the configuration data signal. The configuration data signal includes the display sub-signal provided by the correction configuration mode, and can further include row configuration data provided by the row configuration mode or the display sub-signal provided by the frame configuration mode.

[0122] The display sub-signal provided by the row configuration mode includes the row configuration data and the row image data described above. The row configuration mode configures the source driver for image data display of one row of pixels. The row image data is, for example, the RGB data corresponding to the row in the pixel array. The row configuration data is used to configure the source driver so that the source driver outputs the row image data and timing control signals and the like to the row of pixels in response to the row configuration data.

[0123] The display sub-signal provided by the frame configuration mode is used to configure the source driver for display of one frame of image. The frame configuration data is used to configure the source driver, for example, so that the source driver outputs control signals for the frame of image. The frame configuration data can include, for example, a gamma (Gamma) setting signal, an amplification (AMP) offset control signal, a shift direction selection signal, and the like.

[0124] Figure 5A And 5B A signal format diagram of a display signal provided by the controller to the source driver according to at least one embodiment of the present disclosure is shown.

[0125] As shown in FIG. 1, in a frame display period (including an image display period and a vertical blanking period), the display signal includes a plurality of display sub-signals 301 provided in a row configuration mode, a display sub-signal 302 provided in a frame configuration mode, and a display sub-signal 303 provided in a correction configuration mode. Figure 5A

[0126] In some embodiments of the present disclosure, the frame configuration mode and the correction configuration mode are in the vertical blanking period. The frame configuration mode and the correction configuration mode in the vertical blanking period enable the source driver to perform frame configuration and timing correction in the vertical blanking period to prepare for the display of the next image frame, and save time and improve display efficiency since the frame configuration and timing correction are performed in the vertical blanking period.

[0127] For example, the plurality of display sub-signals 301 are provided in the row configuration mode in the image display period, the display sub-signal 302 is provided in the frame configuration mode in the vertical blanking period, and the display sub-signal 303 is provided in the correction configuration mode in the vertical blanking period.

[0128] As shown in FIG. 1, in a frame display period (including an image display period and a vertical blanking period), the display signal includes a plurality of display sub-signals 301 provided in a row configuration mode, a display sub-signal 302 provided in a frame configuration mode, and a display sub-signal 303 provided in a correction configuration mode. Figure 5A

[0129] For example, in the example of FIG. 1, the plurality of display sub-signals 301 are first provided to the source driver in the row configuration mode using the LVDS interface, then the display sub-signal 302 is provided to the source driver in the frame configuration mode using the LVDS interface, and then the display sub-signal 303 is provided to the source driver in the correction configuration mode using the LVDS interface. For example, for the row configuration mode including the plurality of display sub-signals 301, the plurality of display sub-signals 301 are sequentially provided to the source driver using the LVDS interface. That is, in the example of FIG. 1, the plurality of display sub-signals 301 are first provided to the source driver using the LVDS interface, then the display sub-signal 302 is provided to the source driver using the LVDS interface, and then the display sub-signal 303 is provided to the source driver using the LVDS interface. Figure 5A Figure 5A

[0130] As shown in FIG. 1, each display sub-signal 301 provided in the row configuration mode includes row data LPC and image data (e.g., RGB data). As shown in FIG. 1, the display sub-signal 302 provided in the frame configuration mode includes frame data FPC. As shown in FIG. 1, the display sub-signal 303 provided in the correction configuration mode includes correction data CPC. Figure 5A Figure 5B ​​​​​As shown, the row data LPC includes a pattern recognition signal A and row configuration data. For example, the pattern recognition signal A includes a reset signal RESET and a row mode start signal LPC Start. For example, the row mode start signal can be a logic invalid level, such as "000 000". Please refer to the description above for the pattern recognition signal and row configuration data of the row configuration mode.

[0131] like Figure 5A As shown, each display sub-signal 302 provided in frame configuration mode includes frame data FPC and invalid data IDLE0 and IDLE1. In embodiments of this disclosure, IDLE0 and IDLE1 are, for example, both logic invalid levels. Figure 5B As shown, the Frame Data Programming (FPC) includes a pattern recognition signal B and frame configuration data. For example, the pattern recognition signal B of the Frame Data Programming (FPC) is a reset signal RESET and a frame mode start signal FPC Start. For example, the frame mode start signal differs from the line mode start signal to distinguish between frame configuration mode and line configuration mode; the frame mode start signal can be, for example, a logic active level such as "111 111". Please refer to the description above for the pattern recognition signal and frame configuration data for the frame configuration mode.

[0132] like Figure 5A As shown, the frame configuration mode includes a power control sub-mode. The display sub-signal 302 provided in frame configuration mode includes a low-power signal 312 provided to the source driver in power control sub-mode. The low-power signal 312 includes, for example, invalid data IDLE0 and invalid data IDLE1. During the period when the controller provides invalid data IDLE0 and invalid data IDLE1 to the source driver in power control sub-mode, at least a portion of the circuitry in the source driver is in a power-down state to conserve power. Figure 5A In the example, before providing invalid data IDLE0 to the source driver in power control sub-mode, the controller provides the trigger signal PSI to the source driver again to indicate that the source driver enters a low-power operating state.

[0133] like Figure 5A As shown, each display sub-signal 303 provided in the calibration configuration mode includes calibration data ASC. (As...) Figure 5B As shown, the correction data ASC includes a pattern recognition signal C and a correction signal. The pattern recognition signal C can be, for example, a logic invalid level. Please refer to the description above for correction parameters.

[0134] like Figure 5A As shown, after transmitting the display signal for one display cycle to the source driver, the display signal for the next display cycle continues to be transmitted to the source driver.

[0135] like Figure 5AAs shown, the display sub-signal provided by each mode further includes a trigger signal for instructing the source driver to perform the transmission operation according to the at least two modes. For example, before providing each display sub-signal to the source driver, a trigger signal is provided to the source driver to inform the source driver to perform the transmission operation for the at least two modes.

[0136] In some embodiments of the present disclosure, the set timing relationship between the data transmission control signal and the data polarity inversion control signal includes that a first transition edge of the data polarity inversion control signal is later than a second transition edge of the data transmission control signal, and a first transition state of the data polarity inversion control signal after the first transition edge at least partially coincides with a second transition state of the data transmission control signal after the second transition edge.

[0137] The data polarity inversion control signal controls the polarity inversion of the data signal output by the source driver through the switching of high and low levels to achieve the AC driving of the liquid crystal. The data transmission control signal is used to latch the data and the data polarity inversion signal input to the source driver at the rising edge and control the data release to the panel at the falling edge.

[0138] In some embodiments of the present disclosure, in addition to transmitting the display signal to the source driver in the at least two modes, the controller can also transmit the display signal to the source driver in a single mode. In this embodiment, the transmission operation of the at least two modes performed by the source driver through the trigger signal facilitates the compatibility of the source driver and the controller to other transmission operations in addition to the transmission operation of the at least two modes, and provides compatibility. For example, in addition to the transmission operation of the at least two modes, the controller and the source driver can also compatibly perform the transmission operation of the single mode. For example, the display signal transmitted in the at least two modes conforms to a first signal transmission protocol, and the display signal transmitted to the source driver in the single mode conforms to a second signal transmission protocol. If the controller and the source driver perform the transmission operation of the at least two modes, the controller first provides a trigger signal to the source driver as an indication signal of the transmission operation of the at least two modes; if the controller and the source driver perform the transmission operation of the single mode, the controller provides a single mode indication signal different from the trigger signal to the source driver. The second signal transmission protocol can be some protocol different from the first signal transmission protocol, such as some transmission protocol in the related art. By setting the trigger signal, signal line multiplexing can be achieved, so that the chip has multiple functions, thereby also reducing the difficulty of popularizing the first signal transmission protocol.

[0139] Figure 6A A timing diagram of a trigger signal PSI provided by at least one embodiment of the present disclosure is shown.

[0140] As Figure 6AAs shown, the trigger signal PSI includes a data transmission control signal LOAD and a data polarity inversion control signal POL. The first transition edge (e.g., rising edge) of the data polarity inversion control signal POL is later than the second transition edge (e.g., rising edge) of the data transmission control signal LOAD. The first transition state (e.g., high level state) of the data polarity inversion control signal POL after the first transition edge coincides with the second transition state (e.g., high level state) of the data transmission control signal LOAD after the second transition edge for at least a portion of the time.

[0141] In some embodiments of this disclosure, for example, the driver in the controller can be adjusted such that, within the same cycle of the data transmission control signal LOAD and the data polarity inversion control signal POL, the data polarity inversion control signal POL occurs later than the data transmission control signal LOAD by a time length tS2, thereby causing the rising edge of the data polarity inversion control signal POL to occur later than the rising edge of the data transmission control signal LOAD. The data polarity inversion control signal POL and the data transmission control signal LOAD are simultaneously at a high level for a time length tH2 after their rising edges.

[0142] Figure 6B A timing diagram of a single-mode indication signal provided in at least one embodiment of the present disclosure is shown.

[0143] like Figure 6B As shown, the single-mode indication signal includes a data transmission control signal LOAD' and a data polarity inversion control signal POL', and the first transition edge (e.g., rising edge) of the data polarity inversion control signal POL' precedes the second transition edge (e.g., rising edge) of the data transmission control signal LOAD', and the first transition state (e.g., high level state) of the data polarity inversion control signal POL' after the first transition edge coincides with the second transition state (e.g., high level state) of the data transmission control signal LOAD' after the second transition edge at least for a portion of the time.

[0144] In some embodiments of this disclosure, for example, the driver in the controller can be adjusted such that, within the same cycle of the data transmission control signal LOAD' and the data polarity inversion control signal POL', the data polarity inversion control signal POL' precedes the data transmission control signal LOAD' by a time length tS1, thereby causing the rising edge of the data polarity inversion control signal POL' to precede the rising edge of the data transmission control signal LOAD'.

[0145] Figure 6A and Figure 6BThe embodiment of the present disclosure can distinguish between the single mode transmission operation and the transmission operation of at least two modes by means of the data transmission control signal and the data polarity inversion control signal, without the need to improve the hardware circuit of the interface, and is easy to implement. In this way, the same set of controllers and source drivers can be used to select the first signal transmission protocol or the second signal transmission protocol as needed, without the need to provide a set of controllers and source drivers for the first signal transmission protocol and the second signal transmission protocol respectively, thereby reducing the design, research and development, manufacturing and management costs for the supplier.

[0146] The controller and the source driver can be connected through the mini-LVDS signal line, the POL signal line and the LOAD signal line, so that other signal lines such as the POL2 control signal line and the POLC control signal line, the horizontal dot inversion (H2DOT) control signal line, the bias voltage (PWRC) control signal line, etc. can be all or partially omitted. Therefore, the example not only reduces the number of signal lines between the controller and the source driver, but also informs the source driver to perform which transmission operation to be compatible with the single mode transmission operation.

[0147] Figure 7 A timing relationship diagram for correcting the display sub-signal transmitted in the configuration mode is shown.

[0148] As shown in Figure 7 , the timing relationship diagram includes the data polarity inversion control signal POL and the data transmission control signal LOAD, and the first transition edge (e.g., rising edge) of the data polarity inversion control signal POL is later than the second transition edge (e.g., rising edge) of the data transmission control signal LOAD, and the first transition state (e.g., high level state) of the data polarity inversion control signal POL after the first transition edge at least partially coincides with the second transition state (e.g., high level state) of the data transmission control signal LOAD after the second transition edge, so that the controller provides the trigger signal to the source driver. In this embodiment, the controller continuously provides two trigger signals to the source driver, and multiple provision of the trigger signal can at least partially avoid noise interference and improve the accuracy of the source driver in identifying the transmission mode.

[0149] In this embodiment, the source driver determines to perform the transmission operation of at least two modes in response to receiving the two trigger signals. After the source driver receives the two trigger signals, the data signal continues to be received, and if the data signal is the correction mode signal tASC (e.g., logic invalid level "0"), it is determined that the controller provides the data signal in the correction configuration mode, and the data signal received after the correction mode signal is the correction signal.

[0150] In this embodiment, a power supply (e.g., voltage source) VDD supplies power to the source driver.

[0151] In some embodiments of the present disclosure, the controller provides the display signals to the source driver in sequence in the row configuration mode, the frame configuration mode and the correction configuration mode through the low-voltage differential signal interface.

[0152] In some embodiments of the present disclosure, the signal transmission method is applied to a display device. After the display device enters the working state, the controller provides a plurality of display sub-signals to the source driver in sequence in the row configuration mode, the frame configuration mode and the correction configuration mode. During the process of starting up the display device, the controller provides the display sub-signals in the correction configuration mode and the display sub-signals provided in the frame configuration mode in sequence.

[0153] During the process of starting up the display device, the controller first provides the correction signal to the source driver to determine the number of delay units in the clock path, and then provides the frame configuration data to the source driver, so that the controller prepares for image display in advance. During the process of starting up the display device, no image display is performed, and therefore the display sub-signals are not provided to the source driver in the row configuration mode. After the source driver is configured according to the correction parameter and configured according to the frame configuration data, the display device enters the working state.

[0154] For example, in the working state of the display device, the controller first provides the row configuration data and the row image data to the source driver in the row configuration mode, so that the display device displays the image data of each row in sequence to display a complete frame of image. After the display device displays a complete frame of image, the vertical blanking period is entered. During the vertical blanking period, the controller first provides the frame configuration data to the source driver in the frame configuration mode, so that the source driver performs frame configuration. For example, the source driver enters the low-power consumption state according to the frame configuration data. Then, the controller provides the display sub-signals to the source driver in the correction configuration mode.

[0155] Figure 8 A schematic block diagram of a signal transmission device 800 provided by at least one embodiment of the present disclosure is shown. The signal transmission device 800 is applied to a source driver, and the source driver is in communication connection with a controller through a low-voltage differential signal interface.

[0156] For example, as shown in Figure 8 The signal transmission device 800 includes an acquisition unit 810, a determination unit 820 and an adjustment unit 830.

[0157] The acquisition unit 810 is configured to acquire a clock signal and a correction signal provided by the controller.

[0158] The acquisition unit 810 may, for example, perform Figure 2A the steps S10 described above.

[0159] The determining unit 820 is configured to determine a timing offset value between the clock signal and the correction signal according to the clock signal and the correction signal.

[0160] The determining unit 820 may, for example, perform Figure 2A the step S20 described.

[0161] The adjusting unit 830 is configured to adjust a timing relationship between the clock signal and the correction signal based on the timing offset value by using a delay unit, wherein the delay unit is arranged in a clock path of the clock signal or a data path of the correction signal.

[0162] The adjusting unit 830 may, for example, perform Figure 2A the step S30 described.

[0163] The apparatus 800 can alleviate the delay between the clock signal and the image data signal in the process of transmitting the image data signal between the controller and the source driver, ensure the accurate transmission of the image data signal, and facilitate the improvement of the communication frequency between the source driver and the controller.

[0164] Figure 9 A schematic block diagram of a source driver 900 provided by at least one embodiment of the present disclosure is shown. The source driver 900 is communicatively connected with a controller through a low-voltage differential signal interface.

[0165] For example, as Figure 9 shown, the source driver 900 includes a processing circuit 910 and a delay circuit 920.

[0166] The processing circuit 910 is configured to acquire a clock signal and a correction signal provided by the controller, and determine a timing offset value between the clock signal and the correction signal according to the clock signal and the correction signal.

[0167] The processing circuit 910 may, for example, perform Figure 2A the steps S10 and S20 described.

[0168] The delay circuit 920 is arranged in a clock path of the clock signal or a data path of the correction signal, and is configured to adjust a timing relationship between the clock signal and the correction signal based on the timing offset value.

[0169] The delay circuit 920 may, for example, perform Figure 2A the step S30 described.

[0170] The source driver 900 can alleviate the delay between the clock signal and the image data signal in the process of transmitting the data signal between the controller and the source driver, ensure the accurate transmission of the image data signal, and facilitate the improvement of the communication frequency between the source driver and the controller.

[0171] For example, the acquisition unit 810, the determination unit 820 and the adjustment unit 830 can be hardware, software, firmware and any feasible combination thereof. For example, the acquisition unit 810, the determination unit 820 and the adjustment unit 830 can be special-purpose or general-purpose circuit, chip or device, etc., or a combination of processor and memory. The embodiments of the present disclosure do not limit the specific implementation form of each unit.

[0172] For example, the processing circuit 910 and the delay circuit 920 can be hardware or firmware and any feasible combination thereof. The processing circuit 910 and the delay circuit 920 can be special-purpose or general-purpose circuit, chip. The embodiments of the present disclosure do not limit the specific implementation form of each unit.

[0173] It should be noted that in the embodiments of the present disclosure, the units of the signal transmission device 800 and the source driver 900 correspond to the steps of the aforementioned signal transmission method, and the specific functions of the signal transmission device 800 and the source driver 900 can be referred to the related description of the signal transmission method, which will not be repeated here. Figure 8 The signal transmission device 800 and Figure 9 The components and structures of the source driver 900 shown are only exemplary and are not limiting, and the signal transmission device 800 and the source driver 900 can also include other components and structures as needed.

[0174] Figure 10 A schematic block diagram of an electronic device provided by at least one embodiment of the present disclosure is shown.

[0175] As Figure 10 The electronic device 1000 shown includes a controller 1010, a source driver 1020 and a display panel 1030.

[0176] The controller 1010 is configured to provide a display signal to the source driver 1020. For the introduction of the display signal, please refer to the description above.

[0177] The source driver 1020, for example, performs the above Figure 2AThe described signal transmission method. The source driver 1020 is connected with the controller 1010 through a low voltage differential signal interface to receive a clock signal, a display signal, etc. The display panel 1030, for example, is a liquid crystal display panel, used to receive a driving signal (i.e., a gray scale voltage signal) provided from the source driver 1020 to display an image, the driving signal being generated by the source driver based on the display signal.

[0178] The electronic device 1000 can be various electronic devices with image display functions, including but not limited to smart phones, tablet computers, notebook computers, displays, televisions, etc.

[0179] The electronic device 1000 is to alleviate the delay between the clock signal and the data signal in the process of transmitting the data signal between the controller and the source driver, ensure the accurate transmission of the data signal, and be conducive to improving the communication frequency between the source driver and the controller.

[0180] Although as described above, the following points also need to be explained:

[0181] (1) The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures can be referred to the usual design.

[0182] (2) In the case of no conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0183] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A signal transmission method applied to a source driver, wherein, The source driver and the controller are connected via a low-voltage differential signal interface, and the method includes: Obtain the clock signal and correction signal provided by the controller; Based on the clock signal and the correction signal, determine the timing offset value between the clock signal and the correction signal; and Based on the timing offset value, a delay unit is used to adjust the timing relationship between the clock signal and the correction signal, wherein the delay unit is disposed in the clock path of the clock signal or the data path of the correction signal. Wherein, the timing offset value is the offset between the sampling time of the clock signal and the reference time of the correction signal during the first signal period, wherein the correction signal is a signal that alternates between the first signal and the second signal. Determining the timing offset value between the clock signal and the correction signal based on the clock signal and the correction signal includes: Obtain the first time length from the sampling time to the first transition edge of the correction signal and the second time length to the second transition edge; and Based on the first time length and the second time length, the timing offset value between the clock signal and the correction signal is determined. Wherein, the first transition edge is the transition edge where the correction signal transitions from the second signal to the first signal, and the second transition edge is the transition edge where the correction signal transitions from the first signal to the second signal.

2. The method according to claim 1, wherein, Obtaining the first time length from the sampling time to the first transition edge of the correction signal and the second time length to the second transition edge includes: The correction signal is counted positively from the sampling time to the second transition edge, and the positive count represents the second time length. The correction signal is counted backwards from the sampling time to the first transition edge, and the first time length is represented by the count backwards.

3. The method according to claim 2, wherein, Determining the timing offset value between the clock signal and the correction signal based on the first time length and the second time length includes: The average of the positive count and the reverse count is used as the timing offset value.

4. The method according to claim 1, wherein, Based on the timing offset value, adjusting the timing relationship between the clock signal and the correction signal using a delay unit includes: The number of delay units is determined based on the timing offset value; and Adjust the number of delay units in the clock path or adjust the number of delay units in the data path.

5. The method according to claim 1, wherein, The controller provides display signals in at least two modes, the display signals comprising multiple display sub-signals, each of the at least two modes providing the multiple display sub-signals, and each display sub-signal including a pattern recognition signal. Determining the timing offset between the clock signal and the correction signal based on the clock signal and the correction signal includes: In response to the pattern recognition signal being a correction mode signal, it is determined that the controller provides the display sub-signal in a correction configuration mode and that the display sub-signal includes the correction signal; and The timing offset between the clock signal and the correction signal is determined based on the clock signal and the correction signal.

6. The method according to claim 5, wherein, The signal following the correction mode signal is the correction signal.

7. The method according to claim 5, wherein, The display sub-signal provided in each mode also includes a trigger signal, which instructs the source driver to perform a transmission operation according to the at least two modes.

8. The method according to claim 7, wherein, The trigger signal includes a data transmission control signal and a data polarity reversal control signal. Wherein, the first transition edge of the data polarity reversal control signal is later than the second transition edge of the data transmission control signal, and the first transition state of the data polarity reversal control signal after the first transition edge coincides with the second transition state of the data transmission control signal after the second transition edge for at least part of the time.

9. The method according to claim 5, wherein, The at least two modes also include: line configuration mode or frame configuration mode. The display sub-signal provided in the row configuration mode is used to configure the source driver for displaying one row of pixels. The display sub-signals provided by the frame configuration mode are used to configure the source driver for the display of a frame of pixels.

10. The method according to claim 9, wherein, The controller provides the display signal to the source driver sequentially through the low-voltage differential signal interface in the row configuration mode, the frame configuration mode, and the correction configuration mode.

11. The method according to claim 9, wherein, The frame configuration mode and the correction configuration mode during vertical blanking.

12. A signal transmission device applied to a source driver, wherein, The source driver and controller are connected via a low-voltage differential signal interface, and the signal transmission device includes: The acquisition unit is configured to acquire a clock signal and a correction signal provided by the controller, wherein the correction signal is a signal that alternates between a first signal and a second signal; The determining unit is configured to determine a timing offset value between the clock signal and the correction signal based on the clock signal and the correction signal; and The adjustment unit is configured to adjust the timing relationship between the clock signal and the correction signal based on the timing offset value using a delay unit, wherein the delay unit is located in the clock path of the clock signal or the data path of the correction signal. The determining unit is configured as follows: Obtain the first time length from the sampling time to the first transition edge of the correction signal and the second time length to the second transition edge; and Based on the first time length and the second time length, the timing offset value between the clock signal and the correction signal is determined. Wherein, the first transition edge is the transition edge where the correction signal transitions from the second signal to the first signal, and the second transition edge is the transition edge where the correction signal transitions from the first signal to the second signal.

13. A source driver for communicating with a controller via a low-voltage differential signal interface, the source driver comprising: The processing circuit is configured to acquire a clock signal and a correction signal provided by the controller, and determine a timing offset value between the clock signal and the correction signal based on the clock signal and the correction signal, wherein the correction signal is a signal that alternates between a first signal and a second signal; as well as A delay circuit, located in the clock path of the clock signal or the data path of the correction signal, is configured to adjust the timing relationship between the clock signal and the correction signal based on the timing offset value. The processing circuit is configured as follows: Obtain the first time length from the sampling time to the first transition edge of the correction signal and the second time length to the second transition edge; and Based on the first time length and the second time length, the timing offset value between the clock signal and the correction signal is determined. Wherein, the first transition edge is the transition edge where the correction signal transitions from the second signal to the first signal, and the second transition edge is the transition edge where the correction signal transitions from the first signal to the second signal.

14. An electronic device comprising: The source driver as described in claim 13; A controller, wherein the controller is configured to provide a display signal to the source driver; and A display panel is connected to the source driver to receive drive signals provided by the source driver, wherein the drive signals are generated based on the display signals.

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