Control method for implementing exclusive-or operation by NAND flash memory

Abstract

The application provides a control method for implementing XOR operation of NAND flash memory, comprising providing NAND flash memory, wherein the NAND flash memory comprises at least one memory block and a plurality of sense amplifiers, the memory block comprises a plurality of synaptic strings, a plurality of bit lines and a plurality of word lines, the synaptic string comprises a plurality of storage units connected in series, the synaptic string is connected in one-to-one correspondence with the bit line, and the word line is connected with all the synaptic strings; the sense amplifier is connected in one-to-one correspondence with the bit line; and by controlling the storage mode of data and the voltage of the word line, the XOR operation of the NAND flash memory is realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of NAND flash memory, in particular to a control method for implementing XOR operation of NAND flash memory. BACKGROUND

[0002] Figure 1 A circuit schematic diagram of NAND flash memory for implementing XOR operation in the prior art, Figure 1 A circuit schematic diagram of NAND flash memory for implementing XOR operation in the prior art, Figure 1 and Figure 2 One readout amplifier is connected to two bit lines, which is incompatible with normal NAND flash memory, and each bit line is controlled by a separate switch, which is also incompatible with normal NAND flash memory structure and increases the area cost.

[0003] Therefore, it is necessary to provide a new control method for NAND flash memory to implement XOR operation to solve the above problems in the prior art. SUMMARY

[0004] The purpose of the present application is to provide a control method for NAND flash memory to implement XOR operation, which is compatible with normal NAND flash memory structure and implements XOR operation.

[0005] To achieve the above purpose, the control method for NAND flash memory to implement XOR operation comprises the following steps:

[0006] S0: providing NAND flash memory, the NAND flash memory comprising at least one memory block and a plurality of readout amplifiers, the memory block comprising a plurality of synaptic strings, a plurality of bit lines and a plurality of word lines, the synaptic string comprising a plurality of series-connected memory cells, the synaptic string being connected to the bit line one by one, the word line being connected to all the synaptic strings, and the readout amplifier being connected to the bit line one by one;

[0007] S1: in the same memory block, selecting any synaptic string as a first synaptic string, selecting any synaptic string from the remaining synaptic strings as a second synaptic string, selecting any memory cell in the first synaptic string as a first memory cell, selecting any memory cell in the second synaptic string as a second memory cell, writing first data to the first memory cell, and writing second data to the second memory cell, the word line connected to the first memory cell being different from the word line connected to the second memory cell, and the first data and the second data being complementary data;

[0008] S2: applying a first potential voltage to the word line connected to the first memory cell and a second potential voltage to the word line connected to the second memory cell, and the first potential voltage being different from the second potential voltage.

[0009] S3: reading data from the first synapse string and outputting first operation data through a corresponding read-out amplifier, and reading data from the second synapse string and outputting second operation data through a corresponding read-out amplifier;

[0010] S4: obtaining result data according to at least one of the first operation data and the second operation data.

[0011] The control method for implementing XOR operation of the NAND flash has the advantages that one read-out amplifier is connected to one bit line of one memory block, on the basis of normal NAND flash compatibility, in the same memory block, any one of the synapse strings is selected as a first synapse string, any one of the remaining synapse strings is selected as a second synapse string, any one of the memory cells in the first synapse string is selected as a first memory cell, and any one of the memory cells in the second synapse string is selected as a second memory cell, first data is written into the first memory cell, second data is written into the second memory cell, the word line connected to the first memory cell is different from the word line connected to the second memory cell, and the first data and the second data are complementary data, a first potential voltage is applied to the word line connected to the first memory cell, a second potential voltage is applied to the word line connected to the second memory cell, and the first potential voltage is different from the second potential voltage, data is read from the first synapse string through a corresponding read-out amplifier and first operation data is output, data is read from the second synapse string through a corresponding read-out amplifier and second operation data is output, and result data is obtained according to at least one of the first operation data and the second operation data, by controlling the storage mode of data and the voltage of the word line, the XOR operation of the NAND flash is realized.

[0012] Optionally, the step S1 is further preceded by a threshold voltage setting step, the first data and the second data are binary data, when the first data is binary data 1 and the second data is binary data 0, the threshold voltage setting step includes:

[0013] setting the threshold voltage of the first memory cell as a first threshold voltage, setting the threshold voltage of the second memory cell as a second threshold voltage, and setting the threshold voltage of the remaining memory cells as a third threshold voltage, wherein the third threshold voltage is less than the first threshold voltage, and the first threshold voltage is less than the second threshold voltage;

[0014] when the first data is binary data 0 and the second data is binary data 1, the threshold voltage setting step includes:

[0015] The second storage unit threshold voltage is set as a first threshold voltage, the threshold voltage of the first storage unit is set as a second threshold voltage, and the threshold voltage of the remaining storage units is set as a third threshold voltage, wherein the third threshold voltage is less than the first threshold voltage, and the first threshold voltage is less than the second threshold voltage.

[0016] Optionally, the first potential voltage is greater than the third threshold voltage and less than the first threshold voltage, the second potential voltage is greater than the first threshold voltage and less than the second threshold voltage, or the second potential voltage is greater than the third threshold voltage and less than the first threshold voltage, and the first potential voltage is greater than the first threshold voltage and less than the second threshold voltage.

[0017] Optionally, the step S1 further comprises:

[0018] The first data or the second data is written to the remaining storage units of the first synaptic string and the remaining storage units of the second synaptic string, and at least one of the two storage units connected by a word line in the first synaptic string and the second synaptic string does not store data.

[0019] Optionally, the step S2 further comprises: applying a third potential voltage to the remaining word lines, wherein the third potential voltage is different from the first potential voltage and the second potential voltage.

[0020] Optionally, the first potential voltage is greater than the third threshold voltage and less than the first threshold voltage, the second potential voltage is greater than the first threshold voltage and less than the second threshold voltage, the third potential voltage is greater than the second threshold voltage, or the second potential voltage is greater than the third threshold voltage and less than the first threshold voltage, the first potential voltage is greater than the first threshold voltage and less than the second threshold voltage, and the third potential voltage is greater than the second threshold voltage.

[0021] Optionally, the result data is obtained according to at least one of the first operation data and the second operation data, comprising:

[0022] The first operation data and the second operation data are subjected to an or logical operation, an or logical operation, an and logical operation, or an and not logical operation to obtain the result data.

[0023] Optionally, before the step S1 is performed, a threshold voltage setting step is further included, the first data and the second data are both binary data, when the first data is binary data 1 and the second data is binary data 0, the threshold voltage setting step comprises:

[0024] setting the threshold voltage of the second memory cell as a first threshold voltage, setting the threshold voltage of the first memory cell as a second threshold voltage, and setting the threshold voltage of the remaining memory cells as the first threshold voltage, wherein the first threshold voltage is less than the second threshold voltage.

[0025] Optionally, before the step S1, there is further a threshold voltage setting step, the first data and the second data are binary data, when the first data is binary data 0 and the second data is binary data 1, the threshold voltage setting step comprises:

[0026] setting the threshold voltage of the second memory cell as a first threshold voltage, setting the threshold voltage of the first memory cell as a second threshold voltage, and setting the threshold voltage of the remaining memory cells as the first threshold voltage, wherein the first threshold voltage is less than the second threshold voltage.

[0027] Optionally, the result data is obtained according to at least one of the first operation data and the second operation data, comprising:

[0028] performing AND logic operation or NAND logic operation on the first operation data and the second operation data to obtain the result data. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figure 1 a circuit schematic diagram of an existing NAND flash memory for implementing XOR operation;

[0030] Figure 2 a circuit schematic diagram of another existing NAND flash memory for implementing XOR operation;

[0031] Figure 3 a flow chart of a control method of NAND flash memory for implementing XOR operation in some embodiments of the present application;

[0032] Figure 4 a structure schematic diagram of NAND flash memory in some embodiments of the present application;

[0033] Figure 5 a threshold voltage distribution schematic diagram in some first embodiments of the present application;

[0034] Figure 6 a threshold voltage distribution schematic diagram in some second embodiments of the present application;

[0035] Figure 7 a threshold voltage distribution schematic diagram in some third embodiments of the present application;

[0036] Figure 8 a threshold voltage distribution schematic diagram in some fourth embodiments of the present application;

[0037] Figure 9 The threshold voltage distribution diagram in some embodiments of the present application. DETAILED DESCRIPTION

[0038] For the purpose of making the objects, technical solutions and advantages of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of the present application. Unless otherwise defined, the technical terms or scientific terms used herein should be understood as the common meanings thereof to those of ordinary skill in the art to which the present application belongs. The similar words such as “comprise” used herein are intended to cover the elements or objects recited before the words and the equivalents thereof, and do not exclude other elements or objects.

[0039] In view of the problems in the prior art, the embodiments of the present application provide a control method for implementing XOR operation by NAND flash memory. Referring to Figure 3 , the control method for implementing XOR operation by NAND flash memory comprises the following steps:

[0040] S0: providing a NAND flash memory, the NAND flash memory comprising at least one memory block and a plurality of sense amplifiers, the memory block comprising a plurality of synaptic strings, a plurality of bit lines and a plurality of word lines, the synaptic string comprising a plurality of storage units connected in series, the synaptic string being connected to the bit line one by one, the word line being connected to all the synaptic strings, and the sense amplifier being connected to the bit line one by one;

[0041] S1: in the same memory block, selecting any synaptic string as a first synaptic string, selecting any synaptic string from the remaining synaptic strings as a second synaptic string, selecting any storage unit in the first synaptic string as a first storage unit, selecting any storage unit in the second synaptic string as a second storage unit, writing first data to the first storage unit, and writing second data to the second storage unit, the word line connected to the first storage unit being different from the word line connected to the second storage unit, and the first data and the second data being complementary data;

[0042] S2: applying a first potential voltage to the word line connected to the first storage unit, and applying a second potential voltage to the word line connected to the second storage unit, the first potential voltage being different from the second potential voltage;

[0043] S3: reading data from the first synapse string by a corresponding read-out amplifier and outputting first operation data, and reading data from the second synapse string by a corresponding read-out amplifier and outputting second operation data;

[0044] S4: obtaining result data according to at least one of the first operation data and the second operation data.

[0045] In some embodiments, before performing the step S1, a threshold voltage setting step is further included, the first data and the second data are both binary data, when the first data is binary data 1 and the second data is binary data 0, the threshold voltage setting step includes: setting the threshold voltage of the first storage unit as a first threshold voltage, setting the threshold voltage of the second storage unit as a second threshold voltage, and setting the threshold voltage of the remaining storage units as a third threshold voltage, wherein the third threshold voltage is less than the first threshold voltage, and the first threshold voltage is less than the second threshold voltage.

[0046] In yet some embodiments, before performing the step S1, a threshold voltage setting step is further included, the first data and the second data are both binary data, when the first data is binary data 0 and the second data is binary data 1, the threshold voltage setting step includes: setting the threshold voltage of the second storage unit as a first threshold voltage, setting the threshold voltage of the first storage unit as a second threshold voltage, and setting the threshold voltage of the remaining storage units as a third threshold voltage, wherein the third threshold voltage is less than the first threshold voltage, and the first threshold voltage is less than the second threshold voltage.

[0047] In some embodiments, the first potential voltage is greater than the third threshold voltage and less than the first threshold voltage, and the second potential voltage is greater than the first threshold voltage and less than the second threshold voltage, or the second potential voltage is greater than the third threshold voltage and less than the first threshold voltage, and the first potential voltage is greater than the first threshold voltage and less than the second threshold voltage.

[0048] In some embodiments, the obtaining result data according to at least one of the first operation data and the second operation data includes: performing an or logic operation, an or logic operation, an and logic operation or an and not logic operation on the first operation data and the second operation data to obtain the result data.

[0049] Figure 4 The structure of a NAND flash memory in some embodiments of the present application is shown in FIG. 1. Referring to FIG. 1, the NAND flash memory includes a plurality of memory cells 10, a plurality of word lines 20, a plurality of bit lines 30, a plurality of source lines 40, a plurality of control lines 50, a plurality of read-out amplifiers 60, and a plurality of sense amplifiers 70. Figure 4The NAND flash memory includes a first memory block 101, a first sense amplifier 102, a second sense amplifier 103, a third sense amplifier 104, and a fourth sense amplifier 105.

[0050] Referring to Figure 4 The first memory block 101 includes four synaptic strings, four bit lines, and four word lines. The four synaptic strings are a first synaptic string 1011, a second synaptic string 1012, a third synaptic string 1013, and a fourth synaptic string 1014. The four bit lines are a first bit line 1015, a second bit line 1016, a third bit line 1017, and a fourth bit line 1018. The four word lines are a first word line 1019, a second word line 10110, a third word line 10111, and a fourth word line 10112. The first synaptic string 1011, the second synaptic string 1012, the third synaptic string 1013, and the fourth synaptic string 1014 each include four storage cells 10113 connected in series.

[0051] Referring to Figure 4 The first synaptic string 1011 is connected to the first sense amplifier 102 through the first bit line 1015. The second synaptic string 1012 is connected to the second sense amplifier 103 through the second bit line 1016. The third synaptic string 1013 is connected to the third sense amplifier 104 through the third bit line 1017. The fourth synaptic string 1014 is connected to the fourth sense amplifier 105 through the fourth bit line 1018.

[0052] Referring to Figure 4 The first word line 1019 is connected to a first storage cell of the first synaptic string 1011, a first storage cell of the second synaptic string 1012, a first storage cell of the third synaptic string 1013, and a first storage cell of the fourth synaptic string 1014. The second word line 10110 is connected to a second storage cell of the first synaptic string 1011, a second storage cell of the second synaptic string 1012, a second storage cell of the third synaptic string 1013, and a second storage cell of the fourth synaptic string 1014. The third word line 10111 is connected to a third storage cell of the first synaptic string 1011, a third storage cell of the second synaptic string 1012, a third storage cell of the third synaptic string 1013, and a third storage cell of the fourth synaptic string 1014. The fourth word line 10112 is connected to a fourth storage cell of the first synaptic string 1011, a fourth storage cell of the second synaptic string 1012, a fourth storage cell of the third synaptic string 1013, and a fourth storage cell of the fourth synaptic string 1014.

[0053] Figure 5Fig. 1 is a schematic diagram of threshold voltage distribution in some embodiments of the present application. Referring to Fig. 1, L represents a third threshold voltage distribution curve, 1 represents a first threshold voltage distribution curve, and 0 represents a second threshold voltage distribution curve. Figure 5 Fig. 1 is a schematic diagram of threshold voltage distribution in some embodiments of the present application. Referring to Fig. 1, L represents a third threshold voltage distribution curve, 1 represents a first threshold voltage distribution curve, and 0 represents a second threshold voltage distribution curve. W1(1) represents a voltage when binary data 1 is input. W1(0) represents a voltage when binary data 0 is input.

[0054] Fig. 1 is a schematic diagram of threshold voltage distribution in some embodiments of the present application. Referring to Fig. 1, L represents a third threshold voltage distribution curve, 1 represents a first threshold voltage distribution curve, and 0 represents a second threshold voltage distribution curve. Figure 4 Fig. 1 is a schematic diagram of threshold voltage distribution in some embodiments of the present application. Referring to Fig. 1, L represents a third threshold voltage distribution curve, 1 represents a first threshold voltage distribution curve, and 0 represents a second threshold voltage distribution curve. Figure 5 A first data is written into a first memory cell of the first synapse string 1011, the first data is binary data 0, a second data is written into a second memory cell of the second synapse string 1012, the second data is binary data 1, and the remaining memory cells of the first synapse string 1011 and the second synapse string 1012 are not written with data. The first memory cell of the first synapse string 1011 is a first memory cell, and the second memory cell of the second synapse string 1012 is a second memory cell. The threshold voltage of the first memory cell is set as a second threshold voltage, the threshold voltage of the second memory cell is set as a first threshold voltage, and the threshold voltage of the remaining memory cells of the first synapse string 1011 and the second synapse string 1012 is set as a third threshold voltage, i.e., the threshold voltage of the memory cell not written with data is the third threshold voltage L. A first potential voltage is applied to the first word line 1019, the size of the first potential voltage is V W1(0) , which is equivalent to providing binary data 0 for the NOR operation through the first word line 1019. A second potential voltage is applied to the second word line 10110, the size of the second potential voltage is V W1(1) At this time, the first readout amplifier 102 can read data from the first synapse string 1011 and output first operation data, the first operation data is binary data 0, and the second readout amplifier 103 can read data from the second synapse string 1012 and output second operation data, the second operation data is binary data 0. Then, the first operation data and the second operation data are subjected to NAND logic operation to obtain result data, the result data is binary data 1, i.e., the NOR operation of binary data 0 and binary data 0 is realized through the NAND flash memory.

[0055] Figure 8 Fig. 1 is a schematic diagram of threshold voltage distribution in some embodiments of the present application. Referring to Fig. 1, L represents a third threshold voltage distribution curve, 1 represents a first threshold voltage distribution curve, and 0 represents a second threshold voltage distribution curve. Figure 8 Fig. 1 is a schematic diagram of threshold voltage distribution in some embodiments of the present application. Referring to Fig. 1, L represents a third threshold voltage distribution curve, 1 represents a first threshold voltage distribution curve, and 0 represents a second threshold voltage distribution curve. W1(1) represents a voltage when binary data 1 is input. W1(0)V0

[0056] Referring to Figure 4 and Figure 8 , a first data of binary data 0 is written to a first memory cell of the first synaptic string 1011, a second data of binary data 1 is written to a second memory cell of the second synaptic string 1012, and the remaining memory cells of the first synaptic string 1011 and the second synaptic string 1012 are not written with data. The first memory cell of the first synaptic string 1011 is a first memory cell, and the second memory cell of the second synaptic string 1012 is a second memory cell. The threshold voltage of the first memory cell is set to a second threshold voltage, the threshold voltage of the second memory cell is set to a first threshold voltage, and the threshold voltage of the remaining memory cells of the first synaptic string 1011 and the second synaptic string 1012 is set to a third threshold voltage, i.e., the threshold voltage of the memory cell not written with data is the third threshold voltage L. A first potential voltage V W1(0) is applied to the first word line 1019, which is equivalent to providing binary data 0 for the AND operation through the first word line 1019, and a second potential voltage V W1(1) is applied to the second word line 1010. With reference to the threshold distribution shown in Figure 5 , if the results of the first readout amplifier 102 and the second readout amplifier 103 are both inverted, i.e., the first operation data is binary data 1 and the second operation data is binary data 1, the AND logic operation is performed on the first operation data and the second operation data to obtain a result data, which is binary data 1. If the result of the first readout amplifier 102 or the second readout amplifier 103 is inverted, i.e., the first operation data is binary data 1 and the second operation data is binary data 0, the OR logic operation or the NAND logic operation is performed on the first operation data and the second operation data to obtain a result data, which is binary data 1. If the first operation data is binary data 0 and the second operation data is binary data 1, the OR logic operation or the NAND logic operation is performed on the first operation data and the second operation data to obtain a result data, which is binary data 1.

[0057] Referring to Figure 4 and Figure 5, the first data is binary data 1, the second data is binary data 0, and the remaining storage units of the first synapse string 1011 and the second synapse string 1012 are not written with data. Wherein the first storage unit of the first synapse string 1011 is the first storage unit, and the second storage unit of the second synapse string 1012 is the second storage unit. The threshold voltage of the first storage unit is set to the first threshold voltage, the threshold voltage of the second storage unit is set to the second threshold voltage, and the threshold voltage of the remaining storage units of the first synapse string 1011 and the second synapse string 1012 is set to the third threshold voltage, that is, the threshold voltage of the storage unit without writing data is the third threshold voltage L. A first potential voltage is applied to the first word line 1019, and the size of the first potential voltage is V W1(1) , which is equivalent to providing binary data 1 for the same gate or operation through the first word line 1019, a second potential voltage is applied to the second word line 10110, and the size of the second potential voltage is V W1(0) At this time, the first readout amplifier 102 can read data from the first synapse string 1011 and output first operation data, and the first operation data is binary data 0. The second readout amplifier 103 can read data from the second synapse string 1012 and output second operation data, and the second operation data is binary data 0. Then, the first operation data and the second operation data are subjected to NAND logic operation to obtain result data, and the result data is binary data 1, that is, the binary data 1 and the binary data 1 are subjected to the same or operation through the NAND flash memory.

[0058] Referring to Figure 4 and Figure 8, the first data is binary data 1, the second data is binary data 0, and the remaining storage units of the first synapse string 1011 and the remaining storage units of the second synapse string 1012 are not written with data. The first storage unit of the first synapse string 1011 is the first storage unit, and the second storage unit of the second synapse string 1012 is the second storage unit. The threshold voltage of the first storage unit is set to the first threshold voltage, the threshold voltage of the second storage unit is set to the second threshold voltage, and the threshold voltage of the remaining storage units of the first synapse string 1011 and the remaining storage units of the second synapse string 1012 is set to the third threshold voltage, i.e. the threshold voltage of the storage unit not written with data is the third threshold voltage L. A first potential voltage is applied to the first word line 1019, and the size of the first potential voltage is V W1(1) , which is equivalent to providing binary data 1 for the AND operation through the first word line 1019. A second potential voltage is applied to the second word line 10110, and the size of the second potential voltage is V W1(0) . With reference to the threshold distribution shown in Figure 5 , if the results of the first readout amplifier 102 and the second readout amplifier 103 are both inverted, i.e. the first operation data is binary data 1 and the second operation data is binary data 1, the AND logic operation is performed on the first operation data and the second operation data to obtain the result data, which is binary data 1. If the result of the first readout amplifier 102 or the second readout amplifier 103 is inverted, i.e. the first operation data is binary data 1 and the second operation data is binary data 0, the OR logic operation or the NAND logic operation is performed on the first operation data and the second operation data to obtain the result data, which is binary data 1. If the first operation data is binary data 0 and the second operation data is binary data 1, the OR logic operation or the NAND logic operation is performed on the first operation data and the second operation data to obtain the result data, which is binary data 1.

[0059] Referring to Figure 4 and Figure 5, the first data is binary data 1, the second data is binary data 0, and the remaining storage units of the first synapse string 1011 and the second synapse string 1012 are not written with data. Wherein the first storage unit of the first synapse string 1011 is the first storage unit, and the second storage unit of the second synapse string 1012 is the second storage unit. The threshold voltage of the first storage unit is set to the first threshold voltage, the threshold voltage of the second storage unit is set to the second threshold voltage, and the threshold voltage of the remaining storage units of the first synapse string 1011 and the second synapse string 1012 is set to the third threshold voltage, i.e. the threshold voltage of the storage unit without writing data is the third threshold voltage L. A first potential voltage is applied to the first word line 1019, and the size of the first potential voltage is V W1(0) , which is equivalent to providing binary data 0 for the exclusive or operation through the first word line 1019, a second potential voltage is applied to the second word line 10110, and the size of the second potential voltage is V W1(1) At this time, the first readout amplifier 102 can read data from the first synapse string 1011 and output first operation data, and the first operation data is binary data 1. The second readout amplifier 103 can read data from the second synapse string 1012 and output second operation data, and the second operation data is binary data 0. Then, the first operation data and the second operation data are subjected to NAND logic operation to obtain result data, and the result data is binary data 0, i.e. the exclusive or operation of binary data 0 and binary data 1 is realized through the NAND flash memory.

[0060] Referring to Figure 4 and Figure 8, the first data is binary data 1, the second data is binary data 0, and the remaining storage units of the first synapse string 1011 and the second synapse string 1012 are not written with data. The first storage unit of the first synapse string 1011 is the first storage unit, and the second storage unit of the second synapse string 1012 is the second storage unit. The threshold voltage of the first storage unit is set to the first threshold voltage, the threshold voltage of the second storage unit is set to the second threshold voltage, and the threshold voltage of the remaining storage units of the first synapse string 1011 and the second synapse string 1012 is set to the third threshold voltage, i.e. the threshold voltage of the storage unit without data is the third threshold voltage L. A first potential voltage is applied to the first word line 1019, and the size of the first potential voltage is V W1(0) , which is equivalent to providing binary data 0 for the AND operation through the first word line 1019. A second potential voltage is applied to the second word line 10110, and the size of the second potential voltage is V W1(1) . With reference to the threshold distribution shown in Figure 5 , if the results of the first readout amplifier 102 and the second readout amplifier 103 are both inverted, i.e. the first operation data is binary data 0 and the second operation data is binary data 1, the AND logic operation is performed on the first operation data and the second operation data to obtain the result data, and the result data is binary data 0. If the result of the first readout amplifier 102 or the second readout amplifier 103 is inverted, the first operation data is binary data 0 and the second operation data is binary data 0, the OR logic operation is performed on the first operation data and the second operation data to obtain the result data, and the result data is binary data 0; if the first operation data is binary data 1 and the second operation data is binary data 1, the NAND logic operation is performed on the first operation data and the second operation data to obtain the result data, and the result data is binary data 0.

[0061] Referring to Figure 4 and Figure 5, the first data is binary data 0, the second data is binary data 1, and the remaining storage units of the first synapse string 1011 and the second synapse string 1012 are not written with data. Wherein the first storage unit of the first synapse string 1011 is the first storage unit, and the second storage unit of the second synapse string 1012 is the second storage unit. The threshold voltage of the first storage unit is set to the second threshold voltage, the threshold voltage of the second storage unit is set to the first threshold voltage, and the threshold voltage of the remaining storage units of the first synapse string 1011 and the second synapse string 1012 is set to the third threshold voltage, that is, the threshold voltage of the storage unit without writing data is the third threshold voltage L. A first potential voltage is applied to the first word line 1019, and the size of the first potential voltage is V W1(1) , which is equivalent to providing binary data 1 for the same gate or operation through the first word line 1019, a second potential voltage is applied to the second word line 10110, and the size of the second potential voltage is V W1(0) At this time, the first readout amplifier 102 can read data from the first synapse string 1011 and output first operation data, and the first operation data is binary data 0. The second readout amplifier 103 can read data from the second synapse string 1012 and output second operation data, and the second operation data is binary data 1. Then, the first operation data and the second operation data are subjected to NAND logic operation to obtain result data, and the result data is binary data 0, that is, the same or operation of binary data 1 and binary data 0 is realized through the NAND flash memory.

[0062] Referring to Figure 4 and Figure 8, the first data is binary data 0, the second data is binary data 1, and the remaining storage units of the first synaptic string 1011 and the second synaptic string 1012 are not written with data. The first storage unit of the first synaptic string 1011 is the first storage unit, and the second storage unit of the second synaptic string 1012 is the second storage unit. The threshold voltage of the first storage unit is set to the second threshold voltage, the threshold voltage of the second storage unit is set to the first threshold voltage, and the threshold voltage of the remaining storage units of the first synaptic string 1011 and the second synaptic string 1012 is set to the third threshold voltage, i.e., the threshold voltage of the storage unit without writing data is the third threshold voltage L. The first potential voltage is applied to the first word line 1019, and the size of the first potential voltage is V W1(1) , which is equivalent to providing binary data 1 for the AND operation through the first word line 1019. The second potential voltage is applied to the second word line 10110, and the size of the second potential voltage is V W1(0) . With reference to the threshold distribution shown in Figure 5 , if the results of the first readout amplifier 102 and the second readout amplifier 103 are both inverted, i.e., the first operation data is binary data 1 and the second operation data is binary data 0, the AND logic operation is performed on the first operation data and the second operation data to obtain the result data, and the result data is binary data 0. If the result of the first readout amplifier 102 or the second readout amplifier 103 is inverted, the first operation data is binary data 0, and the second operation data is binary data 0, the OR logic operation is performed on the first operation data and the second operation data to obtain the result data, and the result data is binary data 0; if the first operation data is binary data 1 and the second operation data is binary data 1, the NAND logic operation is performed on the first operation data and the second operation data to obtain the result data, and the result data is binary data 0.

[0063] Referring to Figure 4 and Figure 5, the first data is binary data 0, the second data is binary data 1, and the remaining storage units of the first synaptic string 1011 and the second synaptic string 1012 are not written with data. The third storage unit of the third synaptic string 1013 is the first storage unit, and the fourth storage unit of the fourth synaptic string 1014 is the second storage unit. At this time, the same operation as that on the first synaptic string 1011 and the second synaptic string 1012 can be performed. And because the threshold voltage of the storage unit not written with data is very low, the voltage on the word line is V W1(1) or V W1(0) , and the storage unit not written with data is turned on.

[0064] In some embodiments, the step S1 further comprises: writing the first data or the second data to the remaining storage units of the first synaptic string and the second synaptic string, and at least one of the two storage units connected by one word line in the first synaptic string and the second synaptic string does not store data.

[0065] In some embodiments, the step S2 further comprises: applying a third potential voltage to the remaining word lines, the third potential voltage being different from the first potential voltage and the second potential voltage.

[0066] In some embodiments, the first potential voltage is greater than the third threshold voltage and less than the first threshold voltage, the second potential voltage is greater than the first threshold voltage and less than the second threshold voltage, the third potential voltage is greater than the second threshold voltage, or the second potential voltage is greater than the third threshold voltage and less than the first threshold voltage, the first potential voltage is greater than the first threshold voltage and less than the second threshold voltage, and the third potential voltage is greater than the second threshold voltage.

[0067] Figure 4 The figure is a schematic diagram of threshold voltage distribution in the second embodiments of the present application. Referring to Figure 8 , in the figure, L represents the third threshold voltage distribution curve, 1 represents the first threshold voltage distribution curve, 0 represents the second threshold voltage distribution curve, V W1(1) represents the voltage when binary data 1 is input, V W1(0) represents the voltage when binary data 0 is input, V W1(H) represents the third potential voltage.

[0068] Referring to Figure 5 and Figure 4, the first data is binary data 0, the second data is binary data 1, and the remaining storage units of the first synaptic string 1011 and the second synaptic string 1012 are not written with data. Wherein the first storage unit of the first synaptic string 1011 is the first storage unit, and the second storage unit of the second synaptic string 1012 is the second storage unit. The first data is written to the third storage unit of the first synaptic string 1011, and the second data is written to the second storage unit of the second synaptic string 1012. The threshold voltage of the first storage unit and the threshold voltage of the third storage unit of the first synaptic string 1011 are set to the second threshold voltage, the threshold voltage of the second storage unit and the threshold voltage of the fourth storage unit of the second synaptic string 1012 are set to the first threshold voltage, and the threshold voltage of the remaining storage units of the first synaptic string 1011 and the second synaptic string 1012 is set to the third threshold voltage, that is, the threshold voltage of the storage unit which is not written with data is the third threshold voltage L. The first potential voltage is applied to the first word line 1019, and the size of the first potential voltage is V W1(0) , which is equivalent to providing binary data 0 for the same gate or operation through the first word line 1019, the second potential voltage is applied to the second word line 10110, and the size of the second potential voltage is V W1(1) , the third potential voltage is applied to the third word line 10111 and the fourth word line 10112, at this time the first readout amplifier 102 can read data from the first synaptic string 1011 and output the first operation data, the first operation data is binary data 0, the second readout amplifier 103 can read data from the second synaptic string 1012 and output the second operation data, the second operation data is binary data 0, then the first operation data and the second operation data are subjected to NAND logic operation to obtain the result data, the result data is binary data 1, that is, the binary data 0 and the binary data 0 are subjected to the same or operation through the NAND flash.

[0069] Referring to Figure 5 and Figure 6 , the first potential voltage is applied to the third word line 10111, and the size of the first potential voltage is V W1(1) , which is equivalent to providing binary data 1 for the same gate or operation through the third word line 10111, the second potential voltage is applied to the second word line 10110, and the size of the second potential voltage is V W1(0), the third potential voltage is applied to the first word line 1019 and the second word line 10110, at this time, the first readout amplifier 102 can read data from the first synapse string 1011 and output first operation data, the first operation data is binary data 0, the second readout amplifier 103 can read data from the second synapse string 1012 and output second operation data, the second operation data is binary data 0, then the first operation data and the second operation data are subjected to NAND logic operation to obtain result data, the result data is binary data 1, that is, the XOR operation of binary data 1 and binary data 1 is realized by NAND flash.

[0070] In some embodiments, before the step S1 is performed, a threshold voltage setting step is further included, the first data and the second data are both binary data, when the first data is binary data 1 and the second data is binary data 0, the threshold voltage setting step includes: setting the threshold voltage of the first storage unit as a first threshold voltage, setting the threshold voltage of the second storage unit as a second threshold voltage, and setting the threshold voltage of the remaining storage units as the first threshold voltage, wherein the first threshold voltage is less than the second threshold voltage.

[0071] In some embodiments, before the step S1 is performed, a threshold voltage setting step is further included, the first data and the second data are both binary data, when the first data is binary data 0 and the second data is binary data 1, the threshold voltage setting step includes: setting the threshold voltage of the second storage unit as a first threshold voltage, setting the threshold voltage of the first storage unit as a second threshold voltage, and setting the threshold voltage of the remaining storage units as the first threshold voltage, wherein the first threshold voltage is less than the second threshold voltage.

[0072] In some embodiments, the result data is obtained according to at least one of the first operation data and the second operation data, including: performing AND logic operation or NAND logic operation on the first operation data and the second operation data to obtain the result data.

[0073] Figure 6 The threshold voltage distribution diagram in the third embodiment of the present application is shown in the figure. Figure 4 , in which L / 1 represents the first threshold voltage distribution curve, 0 represents the second threshold voltage distribution curve, V W1(1) represents the voltage when binary data 1 is inputted, W1(0) represents the voltage when binary data 0 is inputted.

[0074] Referring to Figure 6 and Figure 4, the first data is binary data 0, the second data is binary data 1, and the remaining storage units of the first synaptic string 1011 and the second synaptic string 1012 are not written with data. Wherein, the first storage unit of the first synaptic string 1011 is the first storage unit, and the second storage unit of the second synaptic string 1012 is the second storage unit. The threshold voltage of the first storage unit is set as the second threshold voltage, the threshold voltage of the second storage unit is set as the first threshold voltage, and the threshold voltage of the remaining storage units of the first synaptic string 1011 and the second synaptic string 1012 is set as the first threshold voltage. A first potential voltage is applied to the first word line 1019, and the size of the first potential voltage is V W1(0) , which is equivalent to providing binary data 0 for the NAND operation through the first word line 1019, a second potential voltage is applied to the second word line 10110, and the size of the second potential voltage is V W1(1) At this time, the first readout amplifier 102 can read data from the first synaptic string 1011 and output first operation data, the first operation data is binary data 1, and the second readout amplifier 103 can read data from the second synaptic string 1012 and output second operation data, the second operation data is binary data 1, then the first operation data and the second operation data are subjected to AND logic operation to obtain result data, the result data is binary data 1, that is, the NAND flash realizes the XOR operation of binary data 0 and binary data 0.

[0075] Figure 6 It is a threshold voltage distribution diagram in some embodiments of the present application. Referring to Figure 7 , in the figure, L / 1 represents the first threshold voltage distribution curve, 0 represents the second threshold voltage distribution curve, V W1(1) represents the voltage when inputting binary data 1, and V W1(0) represents the voltage when inputting binary data 0.

[0076] Referring to Figure 7 and Figure 4, the first data is binary data 0, the second data is binary data 1, and the remaining storage units of the first synaptic string 1011 and the second synaptic string 1012 are not written with data. Wherein, the first storage unit of the first synaptic string 1011 is the first storage unit, and the second storage unit of the second synaptic string 1012 is the second storage unit. The threshold voltage of the first storage unit is set to the second threshold voltage, the threshold voltage of the second storage unit is set to the first threshold voltage, and the threshold voltage of the remaining storage units of the first synaptic string 1011 and the second synaptic string 1012 is set to the first threshold voltage. A first potential voltage is applied to the first word line 1019, and the size of the first potential voltage is V W1(0) , which is equivalent to providing binary data 0 for the AND operation through the first word line 1019, and a second potential voltage is applied to the second word line 10110, and the size of the second potential voltage is V W1(1) . With respect to the threshold distribution shown in Figure 7 , if the result of the first readout amplifier 102 is reversed, the first operation data is binary data 0, and the second operation data is binary data 1, then the NAND logic operation is performed on the first operation data and the second operation data to obtain the result data, and the result data is binary data 1.

[0077] Referring to Figure 9 and Figure 9 , the first data is written to the first storage unit of the first synaptic string 1011, the first data is binary data 1, the second data is written to the second storage unit of the second synaptic string 1012, the second data is binary data 0, and the remaining storage units of the first synaptic string 1011 and the second synaptic string 1012 are not written with data. Wherein, the first storage unit of the first synaptic string 1011 is the first storage unit, and the second storage unit of the second synaptic string 1012 is the second storage unit. The threshold voltage of the first storage unit is set to the first threshold voltage, the threshold voltage of the second storage unit is set to the second threshold voltage, and the threshold voltage of the remaining storage units of the first synaptic string 1011 and the second synaptic string 1012 is set to the first threshold voltage. A first potential voltage is applied to the first word line 1019, and the size of the first potential voltage is V W1(1) , which is equivalent to providing binary data 1 for the AND operation through the first word line 1019, and a second potential voltage is applied to the second word line 10110, and the size of the second potential voltage is V W1(0)At this time, the first read amplifier 102 can read data from the first synapse string 1011 and output first operation data, the first operation data is binary data 1, the second read amplifier 103 can read data from the second synapse string 1012 and output second operation data, the second operation data is binary data 1, and then the first operation data and the second operation data are subjected to AND logic operation to obtain result data, the result data is binary data 1, that is, the XOR operation of binary data 1 and binary data 1 is realized through the NAND flash memory.

[0078] Referring to Figure 4 and Figure 9 , the first data is written into the first memory cell of the first synapse string 1011, the first data is binary data 1, the second data is written into the second memory cell of the second synapse string 1012, the second data is binary data 0, and the remaining memory cells of the first synapse string 1011 and the remaining memory cells of the second synapse string 1012 are not written with data. Wherein, the first memory cell of the first synapse string 1011 is the first memory cell, and the second memory cell of the second synapse string 1012 is the second memory cell. The threshold voltage of the first memory cell is set as the first threshold voltage, the threshold voltage of the second memory cell is set as the second threshold voltage, and the threshold voltage of the remaining memory cells of the first synapse string 1011 and the remaining memory cells of the second synapse string 1012 is set as the first threshold voltage. The first potential voltage is applied to the first word line 1019, the size of the first potential voltage is V W1(1) , which is equivalent to providing binary data 1 for performing NAND operation through the first word line 1019, the second potential voltage is applied to the second word line 10110, the size of the second potential voltage is V W1(0) . With respect to the threshold distribution shown in Figure 7 , if the result of the second read amplifier 103 is reversed, the first operation data is binary data 1, the second operation data is binary data 0, and then the first operation data and the second operation data are subjected to NAND logic operation to obtain result data, the result data is binary data 1.

[0079] Referring to Figure 4 and Figure 7, the first data is binary data 1, the second data is binary data 0, and the remaining storage units of the first synaptic string 1011 and the second synaptic string 1012 are not written with data. Wherein the first storage unit of the first synaptic string 1011 is the first storage unit, and the second storage unit of the second synaptic string 1012 is the second storage unit. The threshold voltage of the first storage unit is set to the first threshold voltage, the threshold voltage of the second storage unit is set to the second threshold voltage, and the threshold voltage of the remaining storage units of the first synaptic string 1011 and the second synaptic string 1012 is set to the first threshold voltage. A first potential voltage is applied to the first word line 1019, and the size of the first potential voltage is V W1(0) , which is equivalent to providing binary data 0 for NAND operation through the first word line 1019, a second potential voltage is applied to the second word line 10110, and the size of the second potential voltage is V W1(1) At this time, the first readout amplifier 102 can read data from the first synaptic string 1011 and output first operation data, the first operation data is binary data 1, and the second readout amplifier 103 can read data from the second synaptic string 1012 and output second operation data, the second operation data is binary data 0, then the first operation data and the second operation data are subjected to AND logic operation to obtain result data, the result data is binary data 0, that is, the NAND flash realizes the XOR operation of binary data 0 and binary data 1.

[0080] Referring to Figure 4 and Figure 9 , the first data is binary data 1, the second data is binary data 0, and the remaining storage units of the first synaptic string 1011 and the second synaptic string 1012 are not written with data. Wherein the first storage unit of the first synaptic string 1011 is the first storage unit, and the second storage unit of the second synaptic string 1012 is the second storage unit. The threshold voltage of the first storage unit is set to the first threshold voltage, the threshold voltage of the second storage unit is set to the second threshold voltage, and the threshold voltage of the remaining storage units of the first synaptic string 1011 and the second synaptic string 1012 is set to the first threshold voltage. A first potential voltage is applied to the first word line 1019, and the size of the first potential voltage is V W1(0), which is equivalent to providing binary data 0 for the NOR operation through the first word line 1019, applying a second potential voltage to the second word line 10110, the size of the second potential voltage is V W1(1) . With respect to the threshold distribution shown in Figure 7 , if the result of the second readout amplifier 103 is reversed, the first operation data is binary data 1, and the second operation data is binary data 1, then the NAND logic operation is performed on the first operation data and the second operation data to obtain the result data, which is binary data 0.

[0081] Referring to Figure 4 and Figure 7 , the first data is written to the first storage unit of the first synaptic string 1011, the first data is binary data 0, the second data is written to the second storage unit of the second synaptic string 1012, the second data is binary data 1, and the remaining storage units of the first synaptic string 1011 and the remaining storage units of the second synaptic string 1012 are not written data. Among them, the first storage unit of the first synaptic string 1011 is the first storage unit, and the second storage unit of the second synaptic string 1012 is the second storage unit. The threshold voltage of the first storage unit is set to the second threshold voltage, the threshold voltage of the second storage unit is set to the first threshold voltage, and the threshold voltage of the remaining storage units of the first synaptic string 1011 and the remaining storage units of the second synaptic string 1012 is set to the first threshold voltage. A first potential voltage is applied to the first word line 1019, the size of the first potential voltage is V W1(1) , which is equivalent to providing binary data 1 for the NOR operation through the first word line 1019, applying a second potential voltage to the second word line 10110, the size of the second potential voltage is V W1(0) At this time, the first readout amplifier 102 can read data from the first synaptic string 1011 and output the first operation data, which is binary data 0, and the second readout amplifier 103 can read data from the second synaptic string 1012 and output the second operation data, which is binary data 1, and then the NAND logic operation is performed on the first operation data and the second operation data to obtain the result data, which is binary data 0, that is, the NOR operation of binary data 1 and binary data 0 is realized through the NAND flash memory.

[0082] Referring to Figure 4 and Figure 9The first data is written into the first memory cell of the first synapse string 1011, the first data is binary data 0, the second data is written into the second memory cell of the second synapse string 1012, the second data is binary data 1, and the remaining memory cells of the first synapse string 1011 and the remaining memory cells of the second synapse string 1012 are not written with data. The first memory cell of the first synapse string 1011 is the first memory cell, and the second memory cell of the second synapse string 1012 is the second memory cell. The threshold voltage of the first memory cell is set as the second threshold voltage, the threshold voltage of the second memory cell is set as the first threshold voltage, and the threshold voltage of the remaining memory cells of the first synapse string 1011 and the remaining memory cells of the second synapse string 1012 is set as the first threshold voltage. A first potential voltage is applied to the first word line 1019, and the size of the first potential voltage is V W1(1) , which is equivalent to providing binary data 1 for the AND operation through the first word line 1019. A second potential voltage is applied to the second word line 10110, and the size of the second potential voltage is V W1(0) . With respect to the threshold distribution shown in Figure 7 , if the result of the first readout amplifier 102 is reversed, the first operation data is binary data 1, and the second operation data is binary data 1, then the NAND logic operation is performed on the first operation data and the second operation data to obtain the result data, and the result data is binary data 0.

[0083] In some embodiments of the present application, the threshold distribution as shown in Figure 4 and Figure 7 Figure 4 Figure 9 Figure 7 Figure 5 Figure 7 is used, each readout amplifier is connected to multiple memory blocks, and steps S1 to S3 are performed in different memory blocks. At this time, the current read by the corresponding readout amplifier is the cumulative current, that is, each binary data 1 corresponds to a current, and the current can be converted to digital by an analog-to-digital converter. The number of binary data 1 in the first operation data and the number of binary data 1 in the second operation data can be obtained, and the difference between the total number of first data written and the number of binary data 1 is the number of binary data 0.

[0084] Although the embodiments of the present application have been described in detail above, it is obvious to those skilled in the art that various modifications and changes can be made to these embodiments. However, it should be understood that such modifications and changes are within the scope and spirit of the present application as described in the claims. Moreover, the present application described herein can have other embodiments, and can be implemented or realized in various ways.

Claims

1. A control method for implementing XOR operation in NAND flash memory, characterized in that, Includes the following steps: S0: Provide NAND flash memory, the NAND flash memory including at least one memory block and several sense amplifiers, the memory block including several synapse strings, several bit lines and several word lines, the synapse strings including several memory cells connected in series, the synapse strings and the bit lines are connected one-to-one, the word lines are all connected to all the synapse strings, and the sense amplifiers are connected one-to-one to the bit lines. S1: In the same storage block, any of the synaptic strings is selected as the first synaptic string, any of the remaining synaptic strings is selected as the second synaptic string, any storage unit in the first synaptic string is selected as the first storage unit, any storage unit in the second synaptic string is selected as the second storage unit, first data is written to the first storage unit, and second data is written to the second storage unit. The word lines connected to the first storage unit and the word lines connected to the second storage unit are different, and the first data and the second data are inverse data of each other. S2: Apply a first potential voltage to the word line connected to the first memory cell, and apply a second potential voltage to the word line connected to the second memory cell, wherein the first potential voltage and the second potential voltage are different; S3: Read data from the first synaptic string through the corresponding readout amplifier and output the first operation data; read data from the second synaptic string through the corresponding readout amplifier and output the second operation data; S4: Obtain result data based on at least one of the first operation data and the second operation data.

2. The control method for implementing XOR operation in NAND flash memory according to claim 1, characterized in that, Before performing step S1, a threshold voltage setting step is also included. Both the first data and the second data are binary data. When the first data is binary data 1 and the second data is binary data 0, the threshold voltage setting step includes: The threshold voltage of the first memory cell is set as the first threshold voltage, the threshold voltage of the second memory cell is set as the second threshold voltage, and the threshold voltage of the remaining memory cells is set as the third threshold voltage, wherein the third threshold voltage is less than the first threshold voltage, and the first threshold voltage is less than the second threshold voltage. When the first data is binary data 0 and the second data is binary data 1, the threshold voltage setting step includes: The threshold voltage of the second memory cell is set as the first threshold voltage, the threshold voltage of the first memory cell is set as the second threshold voltage, and the threshold voltage of the remaining memory cells is set as the third threshold voltage, wherein the third threshold voltage is less than the first threshold voltage, and the first threshold voltage is less than the second threshold voltage.

3. The control method for implementing XOR operation in NAND flash memory according to claim 2, characterized in that, The first potential voltage is greater than the third threshold voltage and less than the first threshold voltage; the second potential voltage is greater than the first threshold voltage and less than the second threshold voltage; or, the second potential voltage is greater than the third threshold voltage and less than the first threshold voltage; and the first potential voltage is greater than the first threshold voltage and less than the second threshold voltage.

4. The control method for implementing XOR operation in NAND flash memory according to claim 2, characterized in that, Step S1 further includes: Write first data or second data to the remaining storage units of the first synaptic string, write first data or second data to the remaining storage units of the second synaptic string, and in the first synaptic string and the second synaptic string, at least one of the two storage units connected by a word line does not store data.

5. The control method for implementing XOR operation in NAND flash memory according to claim 4, characterized in that, Step S2 further includes: applying a third potential voltage to the remaining word lines, the third potential voltage being different from the first potential voltage and the second potential voltage.

6. The control method for implementing XOR operation in NAND flash memory according to claim 5, characterized in that, The first potential voltage is greater than the third threshold voltage and less than the first threshold voltage; the second potential voltage is greater than the first threshold voltage and less than the second threshold voltage; the third potential voltage is greater than the second threshold voltage; or, the second potential voltage is greater than the third threshold voltage and less than the first threshold voltage; the first potential voltage is greater than the first threshold voltage and less than the second threshold voltage; and the third potential voltage is greater than the second threshold voltage.

7. The control method for implementing XOR operation in NAND flash memory according to any one of claims 2 to 6, characterized in that, The step of obtaining result data based on at least one of the first calculation data and the second calculation data includes: Perform NOR, OR, AND, or NAND operations on the first and second operational data to obtain the result data.

8. The control method for implementing XOR operation in NAND flash memory according to claim 1, characterized in that, Before performing step S1, a threshold voltage setting step is also included. Both the first data and the second data are binary data. When the first data is binary data 1 and the second data is binary data 0, the threshold voltage setting step includes: The threshold voltage of the first memory cell is set as a first threshold voltage, the threshold voltage of the second memory cell is set as a second threshold voltage, and the threshold voltage of the remaining memory cells is set as a first threshold voltage, wherein the first threshold voltage is less than the second threshold voltage.

9. The control method for implementing XOR operation in NAND flash memory according to claim 1, characterized in that, Before performing step S1, a threshold voltage setting step is also included. Both the first data and the second data are binary data. When the first data is binary data 0 and the second data is binary data 1, the threshold voltage setting step includes: The threshold voltage of the second memory cell is set to the first threshold voltage, the threshold voltage of the first memory cell is set to the second threshold voltage, and the threshold voltage of the remaining memory cells is set to the first threshold voltage, wherein the first threshold voltage is less than the second threshold voltage.

10. The control method for implementing XOR operation in NAND flash memory according to claim 8 or 9, characterized in that, The step of obtaining result data based on at least one of the first calculation data and the second calculation data includes: Perform AND or NAND logical operations on the first and second operation data to obtain the result data.

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