High-reliability, low-cost, fast read-write OTP memory and data read-write method

Abstract

A high-reliability, low-cost, fast read / write OTP memory and data read / write method, relating to integrated circuit technology, comprises an array of M×N antifuse memory modules, where M and N are both integers greater than 2. Each antifuse memory module includes a first storage unit and a second storage unit, the second storage unit comprising a second selection MOS transistor, a second isolation MOS transistor, a second gate capacitor, and a second detection MOS transistor. One active terminal of the second selection MOS transistor is connected to the first column line of its column, and the other active terminal is connected to the gate terminal of the second detection MOS transistor. One active terminal of the second detection MOS transistor is connected to the first column line, and the other active terminal is connected to the second column line. The gate terminal is connected to the active terminal of the second gate capacitor via a second isolation MOS transistor. The gate capacitor comprises a gate plate, an active region, and a gate oxide layer therebetween. The present invention fundamentally overcomes misreading caused by charge crosstalk.

Description

Technical Field

[0001] The present invention relates to integrated circuit technology, and in particular to memory technology. Background Art

[0002] US Patent No. 8780660 and Chinese Patent Application No. 201310119745.5 disclose XPM memory technology. Figure 1 The drawback is that

[0003] a1. When data is written (prog), the voltage of WL (WP) needs to pass through the level shift high-voltage switch circuit of the peripheral circuit to provide the breakdown voltage Vpp (8-9V, under 0.18um process) to the selected WL and the voltage Vdd (3-4V) to the unselected WL, resulting in a complex circuit and a large area.

[0004] a2. Based on the Vpp / Vdd switching circuit of the above WL, the CP (charge pump) needs to be turned off and then on before and after changing the programming address, which wastes time and power consumption.

[0005] a3. Each WL requires an independent poly line, which results in an excessively large memory array area.

[0006] a4. Read detection requires two NMOS devices to prevent read data errors caused by charge crosstalk during read operations.

[0007] US Patent No. 10504908 discloses the second prior art, see Figure 2 , and its operating voltage table is shown in Table 1.

[0008] Table 1

[0009]

[0010] Its disadvantages are:

[0011] b1. During data writing (prog), the voltage of the WL (WP) needs to change from 5.5V (Vpp) to 2.5V (Vdd). This requires a peripheral circuit's level shift high-voltage switch circuit to provide Vpp (5V, 0.11um process) to the selected WL and Vdd (2.5V) to the unselected WL. This circuit is complex and large in area.

[0012] b2. Based on the Vpp / Vdd switching circuit of the above WL, the CP (charge pump) needs to be turned off and then on before and after changing the programming address, which wastes time and power.

[0013] b3. Each WL requires an independent poly line, resulting in an excessively large storage array area.

[0014] b4. The sensing device consists of only one NMOS device (Mms). During a read operation, voltage variations on Vwp and Vws can easily couple to the gate of the sense device (Mms), causing it to erroneously turn on and thus cause data read errors. To avoid misreading, a series NMOS device (such as Twr in the first prior art) is added to prevent charge crosstalk during the read operation and the resulting read errors.

[0015] Interpretation:

[0016] Prog: Programming (writing data)

[0017] Read:

[0018] SXSY: Select X, Select Y (row selected, column selected)

[0019] SXUY: Select X, not Y (row selected, column unselected)

[0020] UXSY: Unselect X, select Y (row unselected, column selected)

[0021] UXUY: Unselect X, Unselect Y (row unselected, column unselected)

[0022] WS(X): WS line of row x

[0023] BL(Y): BL line of column Y

[0024] Vrd: read voltage

[0025] dVox: voltage difference across the gate capacitance

[0026] Vpp: programming voltage

[0027] Float: Floating

[0028] Sense: Detection

[0029] Pulse Summary of the Invention

[0030] The technical problem to be solved by the present invention is to provide a fast read and write OTP embedded memory with high reliability and low cost, and the characteristics of power saving, time saving and small area.

[0031] The technical solution adopted by the present invention to solve the above technical problems is to provide a highly reliable, low-cost, fast read-write OTP memory, comprising an array consisting of M×N anti-fuse storage modules, where M and N are both integers greater than 2, and each anti-fuse storage module comprises a first storage unit and a second storage unit.

[0032] The first storage unit is composed of a first gate capacitor, a first isolation MOS transistor, a first selection MOS transistor, and a first detection MOS transistor. One active end of the first selection MOS transistor is connected to the first column line of the column in which it is located, and the other active end is connected to the gate end of the first detection MOS transistor. One active end of the first detection MOS transistor is connected to the first column line, and the other active end is connected to the second column line. The gate end is connected to the active end of the first gate capacitor through the first isolation MOS transistor.

[0033] The second storage unit is composed of a second gate capacitor, a second isolation MOS transistor, a second selection MOS transistor, and a second detection MOS transistor. One active end of the second selection MOS transistor is connected to the first column line of the column in which it is located, and the other active end is connected to the gate end of the second detection MOS transistor. One active end of the second detection MOS transistor is connected to the first column line, and the other active end is connected to the second column line. The gate end is connected to the active end of the second gate capacitor through the second isolation MOS transistor.

[0034] The gate capacitor is composed of a gate plate, an active area and a gate oxide layer therebetween;

[0035] The gate terminal of the first gate capacitor and the gate terminal of the second gate capacitor are connected to a common row line (WL);

[0036] The gate end of the first selection MOS transistor is connected to the first row line of the row;

[0037] The gate end of the first isolation MOS transistor is connected to the second row line of the row;

[0038] The gate end of the second selection MOS transistor is connected to the third row line of the row where it is located;

[0039] The gate end of the second isolation MOS transistor is connected to the fourth row line of the row where it is located.

[0040] Furthermore, the public lines are connected to each other.

[0041] The present invention also provides a method for reading and writing data of the aforementioned high-reliability, low-cost, fast-reading and writing OTP embedded memory.

[0042] The writing steps include:

[0043] (p1) access breakdown level to the common row line (WL);

[0044] (p2) A voltage level sufficient to turn on the isolation MOS transistor and prevent the gate dielectric from being broken down is connected to the row line connected to the gate terminal of the write target memory cell; typically Vpp / 2 or Vdd.

[0045] (p3) A voltage level (Vcc) sufficient to turn on the select MOS transistor in the write target memory cell is connected to the row line connected to the gate terminal of the select MOS transistor, and the other row lines are grounded.

[0046] (p4) The first column line and the second column line of the column where the write target memory cell is located are connected to the ground level, and the column lines not connected to the write target memory cell are connected to the high level or left floating.

[0047] The reading steps include:

[0048] (r1) Access the read level to the common row line (WL);

[0049] (r2) connecting a read voltage level to the row line connected to the gate terminal of the isolation MOS transistor in the read target memory cell;

[0050] (r3) connecting the row line connected to the gate terminal of the select MOS tube in the read target memory cell to the read voltage level;

[0051] (r4) The first column line of the column where the read target memory cell is located is grounded, and the first column line not connected to the read target memory cell is connected to a read level or is left floating;

[0052] (r5) The second column line not connected to the read target memory cell is connected to the read level or is left floating;

[0053] (r6) Detect the level of the second column line connected to the read target storage unit to realize data reading.

[0054] The present invention adds an isolation MOS transistor between the read / write gate capacitor and the select MOS transistor. Its function is to isolate the VPP high voltage during write operations and to select the target memory cell during read operations. The isolation MOS transistor can be a LV (1.8V) or 3.3V IO NMOS device.

[0055] All WLs can be connected to a common voltage: VPP during writing and Vrd during reading. This allows two adjacent WLs to share a single polysilicon line, reducing the area of ​​the memory array.

[0056] During the read operation, WLS and WS use complementary switches (see Table 2), so that the detection circuit only needs one NMOS device (two NMOS devices are required in the first prior art), which can ensure that the problem of charge crosstalk does not occur.

[0057] During write operations, all WLs are connected to Vpp, and there is no need to change the voltage when changing the address. Therefore, the peripheral address decoding circuit does not require a complex high-voltage switching circuit (level shift), which greatly reduces the area of ​​the memory peripheral circuit, greatly saves the time for the CP voltage to ramp up and down, and saves power consumption.

[0058] Compared to the prior art, the present invention uses a single isolation MOS transistor to achieve two functions: (1) voltage division protection during write operations, and (2) eliminating gate charge interference on the select MOS transistor during read operations, thus preventing the generation of false read currents. During read operations, WLS = 0V and WS = Vrd on the UXSY unit, which drives the gate voltage of the detection MOS transistor to 0V, effectively preventing false read currents on the BL. Compared to the first prior art solution that uses a single Twr transistor, the present invention omits the Twr transistor.

[0059] The second prior art uses independent WL lines, while the present invention uses shared WL lines, resulting in a smaller footprint. Furthermore, the present invention employs different read voltages to fundamentally overcome misreading caused by charge crosstalk. Using different write voltages eliminates the need for Vpp level conversion circuits in peripheral circuits, saving area. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] Figure 1 It is a circuit diagram of the first prior art.

[0061] Figure 2 It is a circuit diagram of the second prior art.

[0062] Figure 3 It is a circuit diagram of the present invention. DETAILED DESCRIPTION

[0063] Description of reference numerals:

[0064] WL: Public Line

[0065] Ws11: The first line in the first row

[0066] WLs11: Second line in the first line

[0067] WLs12: The third line in the first row

[0068] Ws12: The fourth line in the first row

[0069] Ws21: First line in the second row

[0070] WLs21: The second line in the second row

[0071] WLs22: Third line in the second row

[0072] Ws22: The fourth line in the second row

[0073] BL: First column line

[0074] BR: Second column line

[0075] A first selection MOS transistor 211, a first isolation MOS transistor 212, a first gate capacitor 213, and a first detection MOS transistor 214;

[0076] A second gate capacitor 223, a second isolation MOS transistor 222, a second selection MOS transistor 221, and a first detection MOS transistor 224;

[0077] The “active end” referred to in the present invention refers to the circuit connection end of the active region. The source end and the drain end of the MOS transistor are collectively referred to as the active end.

[0078] The present invention includes an array consisting of M×N antifuse memory modules, where M and N are both integers greater than 4. Figure 3 An array of 2×4 antifuse memory modules (2 rows and 4 columns) is shown, and the portion within the elliptical area is an antifuse memory module.

[0079] Each antifuse memory module includes a first memory cell and a second memory cell.

[0080] A storage unit consists of a selection MOS tube, an isolation MOS tube, a gate capacitor and a detection MOS tube.

[0081] Taking the first storage unit where the first gate capacitor 213 is located as an example, one active end of the first selection MOS transistor 211 is connected to the first column line BL4 of the column where it is located, and the other active end is connected to the active end of the first gate capacitor 213 through the first isolation MOS transistor 212; one active end of the first detection MOS transistor 214 is connected to the first column line BL4 of the column where it is located, and the other active end is connected to the second column line BR4. The same is true for the second storage unit where the second gate capacitor 223 is located, see Figure 3 .

[0082] The gate end of the first gate capacitor 213 and the gate end of the second gate capacitor 223 are connected to the common row line WL1 of the anti-fuse memory module;

[0083] The gate end of the first selection MOS transistor 211 is connected to the first row wire Ws11 of the row;

[0084] The gate end of the first isolation MOS transistor 212 is connected to the second row line WLs11 of the row;

[0085] The gate terminal of the second isolation MOS transistor 222 is connected to the third row line WLs12 of the row where it is located;

[0086] The gate terminal of the second selection MOS transistor 221 is connected to the fourth row wire Ws12 of the row where it is located.

[0087] Figure 3In the example, WL1 is a common row line connected to the anti-fuse memory modules of the first row, and WL2 is a common row line connected to the anti-fuse memory modules of the second row. If there are more rows, each row has a common row line. As a preferred method, the common row lines of each row are connected to each other, or are connected to a common connection point, for example Figure 3 WL1 and WL2 in the circuit are connected together. This method can simplify the external circuit.

[0088] The operating voltage table for this embodiment is shown in Table 2, where Vpp = 8V, Vdd = 3.3V, Vcc = 1.8V, Vrd <= Vcc, and the symbol " / " represents "or." X and Y represent sequence numbers (row and column numbers). Compared to Table 1, the voltage of WL remains stable during the write process and the read process, saving external circuit area.

[0089] Table 2

[0090]

[0091] The above operating voltage table shows the memory read and write method of the present invention, which specifically includes the following steps:

[0092] The writing steps include:

[0093] (p1) access breakdown level for common row line;

[0094] (p2) connecting the row line connected to the gate terminal of the isolation MOS transistor in the write target memory cell to a voltage level sufficient to turn on the isolation MOS transistor;

[0095] (p3) A voltage level sufficient to turn on the select MOS transistor in the write target memory cell is connected to the row line connected to the gate terminal of the select MOS transistor, and the other row lines are grounded;

[0096] (p4) The first column line and the second column line of the column where the write target memory cell is located are connected to the ground level, and the column lines not connected to the write target memory cell are connected to the high level or left floating.

[0097] The reading steps include:

[0098] (r1) Access the read level to the common row line;

[0099] (r2) connecting a read voltage level to the row line connected to the gate terminal of the isolation MOS transistor in the read target memory cell;

[0100] (r3) connecting the row line connected to the gate terminal of the select MOS tube in the read target memory cell to the read voltage level;

[0101] (r4) The first column line of the column where the read target memory cell is located is grounded, and the first column line not connected to the read target memory cell is connected to a read level or is left floating;

[0102] (r5) The second column line not connected to the read target memory cell is connected to the read level or is left floating;

[0103] (r6) Detect the level of the second column line connected to the read target storage unit to realize data reading.

[0104] Compared with Table 1, the present invention does not need to frequently switch the WL voltage, and can save an external decoder circuit.

Claims

1. A highly reliable, low-cost, fast read / write OTP memory, comprising an array of M×N antifuse memory modules, where M and N are both integers greater than 2, characterized in that: Each antifuse memory module includes a first memory cell and a second memory cell. The first storage unit is composed of a first selection MOS transistor, a first isolation MOS transistor, a first gate capacitor, and a first detection MOS transistor. One active end of the first selection MOS transistor is connected to the first column line of the column in which it is located, and the other active end is connected to the gate end of the first detection MOS transistor. One active end of the first detection MOS transistor is connected to the first column line, and the other active end is connected to the second column line. The gate end is connected to the active end of the first gate capacitor through the first isolation MOS transistor. The second storage unit is composed of a second selection MOS transistor, a second isolation MOS transistor, a second gate capacitor, and a second detection MOS transistor. One active end of the second selection MOS transistor is connected to the first column line of the column in which it is located, and the other active end is connected to the gate end of the second detection MOS transistor. One active end of the second detection MOS transistor is connected to the first column line, and the other active end is connected to the second column line. The gate end is connected to the active end of the second gate capacitor through the second isolation MOS transistor. The gate capacitor is composed of a gate plate, an active area and a gate oxide layer therebetween; A gate terminal of the first gate capacitor and a gate terminal of the second gate capacitor are connected to a common row line; The gate end of the first selection MOS transistor is connected to the first row line of the row; The gate end of the first isolation MOS transistor is connected to the second row line of the row; The gate end of the second selection MOS transistor is connected to the third row line of the row where it is located; The gate end of the second isolation MOS transistor is connected to the fourth row line of the row where it is located.

2. The high-reliability, low-cost, fast read-write OTP memory according to claim 1, wherein: The public lines are connected to each other.

3. A highly reliable, low-cost, fast read and write method for OTP memory data writing, characterized in that: The highly reliable, low-cost, fast-read-write OTP embedded memory comprises an array of M×N antifuse memory modules, where M and N are both integers greater than 2, and each antifuse memory module comprises a first storage unit and a second storage unit. The first storage unit is composed of a first selection MOS transistor, a first isolation MOS transistor, a first gate capacitor, and a first detection MOS transistor. One active end of the first selection MOS transistor is connected to the first column line of the column in which it is located, and the other active end is connected to the gate end of the first detection MOS transistor. One active end of the first detection MOS transistor is connected to the first column line, and the other active end is connected to the second column line. The gate end is connected to the active end of the first gate capacitor through the first isolation MOS transistor. The second storage unit is composed of a second selection MOS transistor, a second isolation MOS transistor, a second gate capacitor, and a second detection MOS transistor. One active end of the second selection MOS transistor is connected to the first column line of the column in which it is located, and the other active end is connected to the gate end of the second detection MOS transistor. One active end of the second detection MOS transistor is connected to the first column line, and the other active end is connected to the second column line. The gate end is connected to the active end of the second gate capacitor through the second isolation MOS transistor. The gate capacitor is composed of a gate plate, an active area and a gate oxide layer therebetween; A gate terminal of the first gate capacitor and a gate terminal of the second gate capacitor are connected to a common row line; The gate end of the first selection MOS transistor is connected to the first row line of the row; The gate end of the first isolation MOS transistor is connected to the second row line of the row; The gate end of the second selection MOS transistor is connected to the third row line of the row where it is located; The gate end of the second isolation MOS transistor is connected to the fourth row line of the row where it is located; The writing steps include: (p1) access breakdown level to the common row line (WL); (p2) connecting the row line connected to the gate terminal of the isolation MOS transistor in the write target memory cell to a voltage level sufficient to turn on the isolation MOS transistor; (p3) A voltage level sufficient to turn on the select MOS transistor in the write target memory cell is connected to the row line connected to the gate terminal of the select MOS transistor, and the other row lines are grounded; (p4) The first column line and the second column line of the column where the write target memory cell is located are connected to the ground level, and the column lines not connected to the write target memory cell are connected to the high level or left floating.

4. A highly reliable, low-cost, fast read-write OTP memory data reading method, characterized in that: The highly reliable, low-cost, fast-read-write OTP embedded memory comprises an array of M×N antifuse memory modules, where M and N are both integers greater than 2, and each antifuse memory module comprises a first storage unit and a second storage unit. The first storage unit is composed of a first selection MOS transistor, a first isolation MOS transistor, a first gate capacitor, and a first detection MOS transistor. One active end of the first selection MOS transistor is connected to the first column line of the column in which it is located, and the other active end is connected to the gate end of the first detection MOS transistor. One active end of the first detection MOS transistor is connected to the first column line, and the other active end is connected to the second column line. The gate end is connected to the active end of the first gate capacitor through the first isolation MOS transistor. The second storage unit is composed of a second selection MOS transistor, a second isolation MOS transistor, a second gate capacitor, and a second detection MOS transistor. One active end of the second selection MOS transistor is connected to the first column line of the column in which it is located, and the other active end is connected to the gate end of the second detection MOS transistor. One active end of the second detection MOS transistor is connected to the first column line, and the other active end is connected to the second column line. The gate end is connected to the active end of the second gate capacitor through the second isolation MOS transistor. The gate capacitor is composed of a gate plate, an active area and a gate oxide layer therebetween; A gate terminal of the first gate capacitor and a gate terminal of the second gate capacitor are connected to a common row line; The gate end of the first selection MOS transistor is connected to the first row line of the row; The gate end of the first isolation MOS transistor is connected to the second row line of the row; The gate end of the second selection MOS transistor is connected to the third row line of the row where it is located; The gate end of the second isolation MOS transistor is connected to the fourth row line of the row where it is located; The reading steps include: (r1) Access the read level to the common row line; (r2) connecting a read voltage level to the row line connected to the gate terminal of the isolation MOS transistor in the read target memory cell; (r3) connecting the row line connected to the gate terminal of the select MOS tube in the read target memory cell to the read voltage level; (r4) The first column line of the column where the read target memory cell is located is grounded, and the first column line not connected to the read target memory cell is connected to a read level or is left floating; (r5) The second column line not connected to the read target memory cell is connected to the read level or is left floating; (r6) Detect the level of the second column line connected to the read target storage unit to realize data reading.

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