Sigma-delta analog-to-digital converter circuit using data sharing for energy saving

Abstract

Embodiments of the present disclosure relate to sigma-delta analog-to-digital converter circuits utilizing data sharing for energy saving. A continuous-time sigma-delta analog-to-digital converter circuit includes a sigma-delta modulator circuit configured to receive an analog input signal. A single-bit quantizer of the modulator generates a digital output signal at a sampling frequency. A data storage circuit stores bits of the digital output signal, and a digital-to-analog converter (DAC) element is actuated in response to the stored bits to generate an analog feedback signal for comparison with the analog input signal. A filter circuit includes multiple-signal processing paths and a summing circuit configured to sum outputs from the multiple-signal processing paths to generate a converted output signal. A fanout circuit selectively applies the stored bits from the data storage circuit to inputs of the multiple-signal processing paths of the filter circuit.

Description

[0001] priority

[0002] This application claims priority to U.S. Provisional Application No. 63 / 247,896, filed September 24, 2021, the disclosure of which is incorporated herein by reference. Technical Field

[0003] The embodiments generally relate to analog-to-digital converter circuits, and more specifically, to Σ-Δ analog-to-digital converter circuits. Background Technology

[0004] Continuous-time (CT) Σ-Δ (ΣΔ) modulators are used to efficiently digitize a wide variety of analog signals. These modulators are suitable for many different applications. Due to their tolerance to component mismatch, ease of use of input circuitry, and inherent anti-aliasing filtering and noise shaping capabilities, CT ΣΔ modulators have become the circuit of choice for many designers requiring high dynamic range, medium to wide bandwidth data converters. In fact, with recent advancements in faster CMOS technology and design innovations such as better architectures and faster amplifiers, this option has become even more attractive. In this context, CT ΣΔ modulators now offer the best of both worlds: high resolution and high bandwidth.

[0005] Those skilled in the art recognize that high-performance CTΣΔ analog-to-digital converters (ADCs) suffer performance degradation due to feedback digital-to-analog converter (DAC) mismatch. Therefore, designers prefer to use single-bit quantization and single-bit DACs in the feedback loop that provides inherent linearity, whenever possible.

[0006] It should also be recognized that the CTΣΔ modulator will typically and preferably operate at very high frequencies. As a result, significant power consumption occurs in both the analog and digital circuitry sections. This power consumption increases exponentially with any increase in the quantizer sampling frequency as performance improves. Furthermore, designing the required higher complexity digital circuitry and analog-to-digital interfaces at these higher data rates becomes increasingly challenging.

[0007] Therefore, it is necessary to address the aforementioned and other issues related to high-speed, high-performance CTΣΔ analog-to-digital converters. Summary of the Invention

[0008] In one embodiment, a continuous-time Σ-Δ analog-to-digital converter circuit includes: a Σ-Δ modulator circuit configured to receive an analog input signal and including a single-bit quantizer configured to generate a digital output signal at a sampling frequency; and a single-bit digital-to-analog converter (DAC) circuit configured to process the digital output signal to generate an analog feedback signal for comparison with the analog input signal; wherein the single-bit DAC circuit includes: a plurality of flip-flops, series-coupled and configured to store bits of the digital output signal; and a plurality of single DAC elements controlled by the stored bits of the digital output signal output from the plurality of flip-flops; a polyphase filter circuit including a plurality of signal processing paths, wherein each signal processing path includes a polyphase filter bank, and wherein the outputs from the plurality of signal processing paths are summed to generate a converted output signal; and a fan-out circuit configured to selectively apply bits of the digital output signal output from the plurality of flip-flops to the inputs of the plurality of signal processing paths of the polyphase filter circuit.

[0009] In one embodiment, a continuous-time Σ-Δ analog-to-digital converter circuit includes: a Σ-Δ modulator circuit configured to receive an analog input signal and including: a single-bit quantizer configured to generate a digital output signal at a sampling frequency; a data storage circuit configured to store bits of the digital output signal; and a plurality of digital-to-analog converter (DAC) elements coupled to the data storage circuit and actuated in response to the stored bits to generate an analog feedback signal for comparison with the analog input signal; a filter circuit including a plurality of polyphase signal processing paths and a summing circuit configured to sum the outputs from the plurality of polyphase signal processing paths to generate a converted output signal; and a fan-out circuit configured to selectively apply the stored bits from the data storage circuit to the inputs of the plurality of polyphase signal processing paths of the filter circuit. Attached Figure Description

[0010] To better understand the embodiments, reference will now be made to the accompanying drawings by way of example only, wherein:

[0011] Figure 1 This is a block diagram of a Σ-Δ analog-to-digital converter circuit with single-bit quantization;

[0012] Figure 2 It is used for Figure 1 Block diagram of a single-bit finite impulse response digital-to-analog converter;

[0013] Figure 3 It is used for Figure 1 Block diagram of a digital filter circuit; and

[0014] Figure 4 This is a block diagram of an alternative embodiment for a Σ-Δ analog-to-digital converter circuit with single-bit quantization. Detailed Implementation

[0015] Figure 1 A time-domain block diagram of a Σ-Δ analog-to-digital converter circuit 10 is shown. Circuit 10 includes a second-order (by way of example only) Σ-Δ modulator circuit 12, having an output configured to receive an analog input signal A and an output configured to generate a digital output signal B consisting of a pulse density modulated pulse stream of 1-bit code. The instantaneous amplitude of the input signal A is represented by the ratio formed by dividing the count of the number of pulses in the pulse stream of signal B by the total number of samples of input signal A within a known time interval (set by the sampling rate fs). Circuit 10 also includes a digital filter circuit 14, which decimates and filters the pulses in the pulse stream of the digital output signal B to generate a K-bit digital signal C having a value corresponding to the amplitude of the analog input signal.

[0016] The second-order Σ-Δ modulator circuit 12 includes a first differential amplifier 20a (or summing circuit) having a first (non-inverting) input receiving an analog input signal A and a second (inverting) input receiving an analog feedback signal D. The first differential amplifier 20a outputs a first analog differential signal vdif1 in response to the difference between the analog input signal A and the analog feedback signal D (i.e., vdif1(t) = A(t) - D(t)). The first analog differential signal vdif1 is integrated by a first integrator circuit 22a to generate a first integral signal vint1, whose slope and amplitude depend on the sign and amplitude of the first analog differential signal vdif1. The second-order Σ-Δ modulator circuit 12 further includes a second differential amplifier 20b (or summing circuit) having a first (non-inverting) input receiving the first integral signal vint1 and a second (inverting) input receiving the analog feedback signal D. The second differential amplifier 20b outputs a second analog differential signal vdif2 in response to the difference between the first integral signal vint1 and the analog feedback signal D (i.e., vdif1(t) = vint1(t) - D(t)). The second analog differential signal vdif2 is integrated by a second integrator circuit 22b to generate a second integral signal vint2, which has a slope and amplitude that depend on the sign and amplitude of the second analog differential signal vdif2. A voltage comparator circuit 24 samples the second integral signal vint2 at a sampling rate fs in response to a sampling clock and compares each sample of the second integral signal vint2 with a reference signal vref to generate a corresponding single-bit pulse of a digital output signal B (if vint2 ≥ vref, the single bit has a first logical state, and if vint2 < vref, the single bit has a second logical state). The voltage comparator circuit 24 effectively operates as a single-bit quantization circuit. A single-bit digital-to-analog converter (DAC) circuit 26 in the feedback loop then converts the logical state of the digital output signal B to a corresponding analog voltage level for the analog feedback signal D.

[0017] A key feature of the Σ-Δ modulator circuit 12 is its ability to push quantization noise resulting from the operation of the quantization circuit 24 to higher frequencies away from the signal of interest. This is known in the art as noise shaping. A digital filter circuit 14 can then be implemented with low-pass filtering characteristics to substantially remove the high-frequency components of the shaped quantization noise.

[0018] Now refer to Figure 2 , which shows it being used as Figure 1A block diagram of a single-bit finite impulse response (FIR) digital-to-analog converter (DAC) circuit 30 in the feedback loop of the circuit shown. The FIR DAC circuit 30 includes an input 32 for receiving a bit sequence of the digital output signal B from the quantizer circuit 24. Multiple flip-flop circuits 34(1)-34(n) are cascaded in series and timed by a sampling clock at a sampling rate fs. The data input (D) of the first flip-flop circuit 34(1) is coupled to input 32, and the data output (Q) of the first flip-flop circuit 34(1) is coupled to the data input of the second flip-flop circuit 34(2). This series coupling of the flip-flop output to the input is repeated across the multiple flip-flop circuits 34(1)-34(n), with the data input (D) of the last flip-flop circuit 34(n) coupled to the data output (Q) of the penultimate flip-flop circuit. The value n can be any integer greater than or equal to 2. In one embodiment, n = 4, as shown in the figure. Figure 2 As shown.

[0019] The FIR DAC 30 also includes multiple single-bit digital-to-analog converter (DAC) elements 36(1)-36(n). The input of each DAC element 36 is coupled to receive the data output (Q) of the corresponding flip-flop circuit 34(1)-34(n). Thus, the input of the first DAC element 36(1) receives digital bits from the data output (Q) of the first flip-flop circuit 34(1), and so on. In this embodiment, each single-bit DAC element 36 is implemented, for example, as a digitally controlled unit element current source. The outputs from the DAC elements 36(1)-36(n) are summed at summation point 38 to generate an analog feedback signal D.

[0020] Now for reference Figure 3 The figure shows the use of Figure 1A block diagram of m groups of polyphase filters 40 of the digital filter circuit 14 shown in the circuit. The value m can be any integer greater than or equal to 2. In one embodiment, m = 4, 6, 8, or 10. Filter 40 includes input 42, which is configured to receive a bit sequence of digital output signal B from quantizer circuit 24. In a first signal processing path, bits of digital output signal B are decimated by factor M using decimation circuit 44 (1), wherein K bits of the decimated signal are processed by a first polyphase filter group 46 (1) having a transfer function E1(z) to generate bits at a rate fs / M. Digital output signal B is further delayed by one cycle of the sampling clock in delay circuit 48 and then processed in a second signal processing path, including decimation by factor M using decimation circuit 44 (2), wherein bits of the decimated signal are processed by a second polyphase filter group 46 (2) having a transfer function E2(z) to generate bits at a rate fs / M. The delayed signal is then further delayed by one cycle of the sampling clock in delay circuit 50, and then processed in the third signal processing path, including decimation by a factor of M using decimation circuit 44(3), wherein the bits of the decimated signal are processed by a third polyphase filter bank 46(3) with a transfer function of E3(z) to generate bits at a rate of fs / M. This arrangement is repeated as needed according to the filter stage order until the m-th stage where delay circuit 52 applies a delay of one cycle of the sampling clock, and the delayed signal is processed in the m-th signal processing path, including decimation by a factor of M using decimation circuit 44(m), wherein the bits of the decimated signal are processed by a third polyphase filter bank 46(3) with a transfer function of E3(z) to generate bits at a rate of fs / M. m (z) The m-th polyphase filter bank 46(m) of the transfer function is processed to generate bits at a rate fs / M. The outputs of the m polyphase filter banks 46 are summed by summing circuits 54, 56, and 58 to generate bits of the digital signal C at a rate fs / M. The operation and configuration of the polyphase decimation filter 40 are well known to those skilled in the art.

[0021] It should be noted that the signal interface used for the digital output signal B from the quantizer circuit 24 to the single-bit DAC circuit 26 and the digital filter circuit 14, and the digital filter circuit 14 itself, are both high-speed interfaces that must operate at a sampling rate fs used for the sampling clock. Therefore, there is significant digital design complexity and power consumption. Addressing these issues would be beneficial.

[0022] Now for reference Figure 4 It shows a block diagram of an alternative embodiment of the Σ-Δ analog-to-digital converter circuit 100. Figure 1 , Figure 2 , Figure 3 and Figure 4 Similar reference numerals in the figures indicate similar, analogous, or identical components. Figure 4 Circuit 100 and Figure 1 , Figure 2 and Figure 3 The main difference in circuit 10 lies in how the bit sequence of the digital output signal B from quantizer circuit 24 is passed to digital filter circuit 14. Used as... Figure 4 The single-bit finite impulse response (FIR) digital-to-analog converter (DAC) circuit 30' of the single-bit DAC circuit 26 in the middle circuit also includes a timing data register 110. The data output (Q) from the flip-flops 34(1)-34(n) is applied to the inputs of the corresponding single-bit DAC elements 36(1)-36(n), and also to the n single-bit inputs of the bit storage location 111 of the timing data register 110. The data register 110 operates in response to each assertion of the input clock signal to latch the data output (Q) from the flip-flops 34 in location 111. The input clock signal for the data register 110 operates to latch the data at a frequency of fs / n (where n equals the number of flip-flops 34). Therefore, the data register 110 will store an n-bit word (or frame) comprising n consecutive bits of the digital output signal B at a rate corresponding to the frequency fs / n. Figure 4 The digital filter circuit 14 in the middle circuit also includes a data register 112 with m groups of polyphase filters 40'. The data register 112 includes m bit positions 113 (where m equals the number of signal processing paths in the polyphase filter 40'). In this configuration, each signal processing path includes a polyphase group 46. A controlled fan-out circuit 114 operates to distribute each word (or frame) of n bits output from the data register 110 to the m inputs of the data register 112 using a multiplexing operation that implements parallel data shifting. It should be noted that because the operations of registers 110, 112, and the fan-out circuit 114 perform decimation, it is not necessary to include decimation circuitry (such as circuit 44) in each signal processing path. A control circuit 116, operating in response to an input clock signal with a frequency of fs / n, controls the multiplexing operation of the fan-out circuit 114 to transfer each n-bit word (or frame) of data bits from the data register 110 to the n positions 113 in the m-bit data register 112. Then the data bits stored in data register 112 are output to the corresponding signal processing path of polyphase filter 40'.

[0023] In one embodiment, n = M such that the decimation rate setting corresponds to the bit size of the register and the flip-flop. However, it should be noted that n may be different from M. In this case, the fan-out circuit 114 and the control circuit 116 are designed to reconstruct (i.e., rearrange) the n bits output from the flip-flop into an M-bit wide word, which will be available by decimation through M digital filters operating at a rate corresponding to fs / M.

[0024] In one embodiment, n = m, so the controlled fanout circuit 114 simply operates as a parallel shift circuit to transfer a data word including n bits from the data register 110 to the corresponding m bits in the data register 112. The word is shifted at a rate corresponding to fs / n.

[0025] In another embodiment, n < m, so the operation of the controlled fanout circuit 114 is more complex. As an example of such more complex operation, the controlled fanout circuit 114 implements a barrel shift function to transfer each word including n bits from the data register 110 to certain bit positions of the m bits in the data register 112. The barrel shift is performed at a rate corresponding to fs / n.

[0026] A better understanding of the barrel shift function can be obtained by considering a specific example where n = 4 and m = 6. At a given pulse of the input clock signal (frequency fs / n), the control circuit 116 controls the demultiplexing switching operation of the fanout circuit 114 to transfer a data word (or frame) including 4 data bits from the data register 110 to the first four bit positions (i.e., bits 1 to 4) in the data register 112. At the next (subsequent) pulse of the input clock signal (frequency fs / n), the control circuit 116 controls the demultiplexing switching operation of the fanout circuit 114 to transfer the next data word (or frame) including 4 data bits from the data register 110 to the last two (i.e., bits 5 to 6) and the first two (i.e., bits 1 to 2) bit positions in the data register 112 (illustrating the barrel shift operation). At subsequent pulses of the input clock signal (frequency fs / n), the control circuit 116 controls the demultiplexing switching operation of the fanout circuit 114 to transfer the next data word (or frame) including 4 data bits from the data register 110 to the last four bit positions (i.e., bits 3 to 6) in the data register 112.

[0027] Now consider a specific example with n=4 and m=10. At a given pulse of the input clock signal (frequency fs / n), control circuitry 116 controls the multiplexing operation of fan-out circuitry 114 to transfer a data word (or frame) comprising 4 data bits from data register 110 to the first four bit positions (i.e., bits 1 to 4) in data register 112. At the next (subsequent) pulse of the input clock signal (frequency fs / n), control circuitry 116 controls the multiplexing operation of fan-out circuitry 114 to transfer the next data word (or frame) comprising 4 data bits from data register 110 to the last four positions (i.e., bits 5 to 8) in data register 112. In the subsequent pulse of the input clock signal (frequency fs / n), the control circuit 116 controls the multiplexing operation of the fan-out circuit 114 to transfer the subsequent data word (or frame) including 4 data bits from the data register 110 to the last two (i.e., bits 9 to 10) and the first two (i.e., bits 1 to 2) bit positions in the data register 112 (illustrating the barrel shift operation).

[0028] Now consider a specific example with n=4 and m=8. At a given pulse of the input clock signal (frequency fs / n), control circuit 116 controls the multiplexing operation of fan-out circuit 114 to transfer a data word (or frame) comprising 4 data bits from data register 110 to the first four bit positions (i.e., bits 1 to 4) in data register 112. At the next (subsequent) pulse of the input clock signal (frequency fs / n), control circuit 116 controls the multiplexing operation of fan-out circuit 114 to transfer the next data word (or frame) comprising 4 data bits from data register 110 to the last four bit positions (i.e., bits 5 to 8) in data register 112. At a subsequent pulse of the input clock signal (frequency fs / n), control circuit 116 controls the multiplexing operation of fan-out circuit 114 to transfer the subsequent data word (or frame) comprising 4 data bits from data register 110 to the first four bit positions (i.e., bits 1 to 4) in data register 112 (illustrating a barrel shift operation).

[0029] and Figure 1-3 Compared to the implementation, Figure 4 The circuit 100 achieves considerable power savings, where the analog and digital resources of the circuit are shared by the FIR DAC 30' and the polyphase filter 40'. It is advantageous to reuse data latched by the flip-flop 34 of the FIR DAC 30' to provide data for the inputs of the single-bit DAC element and the decimation circuit 44, since this data is generated at a rate corresponding to the frequency fs / n. Power reduction is achieved, at least because a high-speed (i.e., corresponding to the sampling frequency fs) digital data register and associated clock and control circuitry are not required.

[0030] While the invention has been detailed and described in the accompanying drawings and foregoing description, such description is to be considered illustrative or exemplary rather than restrictive; the invention is not limited to the disclosed embodiments. Other variations to the disclosed embodiments will be understood and implemented by those skilled in the art in practicing the claimed invention through study of the drawings, the disclosure, and the appended claims.

Claims

1. A continuous-time Σ-Δ analog-to-digital converter circuit, comprising: A Σ-Δ modulator circuit is configured to receive an analog input signal, and the Σ-Δ modulator circuit includes a single-bit quantizer configured to generate a digital output signal at a sampling frequency, and the Σ-Δ modulator circuit further includes a single-bit digital-to-analog converter (DAC) circuit configured to process the digital output signal to generate an analog feedback signal for comparison with the analog input signal. The single-bit digital-to-analog converter circuit mentioned above includes: Multiple flip-flops, connected in series and configured to store bits of the digital output signal; and Multiple single DAC elements are controlled by storage bits of the digital output signal output from the multiple flip-flops; A polyphase filter circuit includes multiple signal processing paths, each of which includes a polyphase filter bank, and the outputs from the multiple signal processing paths are summed to generate a converted output signal; and The fan-out circuit is configured to selectively apply bits of the digital output signal from the plurality of flip-flops to the inputs of the plurality of signal processing paths of the polyphase filter circuit.

2. The circuit according to claim 1 further includes: A first register circuit is configured to latch the storage bits of the digital output signal output from the plurality of flip-flops at a rate depending on a clock frequency that is a fraction of the sampling frequency. The input of the fan-out circuit is coupled to the output of the first register circuit. as well as The second register circuit is configured to store the bits selectively applied; The input of the second register circuit is coupled to the output of the fan-out circuit, and the output of the second register circuit is coupled to the plurality of signal processing paths of the polyphase filter circuit.

3. The circuit of claim 2, wherein the plurality of flip-flops comprises n flip-flops, and wherein the clock frequency is equal to the sampling frequency divided by n.

4. The circuit according to claim 3, wherein the plurality of signal processing paths includes m signal processing paths.

5. The circuit according to claim 4, wherein n = m.

6. The circuit according to claim 4, wherein n < m.

7. The circuit of claim 6, wherein the fan-out circuit uses a barrel shift function to apply the stored bits of the digital output signal latched in the first register circuit to select bits of the second register circuit.

8. The circuit of claim 7, wherein the barrel shift function is implemented at a rate dependent on the clock frequency.

9. The circuit of claim 2, wherein the storage bits of the digital output signal latched by the first register circuit form a data word, and wherein the fan-out circuit uses a barrel shift function to apply the data word for storage in the second register circuit.

10. The circuit of claim 9, wherein the barrel shift function is implemented at a rate dependent on the clock frequency.

11. The circuit of claim 1, wherein each single DAC element includes a unit element current source controlled by a corresponding storage bit of the storage bits of the digital output signal output from the plurality of flip-flops.

12. The circuit of claim 1, wherein each of the plurality of flip-flops is timed at the sampling frequency.

13. A continuous-time Σ-Δ analog-to-digital converter circuit, comprising: A Σ-Δ modulator circuit, configured to receive an analog input signal, includes: A single-bit quantizer is configured to generate a digital output signal at the sampling frequency; Data storage circuitry is configured to store bits of the digital output signal; and Multiple digital-to-analog converter (DAC) elements are coupled to the data storage circuit and actuated in response to the stored bits to generate an analog feedback signal for comparison with the analog input signal; A filter circuit includes multiple polyphase signal processing paths and a summing circuit configured to sum the outputs from the multiple polyphase signal processing paths to generate a converted output signal; and The fan-out circuit is configured to selectively apply stored bits from the data storage circuit to the inputs of the plurality of polyphase signal processing paths of the filter circuit.

14. The circuit of claim 13, wherein the data storage circuit includes a plurality of triggers connected in series and timing at the sampling frequency.

15. The circuit of claim 14, wherein the data outputs of the plurality of flip-flops control the plurality of DAC elements.

16. The circuit of claim 13, wherein the data storage circuit further comprises a register circuit configured to latch the stored bits of the digital output signal at a rate dependent on a clock frequency, the clock frequency being a fraction of the sampling frequency; and The input of the fan-out circuit is coupled to the output of the register circuit.

17. The circuit of claim 16, wherein the fraction depends on the number of storage bits of the digital output signal.

18. The circuit of claim 16, further comprising an additional register circuit configured to couple the output of the fan-out circuit to the plurality of polyphase signal processing paths of the filter circuit.

19. The circuit of claim 16, wherein the stored bits of the digital output signal latched by the register circuit form a data word; and wherein the fan-out circuit uses a barrel shift function to apply the data word to the plurality of polyphase signal processing paths of the filter circuit.

20. The circuit of claim 19, wherein the barrel shift function is implemented at a rate dependent on the clock frequency.

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