Digital domain open loop baseband calibration based on zero intermediate frequency transmission, fitting method and device, processor and computer readable storage medium

Abstract

The present application relates to a kind of digital domain open loop baseband calibration based on zero intermediate frequency transmission and fitting method, wherein the method comprises the following processing steps: (1) the transmission processing of IQ data in digital domain is handled in FPGA inside;(2) system cooperates host computer and sends parameters to FPGA according to least square method and step-by-step approximation method to obtain appropriate calibration value;(3) for non-calibration frequency point parameters, based on the same channel configuration, multiple calibration frequency points are fitted to obtain calibration data.The present application also relates to a corresponding device, processor and its storage medium.Using the digital domain open loop baseband calibration based on zero intermediate frequency transmission and fitting method, device, processor and its computer readable storage medium of the present application, different step sizes are used to more quickly approach correction value, and there is no loss in correction accuracy.For the fitting of non-calibration frequency points, more accurate frequency response characteristics are provided, and the error caused by the uncertainty of each component on the hardware path is eliminated.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of digital signal processing, in particular to the technical field of baseband IQ calibration and fitting, and more particularly to a digital domain open-loop baseband calibration and fitting method, device, processor and computer storage medium based on zero intermediate frequency transmission. BACKGROUND

[0002] The main function of the radio frequency transmitter is to realize baseband signal modulation, up-conversion and power amplification. The zero intermediate frequency transmission architecture is relatively simple and is a relatively common transmission modulation scheme. It is divided into an IQ baseband generator and an IQ mixer. The function of the IQ modulator is to move the baseband IQ signal to the carrier. However, due to the interference in the hardware transmission and the error in the DAC conversion accuracy, some amplitude and phase deviations will be caused during the IQ mixing. Therefore, it is necessary to calibrate the two IQ channels. Since the calibration cost is high and there are many interference factors in the hardware, the digital domain calibration is generally used.

[0003] The common way of IQ imbalance calibration is digital domain open-loop calibration and closed-loop calibration. The digital domain open-loop calibration method has the advantages of less interference factors, simple controllable variables, and lower cost compared with the closed-loop calibration. The common open-loop calibration method is to store the calibration data of each frequency point in a table, and then directly fit according to the linear interpolation. When the frequency points are less, the fitting characteristics are poor. When the number of points is too large, the number of calibration tables is too large, which increases the calculation amount, and further reduces the conversion efficiency and the conversion stability of the overall transmission system. SUMMARY

[0004] The present application overcomes the shortcomings of the prior art and provides a fast and low-cost digital domain open-loop baseband calibration and fitting method, device, processor and computer storage medium based on zero intermediate frequency transmission.

[0005] In order to achieve the above-mentioned purpose, the digital domain open-loop baseband calibration and fitting method, device, processor and computer storage medium based on zero intermediate frequency transmission of the present application are as follows:

[0006] The digital domain open-loop baseband calibration and fitting method based on zero intermediate frequency transmission mainly comprises the following steps:

[0007] (1) The IQ data is transmitted and processed in the digital domain inside the FPGA;

[0008] (2) The system cooperates with the host computer to send parameters to the FPGA for processing according to the least square method and the step-by-step approximation method to obtain appropriate calibration values;

[0009] (3) For non-calibration frequency point parameters, based on the same channel configuration, multiple calibration frequency points are fitted to obtain calibration data.

[0010] Preferably, the step (1) is specifically:

[0011] In the process of transmitting IQ data inside the FPGA, the following formula is used for processing in the digital domain:

[0012] I c = I-d i ;

[0013]

[0014] Where I c is the processed I channel data, I is the original I channel data, d i is the I channel DC bias adjustment factor, Q c is the processed Q channel data, Q is the original Q channel data, d q is the Q channel DC bias adjustment factor.

[0015] Preferably, the step (2) specifically includes the following steps:

[0016] (2.1) The system sets the initial amplitude scaling factor to The initial step is ε0, and the initial power value is recorded;

[0017] (2.2) According to the initial step ε0, increase the coefficient And judge whether the first signal power is reduced, if so, enter step (2.3), otherwise, enter step (2.4);

[0018] (2.3) According to the initial step ε0, increase the coefficient And judge whether the signal power is reduced, if so, repeat the step, otherwise, enter step (2.5);

[0019] (2.4) According to the initial step ε0, decrease the coefficient And judge whether the signal power is reduced, if so, repeat the step, otherwise, enter step (2.5);

[0020] (2.5) Record the scaling factor And the corresponding power value under the current best state, and judge whether the current step reaches the best preset step, if so, directly store the correction value, otherwise, enter step (2.6);

[0021] (2.6) Reduce the current step by half and return to step (2.2) for repeated processing.

[0022] Preferably, the step (2) further comprises:

[0023] According to different frequency points, the calibration data are sequentially stored in the BRAM of the FPGA.

[0024] Preferably, the step (3) specifically comprises the following steps:

[0025] (3.1) inputting the non-calibration frequency point parameter and obtaining the corresponding index according to the frequency point;

[0026] (3.2) looking up the LUT table to obtain the correction value of the corresponding frequency point;

[0027] (3.3) reading the correction data of each frequency point, and applying the Lagrange interpolation method to the extracted value to obtain the fitting calibration value.

[0028] The digital domain open loop baseband calibration and fitting device based on the zero intermediate frequency transmission mainly comprises:

[0029] a processor configured to execute computer executable instructions;

[0030] a memory storing one or more computer executable instructions, which, when executed by the processor, implement each step of the above-mentioned digital domain open loop baseband calibration and fitting method based on the zero intermediate frequency transmission.

[0031] The processor for the digital domain open loop baseband calibration and fitting based on the zero intermediate frequency transmission mainly comprises: the processor is configured to execute computer executable instructions, and the computer executable instructions, when executed by the processor, implement each step of the above-mentioned digital domain open loop baseband calibration and fitting method based on the zero intermediate frequency transmission.

[0032] The computer readable storage medium mainly comprises: a computer program is stored thereon, and the computer program can be executed by the processor to implement each step of the above-mentioned digital domain open loop baseband calibration and fitting method based on the zero intermediate frequency transmission.

[0033] The present invention employs a digital domain open-loop baseband calibration and fitting method, apparatus, processor, and computer storage medium based on zero-IF transmission. During calibration, a multi-step parameter approximation method is used, utilizing different step sizes to more quickly approximate the correction value without sacrificing calibration accuracy. Compared to existing technologies, it is simpler and more efficient in operation. Among non-calibration frequency points, calibration data is fitted from multiple calibration frequency points under the same channel configuration, avoiding the various drawbacks of linear fitting. Compared to existing technologies, it provides more accurate frequency response characteristics for fitting non-calibration frequency points, eliminating errors caused by uncertainties in various components along the hardware path. Furthermore, this method reuses existing calibration data without reducing fitting efficiency. Attached Figure Description

[0034] Figure 1 This is a schematic diagram of the baseband calibration process of the digital domain open-loop baseband calibration and fitting method based on zero intermediate frequency transmission according to the present invention.

[0035] Figure 2 This is a schematic diagram illustrating the data fitting process of the digital domain open-loop baseband calibration and fitting method based on zero intermediate frequency transmission according to the present invention. Detailed Implementation

[0036] To more clearly describe the technical content of the present invention, the following description is provided in conjunction with specific embodiments.

[0037] Before describing the embodiments of the present invention in detail, it should be noted that, in the following, the terms “comprising,” “including,” or any other variations are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed or inherent to such process, method, article, or apparatus.

[0038] This digital domain open-loop baseband calibration and fitting method based on zero intermediate frequency transmission includes the following processing steps:

[0039] (1) The FPGA internally processes the IQ data in the digital domain for transmission;

[0040] (2) The system works with the host computer to send parameters to the FPGA for processing according to the least squares method and the successive approximation method to obtain appropriate calibration values;

[0041] (3) For non-calibration frequency parameters, calibration data is obtained by fitting multiple calibration frequency points under the same channel configuration.

[0042] In a preferred embodiment of the present invention, step (1) specifically comprises:

[0043] During the transmission of IQ data within the FPGA, the following formula is used in the digital domain:

[0044] I c =Id i ;

[0045]

[0046] Among them, I c To process the I-channel data, where I is the original I-channel data, and d... i Q is the DC bias adjustment factor for the I-channel. c This is for the processed Q-channel data, where Q is the original Q-channel data, and d q This is the DC bias adjustment factor for the Q-path.

[0047] Please see Figure 1 As shown, in a preferred embodiment of the present invention, step (2) specifically includes the following steps:

[0048] (2.1) The system is set to the initial amplitude scaling factor as follows: The initial step size is ε0, and the initial power value is recorded.

[0049] (2.2) Increase the coefficient according to the initial step ε0. And determine whether the initial signal power has decreased. If so, proceed to step (2.3); otherwise, proceed to step (2.4).

[0050] (2.3) Increase the coefficient according to the initial step ε0. And determine whether the signal power has decreased. If so, repeat the step; otherwise, proceed to step (2.5).

[0051] (2.4) Decrease the coefficient according to the initial step ε0. And determine whether the signal power has decreased. If so, repeat the step; otherwise, proceed to step (2.5).

[0052] (2.5) Record the scaling factor under the current optimal state. And the corresponding power value, and determine whether the current step has reached the optimal preset step. If so, store the correction value directly; otherwise, proceed to step (2.6).

[0053] (2.6) Reduce the current step by half and return to step (2.2) to repeat the process.

[0054] In a preferred embodiment of the present invention, step (2) further includes:

[0055] The calibration data is stored sequentially in the FPGA's BRAM according to different frequency points.

[0056] Referring to Figure 2 As shown in the preferred embodiment of the present application, the step (3) specifically comprises the following steps:

[0057] (3.1) inputting the non-calibration frequency point parameters and obtaining the corresponding index according to the frequency point;

[0058] (3.2) looking up the LUT table to obtain the correction value of the corresponding frequency point;

[0059] (3.3) reading the correction data of each frequency point, and using the Lagrange interpolation method to perform operation fitting processing on the extracted values to obtain the fitting calibration value.

[0060] In actual application, the zero intermediate frequency transmitter is connected with the spectrum analyzer, the transmitter loads the A i cosα signal on the I path and the A q sinα signal on the Q path, and the signal shown in the figure appears on the spectrum analyzer; wherein the image signal is caused by the incomplete cancellation of the phase or amplitude superposition of the I path and the Q path, and the local oscillator signal is caused by the inconsistency of the DC bias of the I path and the Q path and the insufficient isolation of the local oscillator signal of the IQ modulator. Figure 1

[0061] In the technical solution, the FPGA internally processes the IQ data in the transmission process in the digital domain according to the following formulas 1) and 2), and the host computer sends appropriate parameters to the FPGA for processing according to the least square method step-by-step approximation method to obtain appropriate calibration values; for example, when correcting the amplitude, the step can be initially set as ε0, the initial value is 0, and then the amplitude adjustment coefficient is changed Compared with the initial leakage power, the coefficient is first increased until the leakage index deteriorates, if the leakage index deteriorates at the beginning, the coefficient is modified to be reduced according to the initial step ε0 until the deterioration; then the step is continued to repeat the above operation according to half of the initial step ε0, until the step is reduced to ε x ; ε x is determined by the minimum data bit identified by the system; other parameters are executed in a similar manner to the above method;

[0062] According to different frequency points, the calibration data is sequentially stored in the BRAM of the FPGA, and the structure is shown in Table 1. The correction factors corresponding to adjacent indexes need to be adjusted according to different system conditions to avoid affecting the convergence of the overall algorithm.

[0063] ​When the correction value is applied, for the calibration frequency point, only the correction data corresponding to the index of the frequency point is read; for the non-calibration frequency point, it is assumed that the system is applicable to m (mEN*, m≥2) points for fitting (the number of fitting points needs to be determined according to the characteristics of the system), the frequency points F k between the calibration points F x and F x+1 (F m+x-1 and F k are in the same channel); the correction data of each frequency point F x , F x+1 ……, F m+x-1 is read, and according to the obtained values, Lagrange interpolation is used for operation fitting, and the specific calculation is shown in formulas 3) and 4).

[0064] When the fitting frequency point F k is not in the same channel as F x+1 , the correction data of each frequency point F x-m+1 , F x-m+2 ……, F x is read, and the fitting calculation is referred to formulas 5) and 6).

[0065] Table 1: FPGA storage correction data structure

[0066]

[0067] Formula 1): I c = I-d i ; (wherein, I c is the processed I channel data, I is the original I channel data, and d i is the I channel DC bias adjustment factor)

[0068] Formula 2): (wherein, Q c is the processed Q channel data, Q is the original Q channel data, d q is the Q channel DC bias adjustment factor, and I is the original I channel data)

[0069] Formula 3): (wherein, γ j (τ) represents the Lagrange polynomial of the current frequency point τ, m represents the number of suitable fitting points of the system, x is the index position of the lookup table calibration data, F i , F j are the calibration frequency point values corresponding to the cumulative index; and i is the cumulative index value)

[0070] Formula 4): (wherein, γ j (F k ) represents the Lagrange polynomial of the current frequency point F kThe Lagrange polynomial, m represents the number of suitable fitting points for the system, x is the index position of the calibration data in the lookup table, F k To calculate the fitting frequency point, δ j (This refers to the calibration value corresponding to index j, where j is the cumulative multiplication index value.)

[0071] Formula 5): (where γ j (τ) represents the Lagrange polynomial of the current frequency τ, m represents the number of suitable fitting points for the system, x is the index position of the calibration data in the lookup table, and F i F j (i is the calibration frequency value corresponding to the cumulative index; i is the cumulative index value)

[0072] Formula 6): (where γ j (F k ) indicates the current frequency point F k The Lagrange polynomial, m represents the number of suitable fitting points for the system, x is the index position of the calibration data in the lookup table, F k To calculate the fitting frequency point, δ j (This refers to the calibration value corresponding to index j, where j is the cumulative multiplication index value.)

[0073] This digital domain open-loop baseband calibration and fitting device based on zero intermediate frequency transmission includes:

[0074] A processor is configured to execute computer-executable instructions;

[0075] The memory stores one or more computer-executable instructions, which, when executed by the processor, implement the various steps of the digital domain open-loop baseband calibration and fitting method based on zero-IF transmission described above.

[0076] The processor for digital domain open-loop baseband calibration and fitting based on zero-IF transmission is configured to execute computer-executable instructions, which, when executed by the processor, implement the various steps of the aforementioned digital domain open-loop baseband calibration and fitting method based on zero-IF transmission.

[0077] The computer-readable storage medium contains a computer program that can be executed by a processor to implement the various steps of the above-described digital domain open-loop baseband calibration and fitting method based on zero-IF transmission.

[0078] Any procedural or methodological descriptions in flow charts or otherwise described herein can be understood to represent modules, segments, or portions of code that include executable instructions for implementing the specified logical function or process, and the scope of preferred embodiments of the present application includes additional implementations in which the functions are performed in an order different from that shown or discussed, including substantially simultaneously, or in reverse order, as will be understood by those skilled in the art to which embodiments of the present application pertain.

[0079] It should be understood that portions of the present application can be realized with hardware, software, firmware or a combination thereof. In the foregoing embodiments, a plurality of steps or methods can be realized as software or firmware to be executed by a suitable instruction executing device.

[0080] It can be understood by those skilled in the art that all or part of the steps carried out by the above-mentioned embodiments can be instructed by a program to related hardware, and the program can be stored in a computer readable storage medium, and the program includes one of the steps of the method embodiments or a combination thereof when executed.

[0081] The storage medium mentioned above can be a read-only memory, a magnetic disk or an optical disk, etc.

[0082] In the description of the present specification, the description of the terms "an embodiment", "some embodiments", "an example", "a specific example", or "embodiments" and the like means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily mean the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0083] Although the embodiments of the present application have been shown and described above, it can be understood that the above-mentioned embodiments are exemplary and cannot be understood as limiting the present application, and those skilled in the art can make changes, modifications, replacements and variations to the above-mentioned embodiments within the scope of the present application.

[0084] The digital domain open loop baseband calibration and fitting method, device, processor and computer storage medium based on the zero intermediate frequency transmission of the application, when calibrating, a multi-step parameter is used to gradually approach, and different step sizes are used to more quickly approach the correction value, and the correction accuracy is not lost. Compared with the prior art, the operation is more concise and efficient; based on the same channel configuration, multiple calibration frequency points are fitted to obtain calibration data between non-calibration frequency points. Avoid the various disadvantages brought by linear fitting. Compared with the prior art, the fitting of non-calibration frequency points provides more accurate frequency response characteristics, and eliminates the error caused by the uncertainty of each component on the hardware path. At the same time, the method is repeatedly used on the existing calibration data, and does not cause a decrease in fitting efficiency.

[0085] In this specification, the application has been described with reference to its particular embodiments. It is clear, however, that various modifications and changes can be made without departing from the spirit and scope of the application. Therefore, the specification and drawings should be considered illustrative rather than restrictive.

Claims

1. A digital domain open-loop baseband calibration and fitting method based on zero-IF transmission, characterized in that, The method includes the following processing steps: (1) The FPGA internally processes the IQ data in the digital domain for transmission; (2) The system works with the host computer to send parameters to the FPGA for processing according to the least squares method and the successive approximation method to obtain appropriate calibration values; (3) For non-calibration frequency point parameters, under the same channel configuration, multiple calibration frequency points are combined to fit the calibration data; Step (2) specifically includes the following steps: (2.1) The system is set to the initial amplitude scaling factor as follows: The initial step size is ε0, and the initial power value is recorded. (2.2) Increase the coefficient according to the initial step ε0. And determine whether the initial signal power has decreased. If so, proceed to step (2.3); otherwise, proceed to step (2.4). (2.3) Increase the coefficient according to the initial step ε0. And determine whether the signal power has decreased. If so, repeat the step; otherwise, proceed to step (2.5). (2.4) Decrease the coefficient according to the initial step ε0. And determine whether the signal power has decreased. If so, repeat the step; otherwise, proceed to step (2.5). (2.5) Record the scaling factor under the current optimal state. The corresponding power value is also recorded, and it is determined whether the current step size has reached the optimal preset step size. If so, the current scaling factor is stored directly. If the value is not corrected, proceed to step (2.6); (2.6) Reduce the current step by half and return to step (2.2) to repeat the process.

2. The digital domain open-loop baseband calibration and fitting method based on zero-IF transmission according to claim 1, characterized in that, The specific steps (1) are as follows: During the transmission of IQ data within the FPGA, the following formula is used in the digital domain: I c =I-d i ; Among them, I c To process the I-channel data, where I is the original I-channel data, and d... i Q is the DC bias adjustment factor for the I-channel. c This is for the processed Q-channel data, where Q is the original Q-channel data, and d q This is the DC bias adjustment factor for the Q-path.

3. The digital domain open-loop baseband calibration and fitting method based on zero-IF transmission according to claim 1, characterized in that, Step (2) further includes: The calibration data is stored sequentially in the FPGA's BRAM according to different frequency points.

4. The digital domain open-loop baseband calibration and fitting method based on zero-IF transmission according to claim 1, characterized in that, Step (3) specifically includes the following steps: (3.1) Input the non-calibrated frequency point parameters and obtain the corresponding index according to the frequency point; (3.2) Look up the corresponding frequency point in the LUT table; (3.3) Read the correction data of each frequency point, and use the Lagrange interpolation method to perform calculation and fitting processing on the extracted values ​​to obtain the fitted calibration values.

5. A digital domain open-loop baseband calibration and fitting device based on zero intermediate frequency transmission, characterized in that, The device includes: A processor is configured to execute computer-executable instructions; The memory stores one or more computer-executable instructions, which, when executed by the processor, implement the various steps of the digital domain open-loop baseband calibration and fitting method based on zero-IF transmission as described in any one of claims 1 to 4.

6. A processor for digital domain open-loop baseband calibration and fitting based on zero-IF transmission, characterized in that, The processor is configured to execute computer-executable instructions, which, when executed by the processor, implement the various steps of the digital domain open-loop baseband calibration and fitting method based on zero intermediate frequency transmission as described in any one of claims 1 to 4.

7. A computer-readable storage medium, characterized in that, It stores a computer program that can be executed by a processor to implement the various steps of the digital domain open-loop baseband calibration and fitting method based on zero intermediate frequency transmission as described in any one of claims 1 to 4.

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