FPGA embedded single event transient resistant bidirectional decision feedback equalization circuit

Abstract

The present application relates to the field of high-speed interface equalization design in FPGAs, and specifically discloses an equalization circuit, including a slicing circuit 1, a weight unit 1, an adder circuit 1, a slicing circuit 2, a weight unit 2, and an adder circuit 2; the slicing circuit 1 slices an initial pulse signal to obtain a slice signal 1, and the slice signal 1 is assigned a weight 1 by the weight unit 1 to obtain a weight signal 1; the adder circuit 1 superimposes the initial pulse signal and the weight signal 1 to obtain a first superimposed pulse signal; the slicing circuit 2 slices the initial pulse signal to obtain a slice signal 2, and the slice signal 2 is assigned a weight 2 by the weight unit 2 to obtain a weight signal 2; the adder circuit 2 superimposes the first superimposed pulse signal and the weight signal 2, and outputs a second superimposed pulse signal. Through the solution provided by the present application, the signal amplitude variation of the final output signal near the peak is relatively large, solving the inter-symbol interference problem caused by single-particle transients.

Description

Technical Field

[0001] The present application relates to the technical field of high-speed interface equalization design in FPGA based on SerDes technology, and in particular to a single-particle transient-resistant bidirectional decision feedback equalization circuit embedded in FPGA for aerospace applications. Background Art

[0002] To meet the massive data transmission needs of aerospace models and weaponry, the high-speed interfaces embedded in aerospace FPGAs typically require a bit error rate (BER) below 10E-15 under single-event transients in space. The high-speed interface circuitry is primarily divided into the transmitter (TX) and receiver (RX). Due to the high frequency of the highest-speed parallel-to-serial and serial-to-parallel conversions in the TX and RX systems, the data width is relatively small. This, coupled with channel transmission attenuation, results in slight intersymbol interference (ISI). In aerospace applications, high-speed interfaces are also subject to the transient effects of numerous high-energy particles. When a high-energy particle strikes a high-speed interface circuit, it loses energy by generating electron-hole pairs along its path through localized ionization. In the presence of an electric field, the electron-hole pairs along the particle's path separate and are collected by electrodes, resulting in transient interference. This single-event transient in space exacerbates ISI in high-speed data transmission, leading to data rollover errors and increased BER. Summary of the Invention

[0003] The present application provides an equalization circuit, the purpose of which is to solve the inter-symbol interference problem caused by single-event transients.

[0004] In a first aspect, an equalization circuit is provided, comprising:

[0005] a first slicing circuit, configured to slice the initial pulse signal to obtain a first slicing signal;

[0006] a first weighting unit connected to the first slicing circuit, configured to assign a first weight to the first slicing signal to obtain a first weighted signal, wherein the first weight is a negative value greater than -1;

[0007] a first adder circuit, wherein an input end of the first adder circuit is connected to the first weight unit, and the first adder circuit is used to superimpose the initial pulse signal and the first weight signal to obtain a first superimposed pulse signal;

[0008] a second slicing circuit, configured to slice the initial pulse signal to obtain a second slicing signal, wherein the first slicing signal and the second slicing signal are respectively a rising edge signal and a falling edge signal of the initial pulse signal;

[0009] a second weighting unit connected to the second slicing circuit, configured to assign a second weight to the second slicing signal to obtain a second weighted signal, wherein the second weight is a negative value greater than -1;

[0010] A second adder circuit, the input end of the second adder circuit is connected to the output end of the first adder circuit and the second weight unit, and the second adder circuit is used to superimpose the first superimposed pulse signal and the second weight signal, and output a second superimposed pulse signal.

[0011] Compared with the existing technology, the solution provided by this application includes at least the following beneficial technical effects:

[0012] By setting the first slicing unit, the second slicing unit, the first weighting unit and the second weighting unit, the waveforms of the rising and falling edges of the pulse signal can be adjusted so that the signal amplitude change degree of the second superimposed pulse signal near the peak is relatively large (that is, the slopes of the rising and falling edge waveforms are steeper), thereby achieving the elimination of transient interference signals.

[0013] In combination with the first aspect, in certain implementations of the first aspect, the output end of the first adder circuit is connected to the second slicing circuit, the second slicing circuit is used to slice the first superimposed pulse signal to obtain the second slicing signal, and the first slicing signal and the second slicing signal correspond to the same period.

[0014] Since the current pulse signal is corrected according to the current pulse signal itself, it is beneficial to improve the accuracy of the equalization circuit in correcting the pulse signal.

[0015] In combination with the first aspect, in some implementations of the first aspect, an output end of the second adder circuit is connected to the second slicing circuit, the first slicing signal corresponds to a rising edge signal of a first cycle, the second slicing signal corresponds to a falling edge signal of a second cycle, and the second cycle is earlier than the first cycle;

[0016] The superimposing the first superimposed pulse signal and the second weighted signal includes:

[0017] The falling edge signal corresponding to the first period in the first superimposed pulse signal is superimposed on the second weight signal.

[0018] Since the current pulse signal is corrected by pulse signals of other periods, it is beneficial to reduce the timeliness requirement of the equalization circuit.

[0019] In conjunction with the first aspect, in some implementations of the first aspect, the balancing circuit further includes:

[0020] A first delay unit and a third weight unit, wherein the first delay unit and the third weight unit are connected in series between the first slicing circuit and the first adder circuit, the first delay unit is used to delay the first slicing signal to obtain a first delayed signal, the third weight unit is used to assign a third weight to the first delayed signal to obtain a third weight signal, the third weight is a negative value greater than -1, and the first adder circuit is used to superimpose the initial pulse signal, the first weight signal and the third weight signal to obtain the first superimposed pulse signal.

[0021] Since the first slice signal and the first weight signal can be assigned different weight values ​​respectively, the signal near the peak can be adjusted to different degrees.

[0022] In combination with the first aspect, in certain implementations of the first aspect, the first slicing signal corresponds to a rising edge signal, and the first weight is greater than the third weight.

[0023] The closer the signal is to the peak, the greater the degree of attenuation can be, which is beneficial to increasing the steepness of the rising edge.

[0024] In combination with the first aspect, in some implementations of the first aspect, a plurality of delay units and a plurality of weight units are provided between the first slicing circuit and the first adder circuit, and the duration t1 of the first slicing signal satisfies: t1 <T / (2*N a ), T is the period of the initial pulse signal, N a is the number of delay units set between the first slicing circuit and the first adder circuit.

[0025] The duration of the slicing signal is relatively short, which helps to reduce the possibility of cutting knife pulse peaks.

[0026] In conjunction with the first aspect, in some implementations of the first aspect, the balancing circuit further includes:

[0027] A second delay unit and a fourth weight unit, the second delay unit and the fourth weight unit are connected in series between the second slicing circuit and the second adder circuit, the second delay unit is used to delay the second slicing signal to obtain a second delayed signal, the fourth weight unit is used to assign a fourth weight to the second delayed signal to obtain a fourth weight signal, the fourth weight is a negative value greater than -1, and the second adder circuit is used to superimpose the first superimposed pulse signal, the second weight signal and the fourth weight signal to obtain the second superimposed pulse signal.

[0028] Since the second slice signal and the second weight signal can be assigned different weight values ​​respectively, the signal near the peak can be adjusted to different degrees.

[0029] In combination with the first aspect, in some implementations of the first aspect, the second slicing signal corresponds to a falling edge signal, and the second weight is less than the fourth weight.

[0030] The closer the signal is to the peak, the greater the degree of attenuation can be, which is beneficial to increasing the steepness of the falling edge.

[0031] In combination with the first aspect, in some implementations of the first aspect, a plurality of delay units and a plurality of weight units are provided between the second slicing circuit and the second adder circuit, and the duration t2 of the second slicing signal satisfies: t2 <T / (2*N b ), T is the period of the initial pulse signal, N b is the number of delay units set between the second slicing circuit and the second adder circuit.

[0032] The duration of the slicing signal is relatively short, which helps to reduce the possibility of cutting knife pulse peaks.

[0033] In a second aspect, an electronic device method is provided, characterized in that the electronic device includes the equalization circuit as described in any one of the implementations of the first aspect.

[0034] In a third aspect, a weight adjustment method is provided, the method being applied to the balancing circuit as described in any one of the implementations of the first aspect above, wherein the weight is a weight assigned by a target weight unit, and the target weight unit is any weight unit in the balancing circuit; the method comprising:

[0035] Step 1: Determine the target weight, which is a tentatively assigned weight;

[0036] Step 2: Determine whether both the first processed pulse signal and the second processed pulse signal can correspond to correct data results, wherein the first processed pulse signal is a pulse signal obtained by the equalization circuit processing the first initial pulse signal according to the target weight, and the first initial pulse signal is a pulse signal that has undergone a single event transient impact effect; the second processed pulse signal is a pulse signal obtained by the equalization circuit processing the second initial pulse signal according to the target weight, and the second initial pulse signal is a pulse signal that has not undergone a single event transient impact effect;

[0037] If yes, execute step 3: control the target weight unit to assign the target weight;

[0038] If not, step 1 is executed again, and the newly determined target weight is different from the previously determined target weight. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 Schematic diagram of the inter-symbol interference effect on high-speed interfaces caused by spatial single-particle transients.

[0040] Figure 2 The application position of FPGA embedded single-event transient-resistant bidirectional decision feedback equalization circuit in high-speed interface circuit.

[0041] Figure 3 A schematic structural diagram of an equalization circuit provided in an embodiment of the present application.

[0042] Figure 4 A schematic structural diagram of another equalization circuit provided in an embodiment of the present application.

[0043] Figure 5 A schematic structural diagram of another equalization circuit provided in an embodiment of the present application.

[0044] Figure 6 A schematic structural diagram of an equalization circuit provided in an embodiment of the present application.

[0045] Figure 7 A schematic structural diagram of another equalization circuit provided in an embodiment of the present application.

[0046] Figure 8 A schematic structural diagram of another equalization circuit provided in an embodiment of the present application.

[0047] Figure 9 A schematic flowchart of a weight adjustment method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0048] The present application is described in further detail below with reference to the accompanying drawings and specific embodiments.

[0049] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0050] Figure 1In the field of telecommunications, the primary source of intersymbol interference (ISI) is signal distortion caused by single-event transients (SITs). At high altitudes or in space, signals transmitted through circuits are subject to SITs, which can cause intersymbol interference (ISI) within the signal itself, leading to signal superposition. Consider the transmitted signal "101." When subjected to SITs, the overlapping portion of the two "1" signals becomes severely distorted, with rising and falling edges becoming slower. When clock sampling is performed, the high tail amplitude causes the sampled signal to shift from "101" to "111." This is the mechanism responsible for SITs. In actual transmission, a 10E-15 specification means that even trillions of serial data can be transmitted without errors. However, sampling errors caused by ISI ultimately increase the bit error rate (BER).

[0051] Figure 2 This is where the FPGA's embedded single-event transient-resistant bidirectional decision feedback equalization circuit is applied in high-speed interface circuits. High-speed interfaces typically consist of a transmitter (TX) and a receiver (RX). After the highest-speed serial-to-parallel conversion, the circuit structure of this invention is added to suppress the flips caused by inter-symbol interference (ISI) caused by single-event transients. Figure 4 The schematic diagram shows a single-element bidirectional equalization circuit that can be applied to both the TX and RX terminals. The circuit is typically located between the driver circuit and the serial-to-parallel converter. The structures are identical on both TX and RX terminals, and can be inferred from each other.

[0052] Figure 3 Schematic diagram of an equalization circuit provided in an embodiment of the present application. The equalization circuit can be an FPGA-embedded single-event transient-resistant bidirectional decision feedback equalization circuit.

[0053] The equalization circuit may include an input port and an output port, between which a first weight unit 102 , a first slicing circuit 103 , a first adder circuit 104 , a second weight unit 202 , a second slicing circuit 203 , and a second adder circuit 204 are arranged.

[0054] In some embodiments, the first weighting unit 102, the first slicing circuit 103, and the first adder circuit 104 may constitute a forward streaking elimination circuit, which may be used to reduce the rising edge portion before the pulse peak. The second weighting unit 202, the second slicing circuit 203, and the second adder circuit 204 may constitute a backward streaking elimination circuit, which may be used to reduce the falling edge portion after the pulse peak.

[0055] like Figure 3As shown, the input port of the equalization circuit can be connected to the first slicing circuit 103, and the first weight unit 102 is connected in series between the first slicing circuit 103 and the input end of the first adder circuit 104. In addition, the input port of the equalization circuit can also be directly connected to the input end of the first adder circuit 104.

[0056] The input port of the equalization circuit can input an initial pulse signal to the first slicing circuit 103. The first slicing circuit 103 can be used to slice the initial pulse signal. The initial pulse signal forms a sliced signal a0 in the transient time domain after passing through the first slicing circuit 103. The first slicing circuit 103 can be composed of a comparator unit, for example. The sliced signal a0 can correspond to the target period a0 of the initial pulse signal. The target period a0 can be, for example, the rising edge period of a single cycle of the initial pulse signal. The duration t1 of the target period a0 < T / 2, where T is the period of the initial pulse signal.

[0057] The sliced signal a0 can be input from the first slicing circuit 103 to the first weight unit 102. The first weight unit 102 can assign a weight to the sliced signal a0 to obtain a weighted signal a0. The assigned weight can be a correction factor to correct the voltage signal of the current bit. The first weight unit 102 can include a digital-to-analog conversion unit, for example. The amplitude A1 of the sliced signal a0 and the amplitude A of the weighted signal a0 a0 Satisfy: A a0 = W a0 * A1, -1 < W a0 < 0.

[0058] The weighted signal a0 can be input from the first weight unit 102 to the first adder circuit 104. In addition, the input port of the equalization circuit can also input an initial pulse signal to the first adder circuit 104. By superimposing the initial pulse signal and the weighted signal a0 through the first adder circuit 104, a superimposed pulse signal a can be obtained.

[0059] As Figure 3 shown, the output end of the first adder circuit 104 can be connected to the second slicing circuit 203, and the second weight unit 202 is connected in series between the second slicing circuit 203 and the input end of the second adder circuit 204. In addition, the output end of the first adder circuit 104 can also be directly connected to the second slicing circuit 203. The output end of the second adder circuit 204 can be connected to the output port of the equalization circuit.

[0060] The output terminal of the first adder circuit 104 can input the superimposed pulse signal a to the second slicing circuit 203. The second slicing circuit 203 can be used to slice the superimposed pulse signal a to obtain a sliced signal b0. The sliced signal b0 can correspond to the target period b0 of the initial pulse signal or the superimposed pulse signal a. The target period b0 can be, for example, the falling edge period of a single cycle. The duration t2 of the target period b0 < T / 2, where T is the period of the initial pulse signal.

[0061] The sliced signal b0 can be input from the second slicing circuit 203 to the second weighting unit 202. The second weighting unit 202 can assign a weight to the sliced signal b0 to obtain a weighted signal b0. The amplitude A2 of the sliced signal b0 and the amplitude A4 of the weighted signal b0 satisfy: A b0 = W b0 * A2, -1 < W b0 < 0.

[0062] The weighted signal b0 can be input from the second weighting unit 202 to the second adder circuit 204. Additionally, the output terminal of the first adder circuit 104 can also input the superimposed pulse signal a to the second adder circuit 204. By superimposing the superimposed pulse signal a and the weighted signal b0 through the second adder circuit 204, a superimposed pulse signal b can be obtained.

[0063] During the target period a0, the signal of the initial pulse signal can be weakened by the weighted signal a0; during the target period b0, the signal of the initial pulse signal can be weakened by the weighted signal b0. The signal amplitudes of the finally output superimposed pulse signal b in the target period a0 and the target period b0 are both relatively small, making the change degree of the signal amplitude of the superimposed pulse signal b near the peak relatively large (i.e., the waveform slopes of the rising edge and the falling edge are steeper), thereby achieving the elimination of transient interference signals.

[0064] In some embodiments, the equalization circuit may further include an algorithm control circuit 301. The weights W1 assigned to the weighted signal a0 and the weight W2 assigned to the weighted signal b0 can be controlled by the algorithm control circuit 301. The parameters of the algorithm control circuit 301 can be determined by capturing and following the characteristics of single-event transient pulses. In one embodiment, the algorithm control circuit 301 is used to control the switches in the second weighting unit 202 and the first weighting unit 102. In the on state of the algorithm control circuit, the parameters in the weighting unit are given by the algorithm circuit, further realizing the adjustment of the signal amplitude and precisely fitting and subtracting with the rising edge or the falling edge. In the off state of the algorithm circuit, the parameters of the weighting circuit cannot accurately control the magnitude of the amplitude.

[0065] Figure 4 is a schematic structural diagram of another equalization circuit provided by an embodiment of the present application.

[0066] and Figure 3 The equalization circuit shown is different, Figure 4 The equalizing circuit shown may further include a first delay unit 101 , a third weight unit, a second delay unit 201 and a fourth weight unit.

[0067] The first delay unit 101 and the third weight unit may be connected in series between the first slicing circuit 103 and the input of the first adder circuit 104. The second delay unit 201 and the fourth weight unit may be connected in series between the input of the second slicing circuit 203 and the second adder circuit 204.

[0068] The first slicing circuit 103 can slice the initial pulse signal from the input port to obtain a slice signal a0. The duration t1 of the target time period a0 corresponding to the slice signal a0 is <T / (2*N a ), T is the period of the initial pulse signal, N a is the number of delay units provided between the first slicing circuit 103 and the first adder circuit 104. In some embodiments, t1 takes the value T / (5*N a )~2T / (5*N a In one embodiment, t1 takes the value T / (4*N a )~T / (3*N a ).

[0069] The slicing signal a0 can be input by the first slicing circuit 103 to the first delay unit 101. The first delay unit 101 delays the slicing signal a0 to generate a delayed signal a1 having time-domain delay information. The first delay unit 101 may include, for example, a trigger unit. The delayed signal a1 and the slicing signal a0 can be the same transient signal. The delayed signal a1 can correspond to a target period a1, which can be later than and continuous with the target period a0.

[0070] The third weighting unit can assign a weight to the delayed signal a1 to obtain a weighted signal a1. The amplitude A1 of the delayed signal a1 and the amplitude A1 of the weighted signal a1 a1 Satisfied: A a1 =W a1 *A1, -1 <W a1 <0.

[0071] The weight signal a1 can be input to the first adder circuit 104 by the third weight unit. In addition, the input port of the equalization circuit can also input the initial pulse signal to the first adder circuit 104, and the weight signal a0 can be input to the first adder circuit 104 by the first weight unit 102. The first adder circuit 104 superimposes the initial pulse signal, the weight signal a0, and the weight signal a1 to obtain a superimposed pulse signal a.

[0072] The second slicing circuit 203 can slice the superimposed pulse signal a from the first adder circuit 104 to obtain a slice signal b0. The duration t2 of the target time period b0 corresponding to the slice signal b0 is <T / (2*N b ), T is the period of the initial pulse signal, N b is the number of delay units provided between the second slicing circuit 203 and the second adder circuit 204. In some embodiments, t2 takes the value T / (5*N a )~2T / (5*N a In one embodiment, t2 takes the value T / (4*N a )~T / (3*N a ).

[0073] The slicing signal b0 can be input to the second delay unit 201 by the second slicing circuit 203. The second delay unit 201 delays the slicing signal b0 to obtain a delayed signal b1. The delayed signal b1 can correspond to the target period b1, which can be later than the target period b0 and continuous with the target period b0.

[0074] The fourth weighting unit can assign a weight to the delayed signal b1 to obtain a weighted signal b1. The amplitude B1 of the delayed signal b1 and the amplitude B of the weighted signal b1 b1 Satisfied: B b1 =W b1 *B1, -1 <W b1 <0.

[0075] The weight signal b1 can be input to the second adder circuit 204 by the fourth weight unit. In addition, the output end of the first adder circuit 104 can also input the superimposed pulse signal a to the second adder circuit 204, and the weight signal b0 can be input to the second adder circuit 204 by the second weight unit 202. The superimposed pulse signal a, the weight signal b0, and the weight signal b1 are superimposed by the second adder circuit 204 to obtain the superimposed pulse signal b.

[0076] In target time periods a0 and a1, the initial pulse signal can be weakened by weight signals a0 and a1, respectively; in target time periods b0 and b1, the initial pulse signal can be weakened by weight signals b0 and b1, respectively. The signal amplitudes of the superimposed pulse signal b in target time periods a0, a1, b0, and b1 are all relatively small, resulting in a relatively large amplitude variation near the peak of the superimposed pulse signal b (i.e., steeper slopes on the rising and falling edges), thereby eliminating transient interference signals.

[0077] Since the weight signal a0 and the weight signal a1 can be assigned different weight values, respectively, the weight signal b0 and the weight signal b1 can be assigned different weight values, respectively, so that the signal near the peak can be adjusted to different degrees.

[0078] When the weight signal a0 and the weight signal a1 correspond to the rising edge part, since the weight signal a1 is closer to the peak, the weight signal a0 is assigned a weight value W a0 The weight value W assigned to the weight signal a1 a1 Satisfy: 0>W a0 >W a1 >-1. Similarly, when the weight signal b0 and the weight signal b1 correspond to the rising edge part, since the weight signal b0 is closer to the peak, the weight value W assigned to the weight signal b0 is b0 The weight value W assigned to the weight signal b1 b1 Satisfied: -1 <W b0 <W b1 <0.

[0079] In other embodiments provided in the present application, the balancing circuit may include a first delay unit 101 and a third weight unit, but not a second delay unit 201 and a fourth weight unit; or, the balancing circuit may include a second delay unit 201 and a fourth weight unit, but not a first delay unit 101 and a third weight unit.

[0080] Figure 5 This is a schematic structural diagram of another equalization circuit provided in an embodiment of the present application.

[0081] exist Figure 5 In the illustrated embodiment, the equalization circuit may include a plurality of delay units and a plurality of weight units, and the plurality of delay units and the plurality of weight units may correspond one to one.

[0082] like Figure 5 As shown, the equalization circuit may include a first slicing circuit, which is a slicing unit controlled by CLK0. The equalization circuit may also include a delay unit a1, a delay unit a2, and a delay unit a3 controlled by CLK. The delay unit a1, the delay unit a2, and the delay unit a3 may be connected in series in sequence to form a delay chain circuit a in the equalization circuit to form signals in different time domains. The equalization circuit may also include a weight unit Wa0, a weight unit Wa1, a weight unit Wa2, and a weight unit Wa3, which are respectively used to adjust the amplitude weight W a0 、W a1 、W a2 and W a3. Among them, the weight unit Wa0 is used to adjust the amplitude of the slicing signal a0 from the first slicing circuit, the weight unit Wa1 is used to adjust the amplitude of the delayed signal a1 from the delay unit a1, the weight unit Wa2 is used to adjust the amplitude of the delayed signal a2 from the delay unit a2, and the weight unit Wa3 is used to adjust the amplitude of the delayed signal a3 from the delay unit a3. The first adder circuit is used to receive signals from the input port of the equalization circuit, the weight unit Wa0, the weight unit Wa1, the weight unit Wa2 and the weight unit Wa3.

[0083] The equalizing circuit may include a second slicing circuit, which is a slicing unit controlled by CLK1. The equalizing circuit may also include a delay unit b1, a delay unit b2, a delay unit b3, and a delay unit b4 controlled by CLK. The delay unit b1, the delay unit b2, the delay unit b3, and the delay unit b4 may be connected in series in sequence to form a delay chain circuit b in the equalizing circuit. The equalizing circuit may also include a weight unit Wb0, a weight unit Wb1, a weight unit Wb2, a weight unit Wb3, and a weight unit Wb4, which are respectively used to adjust the amplitude weight W b0 、W b1 、W b2 、W b3 and W b4 . Among them, the weight unit Wb0 is used to adjust the amplitude of the slicing signal b0 from the second slicing circuit, the weight unit Wb1 is used to adjust the amplitude of the delayed signal b1 from the delay unit b1, the weight unit Wb2 is used to adjust the amplitude of the delayed signal b2 from the delay unit b2, the weight unit Wb3 is used to adjust the amplitude of the delayed signal b3 from the delay unit b3, and the weight unit Wb4 is used to adjust the amplitude of the delayed signal b4 from the delay unit b4. The second adder circuit is used to receive signals from the first adder circuit, the weight unit Wb0, the weight unit Wb1, the weight unit Wb2, the weight unit Wb3 and the weight unit Wb4, and output the signals through the output port of the equalizer circuit.

[0084] The weight units Wa0, Wa1, Wa2, Wa3, Wb0, Wb1, Wb2, Wb3, and Wb4 can be controlled by an algorithm control circuit. The algorithm control circuit can include an adaptive algorithm unit that provides algorithmic control for single-particle transient characteristics.

[0085] The signal after being adjusted by the weight chain is fed back to the first adder circuit and the second adder circuit, suppressing the rising edge and the falling edge of the disturbed signal, and finally achieving the suppression of the rising edge and the falling edge. Therefore, the solution provided by this application can solve the problem of inter-symbol interference caused by single-event transients in the aerospace space of the FPGA and reduce the bit error rate.

[0086] Figure 6 is a schematic structural diagram of an equalization circuit provided by an embodiment of this application. Different from Figure 3 the embodiment shown, the second slicing circuit 203 can be connected to the output end of the second adder circuit 204. The second weight unit 202 is connected in series between the second slicing circuit 203 and the output end of the second adder circuit 204.

[0087] As Figure 6 shown, the output end of the first adder circuit 104 can input a superimposed pulse signal a to the second adder circuit 204. The superimposed pulse signal a can be output through the output port of the equalization circuit. The second adder circuit 204 can also output the superimposed pulse signal a to the second slicing circuit 203. The second slicing circuit 203 can be used to slice the superimposed pulse signal a to obtain a sliced signal b0. The sliced signal b0 can correspond to a target time period b0 of a single pulse period. The target time period b0 can be, for example, the falling edge time period of a single period. The duration t2 of the target time period b0 < T / 2, where T is the period of the initial pulse signal.

[0088] The sliced signal b0 can be input from the second slicing circuit 203 to the second weight unit 202. The second weight unit 202 can assign a weight to the sliced signal b0 to obtain a weighted signal b0. The amplitude A2 of the sliced signal b0 and the amplitude A4 of the weighted signal b0 satisfy: A b0 = W b0 *A2, -1 < W b0 < 0. The weighted signal b0 can be input from the second weight unit 202 to the second adder circuit 204.

[0089] The output end of the first adder circuit 104 can also input a superimposed pulse signal c (the superimposed pulse signal c can be the Kth pulse signal of the superimposed pulse signal, K is a positive integer, and the superimposed pulse signal c has been processed by the first slicing unit and the first weight unit) to the second adder circuit 204. By superimposing the superimposed pulse signal c and the weighted signal b0 through the second adder circuit 204, a superimposed pulse signal d can be obtained. Specifically, by superimposing the part of the superimposed pulse signal c corresponding to the target time period b0 and the weighted signal b0, the superimposed pulse signal d can be obtained. The part of the superimposed pulse signal d corresponding to the target time period b0 can be weakened by the second slicing unit and the second weight unit. The superimposed pulse signal d can be output through the output port of the equalization circuit.

[0090] In the time period corresponding to the target time period a0, the signal of the initial pulse signal can be weakened by the weight signal a0 to obtain the superimposed pulse signal c; in the time period corresponding to the target time period b0, the superimposed pulse signal c can be weakened by the weight signal b0. In the time periods corresponding to the target time period a0 and the target time period b0, the signal amplitude of the superimposed pulse signal d finally output is relatively small, so that the signal amplitude change degree of the superimposed pulse signal d near the peak is relatively large (that is, the rising and falling edge waveform slopes are steeper), thereby achieving the elimination of transient interference signals. In addition, since the current pulse signal is corrected by pulse signals of other periods, it is beneficial to reduce the timeliness requirements of the equalization circuit.

[0091] Figure 7 This is a schematic structural diagram of another equalization circuit provided in an embodiment of the present application.

[0092] and Figure 6 The equalization circuit shown is different, Figure 4 The equalizing circuit shown may further include a first delay unit 101 , a third weight unit, a second delay unit 201 and a fourth weight unit.

[0093] The first delay unit 101 and the third weight unit may be connected in series between the first slicing circuit 103 and the input of the first adder circuit 104. The second delay unit 201 and the fourth weight unit may be connected in series between the input of the second slicing circuit 203 and the second adder circuit 204.

[0094] The first slicing circuit 103 can slice the initial pulse signal from the input port to obtain a slice signal a0. The slice signal a0 can be input by the first slicing circuit 103 to the first delay unit 101. The first delay unit 101 delays the slice signal a0 to obtain a delayed signal a1. The third weighting unit can assign a weight to the delayed signal a1 to obtain a weighted signal a1. The weighted signal a1 can be input by the third weighting unit to the first adder circuit 104. In addition, the input port of the equalization circuit can also input the initial pulse signal to the first adder circuit 104, and the weighted signal a0 can be input by the first weighting unit 102 to the first adder circuit 104. The initial pulse signal, the weighted signal a0, and the weighted signal a1 are superimposed by the first adder circuit 104 to obtain a superimposed pulse signal a.

[0095] The superimposed pulse signal a can be output through the output port of the equalizer circuit. The second adder circuit 204 can also output the superimposed pulse signal a to the second slicing circuit 203. The second slicing circuit 203 can slice the superimposed pulse signal a from the first adder circuit 104 to obtain a slice signal b0. The slice signal b0 can be input by the second slicing circuit 203 to the second delay unit 201. The second delay unit 201 delays the slice signal b0 to obtain a delayed signal b1. The fourth weighting unit can assign a weight to the delayed signal b1 to obtain a weighted signal b1. The weighted signal b1 can be input by the fourth weighting unit to the second adder circuit 204.

[0096] In addition, the output end of the first adder circuit 104 can also input the superimposed pulse signal c to the second adder circuit 204 (the superimposed pulse signal c can be the Kth pulse signal of the superimposed pulse signal, K is a positive integer, and the superimposed pulse signal c has been processed by the first slicing unit, the first weighting unit, the first delay unit, and the third weighting unit). The weight signal b0 can be input to the second adder circuit 204 by the second weighting unit 202. The superimposed pulse signal c, the weight signal b0, and the weight signal b1 are superimposed by the second adder circuit 204 to obtain a superimposed pulse signal d. The superimposed pulse signal d can be output through the output port of the equalizer circuit.

[0097] In the time periods corresponding to the target time period a0 and the target time period a1, the signal of the initial pulse signal can be weakened by the weight signal a0 and the weight signal a1 respectively; in the time periods corresponding to the target time period b0 and the target time period b1, the signal of the initial pulse signal can be weakened by the weight signal b0 and the weight signal b1. In the time periods corresponding to the target time period a0, the target time period a1, the target time period b0 and the target time period b1, the signal amplitude of the superimposed pulse signal d finally output is relatively small, so that the degree of change of the signal amplitude of the superimposed pulse signal d near the peak is relatively large (that is, the rising and falling edge waveform slopes are steeper), thereby achieving the elimination of transient interference signals. Since the current pulse signal is corrected by pulse signals of other periods, it is beneficial to reduce the timeliness requirements of the equalization circuit. Since the weight signal a0 and the weight signal a1 can be assigned different weight values ​​respectively, the weight signal b0 and the weight signal b1 can be assigned different weight values ​​respectively, so that the signal near the peak can be adjusted to different degrees.

[0098] Figure 8 This is a schematic structural diagram of another equalization circuit provided in an embodiment of the present application. Figure 8 The detailed description of the embodiment shown is given in Figure 5 The embodiment shown. Figure 5 The embodiment shown is slightly different in that the signal input source of the second slicing circuit may be a second adder circuit.

[0099] Since the single-particle transient is a time-varying interference signal randomly generated in space, its different pulse widths and amplitudes have different degrees of aggravation of inter-symbol interference. Figures 1 to 8 The weighting method assigned by the weight unit in the equalization circuit shown in the figure reasonably regulates the slice signal within the local time domain, so that the equalization circuit can better exert the pulse regulation performance, and ultimately achieves the suppression of transient single-particle inter-symbol interference in the rising edge part. Figure 9 This is a schematic flowchart of a weight adjustment method provided in an embodiment of the present application.

[0100] 110 , determining a target weight, where the target weight is a weight tentatively assigned by a target weight unit in the balancing circuit.

[0101] 120. Determine whether the first processed pulse signal and the second processed pulse signal can both correspond to correct data results, wherein the first processed pulse signal is a pulse signal obtained after the equalization circuit processes the first initial pulse signal according to the target weight, and the first initial pulse signal is a pulse signal that has undergone a single-particle transient impact effect; the second processed pulse signal is a pulse signal obtained after the equalization circuit processes the second initial pulse signal according to the target weight, and the second initial pulse signal is a pulse signal that has not undergone a single-particle transient impact effect.

[0102] If yes, execute 130 to control the target weight unit to assign the target weight; if not, re-execute step 110, and the newly determined weight is different from the previously determined weight.

[0103] In some embodiments, the algorithm uses the least mean square (LMS) algorithm to implement iterative updates of parameters of each order. The LMS algorithm is proposed based on the steepest descent algorithm and is an adaptive filtering algorithm that includes two basic processes: a filtering process and an adaptive process. During the filtering process, the adaptive equalizer compares the expected output value with the actual output value to obtain an estimated error signal. During the adaptive process, the system automatically adjusts the equalizer's own parameters based on the mean square error (MSE) minimization criterion. Adaptive filtering is to move the weight coefficient toward the minimum point at the bottom of the surface, and to achieve the optimal filtering by reaching the bottom minimum point. In practice, because the mean square error LMS algorithm is difficult to implement a linear correlator, the SS-LMS algorithm is usually used, that is, only the polarity information of the error signal is extracted to automatically capture and follow the changes in single-particle transients, and then dynamically change the correction factor of the control end through this LMS algorithm.

[0104] Although the present invention is disclosed above in terms of preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make possible changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on the scope defined by the claims of the present invention.

Claims

1. An equalizing circuit, characterized in that: include: A first slicing circuit (103) is used to slice the initial pulse signal to obtain a first slicing signal; a first weighting unit (102) connected to the first slicing circuit (103), the first weighting unit (102) being used to assign a first weight to the first slicing signal to obtain a first weighted signal, wherein the first weight is a negative value greater than -1; a first adder circuit (104), wherein an input end of the first adder circuit (104) is connected to the first weight unit (102), and the first adder circuit (104) is used to superimpose the initial pulse signal and the first weight signal to obtain a first superimposed pulse signal; a second slicing circuit (203) for slicing the first superimposed pulse signal to obtain a second slicing signal, wherein the first slicing signal and the second slicing signal are respectively a rising edge signal and a falling edge signal of the initial pulse signal; a second weighting unit (202) connected to the second slicing circuit (203), the second weighting unit (202) being used to assign a second weight to the second slicing signal to obtain a second weighted signal, wherein the second weight is a negative value greater than -1; A second adder circuit (204) has an input end connected to the output end of the first adder circuit (104) and the second weight unit (202), and the second adder circuit (204) is used to superimpose the first superimposed pulse signal and the second weight signal, and output a second superimposed pulse signal.

2. The equalizing circuit according to claim 1, wherein: The output end of the first adder circuit (104) is connected to the second slicing circuit (203), and the first slicing signal and the second slicing signal correspond to the same period.

3. The equalizing circuit according to claim 1, wherein: The output end of the second adder circuit (204) is connected to the second slicing circuit (203), the first slicing signal corresponds to a rising edge signal of a first cycle, the second slicing signal corresponds to a falling edge signal of a second cycle, and the second cycle is earlier than the first cycle; and the superposition of the first superimposed pulse signal and the second weight signal includes: superimposing the falling edge signal corresponding to the first cycle in the first superimposed pulse signal with the second weight signal.

4. The equalizing circuit according to any one of claims 1 to 3, characterized in that: The balancing circuit further includes: A first delay unit (101) and a third weight unit (105), wherein the first delay unit (101) and the third weight unit (105) are connected in series between the first slicing circuit (103) and the first adder circuit (104), wherein the first delay unit (101) is used to delay the first slicing signal to obtain a first delayed signal, and the third weight unit (105) is used to assign a third weight to the first delayed signal to obtain a third weight signal, wherein the third weight is a negative value greater than -1, and the first adder circuit (104) is used to superimpose the initial pulse signal, the first weight signal and the third weight signal to obtain the first superimposed pulse signal.

5. The equalizing circuit according to claim 4, characterized in that: The first slicing signal corresponds to a rising edge signal, and the first weight is greater than the third weight.

6. The equalizing circuit according to claim 4, wherein: A plurality of delay units and a plurality of weight units are provided between the first slicing circuit (103) and the first adder circuit (104), and the duration t1 of the first slicing signal satisfies: t1 <T / (2*N a ), T is the period of the initial pulse signal, N a is the number of delay units provided between the first slicing circuit (103) and the first adder circuit (104).

7. The equalizing circuit according to any one of claims 1 to 3, characterized in that: The balancing circuit further includes: A second delay unit (201) and a fourth weight unit (205), wherein the second delay unit (201) and the fourth weight unit (205) are connected in series between the second slicing circuit (203) and the second adder circuit (204), the second delay unit (201) is used to delay the second slicing signal to obtain a second delayed signal, the fourth weight unit (205) is used to assign a fourth weight to the second delayed signal to obtain a fourth weight signal, the fourth weight being a negative value greater than -1, and the second adder circuit (204) is used to superimpose the first superimposed pulse signal, the second weight signal and the fourth weight signal to obtain the second superimposed pulse signal.

8. The equalizing circuit according to claim 7, wherein: The second slicing signal corresponds to a falling edge signal, and the second weight is less than the fourth weight.

9. The equalizing circuit according to claim 7, wherein: A plurality of delay units and a plurality of weight units are provided between the second slicing circuit (203) and the second adder circuit (204), and the duration t2 of the second slicing signal satisfies: t2 <T / (2*N b ), T is the period of the initial pulse signal, N b is the number of delay units provided between the second slicing circuit (203) and the second adder circuit (204).

10. An electronic device, characterized in that: The electronic device includes the equalizer circuit according to any one of claims 1 to 9.

11. A weight adjustment method, characterized in that: The method is applied to the equalizing circuit according to any one of claims 1 to 9, wherein the weight is a weight assigned by a target weight unit, and the target weight unit is any weight unit in the equalizing circuit; the method comprises: Step 1: Determine the target weight, which is a tentatively assigned weight; Step 2: Determine whether both the first processed pulse signal and the second processed pulse signal can correspond to correct data results, wherein the first processed pulse signal is a pulse signal obtained by the equalization circuit processing the first initial pulse signal according to the target weight, and the first initial pulse signal is a pulse signal that has undergone a single event transient impact effect; the second processed pulse signal is a pulse signal obtained by the equalization circuit processing the second initial pulse signal according to the target weight, and the second initial pulse signal is a pulse signal that has not undergone a single event transient impact effect; If yes, execute step 3: control the target weight unit to assign the target weight; If not, step 1 is executed again, and the newly determined target weight is different from the previously determined target weight.

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