Video processing circuitry

Abstract

A video processing circuit includes a first buffer and a computing circuit. A first computing circuit generates a first processing result for each of a plurality of consecutive blocks by performing a first one-dimensional processing operation on each of the plurality of consecutive blocks in a first direction different from a second direction before performing a second one-dimensional processing operation on the plurality of consecutive blocks in the second direction. A plurality of first processing results of the plurality of consecutive blocks are further stored into the first buffer.

Description

[0001] CROSS REFERENCE

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 247,817, filed September 24, 2021, which is hereby incorporated by reference in its entirety. TECHNICAL FIELD

[0003] The present disclosure relates to video processing, and more particularly, to a video processing circuit for performing size-based parallel input and parallel output computations (e.g., transform or inverse transform) with bubble cycle reduction. BACKGROUND

[0004] Conventional video coding standards typically employ block-based coding techniques to exploit spatial and temporal redundancies. For example, a basic approach is to divide an entire source picture into blocks, perform intra / inter prediction for each block, perform transform on the residual of each block, and perform quantization and entropy coding. In addition, a reconstructed picture is generated in the encoding loop to provide reference pixel data for encoding subsequent blocks. For certain video coding standards, an in-loop filter can be used to enhance the image quality of the reconstructed picture. A video decoder is used to perform inverse operations of the video encoding operations performed by a video encoder. For example, a video encoder employs a transform circuit and an inverse transform circuit, and a video decoder employs the inverse transform circuit. The transform circuit is used to transform residual data from a spatial domain to a frequency domain. The inverse transform circuit is used to transform residual data from a frequency domain to a spatial domain. Taking a discrete cosine transform (DCT) as an example, a forward DCT (FDCT) of an NxN block of samples is given by Y = AXA T , and an inverse DCT (IDCT) is given by X = A T YA, where X is a matrix of samples, Y is a matrix of coefficients, and A is an NxN transform matrix. The elements of A are:

[0005]

[0006] Consequently, a conventional FDCT / IDCT hardware implementation can include two stages, where the first stage is used for one of horizontal one-dimensional (1D) transform and vertical 1D transform, and the second stage is used for the other one of horizontal 1D transform and vertical 1D transform. In order to save computation resources, a scheme of reusing a transform kernel in both the first stage and the second stage is usually used. However, such a conventional architecture of reusing one transform kernel suffers from bubble cycles caused by switching between the first stage and the second stage, and bubble cycles caused by switching from a small block to a large block. As a result, the performance of the conventional architecture is significantly degraded when a series of small blocks and / or blocks with frequent block size changes need to be processed. SUMMARY

[0007] It is an object of the present application to provide a video processing circuit for performing size-based parallel input and parallel output computation (e.g., transform or inverse transform) and reducing bubble cycles.

[0008] According to a first aspect of the present application, an exemplary video processing circuit is disclosed. The exemplary video processing circuit includes a first buffer and a first computation circuit. The first computation circuit is arranged to generate a first processing result for each of a plurality of consecutive blocks by performing a first one-dimensional processing operation in a first direction different from a second direction on each of the plurality of consecutive blocks before performing a second one-dimensional processing operation in the second direction on the plurality of consecutive blocks, and is further arranged to store a plurality of the first processing results of the plurality of consecutive blocks into the first buffer.

[0009] According to a second aspect of the present application, an exemplary video processing circuit is disclosed. The exemplary video processing circuit includes a computation circuit and a buffer. The computation circuit is arranged to generate a processing result for each of a plurality of consecutive blocks by performing a one-dimensional processing operation in one direction on each of the plurality of consecutive blocks. The buffer is coupled to the computation circuit. Input data of the buffer is pushed into the buffer in a serial manner. All data of a complete queue included in each of the plurality of consecutive blocks is popped out of the buffer and transmitted to the computation circuit in a parallel manner. The buffer concurrently buffers data belonging to different queues.

[0010] According to a third aspect of the present application, an exemplary video processing circuit is disclosed. The exemplary video processing circuit includes a computation circuit and a buffer. The computation circuit is arranged to generate a processing result for each of a plurality of consecutive blocks by performing a one-dimensional processing operation in one direction on each of the plurality of consecutive blocks. The buffer is coupled to the computation circuit. All data of a complete queue included in each of the plurality of consecutive blocks is produced from the computation circuit and pushed into the buffer in a parallel manner. Data buffered in the buffer is popped out of the buffer in a serial manner. The buffer concurrently buffers data belonging to different queues.

[0011] These and other objects of the present application will no doubt become apparent to those of ordinary skill in the art after reading the following detailed description of the preferred embodiments that are illustrated in the various drawing figures. BRIEF DESCRIPTION OF DRAWINGS

[0012] Figure 1 is a block diagram illustrating a video encoding apparatus according to an embodiment of the present application.

[0013] Figure 2 is a block diagram illustrating a video decoding apparatus according to an embodiment of the present application.

[0014] Figure 3 is a block diagram illustrating a SPIPO computation process according to an embodiment of the present application.

[0015] Figure 4 is a schematic diagram of a video processing circuit with a high performance serial architecture according to an embodiment of the present application.

[0016] Figure 5 is a flowchart illustrating a stage decision making method according to an embodiment of the present application.

[0017] Figure 6 is a timing diagram of a conventional design that suffers from performance degradation due to bubble cycle problem caused by switching between a first stage and a second stage.

[0018] Figure 7 is a timing diagram of a video processing circuit as shown in Figure 6 .

[0019] Figure 8 is a schematic diagram of another video processing circuit with a high performance serial architecture according to an embodiment of the present application.

[0020] Figure 9 is a diagram showing one example of a SIVO buffer as shown in Figure 8 .

[0021] Figure 10 is a diagram showing one example of a VISO buffer as shown in Figure 8 .

[0022] Figure 11 is a flowchart illustrating a data transfer method according to an embodiment of the present application.

[0023] Figure 12 is a timing diagram of a conventional design that suffers from performance degradation due to bubble cycle problem caused by switching from a small block to a large block.

[0024] Figure 13 is a timing diagram of a video processing circuit as shown in Figure 12 .

[0025] Figure 14 is a schematic diagram of a video processing circuit with high performance parallel architecture according to an embodiment of the present application. DETAILED DESCRIPTION

[0026] Certain terms are used throughout the following description and claims which refer to particular components. As one skilled in the art will appreciate, electronic equipment manufacturers can refer to a component by different names. This document does not intend to distinguish between components that differ in name but not in function. In the following description and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "including, but not limited to...." Also, the term "couple" is intended to mean either an indirect or direct electrical connection. Thus, if one device is coupled to another device, that connection can be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.

[0027] Figure 1 is a diagram illustrating a video encoding apparatus according to an embodiment of the present application. The video encoding apparatus 100 is a hardware circuit for compressing raw video data to generate compressed video data. It is noted that, Figure 1 the video encoder architecture shown in FIG. 1. Figure 1 is for illustration purposes only and is not meant to limit the present application. For example, the architecture of the video encoding device 100 can vary according to the encoding standard. The video encoding apparatus 100 encodes a frame IMG to generate a bitstream BS for transmission. As shown in Figure 1 , the video encoding apparatus 100 includes a residual calculation circuit 101, a transform circuit (labeled "T") 102, a quantization circuit (labeled "Q") 103, an entropy encoding circuit (labeled "Entropy Encoding") 104, an inverse quantization circuit (labeled "IQ") 105, an inverse transform circuit (labeled "IT") 106, a reconstruction circuit 107, a loop filter (e.g., a deblocking filter 108, labeled "DBF"), a reference frame buffer 109, an inter prediction circuit 110 (which includes a motion estimation circuit (labeled "ME") 111 and a motion compensation circuit (labeled "MC") 112), an intra prediction circuit (labeled "IP") 113, and an intra / inter mode selection switch 114. One or both of the transform circuit 102 and the inverse transform circuit 106 can be implemented by the proposed size-based parallel input and parallel output (SPIPO) computation architecture. Since the present application focuses on the SPIPO computation (e.g., transform and / or inverse transform), and one skilled in the art should readily understand the principles of the remaining functional blocks in the video encoding apparatus 100, the video encoding apparatus 100 is further described for brevity and is omitted here.

[0028] Figure 2is a block diagram illustrating a video decoding apparatus according to an embodiment of the present application. The video decoding apparatus 200 is a hardware circuit for decompressing encoded video data carried by a bitstream BS to generate decompressed video data. It is noted that, Figure 2 The video decoder architecture shown in FIG. 2 is for illustration only and is not meant to limit the present application. For example, the architecture of the video decoding apparatus 200 can vary according to the encoding standard. Referring to Figure 2 The video decoding apparatus 200 can include an entropy decoding circuit (e.g., variable length decoding circuit 202, labeled "VLD"), an inverse scan circuit (labeled "IS") 204, an inverse quantization circuit (labeled "IQ") 206, an inverse transform circuit (labeled "IT") 208, a reconstruction circuit 210, a loop filter (e.g., a deblocking filter 212, labeled "DBF"), a decoded picture buffer (DPB) 214, an intra prediction circuit (labeled "IP") 216, a motion vector calculation circuit (labeled "MV Calc") 218, a motion compensation circuit (labeled "MC") 220, and an inter / intra selection circuit (labeled "Inter / Intra Sel") 222. The inverse transform circuit 208 can be implemented by the proposed SPIPO computing architecture. Since the present application focuses on SPIPO computation (e.g., transform and / or inverse transform), and one skilled in the art should readily understand the principles of the remaining functional blocks in the video decoding apparatus 200, the video decoding apparatus 200 is further described for brevity and is omitted here.

[0029] Figure 3 is a diagram illustrating an SPIPO computing process according to an embodiment of the present application. The transform circuit 102 can follow the SPIPO computing process. Similarly, the inverse transform circuit 106 / 208 can also follow the SPIPO computing process. The SPIPO computing process includes two stages, including a first stage performed for one of horizontal one-dimensional transform and vertical one-dimensional transform, and a second stage performed for the other one of horizontal one-dimensional transform and vertical one-dimensional transform. One picture / frame can be divided into multiple coding units (CUs), each CU can be divided into multiple transform units (TUs), and each TU can be composed of multiple transform blocks (TBs). For example, one TU can be composed of one luma TB and two chroma TBs. A line of transform blocks in a first direction (e.g., a column in vertical direction) is processed by the first stage, and a line of transform blocks in a second direction (e.g., a row in horizontal direction) is processed by the second stage. Accordingly, a transposition (TM) buffer 302 is used to buffer the output data of the first stage (e.g., vertical one-dimensional transform) and provide transposed data as input data of the second stage (e.g., horizontal one-dimensional transform).

[0030] Figure 4is a schematic diagram of a video processing circuit with a high performance serial architecture according to embodiments of the present disclosure. For example, the transform circuit 102 of the video encoding device 100 can be implemented by the video processing circuit 400. As another example, the inverse transform circuit 106 of the video encoding device 100 can be implemented by the video processing circuit 400. As another example, the inverse transform circuit 208 of the video decoding device 200 can be implemented by the video processing circuit 400. According to the high performance serial architecture, the video processing circuit 400 includes a SPIPO computation circuit 402, a stage decision making switch circuit 404, and a ring first in, first output (FIFO)™ buffer 406. The SPIPO computation circuit 402 is a transform kernel that can process a transform from a spatial domain to a frequency domain or an inverse transform from the frequency domain to the spatial domain. The SPIPO computation circuit 402 can include multiple transform logic circuits (labeled as “transform logic”) 408_1-408_n for multiple codec standards, respectively, an input internal buffer 407, and an output internal buffer 409. For example, the transform logic circuit 408_1 is designed to process a transform / inverse transform that conforms to the Versatile Video Coding (VVC) standard (also known as the H.266 standard), and the transform logic circuit 408_n is designed to process a transform / inverse transform that conforms to a different video coding standard.

[0031] To solve the bubble cycle problem due to switching between the first stage and the second stage, the SPIPO computation circuit 402 is designed to support processing a queue of consecutive blocks (i.e., consecutive TBs) in the same stage, the ring FIFO TM buffer 406 is designed to support buffering the first stage processing results of consecutive blocks (i.e., consecutive TBs), and / or the stage decision switching circuit 404 is designed to support adaptive switching between the first stage processing and the second stage processing. In the present embodiment, the SPIPO computation circuit 402 is used to process a first one-dimensional processing operation in a first direction (e.g., a first stage transform in the vertical direction), and reused to process a second one-dimensional processing operation in a second direction (e.g., a second stage transform in the horizontal direction) to save computation resources. Before performing the second stage processing operation (e.g., a horizontal one-dimensional transform) on a plurality of consecutive blocks (e.g., BLK0, BLK1, and BLK2) in the second direction (e.g., the horizontal direction), the SPIPO computation circuit 402 generates the first stage processing results by performing the first one-dimensional processing operation (e.g., a first stage transform in the vertical direction) for each of the consecutive blocks (e.g., BLK0, BLK1, and BLK2), and stores the plurality of first stage processing results of the consecutive blocks (e.g., BLK0, BLK1, and BLK2) into the ring FIFO TM buffer 406. Regarding the ring FIFO TM buffer 406, a write pointer PTR W can be updated to point to a next address where new data should be stored, and a read pointer PTR R can be updated to point to a next address where stored data should be read. The buffer size of the ring FIFO TM buffer 406 can be set appropriately to accommodate the first stage processing results of a transform block with the largest transform block size (e.g., 64x64). According to the VVC standard, the possible width and height of a transform block range from 1, 2, 4, 8, 16, 32 to 64. Thus, when the consecutive blocks (e.g., BLK0, BLK1, and BLK2) are small blocks (e.g., 4x4 blocks), the ring FIFO TM buffer 406 can be used to store the first stage processing results of the consecutive blocks (e.g., BLK0, BLK1, and BLK2) before the first stage processing results are transposed and output to the SPIPO computation circuit 402 for the ongoing second stage processing.

[0032] The stage decision switching circuit 404 controls the adaptive switching of the input data source between the previous stage and the ring FIFO TM buffer 406. In the case that the stage decision switching circuit 404 selects the previous stage as the input data source of the SPIPO computation circuit 402, the SPIPO computation circuit 402 initiates the first stage for processing the non-transposed data from the previous stage to generate the first stage processing results of the consecutive blocks and output them to the ring FIFO TM buffer 406. In another case that the stage decision switching circuit 404 selects the ring FIFO TM buffer 406 as the input data source of the SPIPO computation circuit 402, the SPIPO computation circuit 402 initiates the second stage for processing the transposed data from the ring FIFO TM buffer 406 to provide the next stage of the output data with the consecutive blocks. For example, when the video processing circuit 400 is used as the transform circuit 102, the previous stage is the residual computation circuit 101 and the next stage is the quantization circuit 103. For another example, when the video processing circuit 400 is used as the inverse transform circuit 106, the previous stage is the inverse quantization circuit 105 and the next stage is the quantization circuit 107. For yet another example, when the video processing circuit 400 is used as the inverse transform circuit 208, the previous stage is the inverse quantization circuit 206 and the next stage is the reconstruction circuit 210.

[0033] In this embodiment, the stage decision switching circuit 404 can include a look-ahead buffer 410 arranged to buffer the information of the consecutive blocks (e.g., BLK0, BLK1 and BLK2) provided from the previous stage. The information stored into the look-ahead buffer 410 by the previous stage can include the number of the consecutive blocks (e.g., BLK0, BLK1 and BLK2) ready to be transferred from the previous stage to the video processing circuit 400, the size of each block. The stage decision switching circuit 404 refers to the information in the look-ahead buffer 410 to adaptively select one of the non-transposed data (which is from the previous stage) and the transposed data (provided by the ring FIFO TM buffer 406) as the input data of the SPIPO computation circuit 402.

[0034] Figure 5 is a flowchart illustrating a stage decision making method according to an embodiment of the present application. The stage decision switching circuit 404 can employ the stage decision making method. As long as the results are substantially the same, it is not necessary to follow the order of the stages as shown in Figure 5The exact order of performing the steps is shown. Initially, the stage decision switching circuit 404 enters an idle state (step 502). At step 504, the stage decision switching circuit 404 checks whether the look-ahead buffer 410 is empty. If yes, the stage decision switching circuit 404 enters the idle state to wait for information provided from the previous stage. If no, the stage decision switching circuit 404 selects the non-transposed data transmitted from the previous stage as the input data of the SPIPO computation circuit 402, so that the first stage transformation is started at the SPIPO computation circuit 402 (step 506). At step 508, the stage decision switching circuit 404 checks whether the ring FIFO TM buffer 406 is full or the look-ahead buffer 410 is empty. If the ring FIFO TM buffer 406 is full, it means that the ring FIFO TM buffer 406 cannot buffer more first stage processing results, the SPIPO computation circuit 402 should suspend the first stage transformation and enable the second stage transformation to process any first stage processing results buffered in the ring FIFO TM buffer 406. If the look-ahead buffer 410 is empty, it means that there is no non-transposed data waiting for the first stage transformation at this time, the SPIPO computation circuit 402 should end the first stage transformation and enable the second stage transformation to process any first stage processing results buffered in the ring FIFO TM buffer 406. At step 510, the stage decision switching circuit 404 selects the transposed data transmitted from the ring FIFO TM buffer 406 as the input data of the SPIPO computation circuit 402, so that the 2ndstage transformation is enabled at the SPIPO computation circuit 402. At step 512, the stage decision switching circuit 404 checks whether the ring FIFO TM buffer 406 is empty. If the ring FIFO TM buffer 406 is not empty, the stage decision switching circuit 404 continues to transfer the transposed data from the ring FIFO TM buffer 406 to the SPIPO computation circuit 402. If the ring FIFO TM buffer 406 is empty, it means that each first stage processing result in the ring FIFO TM buffer 406 has been transposed and output to the SPIPO computation circuit 402 for the second stage transformation. Therefore, the flow proceeds to step 504.

[0035] After storing the first-stage processing result of the block into the ring FIFO™ buffer 406, the ring FIFO™ buffer 406 requires some clock cycles to process the first-stage processing result in order to prepare and output transposed data for the second-stage transformation. Since the SPIPO calculation circuit 402 can apply the first-stage transformation to consecutive blocks, the clock cycles required by the ring FIFO™ buffer 406 to prepare the transposed data of the first block of the consecutive block can be hidden within the clock cycles required by the SPIPO calculation circuit 402 to perform the first-stage transformation on other blocks in the consecutive block, thus solving the bubble cycle problem caused by switching between the 4x4 first and second stages. Please refer to the figure for details. Figure 6 , 7 . Figure 6 This is a timing diagram of a traditional design that suffers from performance degradation due to bubble cycle issues caused by the switching between the first and second stages. Figure 7 yes Figure 4 The timing diagram of the video processing circuit 400 is shown. Compared with conventional designs, the proposed high-performance serial architecture enables the conversion circuit 102 and / or the inverse conversion circuit 106 / 208 to achieve better performance due to the reduction of the bubble period.

[0036] Figure 8 This is a schematic diagram of another video processing circuit with a high-performance serial architecture according to an embodiment of the present invention. For example, the conversion circuit 102 of the video encoding device 100 can be implemented by the video processing circuit 800. As another example, the inverse conversion circuit 106 of the video encoding device 100 can be implemented by the video processing circuit 800. As yet another example, the inverse conversion circuit 208 of the video decoding device 200 can be implemented by the video processing circuit 800. The main difference between video processing circuits 400 and 800 is that video processing circuit 800 further includes a serial input variable output (SIVO) buffer 802 and a variable serial output (VISO) buffer 804.

[0037] SIVO buffer 802 is coupled between stage decision switching circuit 404 and SPIPO calculation circuit 402. The output data of stage decision switching circuit 404 is serially pushed into SIVO buffer 802 at a constant throughput, and all data included in the complete queue of each consecutive block (e.g., BLK0, BLK2, and BLK3) is popped from SIVO buffer 802 and transmitted in parallel to SPIPO calculation circuit 402.

[0038] The VISO buffer 804 is coupled between the SPIPO computation circuit 402 and the ring FIFO TM buffer 406, and also coupled between the SPIPO computation circuit 402 and the next stage. The SPIPO computation circuit 402 generates and pushes all data of a complete queue contained in each consecutive block (e.g., BLK0, BLK2, and BLK2) into the VISO buffer 804 in a parallel manner, and buffers the data in the VISO buffer 804 to pop out from the VISO buffer 804 to the next stage or the ring FIFO TM buffer 406 in a serial manner at a constant throughput.

[0039] To solve the bubble cycle problem caused by switching from small blocks to large blocks, the SIVO buffer 802 is designed to have a large enough buffer size to buffer data belonging to different queues at the same time, and the VISO buffer 804 is designed to have a large enough buffer size to buffer data belonging to different queues at the same time. In particular, the spare buffer size of the SIVO buffer 802 / VISO buffer 804 can be used to reduce the bubble cycle. Figure 9 is a diagram illustrating Figure 8 an example of the SIVO buffer 802 shown. Figure 10 is a diagram illustrating Figure 8 an example of the VISO buffer 804 shown. The SPIPO computation circuit 402 needs to wait for a complete queue (e.g., a complete row or a complete column) to start computation, and generates and outputs the processing result of the complete queue, where in VVC one possible width and height, the range of transform block can be from 1, 2, 4, 8, 16, 32 to 64. In the case of a transform block size of 4x4, when all 4 samples are ready in the SIVO buffer 802, the SIVO buffer 802 outputs the 4 samples (non-transposed data or transposed data) to the SPIPO computation circuit 402 in a parallel manner, and when all 4 samples are ready in the SPIPO computation circuit 402, the SPIPO computation circuit 402 outputs the 4 samples to the VISO buffer 804 in a parallel manner. In another case of a transform block size of 8x8, when all 8 samples are ready in the SIVO buffer 802, the SIVO buffer 802 sends the 8 samples (non-transposed data or transposed data) to the SPIPO computation circuit 402 in a parallel manner, and when all 8 samples are ready in the SPIPO computation circuit 402, the SPIPO computation circuit 402 outputs the 8 samples to the VISO buffer 804 in a parallel manner. The spare buffer size in the SIVO buffer 802 can be used to buffer samples of other queues. Similarly, the spare buffer size in the VISO buffer 804 can be used to buffer samples of other queues.

[0040] Figure 11This is a flowchart illustrating a data transmission method according to an embodiment of the present invention. If the results are substantially the same, then it is not necessary to follow... Figure 11 These steps are executed in the exact order shown. Initially, SIVO buffer 802 and VISO buffer 804 enter an idle state (step 1102). In step 1104, the stage decision switching circuit 404 pushes data into SIVO buffer 802 at a constant throughput. In step 1106, SIVO buffer 802 determines whether it has data in at least one variable-size queue. If SIVO buffer 802 does not have data in at least one variable-size queue, the process proceeds to step 1104. If SIVO buffer 802 has data in at least one variable-size queue, SIVO buffer 802 pops a complete variable-size queue of data and pushes a complete variable-size queue of data into SPIPO calculation circuit 402 for either first-stage processing or second-stage processing (step 1108). In step 1110, SPIPO calculation circuit 402 generates processing data for a complete variable-size queue and pushes the processing data for the complete variable-size queue into VISO buffer 804.

[0041] After the SPIPO calculation circuit 402 generates the second-stage processing result of the last complete queue of the current block, it needs to wait for the first complete queue of the next block to be ready, and the ring FIFO™ buffer 406 needs to wait for the first-stage processing result of the first complete queue of the next block to be ready. With the help of the SIVO buffer 802 and / or the VISO buffer 804, data preparation can be hidden within the clock cycles required for the SPIPO calculation circuit 402 to perform the first-stage and second-stage transformations. Please refer to the figure for details. Figure 12 , 13 . Figure 12 This is a timing diagram of a traditional design that suffers from performance degradation due to bubble cycle issues caused by switching from small to large blocks. Figure 13 yes Figure 8 The timing diagram of the video processing circuit 800 is shown. Compared with the conventional design, the proposed high-performance serial architecture enables the conversion circuit 102 and / or the inverse conversion circuit 106 / 208 to have better performance due to the reduction of the bubble period.

[0042] The video decoder can employ a high-performance serial architecture video processing circuit 800 to achieve 4K@60FPS (frames per second). For some video applications requiring 8K@30FPS, this invention proposes a high-performance parallel architecture.

[0043] Figure 14is a schematic diagram of a video processing circuit with a high-performance parallel architecture according to an embodiment of the present application. For example, the transform circuit 102 of the video encoding apparatus 100 can be implemented by the video processing circuit 1400. For another example, the inverse transform circuit 106 of the video encoding apparatus 100 can be implemented by the video processing circuit 1400. For yet another example, the inverse transform circuit 208 of the video decoding apparatus 200 can be implemented by the video processing circuit 1400. Compared with the high-performance serial architecture that shares one common SPIPO computation circuit 402 for both the first-stage transform and the second-stage transform, the high-performance parallel architecture employs two SPIPO computation circuits, each of which is dedicated to the first-stage transform and the second-stage transform, respectively. As shown in FIG. 14A, the video processing circuit 1400 includes two SPIPO computation circuits 402_1, 402_2, each of which has the same architecture as the SPIPO computation circuit 402, a ring FIFO TM buffer 406, two SIVO buffers 802_1, 802_2, each of which has the same architecture as the SIVO buffer 802, and two VISO buffers 804_1, 804_2, each of which has the same architecture as the VISO buffer 804. Figure 14

[0044] To solve the bubble cycle problem due to switching between the first stage and the second stage, each of the SPIPO computation circuits 402_1, 402_2 is designed to support processing consecutive blocks (i.e., consecutive TBs) of one queue in the same stage in succession, and the ring FIFO TM buffer 406 is designed to support buffering the first-stage processing results of consecutive blocks (i.e., consecutive TBs). To solve the bubble cycle problem due to switching from small blocks to large blocks, each of the SIVO buffers 802_1, 802_2 is designed to have a buffer size large enough to buffer data belonging to different queues at the same time, and each of the VISO buffers 804_1, 804_2 is designed to have a buffer size large enough to buffer data belonging to different queues at the same time. Since those skilled in the relevant art can easily understand the technical features of the video processing circuit 1400 after reading the paragraphs for the video processing circuits 400 and 800, further description is omitted here for brevity.

[0045] In the above embodiments, the video processing circuit (e.g., a transform circuit or an inverse transform circuit) can employ all the techniques proposed by the present application to solve both the bubble cycle problems. However, these are for illustrative purposes only and are not meant to limit the present application. For example, the video processing circuit (e.g., a transform circuit or an inverse transform circuit) can employ some of the techniques proposed by the present application to solve only the bubble cycle problems. These alternative designs all fall within the scope of the present application.

[0046] ​Those skilled in the art will readily observe that numerous modifications and changes in the devices and methods can be made without departing from the teachings of the present application. Accordingly, the above disclosure should be interpreted as only being limited and restricted by the appended claims.

Claims

1. A video processing circuit comprising: a first buffer; and a first computing circuit, wherein before performing a second one-dimensional processing operation on a plurality of consecutive blocks in a second direction, the first computing circuit is arranged to perform a first one-dimensional processing operation on each of the plurality of consecutive blocks in a first direction different from the second direction, to generate a first processing result for each of the plurality of consecutive blocks, and further arranged to store a plurality of first processing results of the plurality of consecutive blocks into the first buffer; a stage decision switching circuit for setting input data of the first computing circuit by adaptively switching between non-transposed data of the plurality of consecutive blocks provided from a previous stage of the video processing circuit and transposed data of the plurality of consecutive blocks provided from the first buffer.

2. The video processing circuit of claim 1, wherein, After performing the first one-dimensional processing operation on the plurality of consecutive blocks, the first computing circuit retrieves each of the plurality of first processing results from the first buffer and reuses the first processing result generated according to the first one-dimensional processing operation on each of the plurality of consecutive blocks to perform the second one-dimensional processing operation on each of the plurality of consecutive blocks.

3. The video processing circuit of claim 1, wherein, The stage decision switching circuit comprises: a second buffer for buffering information of the plurality of consecutive blocks provided from the previous stage; the stage decision switching circuit adaptively selects one of the non-transposed data and the transposed data as the input data of the first computing circuit with reference to the information in the second buffer.

4. The video processing circuit of claim 1, wherein, The stage decision switching circuit is further arranged to adaptively select one of the non-transposed data and the transposed data as the input data of the first computing circuit with reference to a buffer state of the first buffer.

5. The video processing circuit of claim 1, wherein, Further comprising: a third buffer coupled between the stage decision switching circuit and the first computing circuit, wherein output data of the stage decision switching circuit is pushed into the third buffer in series, all data of a complete queue included in each of the plurality of consecutive blocks is popped out of the third buffer and transmitted to the first computing circuit in a parallel manner, and the third buffer buffers data belonging to different queues simultaneously.

6. The video processing circuit of claim 1, wherein, Further comprising: a fourth buffer coupled between the first computing circuit and a next stage of the video processing circuit, and further coupled between the first computing circuit and the first buffer, wherein all data of a complete queue included in each of the plurality of consecutive blocks is pushed into the fourth buffer from the first computing circuit in parallel, data buffered in the fourth buffer is popped out of the fourth buffer in series, and the fourth buffer buffers data belonging to different queues simultaneously.

7. The video processing circuit of claim 1, wherein, Further comprising: a second computing circuit for retrieving each of the plurality of first processing results from the first buffer and performing a second one-dimensional processing operation on each of the plurality of consecutive blocks in the second direction according to the first processing result, wherein the first processing result is generated by performing the first one-dimensional processing operation on each of the plurality of consecutive blocks.

8. The video processing circuit of claim 7, wherein, Further comprising: a fifth buffer coupled between a previous stage of the video processing circuit and the first computing circuit, wherein output data of the previous stage is serially pushed into the fifth buffer, all data of a complete queue included in each of the plurality of consecutive blocks is popped from the fifth buffer and transmitted to the first computing circuit in a parallel manner, and the fifth buffer concurrently buffers data belonging to different queues.

9. The video processing circuit of claim 7, wherein, Further comprising: a sixth buffer coupled between the first computing circuit and the first buffer, wherein all data of a complete queue included in each of the plurality of consecutive blocks is generated by the first computing circuit and pushed into the sixth buffer in a parallel manner, data buffered in the sixth buffer is serially popped from the sixth buffer, and the sixth buffer concurrently buffers data belonging to different queues.

10. The video processing circuit of claim 7, wherein, Further comprising: a seventh buffer coupled between the first buffer and the second computing circuit, wherein output data of the first buffer is serially pushed into the seventh buffer, all data of a complete queue included in each of the plurality of consecutive blocks is popped from the seventh buffer and transmitted to the second computing circuit in a parallel manner, and the seventh buffer concurrently buffers data belonging to different queues.

11. The video processing circuit of claim 7, wherein, Further comprising: an eighth buffer coupled between the second computing circuit and a next stage of the video processing circuit, wherein all data of a complete queue included in each of the plurality of consecutive blocks is generated by the second computing circuit and pushed into the eighth buffer in a parallel manner, data buffered in the eighth buffer is serially popped from the eighth buffer, and the eighth buffer concurrently buffers data belonging to different queues.

12. The video processing circuit of claim 1, wherein, The video processing circuit is an inverse transform circuit or a transform circuit.

13. The video processing circuit of claim 1, wherein, The first buffer is a ring-shaped first-in-first-out (FIFO) buffer.

14. A video processing circuit, comprising: a computing circuit arranged to generate a processing result for each of a plurality of consecutive blocks by performing a one-dimensional processing operation on each of the plurality of consecutive blocks in one direction; and a buffer coupled to the computing circuit, wherein input data of the buffer is serially pushed into the buffer, all data of a complete queue included in each of the plurality of consecutive blocks is popped from the buffer and transmitted to the computing circuit in a parallel manner, and the buffer concurrently buffers data belonging to different queues.

15. The video processing circuit of claim 14, wherein, The video processing circuit is an inverse transform circuit or a transform circuit.

16. A video processing circuit, comprising: a computing circuit arranged to generate a processing result for each of a plurality of consecutive blocks by performing a one-dimensional processing operation on each of the plurality of consecutive blocks in one direction; and a buffer coupled to the computing circuit, wherein all data of a complete queue included in each of the plurality of consecutive blocks is generated by the computing circuit and pushed into the buffer in a parallel manner, data buffered in the buffer is serially popped from the buffer, and the buffer concurrently buffers data belonging to different queues.

17. The video processing circuit of claim 16, wherein, The video processing circuit is an inverse transform circuit or a transform circuit.

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