Printed circuit board, electronic device and method for manufacturing the same

Abstract

The present disclosure relates to a printed circuit board including a footprint pin area including a plurality of footprint pins arranged in a linear row for electrical connection with a surface mount connector, the plurality of footprint pins being arranged on one surface of the printed circuit board and a plurality of additional footprint pins being arranged on another surface of the printed circuit board, and a plurality of high speed signal holes for fan-out high speed signals, the plurality of high speed signal holes being configured as through holes and extending through the printed circuit board, at least some of the high speed signal holes being arranged outside of the footprint pin area. The present disclosure also relates to an electronic device including the above printed circuit board and a method of manufacturing the same. According to the printed circuit board, the electronic device and the method of manufacturing the same of the present disclosure, the PCB manufacturing cost can be saved while the high speed signals are completely fanned out.

Description

Technical Field

[0001] This disclosure relates to the fields of telecommunications and data communications, and more particularly to printed circuit boards (PCBs), electronic devices, and methods for manufacturing printed circuit boards or electronic devices. Background Technology

[0002] This section provides only background information relevant to this disclosure and is not necessarily prior art.

[0003] With the rapid development of the telecommunications and data communications fields, the demand for high-speed signal communication is also increasing rapidly. In related technologies, surface mount connectors, such as QSFP-DD (Quad Small Form Factor Pluggable-Double Density) connectors or similar surface mount connectors, are used as I / O ports. These surface mount connectors increase the number of channels to eight, enabling an operating rate of approximately 56 Gbps per channel through NRZ modulation or approximately 112 Gbps per channel through PAM4 modulation, thereby supporting, for example, 400G or 800G.

[0004] However, the arrangement of the footprint pin area for this type of surface mount connector is usually relatively uniform, which may limit the arrangement of high-density signal vias for connection with the footprint pins. These limited design requirements pose difficulties and challenges, especially for connectors similar to QSFP-DD connectors, in terms of signal line fan-out, crosstalk between signals, arrangement flexibility of high-speed signal vias, PCB manufacturing costs, and / or the integrity of high-speed fan-out. Summary of the Invention

[0005] One objective of this disclosure is to provide a printed circuit board that can at least partially solve the aforementioned problems. This objective can be achieved through the following technical solution:

[0006] A first aspect of this disclosure provides a printed circuit board (PCB) including a footprint pin region and a plurality of high-speed signal vias. The footprint pin region includes a plurality of footprint pins arranged along one or more linear rows for electrical connection to a surface mount connector. A portion of the footprint pins are disposed on one surface of the PCB, and the remaining footprint pins are disposed on another surface of the PCB. The plurality of high-speed signal vias extend through the PCB and are electrically connected to the footprint pins for fan-out of high-speed signals. At least a portion of the high-speed signal vias are disposed outside the footprint pin region, and the high-speed signal vias disposed inside the footprint pin region are configured as through-holes. By disposing of some high-speed signal vias outside the footprint pin region, the density of high-speed signal vias within the footprint pin region can be reduced, enabling flexible and reliable fan-out of high-speed signals. Furthermore, the use of through-hole or multiple lamination processes can be avoided, effectively saving on the production costs of PCBs or switches.

[0007] A second aspect of this disclosure provides an electronic device that includes the aforementioned printed circuit board, such as a switch.

[0008] A third aspect of this disclosure provides a method for manufacturing the aforementioned printed circuit boards and / or electronic devices.

[0009] The printed circuit board, electronic device, and / or manufacturing method disclosed herein enable the full fan-out of high-speed signals while satisfying signal integrity, without using VIPPO technology, multiple lamination technology, or / or configuring signal holes inside the footprint pin area as blind holes, etc., simply by cleverly arranging high-speed signal holes, while saving PCB manufacturing costs. Attached Figure Description

[0010] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this disclosure. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0011] Figure 1(a) is a schematic diagram of the footprint pin arrangement on the top layer of a printed circuit board according to an embodiment of the present disclosure;

[0012] Figure 1(b) is a schematic diagram of the footprint pin arrangement on the bottom layer of a printed circuit board according to an embodiment of the present disclosure.

[0013] Figure 1(c) is a schematic diagram of the footprint pin area of ​​a printed circuit board according to an embodiment of the present disclosure;

[0014] Figure 2 This is a schematic diagram of the arrangement of high-speed signal holes on a printed circuit board in related technologies;

[0015] Figure 3 This is a schematic diagram of the arrangement of high-speed signal holes on a printed circuit board according to a first embodiment of the present disclosure;

[0016] Figure 4 This is a schematic diagram of the arrangement of high-speed signal holes on a printed circuit board according to a second embodiment of the present disclosure;

[0017] Figure 5 This is a schematic diagram of the arrangement of high-speed signal holes on a printed circuit board according to a third embodiment of the present disclosure;

[0018] Figure 6 This is a schematic diagram of the arrangement of high-speed signal holes on a printed circuit board according to the fourth embodiment of this disclosure;

[0019] Figure 7 This is a schematic diagram of the arrangement of high-speed signal holes on a printed circuit board according to the fifth embodiment of this disclosure;

[0020] Figure 8 This is a schematic diagram of the arrangement of high-speed signal holes on a printed circuit board according to the sixth embodiment of this disclosure;

[0021] Figure 9 This is a schematic diagram of the arrangement of high-speed signal holes on a printed circuit board according to the seventh embodiment of this disclosure;

[0022] Figure 10 This is a schematic diagram of the arrangement of high-speed signal holes on a printed circuit board according to the eighth embodiment of this disclosure;

[0023] Figure 11 This is a schematic diagram of the arrangement of high-speed signal holes on a printed circuit board according to the ninth embodiment of this disclosure;

[0024] Figure 12 This is a schematic diagram of high-speed signal via wiring on an exemplary printed circuit board according to the present disclosure. Detailed Implementation

[0025] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0026] It should be understood that the terminology used herein is for the purpose of describing particular exemplary embodiments only and is not intended to be limiting. Unless the context clearly indicates otherwise, the expressions “a,” “an,” and “described” as used herein may also mean including the plural form. The terms “comprising,” “including,” and “having” are inclusive and therefore indicate the presence of the stated features, elements, and / or components, but do not exclude the presence or addition of one or more other features, elements, components, and / or combinations thereof.

[0027] Although terms such as "first," "second," etc., may be used in this document to describe multiple elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms may be used only to distinguish one element, component, region, layer, or section from another. Unless the context clearly indicates otherwise, terms such as "first," "second," and "third," as well as other numerical terms, do not imply order or sequence when used in this document. Furthermore, in the description of this disclosure, unless otherwise expressly specified and limited, the terms "set up" and "connected" should be interpreted broadly, for example, as fixed connections, detachable connections, or integral connections; they may be direct connections or indirect connections via an intermediate medium. Those skilled in the art will understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0028] For ease of description, spatial relative terms may be used in the text to describe the relationship of one element or feature relative to another element or feature, as shown in the figure. These relative terms include, for example, "above," "inside," "near," etc. Such spatial relative terms are intended to include different orientations of the device in use or operation, in addition to those depicted in the figure. For example, if the device in the figure is flipped, an element described as "below" or "below other elements or features" would subsequently be oriented as "above" or "above other elements or features." Therefore, the example term "below" can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or in other directions), and the spatial relative descriptors used in the text will be interpreted accordingly.

[0029] In related technologies, there are printed circuit boards with footprint pins and high-speed signal vias for back-to-back surface mount connectors (e.g., QSFP-DD connectors or QSFP-DD800 connectors). This back-to-back mounting method (i.e., connectors are mounted on both surfaces of the printed circuit board) increases the connection density of surface mount connectors. In other words, compared to single-surface mounting, this back-to-back mounting method allows more surface mount connectors to be connected on the printed circuit board.

[0030] In the field of high-speed signal transmission technology, for some common surface mount connectors (e.g., QSFP-DD connectors or QSFP-DD800 connectors), the pin arrangement of these surface mount connectors (and therefore the arrangement of the footprint pins connected to them on the PCB) is relatively fixed, especially the arrangement of these footprint pins and the longitudinal and / or lateral center-to-center spacing (as described in the technical specification "QSFP-DD / QSFP-DD800 / QSFP112 Hardware Specification for QSFP DOUBLE DENSITY 8X AND QSFP 4X PLUGGABLE TRANSCEIVERS Revision 6.01"). Therefore, those skilled in the art are also subject to certain limitations when designing the arrangement of footprint pins and high-speed signal holes on the PCB corresponding to these surface mount connectors.

[0031] Furthermore, as is known to those skilled in the art, connection density is crucial to the performance and cost of printed circuit boards. Therefore, related technologies constantly strive to increase the density of surface mount connectors and their connecting elements. It is generally considered advantageous to place signal vias as close as possible to the footprint pins, as this not only shortens the signal lines between the vias and the footprint pins, reducing signal line costs and minimizing signal loss during routing, but also increases the overall fan-out efficiency of high-speed signals from the high-speed vias. (See Appendix...) Figure 2 As shown, in related technologies, it is more advantageous for all high-speed signal apertures to be arranged as close as possible to the footprint pins (i.e., a centralized arrangement of high-speed signal apertures). This reduces the routing path and time of high-speed signals on the one hand, and avoids the need for technicians to additionally plan the routing path of high-speed signals on the other hand.

[0032] However, the inventors of this disclosure, overcoming the aforementioned technical bias, have discovered that, as shown in the appendix... Figure 2In the high-speed signal via arrangement methods of the related technologies shown, the close proximity of different high-speed signal vias in the horizontal direction may cause crosstalk in high-speed signals. Therefore, this arrangement method requires complex techniques such as multiple laminations on both surfaces of the PCB before drilling high-speed signal vias, or the fabrication of blind vias on both surfaces of the PCB (especially inside the footprint pin area). However, these methods significantly increase the production cost of the PCB. In other words, in the field of high-speed signal transmission technology, it is not necessarily more advantageous to concentrate all high-speed signal vias as much as possible in the footprint pin area. The inventors of this disclosure have discovered that distributing some high-speed signal vias outside the footprint pin area can at least partially achieve the following unexpected technical effects: First, when distributing some high-speed signal vias outside the footprint pin area, i.e., increasing the signal lines between the high-speed signal vias and the footprint pins, the manufacturing cost of the PCB is not increased as conventionally assumed, but rather reduced. Secondly, by reducing the density of high-speed signal vias, the increased distance between some high-speed signal vias and the footprint pins, as well as the increased distance between each high-speed signal via, effectively avoids crosstalk between high-speed signals, thus facilitating the fan-out of high-speed signals from the vias. Thirdly, although the pin arrangement of the surface mount connector is relatively fixed, it is still possible to deviate from this fixed pin arrangement and flexibly configure the corresponding high-speed signal vias. Therefore, the PCB according to this disclosure can achieve full fan-out of high-speed signals while satisfying signal integrity, without using VIPPO technology, multiple lamination technology, or / or by making the signal vias inside the footprint pin area blind vias, while also significantly reducing PCB manufacturing costs.

[0033] Embodiments of this disclosure are described below with reference to the exemplary accompanying drawings.

[0034] Reference Figures 1(a) to 1(c) In some embodiments of this disclosure, the footprint pin arrangement in the footprint pin region A of the printed circuit board includes a plurality of footprint pins arranged along one or more linear rows.

[0035] Here, Figure 1(a) exemplarily shows the footprint pin arrangement in footprint pin region A located on the top layer of the printed circuit board, Figure 1(b) exemplarily shows the footprint pin arrangement in footprint pin region A located on the bottom layer of the printed circuit board, and Figure 1(c) includes the footprint pin arrangement in footprint pin region A shared by the top and bottom layers of the printed circuit board. In other words, from the same perspective (e.g., viewed from the top surface of the PCB towards the bottom surface), Figure 1(c) can be considered as a combination of Figures 1(a) and 1(b). In Figure 1(a), different types of footprint pins arranged on the top layer of the printed circuit board are visible, such as Tx high-speed signal footprint pins 110p filled with diagonal lines, Rx high-speed signal footprint pins 110b, 120b, 130b, 140b filled with a grid, and signal footprint pins 110a, 120a, 130a, 140a, 110s, 120s, 130s, 140s filled with horizontal dashed lines. Similarly, in Figure 1(b), different types of footprint pins 210a, 220a, 230a, 240a, 210b, 220b, 230b, 240b, 210s, 220s, 230s, 240s, and 210p are arranged on the bottom layer of the printed circuit board. Within the scope of this disclosure, the “footprint pins” (or contacts or electrical contact pads) on the printed circuit board can be used to connect to corresponding connector pins of surface mount connectors (e.g., Tx connector pins, Rx connector pins).

[0036] Furthermore, within the scope of this disclosure, a "surface mount connector" can be a small form factor connector, such as a QSFP-DD connector, a QSFP-DD800 connector, a stacked QSFP-DD connector, a stacked QSFP-DD800 connector, or a connector with a pin arrangement consistent with the aforementioned connectors, which facilitates high-speed signal communication between electronic devices, including PCBs according to this disclosure, and other electronic devices. In use, the surface mount connector can be directly mounted to any surface of the printed circuit board, such as the top and / or bottom surface (or upper and / or lower surface, front and / or back). Each surface mount connector includes a surface mount technology (SMT) pin array that, when mounted to the surface of a PCB as described in this disclosure, makes electrical contact with a signal transmission array or contact grid of footprint pins on the corresponding PCB. These footprint pins are electrically connected to high-speed signal vias configured as through-holes and arranged along the top and bottom layers of the PCB, allowing high-speed signals to ultimately fan out through the high-speed signal vias. Within the scope of this disclosure, "stacked" can be understood as combining two identical surface mount connectors to form a single surface mount connector. For example, a stacked QSFP-DD connector can be understood as a combination of two QSFP-DD connectors, which is also specified in the technical documents mentioned above.

[0037] Figure 1(c) shows an array (or set) of all footprint pin projections from the top layer Figure 1(a) and the bottom layer Figure 1(b). These sets of footprint pins together form the footprint pin region A and can be matched with the pin arrangement of QSFP-DD connectors or QSFP-DD800 connectors (or their stacked connectors).

[0038] Within the scope of this disclosure, a "footprint pin area" is an area comprised of these relatively concentrated footprint pin arrays (typically used to mount a surface mount connector on one surface of a PCB (e.g., the footprint pin area on the top layer of the PCB as shown in Figure 1(a) or the footprint pin area on the bottom layer of the PCB as shown in Figure 1(b)), or to mount a surface mount connector on each of its two surfaces). However, this area may not necessarily have a physically visible marking in actual manufactured printed circuit boards. Within the scope of this disclosure, a "footprint pin area" can be an area bounded by a certain range (e.g., 1 mm, 1.5 mm, 2 mm) from the outermost edge of the footprint pin in the footprint pin array. Taking footprint pin area A in Figure 1(c) as an example, the distances a1 between footprint pin area A and the outer edge of the top row of footprint pins, a4 between footprint pin area A and the outer edge of the bottom row of footprint pins, a3 between footprint pin area A and the outer edge of the leftmost row of footprint pins, and a2 between footprint pin area A and the outer edge of the rightmost row of footprint pins can be, for example, less than or equal to 1 mm, 1.5 mm, or 2 mm. For example, the statement that a high-speed signal hole is "outside the footprint pin area" means that the distance between the high-speed signal hole and the outer edge of the outermost footprint pin in the footprint pin array is greater than or equal to 1 mm, 1.5 mm or 2 mm, and in particular, the distance between the high-speed signal hole and all footprint pins in the footprint pin array (for connecting a surface mount connector) in each direction is greater than or equal to 1 mm, 1.5 mm or 2 mm.

[0039] It should also be understood here that each printed circuit board may include not only one footprint pin area, but rather the PCB may include a corresponding number and location of footprint pin areas depending on the arrangement of the footprint pin array for mating with surface mount connectors (e.g., the arrangement of surface mount connectors to be mounted on the PCB).

[0040] Reference Figure 2 In related technologies, high-speed signal vias 2100 on printed circuit boards are always arranged close to the footprint pins 2200. Therefore, all high-speed signal vias 2100 configured as through-holes on the printed circuit board are arranged inside the footprint pin region A. As mentioned earlier, this centralized arrangement requires complex techniques such as multiple laminations or configuring the high-speed signal vias inside the footprint pin region as blind vias to reduce crosstalk between horizontally adjacent high-speed signal vias, making it relatively complex and costly.

[0041] Reference Figure 3In a printed circuit board 300 according to a first embodiment of the present disclosure, the printed circuit board 300 includes a footprint pin region A and a plurality of high-speed signal vias 3110. The footprint pin region A includes a plurality of footprint pins 3120 arranged along one or more linear rows for electrical connection to surface mount connectors (e.g., QSFP-DD connectors, QSFP-DD800 connectors, or other connectors with the same pin arrangement as QSFP-DD or QSFP-DD800 connectors). Some of these footprint pins are disposed on the top layer of the printed circuit board 300, while others are disposed on the bottom layer of the printed circuit board 300. Depending on standards and / or requirements, these footprint pins 3210 are arranged in at least two rows, such as four or eight rows, on the top or bottom layer of the printed circuit board.

[0042] Within the scope of this disclosure, "pin arrangement" may include the lateral center-to-center spacing and / or longitudinal center-to-center spacing between pins. Such lateral center-to-center spacing and / or longitudinal center-to-center spacing are described, for example, in the technical specification "QSFP-DD / QSFP-DD800 / QSFP112 Hardware Specification for QSFP DOUBLE DENSITY 8X AND QSFP 4XPLUGGABLE TRANSCEIVERS Revision 6.01".

[0043] It should also be understood here that the printed circuit board may include multiple footprint pin areas A, and these footprint pin areas may be used to mount different surface mount connectors, such as QSFP-DD connectors, QSFP-DD800 connectors, stacked QSFP-DD connectors, stacked QSFP-DD800 connectors, other connectors with the same pin arrangement as QSFP-DD connectors, QSFP-DD800 connectors, stacked QSFP-DD connectors, stacked QSFP-DD connectors, or combinations thereof.

[0044] Each high-speed signal via 3110 can be electrically connected to the footprint pins 3120 via signal lines (not shown) to fan out high-speed signals (“high-speed signals” are, for example, signals with signal rates higher than 1Gbps, 10Gbps, or 25Gbps fanned out via pairs of high-speed signal vias 3110), such as fanning out Tx high-speed signals and / or Rx high-speed signals. In this embodiment, all high-speed signal vias extend through the printed circuit board 300, wherein all high-speed signal vias within the footprint pin area are configured as through-holes and extend through the printed circuit board 300 (i.e., none of the high-speed signal vias within the footprint pin area are configured as blind vias), while the configuration of high-speed signal vias outside the footprint pin area is not limited, thereby minimizing, for example, the PCB process complexity and manufacturing cost. Here, the high-speed signal vias can also be arranged in pairs to fan out high-speed differential signals with opposite phases. Within the scope of this disclosure, unlike "extending through," which means completely penetrating a printed circuit board from one surface to another, "extending through" only indicates that it is at least partially formed within the printed circuit board. As an example, "high-speed signal via extending through the printed circuit board" may mean that the high-speed signal via extends from one surface (e.g., the top or bottom surface) of the printed circuit board to any layer (including intermediate layers or another surface) of the printed circuit board. For example, if back-drilling is also additionally provided, the high-speed signal via may not completely penetrate from one surface to another. Furthermore, "high-speed signal via extending through the printed circuit board" does not limit the form of the high-speed signal via; rather, the high-speed signal via can be configured as either a through-hole or a blind via. In this disclosure, it is advantageous that all high-speed signal vias within the footprint pin region may not be blind vias, or that all high-speed signal vias within and / or outside the footprint pin region may not be blind vias.

[0045] As in Figure 3As can be seen, some high-speed signal holes 3130 are arranged inside the footprint pin region A, while some high-speed signal holes 3110 are arranged outside the footprint pin region A. In this embodiment, the external high-speed signal holes 3110 are arranged in vertical columns above and below the footprint pin region A. Specifically, columns 3100, 3200, 3300, 3400, and 3500 of the five high-speed signal holes are arranged above the footprint pin region A, while columns 3600, 3700, 3800, 3900, and 31000 of the five high-speed signal holes are arranged below the footprint pin region A. The intervals d1, d2, and d3 between these columns of high-speed signal holes 3100 can be the same, for example, d1 = d2, or they can be different, d1 ≠ d3. In other words, the multiple columns of high-speed signal holes can be arranged either equally spaced or unequally spaced.

[0046] Reference Figure 4 In the printed circuit board 400 according to the second embodiment of the present disclosure, in addition to the columns 4100, 4200, 4300, 4400 of high-speed signal holes arranged above the outside of the footprint pin region A and the columns 4700, 4800, 4900, 41000 of high-speed signal holes arranged below the outside of the footprint pin region A, columns 4500 and 4600 of high-speed signal holes are also arranged on the left and right sides of the footprint pin region A, so that the high-speed signal holes surround the outside of the footprint pin region A.

[0047] It should be understood that high-speed signal holes are not necessarily arranged above, below, to the left or right of the outer surface of the footprint pin area A. Instead, they can be adjusted according to the actual high-speed signal fan-out requirements or the high-speed signal line routing requirements to increase the flexibility and adaptability of the high-speed signal hole arrangement.

[0048] Reference Figure 5 and Figure 6 In the printed circuit boards 500 and 600 according to the third and fourth embodiments of the present disclosure, columns 5100, 5200, 5300, 5400, and 5500 of high-speed signal holes are arranged above the outside of the footprint pin region A, and columns 5600, 5700, and 5800 of high-speed signal holes and groups 5900 and 51000 of high-speed signal holes are arranged below the outside of the footprint pin region A.

[0049] exist Figure 5As can be seen, some high-speed signal holes can be arranged in pairs in column pairs, such as high-speed signal holes 5110 and 5120, 5130 and 5140, and 5910 and 5920, while some high-speed signal holes can be arranged in pairs in row pairs, such as high-speed signal holes 5930 and 5940. When all pairs of high-speed signal holes in a group are arranged in column pairs, the group of high-speed signal holes can be configured as a column as a whole. When some pairs of high-speed signal holes are arranged in column pairs and some pairs of high-speed signal holes are arranged in row pairs, the group of high-speed signal holes can be configured as an L-shape as a whole, such as high-speed signal hole groups 5900 and 51000.

[0050] exist Figure 6 As can be seen, groups 6100 and 6200 of high-speed signal holes can also be arranged on the outer left and outer right sides of the footprint pin area A. The high-speed signal holes in these groups can also be arranged in a column-pair configuration. When all the high-speed signal holes 6210, 6220, 6230, and 6240 in a group are approximately aligned with each other, the group 6200 of high-speed signal holes can be arranged in a column-pair configuration. When some of the high-speed signal holes 6110, 6120, 6130, and 6140 in a group are staggered, the group 6100 of high-speed signal holes can be arranged in an inclined configuration.

[0051] Reference Figure 7 In the printed circuit board 700 according to the fifth embodiment of this disclosure, groups 7100 and 7200 of high-speed signal holes located below the outer edge of the footprint pin region A are arranged in a generally row-like configuration. Each group of high-speed signal holes may include multiple pairs of high-speed signal holes, which may also be arranged in row pairs, such as high-speed signal holes 7110 and 7120, 7210 and 7220. Here, the pairs of high-speed signal holes may be aligned with each other, for example, the pair of high-speed signal holes 7130 and 7140 may be substantially horizontally aligned with the pair of high-speed signal holes 7230 and 7240, or they may be staggered, for example, the pair of high-speed signal holes 7110 and 7120 may be horizontally staggered with the pair of high-speed signal holes 7210 and 7220.

[0052] Reference Figure 8For example, to satisfy high-speed signal integrity, in the printed circuit board 800 according to the sixth embodiment of this disclosure, the group 8300 of high-speed signal holes located above the outer surface of the footprint pin region A includes high-speed signal holes 8310 and 8320, 8340 and 8350 arranged in an inclined pair. The group 8400 of high-speed signal holes includes a pair of high-speed signal holes arranged in a row pair and a pair of high-speed signal holes arranged in a column pair, such that the group 8400 of high-speed signal holes is arranged in an L-shape overall. In addition, the groups 8100 and 8200 of high-speed signal holes located on the outer left and outer right sides of the printed circuit board 800 may each include only a pair of high-speed signal holes.

[0053] Reference Figure 9 In the printed circuit board 900 according to the seventh embodiment of this disclosure, the group 9100 of high-speed signal holes located on the outer left side of the footprint pin region A includes three pairs of high-speed signal holes, while the group 9200 of high-speed signal holes located on the outer right side of the footprint pin region A includes two pairs of high-speed signal holes. In other words, the number of high-speed signal holes located on the outer left and outer right sides of the footprint pin region A can be different. Furthermore, the group 9300 of high-speed signal holes located above the outer side of the footprint pin region A includes only one pair of high-speed signal holes, and its number is also different from other groups of high-speed signal holes located above the outer side. It should be understood that the number of high-speed signal holes in each group of high-speed signal holes located outside the footprint pin region A is not limited, but can be flexibly adjusted and adapted according to, for example, the needs of signal fan-out or footprint pin wiring.

[0054] Reference Figure 10 In the printed circuit board according to the eighth embodiment of this disclosure, the footprint pin region A of the printed circuit board may include a greater number of footprint pins, such as an arrangement of 8 rows of footprint pins. Similar to the arrangement of 4 rows of footprint pins, high-speed signal vias electrically connected to the footprint pins to fan out high-speed signals may also be provided outside the footprint pin region A of the printed circuit board. These external high-speed signal via groups 10300 and 10400 may be arranged above, below, to the left, and / or to the right of the footprint pin region A. Here, the high-speed signal group 10300 on the left is divided into non-contiguous upper and lower subgroups, while the high-speed signal group 10400 on the right is arranged in a continuous group.

[0055] Although the accompanying drawings show high-speed signal vias arranged in columns above, to the left and right of the outer surface of footprint pin region A, and in rows below it, it is understood that any arrangement of high-speed signal vias applicable to a 4-row footprint pin region in this disclosure is also applicable to this 8-row footprint pin region, and vice versa. Importantly, some high-speed signal vias can still be arranged outside footprint pin region A. Here, footprint pin region A comprising 8 rows on one surface of the PCB can be used for connection with stacked connectors (e.g., stacked QSFP-DD connectors or stacked QSFP-DD800 connectors), while footprint pin region A comprising 4 rows on one surface of the PCB can be used for connection with non-stacked connectors (e.g., QSFP-DD connectors or QSFP-DD800 connectors).

[0056] Here, because it includes more rows of footprint pins, the footprint pin region A of these 8 rows is generally larger than the footprint pin region of the aforementioned 4 rows. However, the region A can still be defined as a region bounded by a certain range (e.g., 1 mm, 1.5 mm, 2 mm) from the outer edge of the outermost footprint pin. For example, the distances a1, a2, a3, a4 between the footprint pin region A and the outer edge of the outermost footprint pin can be, for example, less than or equal to 1 mm, 1.5 mm, 2 mm, or 3 mm.

[0057] In addition, Figure 10 It can also be seen that some footprint pins may have only one row of high-speed signal holes arranged in their row spacing, while others may have more than one row, such as two rows of high-speed signal holes 10100 and 10200. Here, the footprint pins adjacent to the row spacing of the footprint pins with two rows of high-speed signal holes have only one row of high-speed signal holes arranged in their row spacing. In other words, one and multiple rows of high-speed signal holes are alternately arranged in the row spacing of the footprint pins.

[0058] Reference Figure 11In the printed circuit board according to the ninth embodiment of this disclosure, a non-stacked surface mount connector (which includes a total of 4 rows of pins corresponding to its mating footprint pins) can be mounted on one surface of the printed circuit board, while a stacked surface mount connector (which includes a total of 8 rows of pins corresponding to its mating footprint pins) can be mounted on the other surface of the printed circuit board. Thus, in a perspective view including both the top and bottom layers of the footprint pin area, the footprint pin area A can include both area A1 for providing footprint pins only on a single surface of the PCB and area A2 for providing footprint pins on both sides of the PCB. In other words, 8 rows of footprint pins are provided on one surface of the PCB (these footprint pins are projected in both area A1 and area A2), while 4 rows of footprint pins are provided on the other surface of the PCB (these footprint pins are only in area A2).

[0059] Although shown here as a non-stacked surface mount device positioned below the PCB, such that the lower region A2 has footprint pin projections on both surfaces of the PCB, while the upper region A1 has footprint pin projections on only a single surface of the PCB, it is understood that this arrangement is not mandatory. For example, depending on the application requirements, the non-stacked surface mount device can also be positioned above the PCB, such that the upper region is configured to have footprint pin projections on both sides.

[0060] Reference Figure 12 In one exemplary embodiment of this disclosure, the printed circuit board may include two footprint pin regions A and A' (only partial regions are shown here), and a schematic wiring arrangement of some high-speed signal vias is shown. Here, footprint pin regions A and A' can be used to connect different surface mount connectors, for example, to mount two surface mount connectors back-to-back on opposite sides of the printed circuit board. A common group 12100 of high-speed signal vias is provided between the two footprint pin regions A and A', such that some high-speed signal vias (e.g., high-speed signal vias 12110 and 12120) in the group 12100 are connected via signal lines to footprint pins in footprint pin region A on its left, while some high-speed signal vias (e.g., high-speed signal vias 12130 and 12140) are connected via signal lines to footprint pins in footprint pin region A' on its right. In other words, four pairs of high-speed signal holes are provided between two adjacent footprint pin areas A and A', of which two pairs of high-speed signal holes are used for the left footprint pin area A, and the other two pairs of high-speed signal holes are used for the right footprint pin area A'.

[0061] from Figure 12As can also be seen, the footprint pins can be connected to high-speed signal holes via signal lines. Here, because some high-speed signal holes are arranged outside the footprint pin area, unlike the conventional compact and concentrated lead layout, in this embodiment, some signal lines are longer (e.g., shown as black lines in the figure) while others are shorter (e.g., shown as black dots in the figure), but this arrangement can more reliably facilitate high-speed signal fan-out.

[0062] This disclosure overcomes the technical bias of centralized arrangement of high-speed signal holes in related technologies through the following embodiments. By arranging some high-speed signal holes outside the footprint pin area, unexpected technical effects are achieved. This not only reduces the density of high-speed signal holes inside the footprint pin area, thereby enabling flexible and reliable fan-out of high-speed signals, but also avoids the use of vias or multiple lamination processes, thus effectively saving PCB or switch production costs.

[0063] First: A printed circuit board, the printed circuit board including a pin region and a plurality of high-speed signal vias, wherein the pin region includes a plurality of pins arranged along one or more linear rows for electrical connection to a surface mount connector, wherein a portion of the plurality of pins is disposed on one surface of the printed circuit board, and the remaining pins are disposed on another surface of the printed circuit board; and the plurality of high-speed signal vias extend through the printed circuit board and are electrically connected to footprint pins of the footprint pin region for fan-out high-speed signals, wherein the plurality of high-speed signal vias are configured as through-holes and extend through the printed circuit board, wherein at least a portion of the plurality of high-speed signal vias are disposed outside the footprint pin region, and wherein the high-speed signal vias disposed inside the footprint pin region are configured as through-holes.

[0064] Second: The printed circuit board according to the first item, wherein the surface mount connector includes the following connectors and / or combinations of the following connectors: QSFP-DD connector, QSFP-DD800 connector, stacked QSFP-DD connector, stacked QSFP-DD800 connector, and connectors with the same pin arrangement as any of the above connectors.

[0065] Third: The printed circuit board according to the first item, wherein the pin arrangement includes the lateral center spacing and / or longitudinal center spacing between each pin.

[0066] Fourth: The printed circuit board according to the first item, wherein the plurality of high-speed signal holes extend from the top surface or the bottom surface of the printed circuit board through to the intermediate layer of the printed circuit board, or the plurality of high-speed signal holes extend from the top surface of the printed circuit board through to the bottom surface.

[0067] Fifth: The printed circuit board according to the first item, wherein the high-speed signal holes are arranged in pairs for fanning out high-speed differential signals.

[0068] Sixth: The printed circuit board according to the first claim, wherein the high-speed signal includes a signal with a signal rate higher than 1Gbps fan-out via the paired high-speed signal apertures.

[0069] Item 7: The printed circuit board according to Item 1, wherein at least a portion of the plurality of high-speed signal vias are used to fan out Tx high-speed signals or Rx high-speed signals.

[0070] Item 8: The printed circuit board according to Item 1, wherein the high-speed signal via disposed inside the footprint pin area is not configured as a blind via.

[0071] Ninth: The printed circuit board according to the first claim, wherein the plurality of pins of the pin region are arranged in at least two rows along a linear pattern on the printed circuit board.

[0072] Item 10: The printed circuit board according to Item 9, wherein the plurality of pins of the pin region are arranged in four or eight rows along a linear pattern on the printed circuit board.

[0073] Item 11: The printed circuit board according to Item 1, wherein the pin region is defined as a region bounded by a distance of 1 mm from the outer edge of the outermost pin.

[0074] Item 12: The printed circuit board according to Item 1, wherein more than one row of high-speed signal vias are arranged in the row spacing of a portion of the pins in the pin region.

[0075] Item 13: The printed circuit board according to Item 1, wherein two rows of high-speed signal vias are arranged in the row spacing of a portion of the pins in the pin region, and only one row of high-speed signal vias is arranged in the row spacing of the pins adjacent to the row spacing of the pins.

[0076] Item 14: A printed circuit board according to any one of items 1 to 13, wherein the footprint pin region is electrically connected to a plurality of surface mount connectors, wherein at least a portion of the plurality of surface mount connectors are arranged back-to-back on two surfaces of the printed circuit board.

[0077] Item 15: The printed circuit board according to Item 14, wherein at least some of the plurality of surface mount connectors are arranged back-to-back and in pairs on two surfaces of the printed circuit board.

[0078] Item 16: The printed circuit board according to Item 14, wherein the footprint pin region on one surface of the printed circuit board is used for connecting a stacked surface mount connector, and the footprint pin region on the other surface of the printed circuit board is used for connecting a non-stacked surface mount connector.

[0079] Item 17: A printed circuit board according to any one of items 1 to 13, wherein at least a portion of the plurality of high-speed signal vias are arranged above and / or below the outer surface of the footprint pin region.

[0080] Item 18: A printed circuit board according to any one of items 1 to 13, wherein at least a portion of the plurality of high-speed signal holes are arranged on the outer left and / or outer right of the footprint pin region.

[0081] Item 19: A printed circuit board according to any one of items 1 to 13, wherein at least a portion of the plurality of high-speed signal holes are arranged around the footprint pin region outside the footprint pin region.

[0082] Item 20: The printed circuit board according to Item 5, wherein the pairs of the high-speed signal holes are arranged in column pairs, row pairs and / or oblique pairs outside the footprint pin area.

[0083] Item 21: A printed circuit board according to any one of items 1 to 13, wherein at least a portion of the plurality of high-speed signal holes are arranged in groups, in multiple columns, in multiple rows, in an L-shape, and / or obliquely outside the footprint pin region.

[0084] Item 22: The printed circuit board according to the preceding item, wherein the high-speed signal holes of the plurality of columns or rows are arranged at equal or non-equal intervals with each other.

[0085] Item 23: A printed circuit board according to any one of items 1 to 13, wherein a group of shared high-speed signal holes is provided among a plurality of footprint pin regions, such that at least a portion of the shared high-speed signal holes arranged outside the footprint pin regions can be respectively connected to adjacent different footprint pin regions.

[0086] Item 24: A printed circuit board according to any one of items 1 to 13, wherein 20 pairs of high-speed signal holes of the plurality of high-speed signal holes are arranged outside the footprint pin area.

[0087] Item 25: The printed circuit board according to the preceding item, wherein 8 pairs of high-speed signal holes of the 20 pairs arranged outside the footprint pin area are arranged above the outside of the footprint pin area, and / or 8 pairs of high-speed signal holes of the 20 pairs are arranged below the outside of the footprint pin area.

[0088] Item 26: The printed circuit board according to the preceding item, wherein the eight pairs of high-speed signal holes arranged above and / or below the outer surface of the footprint pin area are arranged in at least four groups.

[0089] Item 27: The printed circuit board according to Item 25, wherein 4 of the 8 pairs of high-speed signal holes arranged above and / or below the outer surface of the footprint pin area are used to fan out Tx high-speed signals, and the other 4 pairs of high-speed signal holes are used to fan out Rx high-speed signals.

[0090] Item 28: An electronic device, wherein the electronic device includes the printed circuit board according to the above.

[0091] Item 29: The electronic device according to the preceding item, wherein the electronic device is configured as or includes a switch.

[0092] Item 30: A manufacturing method, wherein the method is used to manufacture the printed circuit board and / or electronic device described in any of the preceding items.

[0093] The above description is merely a preferred embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A printed circuit board, the printed circuit board comprising a footprint pin area and a plurality of high-speed signal vias, characterized in that, The footprint pin region includes a plurality of footprint pins arranged along multiple linear rows for electrical connection to a surface mount connector. A portion of the footprint pins are disposed on one surface of the printed circuit board, and the remaining footprint pins are disposed on the other surface of the printed circuit board. More than one row of high-speed signal vias is arranged in the row spacing of the portion of the footprint pins in the footprint pin region. The plurality of high-speed signal holes extend through the printed circuit board and are electrically connected to the footprint pins of the footprint pin region for fan-out high-speed signals, wherein at least a portion of the plurality of high-speed signal holes are arranged outside the footprint pin region, and wherein the high-speed signal holes arranged inside the footprint pin region are configured as through holes.

2. The printed circuit board according to claim 1, wherein, The surface mount connectors include the following connectors and / or combinations of the following connectors: QSFP-DD connectors, QSFP-DD800 connectors, stacked QSFP-DD connectors, stacked QSFP-DD800 connectors, and connectors with the same pin arrangement as any of the above connectors.

3. The printed circuit board according to claim 2, wherein, The pin arrangement includes the lateral center spacing and / or longitudinal center spacing between each pin.

4. The printed circuit board according to claim 1, wherein, The plurality of high-speed signal holes extend from the top or bottom surface of the printed circuit board through to the middle layer of the printed circuit board.

5. The printed circuit board according to claim 1, wherein, The high-speed signal apertures are arranged in pairs to fan out high-speed differential signals.

6. The printed circuit board according to claim 1, wherein, The high-speed signal includes signals with a signal rate higher than 1Gbps fan-out via the paired high-speed signal apertures.

7. The printed circuit board according to claim 1, wherein, At least a portion of the plurality of high-speed signal holes are used to fan out Tx high-speed signals or Rx high-speed signals.

8. The printed circuit board according to claim 1, wherein, The high-speed signal hole arranged inside the footprint pin area is not configured as a blind hole.

9. The printed circuit board according to claim 1, wherein, The plurality of footprint pins in the footprint pin region are arranged in at least two rows along a linear pattern on the printed circuit board.

10. The printed circuit board according to claim 9, wherein, The plurality of footprint pins in the footprint pin region are arranged in four or eight rows along a linear pattern on the printed circuit board.

11. The printed circuit board according to claim 1, wherein, The footprint pin area is defined as the region bounded by a distance of 1 mm from the outermost edge of the footprint pin.

12. The printed circuit board according to claim 1, wherein, Two rows of high-speed signal holes are arranged in the intervals of some of the footprint pin rows in the footprint pin area, and only one row of high-speed signal holes is arranged in the intervals of the footprint pin rows adjacent to the row intervals of the footprint pins.

13. The printed circuit board according to any one of claims 1 to 12, wherein, The footprint pin region is electrically connected to a plurality of surface mount connectors, wherein at least a portion of the plurality of surface mount connectors are arranged back-to-back on two surfaces of the printed circuit board.

14. The printed circuit board according to claim 13, wherein, At least some of the surface mount connectors of the plurality of surface mount connectors are arranged back-to-back and in pairs on two surfaces of the printed circuit board.

15. The printed circuit board according to claim 13, wherein, The footprint pin area on one surface of the printed circuit board is used to connect a stacked surface mount connector, and the footprint pin area on the other surface of the printed circuit board is used to connect a non-stacked surface mount connector.

16. The printed circuit board according to any one of claims 1 to 12, wherein, At least some of the high-speed signal holes are arranged above and / or below the outer surface of the footprint pin area.

17. The printed circuit board according to any one of claims 1 to 12, wherein, At least some of the high-speed signal holes are arranged on the outer left and / or outer right of the footprint pin area.

18. The printed circuit board according to any one of claims 1 to 12, wherein, At least some of the high-speed signal holes are arranged around the footprint pin area outside the footprint pin area.

19. The printed circuit board according to claim 5, wherein, The high-speed signal apertures are arranged in column pairs, row pairs, and / or oblique pairs outside the footprint pin area.

20. The printed circuit board according to any one of claims 1 to 12, wherein, At least some of the high-speed signal holes are arranged in groups, in multiple columns, in multiple rows, in an L-shape, and / or at an angle outside the footprint pin area.

21. The printed circuit board according to claim 20, wherein, The high-speed signal holes in the multiple columns or rows are arranged at equal or non-equal intervals.

22. The printed circuit board according to any one of claims 1 to 12, wherein, A group of shared high-speed signal holes is provided among multiple footprint pin areas, such that the high-speed signal holes in the group of shared high-speed signal holes arranged outside the footprint pin areas can be used to connect to adjacent different footprint pin areas.

23. An electronic device, characterized in that, The electronic device includes a printed circuit board according to any one of claims 1 to 22.

24. The electronic device according to claim 23, wherein, The electronic device is configured as or includes a switch.

25. A manufacturing method, characterized in that, The method is used to manufacture printed circuit boards according to any one of claims 1 to 22 and / or electronic devices according to any one of claims 23 to 24.

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