Method of fabricating a semiconductor device using superlattices having different non-semiconductor thermal stabilities

Abstract

Methods for fabricating semiconductor devices can include forming a first superlattice and a second superlattice adjacent to a semiconductor layer. Each of the first superlattice and the second superlattice can include stacked groups of layers, where each group of layers includes a stack of base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of an adjacent base semiconductor portion. The second superlattice can have greater thermal stability with respect to non-semiconductor atoms therein than the first superlattice. The methods can further include heating the first superlattice and the second superlattice to cause migration of non-semiconductor atoms from the first superlattice to the at least one non-semiconductor monolayer of the second superlattice.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor devices, and more specifically to methods and related methods for manufacturing semiconductor devices having enhanced semiconductor materials. Background Technology

[0002] Structures and techniques for enhancing the performance of semiconductor devices have been proposed, such as by enhancing charge carrier mobility. For example, U.S. Patent Application No. 2003 / 0057416 by Currie et al. discloses strained material layers of silicon, silicon-germanium, and relaxable silicon, as well as impurity-free regions that would otherwise lead to performance degradation. The biaxial strain generated in the upper silicon layer alters the carrier mobility, thereby enabling higher speed and / or lower power devices. Published U.S. Patent Application No. 2003 / 0034529 by Fitzgerald et al. discloses a CMOS inverter also based on a similar strained silicon technique.

[0003] Takagi's U.S. Patent No. 6,472,685B2 discloses a semiconductor device comprising silicon and carbon layers sandwiched between silicon layers, such that the conduction band and valence band of the second silicon layer receive tensile strain. Electrons with smaller effective mass and induced by the electric field applied to the gate electrode are confined within the second silicon layer; therefore, the n-channel MOSFET is considered to have higher mobility.

[0004] U.S. Patent No. 4,937,204 to Ishibashi et al. discloses a superlattice in which multiple layers are grown alternately and epitaxially, the multiple layers being fewer than eight monolayers and including fractional or binary or binary compound semiconductor layers. The direction of the main current is perpendicular to the layers of the superlattice.

[0005] U.S. Patent No. 5,357,119 to Wang et al. discloses a Si-Ge short-period superlattice with higher mobility achieved by reducing alloy scattering in the superlattice. Following these lines, U.S. Patent No. 5,683,934 to Candelaria discloses an enhanced mobility MOSFET comprising a channel layer comprising a silicon alloy and a second material present in a certain percentage, alternatively within the silicon lattice, to subject the channel layer to tensile stress.

[0006] Tsu's U.S. Patent No. 5,216,262 discloses a quantum well structure comprising two barrier regions and a thin epitaxially grown semiconductor layer sandwiched between the barriers. Each barrier region consists of alternating SiO2 / Si layers, with a thickness typically ranging from 2 to 6 monolayers. A much thicker silicon portion is sandwiched between the barriers.

[0007] A Tsu paper titled "Phenomena in silicon nanostructure devices," published online on September 6, 2000, in *Applied Physics and Materials Science & Processing* (pp. 391-402), discloses a silicon / oxygen semiconductor-atomic superlattice (SAS). The Si / O superlattice is disclosed as useful in silicon quantum and light-emitting devices. Specifically, a green electroluminescent diode structure was constructed and tested. The current in the diode structure is vertical, i.e., perpendicular to the layers of the SAS. The disclosed SAS can comprise semiconductor layers separated by adsorbed substances such as oxygen atoms and CO molecules. Silicon growth beyond the adsorbed oxygen monolayer is described as epitaxy with a relatively low defect density. One SAS structure comprises a 1.1 nm thick silicon portion and another structure, the silicon portion being approximately eight silicon atomic layers thick, and the other structure being twice the thickness of this silicon portion. The article titled "Chemical Design of Direct-Gap Light-Emitting Silicon" published by Luo et al. in Physical Review Letters, Volume 89, Issue 7 (August 12, 2002) further discusses the luminescent SAS structure of Tsu.

[0008] U.S. Patent No. 7,105,895 to Wang et al. discloses thin silicon and barrier building blocks of oxygen, carbon, nitrogen, phosphorus, antimony, arsenic, or hydrogen, thereby reducing the current flowing vertically through the lattice by more than four orders of magnitude. The insulating / barrier layer allows for the deposition of low-defect epitaxial silicon adjacent to the insulating layer.

[0009] Mears et al.'s published UK patent application No. 2,347,520 discloses that the principles of aperiodic photonic bandgap (APBG) structures can be applied to electronic bandgap engineering. Specifically, the application discloses that material parameters, such as the location of band minimums and effective mass, can be tailored to produce novel aperiodic materials with desired bandgap structure properties. Other parameters, such as electrical conductivity, thermal conductivity, and dielectric constant or magnetic permeability, are disclosed as potentially being designed into the material.

[0010] Furthermore, U.S. Patent No. 6,376,337 to Wang et al. discloses a method for producing an insulating or barrier layer for semiconductor devices. This method includes depositing a layer of silicon and at least one additional element on a silicon substrate, such that the deposited layer is substantially defect-free, allowing substantially defect-free epitaxial silicon to be deposited on the deposited layer. Alternatively, a monolayer of one or more elements (preferably including oxygen) is adsorbed onto the silicon substrate. Multiple insulating layers sandwiched between the epitaxial silicon layers form a barrier composite.

[0011] Despite the existence of such methods, further enhancements using advanced semiconductor materials and process technologies may be expected to achieve improved performance in semiconductor devices. Summary of the Invention

[0012] A method for manufacturing a semiconductor device may include forming a first superlattice and a second superlattice adjacent to a semiconductor layer. Each of the first and second superlattices may include a plurality of stacked layers, wherein each layer group includes a plurality of stacked base semiconductor monolayers defining base semiconductor portions and at least one non-semiconductor monolayer confined within a lattice of an adjacent base semiconductor portion. Compared to the first superlattice, the second superlattice may have greater thermal stability with respect to the non-semiconductor atoms therein. The method may further include heating the first and second superlattices to cause non-semiconductor atoms from the first superlattice to migrate to at least one non-semiconductor monolayer of the second superlattice.

[0013] In an example embodiment, the first superlattice may be located below the second superlattice, and the method may further include forming a third superlattice above the second superlattice, which is similar to the first and second superlattices briefly described above. Furthermore, compared to the third superlattice, the second superlattice may have greater thermal stability with respect to non-semiconductor atoms.

[0014] The method may also include, for example, forming a semiconductor layer over a first and a second superlattice at a temperature of at least 1000°C and for a time period of at least thirty seconds. Again, for example, the semiconductor layer may have a thickness of at least 500 nm.

[0015] In an example implementation, forming a second superlattice may include forming the second superlattice at a temperature above 600°C. According to another example, forming a first superlattice may include forming the first superlattice at a temperature below 600°C. In some embodiments, the method may further include forming a semiconductor capping layer over the first and second superlattices. For example, heating may include annealing in an environment comprising at least one of hydrogen, nitrogen, helium, and argon. Again, for example, at least one non-semiconductor monolayer may comprise oxygen, and the base semiconductor layer may comprise silicon. Attached Figure Description

[0016] Figure 1 This is a greatly enlarged schematic cross-sectional view of a superlattice for a semiconductor device according to an example embodiment.

[0017] Figure 2 yes Figure 1 A perspective schematic atomic diagram of a portion of the superlattice shown.

[0018] Figure 3 This is a greatly enlarged schematic cross-sectional view of another embodiment of the superlattice according to the example embodiment.

[0019] Figure 4A This is for bulk silicon as in the prior art and for... Figures 1-2 The diagram shows the band structure of the 4 / 1Si / O superlattice calculated from the gamma point (G).

[0020] Figure 4B This is for bulk silicon as in the prior art and for... Figures 1-2 The diagram shows the band structure of the 4 / 1Si / O superlattice calculated from the Z point.

[0021] Figure 4C This is for bulk silicon as in the prior art and for... Figure 3 The diagram shows the band structure of the 5 / 1 / 3 / 1Si / O superlattice calculated from both the gamma point and the Z point.

[0022] Figure 5 and Figure 6 This is a schematic cross-sectional view of a semiconductor device fabricated using a superlattice with different non-semiconductor thermal stability according to the example method.

[0023] Figure 7 The illustration shows the relationship between the example embodiment and Figure 6 A flowchart of the process steps associated with the manufacture of the device.

[0024] Figure 8 This is based on existing methods and also on an example embodiment. Figure 7 A graph of atomic concentration versus depth for semiconductor devices fabricated using this method.

[0025] Figure 9 It corresponds to Figure 8 A table showing various oxygen concentrations.

[0026] Figure 10 It is based on Figure 7 A graph showing the effect of oxygen change on cap thickness in an example implementation of the method.

[0027] Figure 11 It corresponds to Figure 10 A table showing various oxygen concentrations.

[0028] Figure 12 It corresponds to Figure 7 A table of various oxygen concentrations for example implementations of the method.

[0029] Figure 13 This corresponds to the process including primary oxide growth and H2 annealing. Figure 7 A table of various oxygen concentrations for example implementations of the method.

[0030] Figure 14 This corresponds to H2 annealing after growth. Figure 7 A table of various oxygen concentrations for example implementations of the method.

[0031] Figure 15 and Figure 16 It corresponds to Figure 14 The method of oxygen change versus annealing time is illustrated in the graph.

[0032] Figure 17 This corresponds to annealing including H2 and N2. Figure 7 A table of various oxygen concentrations for example implementations of the method.

[0033] Figure 18 This corresponds to annealing including H2+N2+H2. Figure 7 A table of various oxygen concentrations for example implementations of the method.

[0034] Figure 19 It corresponds to Figure 18 The method of atomic concentration versus depth plot.

[0035] Figure 20 This corresponds to having an increased oxygen supply time. Figure 7 A table of various oxygen concentrations for example implementations of the method.

[0036] Figure 21 It corresponds to Figure 20 The method of atomic concentration versus depth plot.

[0037] Figure 22 This corresponds to the use of increased oxygen supply time and N2 annealing. Figure 7 A graph of atomic concentration versus depth for an example implementation of the method.

[0038] Figure 23 It includes according to Figure 7 A schematic cross-sectional view of a semiconductor device with a superlattice channel fabricated by a certain method.

[0039] Figure 24 It includes according to Figure 7A schematic cross-sectional view of a semiconductor device fabricated using a superlattice method and dividing the semiconductor layer into regions with the same conductivity type and different doping concentrations.

[0040] Figure 25 It includes according to Figure 7 A schematic cross-sectional view of a semiconductor device with a superlattice and a metal contact layer on top of the superlattice, fabricated by a certain method. Detailed Implementation

[0041] The exemplary embodiments will now be described more fully below with reference to the accompanying drawings, in which exemplary embodiments are illustrated. However, these embodiments may be implemented in many different forms and should not be construed as limited to the specific examples set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete. The same reference numerals refer to the same elements throughout, and apostrophes are used in different embodiments to indicate similar elements.

[0042] Generally, this disclosure relates to the formation of semiconductor devices using enhanced semiconductor superlattices. Enhanced semiconductor superlattices may also be referred to herein as “MST” layers / films or “MST technology”.

[0043] More specifically, MST technology involves advanced semiconductor materials, such as superlattices 25, which are further described below. The applicant does not wish to be bound by this, but theoretically demonstrates that certain superlattices, as described herein, reduce the effective mass of charge carriers and thereby lead to higher charge carrier mobility. Effective mass is described in the literature using various definitions. As a measure of improvement in effective mass, the applicant uses the “conductivity reciprocal effective mass tensor,” specifically for electrons and holes. and Defined as:

[0044] For electrons:

[0045]

[0046] And for holes:

[0047]

[0048] Where f is the Fermi-Dirac distribution, E F Here, T is the temperature, E(k,n) is the energy of the electron in the state corresponding to the wave vector k and the nth energy band, and the labels i and j refer to the Cartesian coordinates x, y and z. The integration is performed in the Brillouin zone (BZ), and the summation is performed on the energy bands with electron energies above the Fermi energy and on the energy bands with hole energies below the Fermi energy, respectively.

[0049] The applicant defines the reciprocal effective mass tensor of conductivity such that the larger the value of the corresponding component of the reciprocal effective mass tensor, the larger the tensor component of the material's conductivity. Similarly, the applicant does not wish to be bound by it, but theoretically states that the superlattices described herein set the value of the reciprocal effective mass tensor to enhance the conductivity of the material, such as for preferred directions of charge carrier transport. The reciprocal of the appropriate tensor element is called the effective mass of conductivity. In other words, to characterize the structure of semiconductor materials, the effective mass of electron / hole conductivity, calculated as described above and in the direction of expected charge carrier transport, is used to distinguish improved materials.

[0050] The applicant has identified improved materials or structures for use in semiconductor devices. More specifically, the applicant has identified materials or structures having band structures for which the effective mass of electrons and / or holes with appropriate conductivity is significantly less than the corresponding values ​​in silicon. In addition to the enhanced mobility characteristics of these structures, they can also be formed or used to provide piezoelectric, thermoelectric, and / or ferroelectric properties, which are advantageous for use in a variety of different types of devices, as will be discussed further below.

[0051] Now for reference Figure 1 and Figure 2 The material or structure is in the form of a superlattice 25, the structure of which is controlled at the atomic or molecular level and can be formed using known atomic or molecular layer deposition techniques. The superlattice 25 comprises multiple layers 45a-45n arranged in a stacked relationship, as detailed in the specific reference. Figure 1 A schematic cross-sectional view may be the best way to understand it.

[0052] Each layer group 45a-45n of the superlattice 25 exemplarily includes a plurality of stacked base semiconductor monolayers 46 defining corresponding base semiconductor portions 46a-46n and band-modification layers 50 on the base semiconductor portions. For clarity of illustration, Figure 1 The bandgap modification layer 50 is represented by dots.

[0053] The bandgap modification layer 50 exemplarily includes a non-semiconductor monolayer confined within the lattice of an adjacent base semiconductor portion. By "confined within the lattice of an adjacent base semiconductor portion," it means that at least some semiconductor atoms from the opposing base semiconductor portions 46a-46n are chemically bonded together through the intervening non-semiconductor monolayer 50, as in... Figure 2As seen in [the text]. Generally, this configuration can be made possible by controlling the amount of non-semiconductor material deposited on the semiconductor portions 46a-46n using atomic layer deposition techniques, such that not all (i.e., less than full or 100% coverage) of the available semiconductor bonding sites are filled with bonds to non-semiconductor atoms, as will be discussed further below. Therefore, as another monolayer 46 of semiconductor material is deposited on or above the non-semiconductor monolayer 50, the newly deposited semiconductor atoms will fill the remaining empty bonding sites of the semiconductor atoms below the non-semiconductor monolayer.

[0054] In other embodiments, more than one such non-semiconductor monolayer may be possible. It should be noted that references herein to non-semiconductor or semiconductor monolayers mean that the material used for the monolayer would be non-semiconductor or semiconductor if formed in bulk. That is, a single monolayer material, such as silicon, may not necessarily exhibit the same properties as if formed in bulk or relatively thick layers, as those skilled in the art will understand.

[0055] The applicant, not wishing to be bound by this, theoretically demonstrates that the band-modified layer 50 and the adjacent base semiconductor portions 46a-46n result in the superlattice 25 having a lower effective mass of charge carriers in the parallel layer direction than in other cases. Alternatively, this parallel direction is orthogonal to the stacking direction. The band-modified layer 50 can also result in the superlattice 25 having a common band structure, while also advantageously serving as an insulator between layers or regions perpendicularly above and below the superlattice.

[0056] Furthermore, this superlattice structure can advantageously act as a barrier to dopant and / or material diffusion between layers vertically above and below the superlattice 25. Therefore, these properties can advantageously allow the superlattice 25 to provide an interface for high-k dielectrics, which not only reduces the diffusion of high-k materials into the channel region but also advantageously reduces unwanted scattering effects and improves device mobility, as those skilled in the art will understand.

[0057] This also theoretically demonstrates that semiconductor devices including superlattice 25 can enjoy higher charge carrier mobility based on a lower effective conductivity mass than in other cases. In some embodiments, and as a result of band engineering achieved by the present invention, superlattice 25 can further have a substantially direct band gap, which can be particularly advantageous for, for example, optoelectronic devices.

[0058] The superlattice 25 also includes, exemplarily, a capping layer 52 on the upper group 45n. The capping layer 52 may include a plurality of base semiconductor monolayers 46. For example, the capping layer 52 may have between 1 and 100 base semiconductor monolayers 46, and more preferably between 10 and 50 monolayers. However, in some applications, the capping layer 52 may be omitted, or a thickness greater than 100 monolayers may be used.

[0059] Each base semiconductor portion 46a-46n may include a base semiconductor selected from the group consisting of group IV semiconductors, group III-V semiconductors, and group II-VI semiconductors. Of course, the term group IV semiconductor also includes group IV-IV semiconductors, as those skilled in the art will understand. More specifically, the base semiconductor may include at least one of, for example, silicon and germanium.

[0060] Each bandgap modification layer 50 may include a non-semiconductor selected from, for example, the group consisting of oxygen, nitrogen, fluorine, carbon, and carbon-oxygen. It is also desirable that the non-semiconductor be thermally stable through the deposition of subsequent layers, thereby facilitating fabrication. In other embodiments, the non-semiconductor may be another inorganic or organic element or compound compatible with a given semiconductor process, as will be understood by those skilled in the art. More specifically, the base semiconductor may include at least one of, for example, silicon and germanium.

[0061] It should be noted that the term monolayer means including both a single atomic layer and a single molecular layer. It should also be noted that the band-modification layer 50 provided by a single monolayer also means including a monolayer in which not all possible sites are occupied (i.e., there is less than complete or 100% coverage). For example, particularly refer to... Figure 2 The atomic diagram illustrates a 4 / 1 repeating structure for silicon as the basic semiconductor material and oxygen as a bandgap modifier. In the illustrated example, only half of the possible oxygen sites are occupied.

[0062] In other embodiments and / or using different materials, this half-occupancy will not necessarily be as those skilled in the art would understand. Indeed, it can be seen, even in this schematic diagram, that individual oxygen atoms in a given monolayer are not precisely aligned along the plane, as those skilled in the art of atomic deposition will understand. For example, a preferred occupancy range is from approximately one-eighth to one-half of the possible oxygen sites being filled, although other amounts may be used in some embodiments.

[0063] Silicon and oxygen are currently widely used in conventional semiconductor processes, and therefore manufacturers will be able to readily use these materials as described herein. Atomic or monolayer deposition is also now widely used. Therefore, as those skilled in the art will understand, semiconductor devices comprising a superlattice 25 according to the present invention can be readily adopted and implemented.

[0064] The applicant does not wish to be bound by it to theoretically demonstrate that, for superlattices, such as Si / O superlattices, the number of silicon monolayers should ideally be seven or fewer, so that the energy bands of the superlattice are common or relatively uniform everywhere, in order to achieve the desired advantages. Figure 1 and Figure 2 The 4 / 1 repeating Si / O structure shown has been modeled to demonstrate the enhanced mobility of electrons and holes in the X-direction. For example, the calculated effective conductivity mass of electrons (isotropic for bulk silicon) is 0.26, and 0.12 for the 4 / 1 SiO superlattice in the X-direction, resulting in a ratio of 0.46. Similarly, calculations for holes yield a value of 0.36 for bulk silicon and 0.16 for the 4 / 1 Si / O superlattice, resulting in a ratio of 0.44.

[0065] While such direction-preferred characteristics may be desirable in some semiconductor devices, others may benefit from a more uniform increase in mobility in any direction parallel to the layer set. Increased mobility for both electrons and holes, or only one of these types of charge carriers, may also be beneficial, as those skilled in the art will understand.

[0066] The lower effective conductivity mass of the 4 / 1Si / O embodiment of superlattice 25 can be less than two-thirds of the effective conductivity mass that would occur in other cases, and this applies to both electrons and holes. Of course, superlattice 25 can also include at least one type of conductive dopant, as those skilled in the art will understand.

[0067] In fact, now refer to another source Figure 3 Now, another embodiment of the superlattice 25' with different properties according to the present invention is described. In this embodiment, a repeating pattern of 3 / 1 / 5 / 1 is illustrated. More specifically, the lowest basic semiconductor portion 46a' has three monolayers, and the second lowest basic semiconductor portion 46b' has five monolayers. This pattern is repeated throughout the superlattice 25'. The band-modification layers 50' may each comprise a single monolayer. For such a Si / O superlattice 25', the enhancement of charge carrier mobility is independent of orientation in the layer plane. Figure 3 Other elements not specifically mentioned above are referenced above. Figure 1 The similar ones discussed here need not be discussed further.

[0068] In some device embodiments, all the base semiconductor portions of the superlattice may be of the same number of monolayer thicknesses. In other embodiments, at least some of the base semiconductor portions may be of different numbers of monolayer thicknesses. In still other embodiments, all the base semiconductor portions may be of different numbers of monolayer thicknesses.

[0069] exist Figures 4A-4C The diagram presents the band structure calculated using density functional theory (DFT). It is well known in the art that DFT underestimates the absolute value of the band gap. Therefore, all bands above the band gap can be shifted using appropriate "scissor corrections." However, the shape of the bands is known much more reliably. The vertical energy axis should be interpreted from this perspective.

[0070] Figure 4A The diagram shows the results for bulk silicon (represented by solid lines) and for silicon... Figure 1 The 4 / 1Si / O superlattice 25 shown (indicated by dashed lines) represents the band structure calculated from the gamma point (G). These directions refer to the unit cell of the 4 / 1Si / O structure, not the conventional Si unit cell, although the (001) direction in the figure does correspond to the (001) direction of the conventional Si unit cell and thus shows the expected location of the Si conduction band minimum. The (100) and (010) directions in the figure correspond to the (110) and (-110) directions of the conventional Si unit cell. Those skilled in the art will understand that the Si bands in the figure are folded to represent their proper reciprocal lattice orientations in the 4 / 1Si / O structure.

[0071] As can be seen, compared to bulk silicon (Si), the conduction band minimum of the 4 / 1Si / O structure is located at the gamma point, while the valence band minimum appears at the edge of the Brillouin region in the (001) direction, which we call the Z point. It may also be noted that the curvature of the conduction band minimum of the 4 / 1Si / O structure is greater than that of Si, due to band splitting caused by perturbations introduced by the additional oxygen layer.

[0072] Figure 4B The band structure calculated from the Z point is shown for both bulk silicon (solid line) and 4 / 1Si / O superlattice 25 (dashed line). This figure illustrates the enhanced curvature of the valence band in the (100) direction.

[0073] Figure 4C The diagram shows the results for bulk silicon (solid line) and the results for... Figure 3 The band structures of the 25' superlattice 5 / 1 / 3 / 1Si / O structure (dashed lines) are calculated from both the gamma point and the Z point. Due to the symmetry of the 5 / 1 / 3 / 1Si / O structure, the calculated band structures in the (100) and (010) directions are equivalent. Therefore, the effective conductivity and mobility are expected to be isotropic in the plane parallel to the layers, i.e., perpendicular to the (001) stacking direction. Note that in the 5 / 1 / 3 / 1Si / O example, both the conduction band minimum and the valence band maximum are at or near the Z point.

[0074] Although the increased curvature is an indication of reduced effective mass, it can be properly compared and distinguished via calculations of the reciprocal effective mass tensor. This leads the applicant to further theoretically demonstrate that the 5 / 1 / 3 / 1 superlattice 25' should be essentially a direct bandgap. As those skilled in the art will understand, the appropriate matrix elements used for optical transitions are another indication of the distinction between direct and indirect bandgap behavior.

[0075] Using the above techniques, advanced semiconductor devices can be fabricated, in which MST layers of different configurations are used to migrate non-semiconductor atoms from one or more superlattices to another(one or more) superlattice(s) to increase the number of non-semiconductor atoms therein after the superlattice is deposited. (See reference...) Figure 5 In one example embodiment of the semiconductor device 120, the process involves depositing a "less stable" first superlattice layer 125a (regarding the thermal stability of the non-semiconductor material) on a substrate 121, and then depositing a "more stable" second superlattice layer 125 on top of the less unstable superlattice layer. A capping layer 152 is formed on the second superlattice 125b, and these layers are then heated to cause non-semiconductor atoms from the first superlattice 125a to migrate to one or more non-semiconductor monolayers of the second superlattice 125b.

[0076] For further reference Figure 6 and Figure 7 Flowchart 170, starting at block 171, in an alternative embodiment, at blocks 172-174, the less unstable first superlattice 125a' and third superlattice 125c' are formed on each side of the more stable second superlattice layer 125b' (i.e., the second superlattice is located between the first and third superlattice layers in a vertical stack, as shown). More specifically, oxygen-implanted MST layers implanted at temperatures below 600°C are generally more ideally aligned (planar) than those implanted at temperatures above 600°C, making it easier to form oxygen sheets or clusters (assuming all other process conditions are the same).

[0077] In this regard, "planar" refers to silicon subsurface sites where oxygen atoms are more uniformly absorbed into almost all ideal sites between silicon atoms, rather than aggregated into islands. However, oxygen bound in these planar structures is generally less stable for thermal annealing than oxygen aggregated into islands. It should be noted that other factors can also affect stability, such as the monolayer dosage and the spacing between monolayers.

[0078] After forming a second superlattice 125b' as a more stable MST layer embedded between the less stable MST layers 125a' and 125c', the entire superlattice stack is annealed at frame 175. For example, this annealing can occur in an environment containing H2, N2, He, Ar, etc. Other gases may also be included. During annealing, oxygen undergoes a diffusion process such as metastable decomposition, causing oxygen atoms to diffuse upwards through a concentration gradient to define the aggregation of oxygen atoms at the location of the (more stable) second MST layer 125b'. This results in the second superlattice having additional oxygen atoms during its formation compared to the initially deposited superlattice, thereby providing enhanced insulating properties, similar to a buried insulating layer. This process advantageously allows superlattices 125, 125' to have higher oxygen concentrations without associated defects that would otherwise occur if one attempted to deposit such a higher amount of oxygen between the epitaxial growth of the base semiconductor portions 46a-46n. In other words, attempting to directly grow an MST layer with such a high oxygen concentration could additionally lead to undesirable high defect levels.

[0079] Although the examples mentioned above are described based on one or two less stable MST layers adjacent to a more stable MST layer, those skilled in the art will understand that other numbers of more stable / less unstable superlattices can be used in different embodiments. Furthermore, while the examples are presented based on silicon and oxygen, other semiconductor and non-semiconductor materials, as discussed further above, can also be used. For example, in some embodiments, nitrogen can be used to help stabilize oxygen at desired locations, as discussed further below. Additionally, in some embodiments, multiple different MST layer stacks can be located at different positions to define more than one embedded insulating layer.

[0080] Figure 7 The method also includes, exemplarily, forming a relatively thick capping layer (e.g., 500 nm or more) via a high-temperature growth process, for example, for durations greater than 1000°C for more than thirty seconds, and more specifically for durations at 1100°C for one minute or longer (box 176). Such thicknesses are common in certain semiconductor processes, and superlattices 125b, 125b' are advantageously capable of withstanding such high-temperature processes for the necessary durations, whereas MST layers formed using typical formulations are unlikely to withstand such high-temperature processes for these durations. Figure 7 The method exemplarily ends at box 177, although further process operations can typically be performed at this point to fabricate the final device, such as those described further below.

[0081] Turn Figures 8-22 Now describing the use Figure 7The methods illustrated in the figures result in the fabrication of various MST films. As will be further discussed below, different film formulations or configurations are used in different runs in the examples below. For example, these may correspond to different numbers of repeating layer groups, different numbers of semiconductor monolayers in the groups (e.g., 4 / 1, 3 / 1-5 / 1, 10 / 1, etc.), and / or different types of semiconductor and / or non-semiconductor materials in different MST layers, as will be further discussed below with respect to various fabrication examples. Furthermore, in the examples below, an etch-back process is used to fabricate an MST film with reduced defects. Further details of such an etch-back process are set forth in U.S. Patent Nos. 10,566,191 and 10,811,498, assigned to the applicant and incorporated herein by reference in their entirety. In the examples below, the MST film formed using this etch-back process is referred to as a “MEGA” MST layer.

[0082] First refer to Figure 8 Figure 180 and Figure 9 Table 182, in Figure 6 In the first example embodiment of the structure shown, a series of MEGA1(10 / 1)+MEGA6(2 / 1)+MEGA1(10 / 1) MST layers are grown. The silicon cap layer was annealed at 1000°C in an H2 environment for five minutes. Post-growth annealing of the entire stack, including the cap layer, was also performed at 900°C in an N2 environment. MEGA6 is an example of an MST process that tends to form a more stable sheet-like MST layer, while MEGA1 is an example of an MST process that tends to form a more desirable planar (lower thermal stability) MST layer. In Figure 180, curve 5063 shows the oxygen content in the MEGA6 MST film before annealing. 16 The concentration of O) is shown in curve 5064, and the oxygen concentration after H2 growth and H2 annealing is also shown. This manufacturing run confirms that, as a result of some lost oxygen being collected from the MEGA1 layer, oxygen advantageously accumulates on the MEGA6 layer, resulting in a 2.1-fold increase in oxygen in the MEGA6 layer (in Figure 8 At a depth of approximately 44 nm.

[0083] For further reference Figure 10 Figure 184 and Figure 11 The associated table 186, in Figure 6 In another example embodiment of the structure shown, a series of MEGA1(10 / 1)+MEGA6(2 / 1)+MEGA1(10 / 1)MST layers are grown, but the silicon cap is increased in thickness to Furthermore, a growth-after-annealing process was performed at 1000°C for 300 seconds. Figure 184 illustrates the process for... and The dose loss points for the central MST membrane (185), top MST membrane (186), bottom MST membrane (187), and total MST membrane (188) are shown for both cap thicknesses. It will be noted that the central peak of interest exhibits a smaller dose gain (111% vs. 103% gain) with a thicker cap layer. Furthermore, the total dose is similar for both cap thicknesses (26% vs. 27% loss). These results are further presented in Table 186.

[0084] Turn Figure 12 Table 190, performed with Figure 11 The process operation is similar to that presented in the paper, but with the change that the top MEGA1 stack has five fewer cycles (i.e., MEGA1(10 / 1) + MEGA6(2 / 1) + MEGA1(5 / 1) MST layer + (Stacking of the top layers). This resulted in a 9% reduction in baseline intermediate MST layer dose even when the MEGA6 layer was not modified. Assuming the difference was not due to secondary ion mass spectrometry (SIMS) error, reducing the number of top layers to five cycles did not significantly reduce the oxygen dose gain in the intermediate MEGA6 layer.

[0085] Turn Figure 13 Table 192, performed with Figure 11 The process operation is similar to that presented in the paper, but it includes primary oxide growth (i.e., MEGA1(10 / 1) + MEGA6(2 / 1) + MEGA1(10 / 1) MST layer) before H2 annealing after growth. (Cover stack). More specifically, in the illustrated run 5113, the wafer was unloaded and allowed to form a day's worth of native oxide before a five-minute annealing at 1000°C. The result was that the dose gain of the intermediate MST film was lower than that of the thin-cap annealing baseline 5064, but 5% higher than that of the aforementioned thick-cap annealing sample (5114). In other words, native oxide growth prior to annealing was found to have a relatively small impact on the process.

[0086] Turn Figure 14 Table 194, performed with Figure 11 Similar process operation was presented, but with a series of growth followed by H2 annealing at 1000°C for 300, 150, and 600 seconds (i.e., MEGA1(10 / 1) + MEGA6(2 / 1) + MEGA1(10 / 1) MST layer + (Stacking of caps). As seen in Table 194, this manufacturing run shows that the peak oxygen dose continued to increase after ten minutes of annealing. Furthermore, after the longest annealing time, the peak oxygen concentration increased by 10%. Reference Figure 15 and Figure 16Figures 260 and 265 will further illustrate these results. Figure 260 corresponds to the MEGA1(10 / 1)+MEGA6(2 / 1)+MEGA1(10 / 1) MST layer+ The cap was subjected to extended H2 annealing at 1000°C for 300, 150, and 600 seconds, while Figure 265 corresponds to the aforementioned MEGA1(10 / 1)+MEGA6(2 / 1)+MEGA1(5 / 1) MST layer + The embodiments were also subjected to extended H2 annealing at 1000°C for 300, 150, and 600 seconds. Points 261 and 266 represent the central MST membrane oxygen ( 16 O) Dosage loss; points 262 and 267 represent the top MST membrane oxygen dose loss; points 263 and 268 represent the bottom membrane oxygen dose loss; and points 264 and 269 represent the total MST membrane oxygen dose loss. In both cases, the peak oxygen dose continued to increase after ten minutes of annealing, and the peak oxygen concentration changed only slightly.

[0087] Turn Figure 17 Table 270, executed in Figure 14 The same process was presented, but with an even longer annealing at 1000°C to determine when the oxygen dose saturated and / or decreased. More specifically, this post-growth annealing consisted of a first H2 annealing of 300 seconds, followed by a one-hour N2 annealing. This resulted in a 121% increase (135%, including nitrogen impurities) in the peak oxygen dose of the intermediate MST membrane.

[0088] Turn Figure 18 Table 272 shows another similar process run performed, but using a series of H2+N2+H2 growth followed by annealing (MEGA1(10 / 1)+MEGA6(2 / 1)+MEGA1(10 / 1)MST layers+ (Cover). Specifically, one wafer was annealed at 1000°C for 300 seconds after N2 annealing, while another wafer was annealed at 1100°C for 120 seconds after N2 annealing. These rigorous annealing processes demonstrate the stability of the intermediate MST layer, such as... Figure 19 This is further demonstrated in Figure 274. Stability checks of the intermediate MST layer after N2 annealing show that nitrogen advantageously stabilizes the MST layer for baking at 1100°C for up to two minutes. Further details regarding the use of nitrogen in the MST membrane are provided in co-pending U.S. Publication No. 2020 / 0135489, which is assigned to the applicant and is incorporated herein by reference in its entirety.

[0089] For reference now Figure 20In another example implementation described in Table 276, a similar process run was performed, but with the addition of an intermediate (MEGA6) oxygen dosage time (MEGA1(10 / 1) + MEGA6(2 / 1) + MEGA1(10 / 1) MST layer + (Cover). More specifically, the intermediate (MEGA6) MST membrane dose time was increased from 13 seconds used in the previous example to 19 seconds. After annealing at 1000°C for 300 seconds, the intermediate MST layer dose increased by 120% from the new baseline, or by 155% oxygen from the original baseline of 13 seconds. These results are in Figure 21 Further illustration is shown in Figure 278.

[0090] For reference now Figure 22 In another example implementation described in Figure 280, another operation related to... Figures 20-21 A similar process was described, but with the addition of post-growth annealing in an N2 environment. After annealing at 1000°C for 300 seconds, the intermediate MST layer dose increased by 120% from the new baseline. N2 annealing had a relatively small effect on the total oxygen dose and achieved 5.75 E21 atoms / cm². 3 The peak oxygen concentration was 11.5 atomic percent. Therefore, it can be understood from the results shown that N2 annealing helps stabilize oxygen atoms in the sample, and in addition, it adds extra impurities to the silicon lattice of the intermediate MST layer, totaling more than twelve atomic percent impurities.

[0091] In summary, the above-described process provides an advantageous method for forming an epitaxial MST layer with enhanced insulating properties embedded within silicon without introducing unmanageable defect levels within the MST layer. For example, the silicon spacer layer can be between 1 and 30 angstroms, although wider spacing can be used in some embodiments. For instance, the dose per MST layer can range from 1 / 4 to less than that of a complete monolayer, where a lower dose per cycle is feasible but potentially requires more MST donor layers. This arrangement typically allows for a higher dose and / or greater stability of the layer on which oxygen will accumulate. This will facilitate the accumulation of oxygen to the desired target region. Furthermore, nitrogen can also be used in the above-described process, and in the example, nitrogen is used via hydrogen annealing after growth. Nitrogen-containing (NO) or hydrazine (H4N2) can also be used to form nitrogen and / or nitrogen and oxygen monolayers. The growth temperature range for the MST layer advantageously does not require modification from existing process flows, and the annealing temperature can be in the range of 700°C to 1100°C, and more specifically, for example, between 900°C and 1000°C. In some embodiments, laser annealing and rapid thermal processing (RTP) or very fast peak annealing to 900°C to 1200°C may also be used.

[0092] The example membrane stacks described above are all constructed around a 10 / 1+2 / 1+10 / 1 (MEGA1+MEGA6+MEGA1) or 10 / 1+2 / 1+5 / 1 layer configuration. However, those skilled in the art will understand that other combinations of layers or layer types may also be used. An enhanced oxygen MST membrane can also be formed using an oxygen+carbon / carbon-oxygen configuration, as further described in the co-pending application filed by the applicant on July 2, 2021, with attorney's file number 6260056, which is incorporated herein by reference in its entirety. In other example embodiments, 28 Si and / or 18 O materials can also be incorporated into enhanced oxygen MST membranes, as further described in the co-pending U.S. Application Serials Nos. 17 / 236,329 and 17 / 236,289, filed April 21, 2021, and U.S. Application Serials Nos. 17 / 330,860 and 17 / 330,831, filed May 26, 2021, both of which are assigned to the applicant and are incorporated herein by reference in their entirety.

[0093] For example, applications of the oxygen-rich MST layer formed according to the above method may include, but are not limited to: SOI (silicon-on-insulator); local in-situ insulators to reduce parasitic capacitance between adjacent devices; resonant tunneling diodes (RTDs); etch stop; enhanced 3D devices above and below the oxide layer (e.g., FINFETs); deep junction control; contamination removal of metals and dopants (e.g., dopant blocking); mobility enhancement; and epitaxial resistors.

[0094] More specifically, now refer to Figure 23 An example semiconductor device (MOSFET) 220 in which an enhanced oxygen superlattice 225 formed according to the method described above can be incorporated is illustrated. The illustrated MOSFET 220 includes a substrate 221, a source region 222 / drain region 223, a source extension 226 / drain extension 227, and a channel region therebetween provided by the oxygen and carbon / carbon-oxygen superlattice 225. The channel may be formed partially or completely within the superlattice 225. A source silicide layer 230 / drain silicide layer 231 and source contacts 232 / drain contacts 233 cover the source / drain regions, as will be understood by those skilled in the art. The regions indicated by dashed lines 234a, 234b are optional residual portions initially formed with the superlattice 225 but subsequently heavily doped. In other embodiments, these residual superlattice regions 234a, 234b may be absent, as will also be understood by those skilled in the art. The gate 235 exemplarily includes a gate insulating layer 237 adjacent to the channel provided by the superlattice 225 and a gate electrode layer 236 on the gate insulating layer. Sidewall spacers 240, 241 are also disposed in the illustrated MOSFET 220.

[0095] For further reference Figure 24 Another example of a device in which an enhanced oxygen superlattice 325 formed according to the above method can be incorporated is a semiconductor device 300, wherein the superlattice serves as a dopant diffusion barrier superlattice to advantageously increase the surface dopant concentration, thereby allowing higher N₂ concentrations during in-situ doping epitaxial processes by preventing diffusion into the channel region 330 of the device. D (Concentration of active dopant at the metal / semiconductor interface). More specifically, device 300 exemplarily includes a semiconductor layer or substrate 301, and spaced-apart source regions 302 and drain regions 303 formed in the semiconductor layer, wherein a channel region 330 extends between the source regions 302 and drain regions 303. A dopant diffusion barrier superlattice 325 exemplarily extends through the source regions 302 to divide the source regions into a lower source region 304 and an upper source region 305, and the dopant diffusion barrier superlattice 325 also extends through the drain regions 303 to divide the drain regions into a lower drain region 306 and an upper drain region 307.

[0096] The dopant diffusion barrier superlattice 325 can also conceptually be considered as a source dopant barrier superlattice within the source region 302, a drain dopant barrier superlattice within the drain region 303, and a bulk dopant barrier superlattice below the channel 330, although in this configuration all three are provided by a single blanket deposition of the MST material as a continuous film across the substrate 301. The semiconductor material above the dopant barrier superlattice 325 (which defines the upper source region 305 / upper drain region 307 and the channel region 330) can be epitaxially grown on the dopant barrier superlattice 325, for example, as a thick superlattice capping layer or a bulk semiconductor layer. In the illustrated example, the upper source region 305 / upper drain region 307 can each be flush with the upper surface of the semiconductor layer (i.e., they can be embedded within this layer).

[0097] Thus, the upper source region 305 / upper drain region 307 can advantageously have the same conductivity as the lower source region 304 / lower drain region 306, but with a higher dopant concentration. In the illustrated example, the upper source region 305 / upper drain region 307 and the lower source region 304 / lower drain region 306 are N-type for N-channel devices, but these regions can also be P-type for P-channel devices. Surface dopants can be introduced, for example, by ion implantation. However, dopant diffusion is reduced by the diffusion-blocking superlattice 325 MST film material because it traps point defects / interstitials introduced by ion implantation that mediates dopant diffusion.

[0098] Semiconductor device 300 also exemplarily includes a gate 308 on a channel region 330. The gate exemplarily includes a gate insulating layer 309 and a gate electrode 310. Sidewall spacers 311 are also provided in the illustrated example. Further details regarding device 300 and other similar structures in which oxygen-enhanced superlattices may be used are set forth in U.S. Patent No. 10,818,755 to the applicant and incorporated herein by reference in its entirety.

[0099] Turn Figure 24 Now, another example embodiment of a semiconductor device 400 in which an enhanced oxygen superlattice 325 formed according to the method described above can be used is described. More specifically, in the illustrated example, both the source dopant diffusion barrier superlattice 425s and the drain dopant diffusion barrier superlattice 425d advantageously provide Schottky barrier height modulation via heteroepitaxial film integration. More specifically, the lower source region 404 and the lower drain region 406 comprise materials different from those of the upper source region 405 and the upper drain region 407. In this example, the lower source region 404 and the lower drain region 406 are silicon, while the upper source region 405 and the upper drain region 407 are SiGeC, although different materials can be used in different embodiments. Lower metal layers (Ti) 442, 443 are formed on the upper source region 405 and the upper drain region 407 (SiGeC layers). Upper metal layers (Co) 444 and 445 are formed on lower metal layers 442 and 443, respectively. Because MST materials are effective in integrating heteroepitaxial semiconductor materials, doping Si (1-2%) with Si or SiGe on Si can cause a positive conduction band shift. More specifically, this is a SiGeC / MST / n+Si structure that is effective in reducing the Schottky barrier height. Further details regarding device 400 are described in the aforementioned '755 patent.

[0100] Furthermore, etching is a crucial process step in the fabrication of many semiconductor devices. In some cases, uniform etching is important, but in others, selective etching, or etching that stops at a specific depth, is desired. One example is the formation of gate-around-the-all-around (GAA) devices, where alternating stacks of silicon (Si) and silicon-germanium (SiGe) are typically grown, allowing the SiGe to be selectively etched later in the process before the gate is formed around the silicon, leaving only silicon. An example GAA device incorporating an enhanced oxygen superlattice is described in the aforementioned co-pending application, case number 6260056. Enhanced oxygen superlattices can also be used in other devices, such as certain image sensors or RF devices, where it is desirable to remove silicon beneath the device of interest or to etch silicon to a specific depth. Many more examples will be familiar to those skilled in the art.

[0101] Typical MST silicon formulations result in etching rates very similar to conventional silicon. However, the enhanced oxygen MST films described herein can exhibit significantly different etching rates than conventional silicon, making these films suitable for selective etching or etching-stop applications. It is also anticipated that incorporating other elements into the films could facilitate the realization of “signals” that can be used to indicate the endpoint of a given etching, as those skilled in the art will understand.

[0102] Many modifications and other embodiments of the invention will arise in those skilled in the art upon which the teachings presented in the foregoing description and the associated drawings will come to mind. Therefore, it is to be understood that the invention is not limited to the specific embodiments disclosed, and that these modifications and embodiments are intended to be included within the scope of the appended claims.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: A first superlattice and a second superlattice are formed, which are adjacent to the semiconductor layer. Each of the first and second superlattices includes multiple stacked layers, each layer including multiple stacked basic semiconductor monolayers defining a basic semiconductor portion and at least one non-semiconductor monolayer confined within a lattice of an adjacent basic semiconductor portion. The second superlattice has greater thermal stability with respect to the thermally induced migration of non-semiconductor atoms from positions within the first superlattice compared to the thermally induced migration of non-semiconductor atoms from positions within the second superlattice. as well as The first superlattice and the second superlattice are heated to cause non-semiconductor atoms from the first superlattice to migrate to at least one non-semiconductor monolayer of the second superlattice.

2. The method of claim 1, wherein the first superlattice is below the second superlattice; and the method further comprises forming a third superlattice above the second superlattice, and the third superlattice comprising a plurality of stacked layers, wherein each layer comprises a plurality of stacked basic semiconductor monolayers defining a basic semiconductor portion and at least one non-semiconductor monolayer constrained within a lattice of an adjacent basic semiconductor portion; wherein the second superlattice has greater thermal stability with respect to the thermally induced migration of non-semiconductor atoms from positions within the third superlattice compared to the thermally induced migration of non-semiconductor atoms from positions within the third superlattice.

3. The method of claim 1, further comprising forming a semiconductor layer over the first and second superlattices at a temperature of at least 1000°C and for a time period of at least thirty seconds.

4. The method of claim 3, wherein the semiconductor layer has a thickness of at least 500 nm.

5. The method of claim 1, wherein forming the second superlattice comprises forming the second superlattice at a temperature above 600°C.

6. The method of claim 1, wherein forming the first superlattice comprises forming the first superlattice at a temperature below 600°C.

7. The method of claim 1, further comprising forming a semiconductor capping layer over the first superlattice and the second superlattice.

8. The method of claim 1, wherein heating comprises annealing in an environment comprising at least one of hydrogen, nitrogen, helium or argon.

9. The method of claim 1, wherein at least one non-semiconductor monolayer of the first superlattice and the second superlattice comprises oxygen.

10. The method of claim 1, wherein the base semiconductor layers of the first and second superlattices comprise silicon.

11. A method for manufacturing a semiconductor device, the method comprising: A first superlattice is formed on the semiconductor layer; A second superlattice is formed above the first superlattice; A third superlattice is formed above the second superlattice. Each of the first, second, and third superlattices includes multiple stacked layers, each layer including multiple stacked basic semiconductor monolayers defining a basic semiconductor portion and at least one non-semiconductor monolayer confined within a lattice of an adjacent basic semiconductor portion. The second superlattice has greater thermal stability with respect to the thermally induced migration of non-semiconductor atoms from positions within the first and third superlattices, respectively. Heating the first superlattice, the second superlattice, and the third superlattice causes non-semiconductor atoms from the first superlattice and the third superlattice to migrate to at least one non-semiconductor monolayer of the second superlattice; as well as A semiconductor layer is formed above a third superlattice at a temperature of at least 1000°C and for a time period of at least thirty seconds.

12. The method of claim 11, wherein the semiconductor layer has a thickness of at least 500 nm.

13. The method of claim 11, wherein forming the second superlattice comprises forming the second superlattice at a temperature above 600°C.

14. The method of claim 11, wherein forming the first superlattice and the third superlattice comprises forming the first superlattice and the third superlattice at a temperature below 600°C.

15. The method of claim 11, further comprising forming a semiconductor capping layer over a third superlattice.

16. The method of claim 11, wherein heating comprises annealing in an environment comprising at least one of hydrogen, nitrogen, helium, or argon.

17. A method for manufacturing a semiconductor device, the method comprising: A first superlattice and a second superlattice are formed, which are adjacent to the semiconductor layer. Each of the first and second superlattices includes multiple stacked layers, each layer including multiple stacked basic semiconductor monolayers defining a basic semiconductor portion and at least one non-semiconductor monolayer confined within a lattice of an adjacent basic semiconductor portion. The second superlattice has greater thermal stability with respect to the thermally induced migration of non-semiconductor atoms from positions within the first superlattice compared to the thermally induced migration of non-semiconductor atoms from positions within the second superlattice. as well as Heating the first superlattice and the second superlattice causes non-semiconductor atoms from the first superlattice to migrate to at least one non-semiconductor monolayer of the second superlattice; Forming a second superlattice includes forming a second superlattice at a temperature above 600°C, and forming a first superlattice includes forming a first superlattice at a temperature below 600°C.

18. The method of claim 17, wherein the first superlattice is below the second superlattice; and the method further comprises forming a third superlattice above the second superlattice, and the third superlattice comprising a plurality of stacked layers, wherein each layer comprises a plurality of stacked basic semiconductor monolayers defining a basic semiconductor portion and at least one non-semiconductor monolayer constrained within a lattice of an adjacent basic semiconductor portion; and wherein the second superlattice has greater thermal stability with respect to the thermally induced migration of non-semiconductor atoms from positions within the third superlattice compared to the thermally induced migration of non-semiconductor atoms from positions within the second superlattice.

19. The method of claim 17, further comprising forming a semiconductor layer over the first and second superlattices at a temperature of at least 1000°C and for a time period of at least thirty seconds.

20. The method of claim 19, wherein the semiconductor layer has a thickness of at least 500 nm.

21. The method of claim 17, further comprising forming a semiconductor capping layer over the first superlattice and the second superlattice.

22. The method of claim 17, wherein heating comprises annealing in an environment comprising at least one of hydrogen, nitrogen, helium, or argon.

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