A Reliability Testing Method and System for Metal Wiring Structures

Abstract

This application provides a method for reliability testing of metal interconnect structures. The method includes: acquiring the fusing current of a reference chip and the lifetime of its metal interconnect structure; calculating the fusing current of a test chip under different metal interconnect structure lifetimes based on the fusing current of the reference chip and the lifetime of its metal interconnect structure; sequentially applying the fusing current corresponding to different lifetimes of the metal interconnect structure of the test chip to the metal interconnect structure of the test chip, with the order of application being from low to high according to the corresponding lifetime; measuring the resistance value of the metal interconnect structure each time current is applied, and determining the lifetime of the metal interconnect structure of the test chip based on the resistance value. By utilizing the inherent failure mechanism of the metal interconnect structure and directly using the parameter relationships of the reference chip to calculate the lifetime of the test chip, the accuracy and efficiency of metal interconnect structure lifetime assessment can be improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a method and system for testing the reliability of metal interconnect structures. Background Technology

[0002] Metal interconnects are an important part of semiconductor manufacturing processes, and in practical applications, reliability issues caused by electromigration (EM) due to high temperature and current are becoming increasingly prominent.

[0003] To detect anomalies in the process with the highest probability, the via resistance continuity (Via Rc) parameter test in wafer acceptance testing (WAT) is designed with a chain structure (Viachain). Vias connect short metal layers above and below, repeating thousands of units. When process issues cause defects in the metal layer or vias, the WAT Via Rc parameter generally deviates, potentially leading to out-of-control (OOC) or out-of-specification (OOS) errors, posing an EM reliability risk. However, the specific location and size of the defect are difficult to ascertain due to the chain structure. Another traditional structure used for testing is a longer metal layer with two vias connected side-by-side. In anomalies, defects have a relatively lower probability of occurring, making the test results prone to distortion.

[0004] Therefore, it is necessary to provide a more effective and reliable technical solution. Summary of the Invention

[0005] This application provides a method and system for reliability testing of metal interconnect structures, which can improve the accuracy and efficiency of life assessment of metal interconnect structures.

[0006] One aspect of this application provides a method for testing the reliability of a metal interconnect structure, comprising: acquiring the fusing current of a reference chip and the lifetime of the metal interconnect structure of the reference chip; calculating the fusing current of a test chip under different metal interconnect structure lifetimes based on the fusing current of the reference chip and the lifetime of the metal interconnect structure of the reference chip; sequentially applying the fusing current corresponding to different lifetimes of the metal interconnect structure of the test chip to the metal interconnect structure of the test chip, wherein the order of applying the fusing current is from low to high according to the corresponding lifetime; measuring the resistance value of the metal interconnect structure each time the current is applied, and determining the lifetime of the metal interconnect structure of the test chip based on the resistance value.

[0007] In some embodiments of this application, the method for determining the lifespan of the metal interconnect structure of the test chip based on the resistance value includes: if the resistance value is open, it indicates that the lifespan of the metal interconnect structure of the test chip is lower than the lifespan corresponding to the current current; if the resistance value is not open, it indicates that the lifespan of the metal interconnect structure of the test chip is greater than or equal to the lifespan corresponding to the current current.

[0008] In some embodiments of this application, the different lifespans include 1 year, 3 years, and 10 years.

[0009] In some embodiments of this application, the method for determining the lifespan of the metal interconnect structure of the test chip based on the resistance value includes: calculating the fusing current corresponding to the metal interconnect structure of the test chip for 1 year, 3 years, and 10 years of lifespan based on the fusing current of the reference chip and the lifespan of the metal interconnect structure of the reference chip; applying the fusing current corresponding to the metal interconnect structure of the test chip for 1 year of lifespan to the metal interconnect structure of the test chip, measuring the resistance value of the metal interconnect structure; if the resistance value is open, it indicates that the lifespan of the metal interconnect structure of the test chip is less than 1 year, and the test ends; if the resistance value is not open, it indicates that the lifespan of the metal interconnect structure of the test chip is greater than or equal to 1 year, and the test continues; the metal interconnect structure of the test chip... The fusing current corresponding to the interconnect structure's 3-year lifespan is applied to the metal interconnect structure of the test chip, and the resistance value of the metal interconnect structure is measured. If the resistance value is open, it indicates that the lifespan of the metal interconnect structure of the test chip is less than 3 years, and the test ends. If the resistance value is not open, it indicates that the lifespan of the metal interconnect structure of the test chip is greater than or equal to 3 years, and the test continues. The fusing current corresponding to the interconnect structure's 10-year lifespan is applied to the metal interconnect structure of the test chip, and the resistance value of the metal interconnect structure is measured. If the resistance value is open, it indicates that the lifespan of the metal interconnect structure of the test chip is less than 10 years, and the test ends. If the resistance value is not open, it indicates that the lifespan of the metal interconnect structure of the test chip is greater than or equal to 10 years, and the test continues.

[0010] In some embodiments of this application, the formula for calculating the fusing current of the test chip under different metal interconnect structure lifetimes based on the fusing current of the reference chip and the metal interconnect structure lifetime of the reference chip is as follows:

[0011] ,

[0012] in, and These are the lifespan of the metal interconnect structure of the test chip and the fusing current of the test chip, respectively. and These are the metal interconnect structure lifetime of the reference chip and the fusing current of the reference chip, respectively. It is the current density acceleration factor.

[0013] In some embodiments of this application, the method for obtaining the fusing current of a reference chip includes: applying a current to the metal interconnect structure of the reference chip and monitoring the resistance value of the metal interconnect structure in real time; gradually increasing the current until the metal interconnect structure melts and the resistance value is turned on; the current corresponding to the turned-on resistance value is the fusing current of the reference chip.

[0014] In some embodiments of this application, the testing method further includes: obtaining the fusing current of several reference chips, obtaining a square normal distribution map of the fusing current, and taking the 0.1% quantile under the normal distribution as the reference value of the square of the fusing current.

[0015] One aspect of this application also provides a metal interconnect structure reliability testing system, comprising: a processor, which executes the metal interconnect structure reliability testing method as described above when it is in operation.

[0016] Another aspect of this application provides a method for testing the reliability of a metal interconnect structure, comprising: acquiring the fusing current of a reference chip and the lifetime of the metal interconnect structure of the reference chip; acquiring the fusing current of a test chip; and calculating the lifetime of the metal interconnect structure of the test chip based on the fusing current of the reference chip, the lifetime of the metal interconnect structure of the reference chip, and the fusing current of the test chip.

[0017] In some embodiments of this application, the formula for calculating the metal interconnect structure lifetime of the test chip based on the fusing current of the reference chip, the metal interconnect structure lifetime of the reference chip, and the fusing current of the test chip is as follows:

[0018] ,

[0019] in, and These are the lifespan of the metal interconnect structure of the test chip and the fusing current of the test chip, respectively. and These are the metal interconnect structure lifetime of the reference chip and the fusing current of the reference chip, respectively. It is the current density acceleration factor.

[0020] In some embodiments of this application, the method for obtaining the fusing current of a reference chip includes: applying a current to the metal interconnect structure of the reference chip and monitoring the resistance value of the metal interconnect structure in real time; gradually increasing the current until the metal interconnect structure melts and the resistance value is turned on; the current corresponding to the turned-on resistance value is the fusing current of the reference chip.

[0021] In some embodiments of this application, the testing method further includes: obtaining the fusing current of several reference chips, obtaining a square normal distribution map of the fusing current, and taking the 0.1% quantile under the normal distribution as the reference value of the square of the fusing current.

[0022] In some embodiments of this application, the method for obtaining the fusing current of a test chip includes: applying a current to the metal interconnect structure of the test chip and monitoring the resistance value of the metal interconnect structure in real time; gradually increasing the current until the metal interconnect structure melts and the resistance value is turned on; the current corresponding to the turned-on resistance value is the fusing current of the test chip.

[0023] Another aspect of this application provides a metal interconnect structure reliability testing system, comprising: a processor, which executes the metal interconnect structure reliability testing method as described above when it is in operation.

[0024] This application provides a reliability testing method and system for metal interconnect structures. By utilizing the inherent failure mechanism of metal interconnect structures and directly using the parameter relationships of a reference chip to calculate the lifespan of the test chip, the accuracy and efficiency of metal interconnect structure lifespan assessment can be improved. Attached Figure Description

[0025] The following accompanying drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals denote similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting and exemplary, and the drawings are for illustrative purposes only and are not intended to limit the scope of this application. Other embodiments may similarly fulfill the inventive intent of this application. It should be understood that the drawings are not drawn to scale. Wherein:

[0026] Figure 1 This is a flowchart of a reliability testing method for a metal interconnect structure as described in an embodiment of this application;

[0027] Figure 2 This is a flowchart of another reliability testing method for metal interconnect structures described in an embodiment of this application. Detailed Implementation

[0028] The following description provides specific application scenarios and requirements for this application, intended to enable those skilled in the art to make and use the content of this application. Various partial modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but rather to the widest scope consistent with the claims.

[0029] The technical solution of the present invention will be described in detail below with reference to the embodiments and accompanying drawings.

[0030] To assess the potential risks of electromigration to metal interconnect structures, there are generally two approaches: directly measuring electromigration using chain-like structures, which provides representative defect locations, but the validity of the electromigration results is weak due to the Blechlength effect of short interconnects; and measuring electromigration using long metal layer structures, which results in poor defect representativeness and weak accuracy and validity of the test results.

[0031] The methods described above all have certain limitations, making it impossible to correctly assess the reliability risks caused by the offset of resistance continuity parameters due to abnormal events.

[0032] To address the aforementioned issues, this application provides a reliability testing method for metal interconnect structures. By utilizing the inherent failure mechanism of the metal interconnect structure and directly using the parameter relationships of a reference chip to calculate the lifespan of the test chip, the accuracy and efficiency of metal interconnect structure lifespan assessment can be improved.

[0033] Figure 1 This is a flowchart illustrating a reliability testing method for a metal interconnect structure according to an embodiment of this application. The following is in conjunction with… Figure 1 This application provides a detailed description of a reliability testing method for a metal interconnect structure.

[0034] Embodiments of this application provide a reliability testing method for metal interconnect structures, referencing Figure 1 As shown, it includes:

[0035] Step S1: Obtain the fusing current of the reference chip and the lifetime of the metal interconnect structure of the reference chip;

[0036] Step S2: Calculate the fusing current of the test chip under different metal interconnect structure lifetimes based on the fusing current of the reference chip and the metal interconnect structure lifetime of the reference chip.

[0037] Step S3: Apply the fusing current corresponding to different lifetimes of the metal interconnect structure of the test chip to the metal interconnect structure of the test chip in sequence, and apply the fusing current in order from low to high according to the corresponding lifetime.

[0038] Step S4: Each time current is applied, measure the resistance value of the metal interconnect structure, and determine the lifespan of the metal interconnect structure of the test chip based on the resistance value.

[0039] refer to Figure 1 As shown, in step S1, the fusing current of the reference chip and the lifespan of the metal interconnect structure of the reference chip are obtained.

[0040] In some embodiments of this application, the reference chip refers to a qualified chip manufactured according to a reference process. "Qualified" means that it meets the manufacturer's requirements for various chip parameters.

[0041] It should be noted that the Mean Time To Failure (MTTF) of the metal interconnect structure of the reference chip is a known parameter. Since it is a reference chip, its metal interconnect structure lifetime can be determined based on past usage data, or the lifetime of the metal interconnect structure can be calculated based on the reference structure.

[0042] In some embodiments of this application, the method for obtaining the fusing current of a reference chip includes: applying a current to the metal interconnect structure of the reference chip and monitoring the resistance value of the metal interconnect structure in real time; gradually increasing the current until the metal interconnect structure melts and the resistance value is turned on; the current corresponding to the turned-on resistance value is the fusing current of the reference chip.

[0043] The fusing current refers to the critical current at which excessive current breaks down the metal, causing it to melt and break. Therefore, to obtain the fusing current, a current can be directly applied to the metal interconnect structure until it melts; the current value at which melting occurs is the fusing current. To make the result more accurate, the rate of current increase can be slowed down when gradually increasing the current to prevent the obtained fusing current from exceeding the actual fusing current. However, slowing down the rate of current increase also reduces the efficiency of obtaining the fusing current, requiring more time. Therefore, in practical processes, a compromise between efficiency and accuracy can be chosen.

[0044] In some embodiments of this application, the testing method further includes: acquiring the fusing current of several reference chips, obtaining a squared normal distribution plot of the fusing current, and taking the 0.1% quantile of the normal distribution as the reference value of the squared fusing current. Since the squared fusing current is actually used when subsequently using the metal interconnect structure lifetime and fusing current of the reference chips, a normal distribution plot of the squared fusing current can be directly generated to obtain a more representative reference value of the squared fusing current as the parameter actually used. The reason for taking the 0.1% quantile of the normal distribution as the reference value of the squared fusing current is that the conventional method tests and infers the metal interconnect structure lifetime at the 0.1% quantile.

[0045] In other embodiments of this application, other mathematical methods can also be used to obtain representative parameter values. For example, after obtaining multiple fusing currents, the average of the multiple fusing current values ​​can be taken as the parameter actually used. Furthermore, mathematical concepts such as mode and median can be combined for calculation. In summary, compared to obtaining a single measurement that may not be representative, using mathematical statistical methods after multiple measurements can calculate a more representative fusing current parameter.

[0046] Continue to refer to Figure 1 As shown, in step S2, the fusing current of the test chip under different metal interconnect structure lifetimes is calculated based on the fusing current of the reference chip and the metal interconnect structure lifetime of the reference chip.

[0047] In some embodiments of this application, the formula for calculating the fusing current of the test chip under different metal interconnect structure lifetimes based on the fusing current of the reference chip and the metal interconnect structure lifetime of the reference chip is as follows:

[0048] In other words,

[0049]

[0050] in, and These are the lifespan of the metal interconnect structure of the test chip and the fusing current of the test chip, respectively. and These are the metal interconnect structure lifetime of the reference chip and the fusing current of the reference chip, respectively. It is the current density acceleration factor.

[0051] In the above formula, the lifetime of the metal interconnect structure of the test chip is... and the fusing current of the test chip The current density acceleration factor has already been obtained in step S1. Given a fixed metal interconnect structure (length, diameter, density, etc.), which is also known, the only difference lies in setting different test chips to measure the lifetime of the metal interconnect structure. The corresponding fusing current can then be calculated. For example, in some embodiments of this application, the different lifespans are set to 1 year, 3 years, and 10 years. Substituting 1 year, 3 years, and 10 years into the above formula, the corresponding fusing current of the test chip under the condition that the metal interconnect structure lifespan is 1 year, 3 years, and 10 years can be calculated. , , .

[0052] In other embodiments of this application, other lifetimes can be set for the metal interconnect structure of the test chip, such as 1 year, 2 years, 4 years, 6 years, 8 years, 10 years, etc. The specific selection can be set according to actual needs.

[0053] Below is a brief introduction to the derivation process of the above formula.

[0054] Electromigration test lifetime:

[0055]

[0056] in, Related to the operating current and the overcurrent area, the general principle is that by knowing the proportion of the defect area that causes the shift in the continuity parameter of the resistance, the proportion of the lifetime change can be known.

[0057] Under direct current conditions, the energy generated by temperature and current is directly proportional:

[0058]

[0059] For materials of the same type, the melting temperature is constant, meaning the temperature tested is the same under the same ambient temperature. For a constant value:

[0060]

[0061] After the transformation, it is:

[0062]

[0063] For a given test structure, its corresponding Related to materials and wiring, it is a fixed value, that is, the melting temperature in formula (3) and Proportional:

[0064]

[0065] Where A is a constant term.

[0066] At the same current, melting is most likely to occur at the weakest point, that is, the area with the smallest cross-sectional area, where the current density is the highest and the temperature rises the fastest. In other words:

[0067]

[0068] The fusing current of the reference chip With the fusing current of the test chip The corresponding areas are as follows:

[0069]

[0070] Combining formulas (1) and (4):

[0071]

[0072] The above formula can be simplified to obtain:

[0073]

[0074] Continue to refer to Figure 1 As shown, in step S3, the fusing current corresponding to different lifetimes of the metal interconnect structure of the test chip is applied sequentially to the metal interconnect structure of the test chip, and the order of applying the fusing current is from low to high according to the corresponding lifetime.

[0075] For example, in some embodiments of this application, the different lifespans are set to 1 year, 3 years, and 10 years, and the corresponding fusing currents of the test chip under the condition that the metal interconnect structure lifespan is 1 year, 3 years, and 10 years are respectively , , Then, the fuse current will be sequentially... , , It is applied to the metal connection structure of the test chip.

[0076] Continue to refer to Figure 1 As shown, in step S4, the resistance value of the metal interconnect structure is measured each time a current is applied, and the lifespan of the metal interconnect structure of the test chip is determined based on the resistance value.

[0077] In some embodiments of this application, the method for determining the lifespan of the metal interconnect structure of the test chip based on the resistance value includes: if the resistance value is open (indicating that the metal interconnect structure has melted), it means that the lifespan of the metal interconnect structure of the test chip is lower than the lifespan corresponding to the current current; if the resistance value is not open (indicating that the metal interconnect structure has not melted), it means that the lifespan of the metal interconnect structure of the test chip is greater than or equal to the lifespan corresponding to the current current.

[0078] The following describes the detailed process of steps S3 and S4 using metal interconnect structure lifespan settings of 1 year, 3 years, and 10 years as examples.

[0079] The corresponding fusing currents of the test chip under the conditions of 1 year, 3 years, and 10 years of metal interconnect structure life are as follows: , , Sequentially apply the fuse current. , , It is applied to the metal connection structure of the test chip.

[0080] First, the fusing current of the metal interconnect structure of the test chip under a 1-year lifespan is determined. The resistance is applied to the metal interconnect structure of the test chip, and the resistance value of the metal interconnect structure is measured. If the resistance value is open, it means that the lifespan of the metal interconnect structure of the test chip is less than 1 year, and the test ends. If the resistance value is not open, it means that the lifespan of the metal interconnect structure of the test chip is greater than or equal to 1 year, and the test continues.

[0081] Secondly, the fusing current of the metal interconnect structure of the test chip over a 3-year lifespan will be determined. The resistance is applied to the metal interconnect structure of the test chip, and the resistance value of the metal interconnect structure is measured. If the resistance value is open, it means that the lifespan of the metal interconnect structure of the test chip is less than 3 years, and the test ends. If the resistance value is not open, it means that the lifespan of the metal interconnect structure of the test chip is greater than or equal to 3 years, and the test continues.

[0082] Then, the fusing current corresponding to the metal interconnect structure of the test chip over a 10-year lifespan is measured. The resistance is applied to the metal interconnect structure of the test chip, and the resistance value of the metal interconnect structure is measured. If the resistance value is open, it indicates that the lifespan of the metal interconnect structure of the test chip is less than 10 years, and the test ends. If the resistance value is not open, it indicates that the lifespan of the metal interconnect structure of the test chip is greater than or equal to 10 years, and the test continues.

[0083] By repeating this process multiple times, the lifespan of the metal interconnect structure of the test chip can be obtained and divided into three groups: (0-1) years, (1-3) years, and (3-10) years.

[0084] This application provides a reliability testing method for metal interconnect structures. By utilizing the inherent failure mechanism of metal interconnect structures and directly using the parameter relationships of a reference chip to calculate the lifespan of the test chip, the accuracy and efficiency of metal interconnect structure lifespan assessment can be improved.

[0085] Embodiments of this application also provide a metal interconnect structure reliability testing system, including: a processor, which executes the metal interconnect structure reliability testing method as described above when it is working. The metal interconnect structure reliability testing method has been described in detail above and will not be repeated here.

[0086] This application provides a reliability testing system for metal interconnect structures. By utilizing the inherent failure mechanism of metal interconnect structures and directly using the parameter relationships of a reference chip to calculate the lifespan of the test chip, the accuracy and efficiency of metal interconnect structure lifespan assessment can be improved.

[0087] Figure 2This is a flowchart illustrating another reliability testing method for a metal interconnect structure as described in an embodiment of this application. The following is in conjunction with… Figure 2 This application provides a detailed description of another method for testing the reliability of metal interconnect structures as described in the embodiments.

[0088] Embodiments of this application also provide a reliability testing method for metal interconnect structures, referencing... Figure 2 As shown, it includes:

[0089] Step S11: Obtain the fusing current of the reference chip and the lifetime of the metal interconnect structure of the reference chip;

[0090] Step S12: Obtain the fusing current of the test chip;

[0091] Step S13: Calculate the lifespan of the metal interconnect structure of the test chip based on the fusing current of the reference chip, the lifespan of the metal interconnect structure of the reference chip, and the fusing current of the test chip.

[0092] refer to Figure 2 As shown, in step S11, the fusing current of the reference chip and the lifespan of the metal interconnect structure of the reference chip are obtained.

[0093] In some embodiments of this application, the reference chip refers to a qualified chip manufactured according to a reference process. "Qualified" means that it meets the manufacturer's requirements for various chip parameters.

[0094] It should be noted that the Mean Time To Failure (MTTF) of the metal interconnect structure of the reference chip is a known parameter. Since it is a reference chip, its metal interconnect structure lifetime can be determined based on past usage data, or the lifetime of the metal interconnect structure can be calculated based on the reference structure.

[0095] In some embodiments of this application, the method for obtaining the fusing current of a reference chip includes: applying a current to the metal interconnect structure of the reference chip and monitoring the resistance value of the metal interconnect structure in real time; gradually increasing the current until the metal interconnect structure melts and the resistance value is turned on; the current corresponding to the turned-on resistance value is the fusing current of the reference chip.

[0096] The fusing current refers to the critical current at which excessive current breaks down the metal, causing it to melt and break. Therefore, to obtain the fusing current, a current can be directly applied to the metal interconnect structure until it melts; the current value at which melting occurs is the fusing current. To make the result more accurate, the rate of current increase can be slowed down when gradually increasing the current to prevent the obtained fusing current from exceeding the actual fusing current. However, slowing down the rate of current increase also reduces the efficiency of obtaining the fusing current, requiring more time. Therefore, in practical processes, a compromise between efficiency and accuracy can be chosen.

[0097] In some embodiments of this application, the testing method further includes: acquiring the fusing current of several reference chips, obtaining a squared normal distribution plot of the fusing current, and taking the 0.1% quantile of the normal distribution as the reference value of the squared fusing current. Since the squared fusing current is actually used when subsequently using the metal interconnect structure lifetime and fusing current of the reference chips, a normal distribution plot of the squared fusing current can be directly generated to obtain a more representative reference value of the squared fusing current as the parameter actually used. The reason for taking the 0.1% quantile of the normal distribution as the reference value of the squared fusing current is that the conventional method tests and infers the metal interconnect structure lifetime at the 0.1% quantile.

[0098] In other embodiments of this application, other mathematical methods can also be used to obtain representative parameter values. For example, after obtaining multiple fusing currents, the average of the multiple fusing current values ​​can be taken as the parameter actually used. Furthermore, mathematical concepts such as mode and median can be combined for calculation. In summary, compared to obtaining a single measurement that may not be representative, using mathematical statistical methods after multiple measurements can calculate a more representative fusing current parameter.

[0099] Continue to refer to Figure 2 As shown, in step S12, the fusing current of the test chip is obtained.

[0100] In some embodiments of this application, the method for obtaining the fusing current of a test chip includes: applying a current to the metal interconnect structure of the test chip and monitoring the resistance value of the metal interconnect structure in real time; gradually increasing the current until the metal interconnect structure melts and the resistance value is turned on; the current corresponding to the turned-on resistance value is the fusing current of the test chip. The principle of obtaining the fusing current has been explained above and will not be repeated here.

[0101] Step S13: Calculate the lifespan of the metal interconnect structure of the test chip based on the fusing current of the reference chip, the lifespan of the metal interconnect structure of the reference chip, and the fusing current of the test chip.

[0102] In some embodiments of this application, the formula for calculating the metal interconnect structure lifetime of the test chip based on the fusing current of the reference chip, the metal interconnect structure lifetime of the reference chip, and the fusing current of the test chip is as follows:

[0103] ,

[0104] in, and These are the lifespan of the metal interconnect structure of the test chip and the fusing current of the test chip, respectively. and These are the metal interconnect structure lifetime of the reference chip and the fusing current of the reference chip, respectively. Let be the current density acceleration factor. The derivation of the above formula has been explained previously and will not be repeated here.

[0105] In the above formula, the lifetime of the metal interconnect structure of the test chip is... and the fusing current of the test chip The current density acceleration factor has already been obtained in step S11. Given a fixed metal interconnect structure (length, diameter, density, etc.), which is also known, the fusing current of the test chip can be determined. This information was also obtained in step S12, therefore the lifetime of the metal interconnect structure of the test chip can be directly calculated. .

[0106] In some embodiments of this application, to obtain more representative data, multiple test samples can be selected to obtain multiple fusing currents, and then multiple lifetime values ​​can be calculated. The average, median, or mode of these multiple lifetime values ​​can then be taken to obtain more representative lifetime parameters.

[0107] This application provides a reliability testing method for metal interconnect structures. By utilizing the inherent failure mechanism of metal interconnect structures and directly using the parameter relationships of a reference chip to calculate the lifespan of the test chip, the accuracy and efficiency of metal interconnect structure lifespan assessment can be improved.

[0108] Embodiments of this application also provide a metal interconnect structure reliability testing system, including: a processor, which executes the metal interconnect structure reliability testing method as described above when it is working. The metal interconnect structure reliability testing method has been described in detail above and will not be repeated here.

[0109] This application provides a reliability testing system for metal interconnect structures. By utilizing the inherent failure mechanism of metal interconnect structures and directly using the parameter relationships of a reference chip to calculate the lifespan of the test chip, the accuracy and efficiency of metal interconnect structure lifespan assessment can be improved.

[0110] In summary, after reading this application, those skilled in the art will understand that the foregoing application content is presented by way of example only and is not restrictive. Although not explicitly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of this application.

[0111] It should be understood that the term "and / or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be an intermediate element.

[0112] It should also be understood that the terms “comprising,” “containing,” “including,” or “comprise”, when used in this application, indicate the presence of the described features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or groups thereof.

[0113] It should also be understood that although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of this application, a first element in some embodiments may be referred to as a second element in other embodiments. The same reference numerals or the same reference signs denote the same elements throughout the specification.

[0114] Furthermore, this application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Therefore, differences from the illustrated shapes are foreseeable due to factors such as manufacturing techniques and / or tolerances. Therefore, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in shape caused, for example, by manufacturing processes. Thus, the regions shown in the figures are substantially schematic, and their shapes are not intended to illustrate the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

Claims

1. A method for testing the reliability of a metal interconnect structure, characterized in that, include: Obtain the fusing current of the reference chip and the lifetime of the metal interconnect structure of the reference chip; The fusing current of the test chip under different metal interconnect structure lifetimes is calculated based on the fusing current of the reference chip and the metal interconnect structure lifetime of the reference chip. The formula for calculating the fusing current of the test chip under different metal interconnect structure lifetimes based on the fusing current of the reference chip and the metal interconnect structure lifetime of the reference chip is as follows: ， in, and These are the lifespan of the metal interconnect structure of the test chip and the fusing current of the test chip, respectively. and These are the metal interconnect structure lifetime of the reference chip and the fusing current of the reference chip, respectively. It is the current density acceleration factor; The fusing current corresponding to different lifetimes of the metal interconnect structure of the test chip is sequentially applied to the metal interconnect structure of the test chip, and the order of applying the fusing current is from low to high according to the corresponding lifetime. Each time current is applied, the resistance value of the metal interconnect structure is measured, and the lifespan of the metal interconnect structure of the test chip is determined based on the resistance value.

2. The test method as described in claim 1, characterized in that, The method for determining the lifespan of the metal interconnect structure of the test chip based on the resistance value includes: if the resistance value is open, it indicates that the lifespan of the metal interconnect structure of the test chip is lower than the lifespan corresponding to the current current; if the resistance value is not open, it indicates that the lifespan of the metal interconnect structure of the test chip is greater than or equal to the lifespan corresponding to the current current.

3. The test method as described in claim 2, characterized in that, The different lifespans include 1 year, 3 years, and 10 years.

4. The test method as described in claim 3, characterized in that, The method for determining the lifespan of the metal interconnect structure of the test chip based on the resistance value includes: Based on the fusing current of the reference chip and the lifespan of the metal interconnect structure of the reference chip, the fusing currents corresponding to the metal interconnect structure of the test chip at 1 year, 3 years, and 10 years of lifespan are calculated. Apply the fusing current corresponding to the metal interconnect structure of the test chip under a 1-year lifespan to the metal interconnect structure of the test chip, and measure the resistance value of the metal interconnect structure. If the resistance value is open, it means that the lifespan of the metal interconnect structure of the test chip is less than 1 year, and the test ends. If the resistance value is not open, it means that the lifespan of the metal interconnect structure of the test chip is greater than or equal to 1 year, and the test continues. Apply the fusing current corresponding to the metal interconnect structure of the test chip under a 3-year lifespan to the metal interconnect structure of the test chip, and measure the resistance value of the metal interconnect structure. If the resistance value is open, it means that the lifespan of the metal interconnect structure of the test chip is less than 3 years, and the test ends. If the resistance value is not open, it means that the lifespan of the metal interconnect structure of the test chip is greater than or equal to 3 years, and the test continues. Apply the fusing current corresponding to the metal interconnect structure of the test chip under a 10-year lifespan to the metal interconnect structure of the test chip, and measure the resistance value of the metal interconnect structure. If the resistance value is open, it means that the lifespan of the metal interconnect structure of the test chip is less than 10 years, and the test ends. If the resistance value is not open, it means that the lifespan of the metal interconnect structure of the test chip is greater than or equal to 10 years, and the test continues.

5. The test method as described in claim 1, characterized in that, Methods for obtaining the fusing current of a reference chip include: A current is applied to the metal interconnect structure of the reference chip and the resistance value of the metal interconnect structure is monitored in real time. Gradually increase the current until the metal interconnect structure melts, and the resistance value becomes open; The current corresponding to the open resistance value is the fuse current of the reference chip.

6. The test method as described in claim 1, characterized in that, Also includes: Obtain the fusing current of several reference chips to get the square normal distribution of the fusing current, and take the 0.1% quantile of the normal distribution as the reference value of the square of the fusing current.

7. A reliability testing system for metal interconnect structures, characterized in that, include: A processor, which, when operating, executes the metal interconnect structure reliability test method as described in any one of claims 1 to 6.

8. A method for testing the reliability of a metal interconnect structure, characterized in that, include: Obtain the fusing current of the reference chip and the lifetime of the metal interconnect structure of the reference chip; Obtain the fusing current of the test chip; The lifetime of the metal interconnect structure of the test chip is calculated based on the fusing current of the reference chip, the lifetime of the metal interconnect structure of the reference chip, and the fusing current of the test chip. The formula for calculating the lifetime of the metal interconnect structure of the test chip based on the fusing current of the reference chip, the lifetime of the metal interconnect structure of the reference chip, and the fusing current of the test chip is as follows: ， in, and These are the lifespan of the metal interconnect structure of the test chip and the fusing current of the test chip, respectively. and These are the metal interconnect structure lifetime of the reference chip and the fusing current of the reference chip, respectively. It is the current density acceleration factor.

9. The test method as described in claim 8, characterized in that, Methods for obtaining the fusing current of a reference chip include: A current is applied to the metal interconnect structure of the reference chip and the resistance value of the metal interconnect structure is monitored in real time. Gradually increase the current until the metal interconnect structure melts, and the resistance value becomes open; The current corresponding to the open resistance value is the fuse current of the reference chip.

10. The test method as described in claim 8, characterized in that, Also includes: Obtain the fusing current of several reference chips to get the square normal distribution of the fusing current, and take the 0.1% quantile of the normal distribution as the reference value of the square of the fusing current.

11. The test method as described in claim 8, characterized in that, Methods for obtaining the fusing current of a test chip include: Apply current to the metal interconnect structure of the test chip and monitor the resistance value of the metal interconnect structure in real time; Gradually increase the current until the metal interconnect structure melts, and the resistance value becomes open; The current corresponding to the open resistance value is the fuse current of the test chip.

12. A reliability testing system for metal interconnect structures, characterized in that, include: A processor, which, when operating, executes the metal interconnect structure reliability test method as described in any one of claims 8 to 11.

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