A method for implementing arbitrary wave triggering in an oscilloscope analyzer

Abstract

The present invention discloses a method for realizing arbitrary wave triggering in an oscilloscope analyzer. The master-slave digital triggering based on "coarse and fine" two-stage triggering is adopted by using the logic resources in the FPGA. The master trigger finds the "coarse" point, locates the trigger point within one FGPA clock cycle, and the slave trigger finds the "fine" point to improve the trigger accuracy to 1 sampling point. Among them, hysteresis comparison technology and carry look-ahead algorithm are introduced in the "coarse" trigger to realize the digital trigger judgment of parallel trigger data, so as to solve the problem of low trigger accuracy. At the same time, the present invention designs an arbitrary wave triggering function. Based on the master-slave digital trigger system, an arbitrary waveform generator with external trigger function is realized. The present invention also solves the problem that the traditional devices with arbitrary wave function cannot simultaneously realize that the arbitrary waveform generator is used as a source to output to other devices under test and the device itself can realize the external trigger function without relying on an external source.

Description

[0001] Technical Field

[0002] The present invention belongs to the technical field of electronic measuring instruments, and more specifically, relates to a method for realizing arbitrary wave triggering in an oscilloscope analyzer. Background Art

[0003] In the field of modern high-speed testing, due to requirements such as the testing environment and testing indicators, testing instruments are required not only to have high-index and multi-functional technical characteristics, but also to have basic characteristics such as portability, light weight, and low power consumption. However, although general desktop oscilloscopes integrated with industrial control computers have high technical performance, they are too bulky and not suitable for the testing environment; although existing portable oscilloscope analysis devices are small in size and low in power consumption, their indicators such as bandwidth, storage depth, and real-time sampling rate are relatively low and do not meet the testing performance. Therefore, designing a portable, high-index, and multi-functional oscilloscope analyzer is of great significance in the field of high-speed signal testing.

[0004] The triggering technology essential in digital storage oscilloscopes is the closest prior art. Triggering technology is an important means for stable waveform display and obtaining signals of interest in digital storage oscilloscopes. In a Chinese invention patent authorized and announced on May 14, 2021, with the authorization announcement number CN110596439B and the title "A Digital Trigger Detection Method", it is proposed to sample and deserialize the output signal (trigger signal) of a trigger comparator using a high-speed gigabit transceiver in an FPGA, and output parallel trigger data; in the FPGA, the state of the parallel trigger signal is judged to identify the position of the state jump, so as to determine the position of the trigger point in the parallel acquisition data. Although this invention patent solves the limitation of the internal working clock frequency of the FPGA on the trigger accuracy and improves the trigger accuracy to a certain extent, in essence, this invention patent still generates trigger signals through an analog channel, and it is impossible to avoid the jitter of the analog device comparator and the systematic error introduced by the different paths of the trigger signal and the ADC sampling data.

[0005] In digital storage oscilloscopes, trigger sources are generally divided into internal trigger sources and external trigger sources. The internal trigger source is the input signal of the analog channel, and the external trigger source is the signal input through the external trigger input port. To implement the external trigger function of traditional digital storage oscilloscopes, an additional signal generator must be used as the external trigger input signal source, and then the signal is processed through a dedicated external trigger channel or analog channel. The external trigger signal (ETS) is obtained through an analog comparator. This not only increases the additional usage cost but also has higher requirements for the test environment, and at the same time, the trigger accuracy is relatively low. Traditional digital storage oscilloscopes with arbitrary waveform functions do not have the arbitrary waveform trigger function. They cannot simultaneously implement the function of using the arbitrary waveform generator as a source to output to other devices under test and the function of achieving external trigger without relying on an external source for their own devices. Traditional devices can only implement one of these functions at the same time, which is not suitable for the analysis of electronic systems with small space, multiple parameters, and high flexibility.

[0006] Figure 1 is the trigger principle block diagram of a traditional oscilloscope analyzer with arbitrary waveform function

[0007] such as Figure 1 shown, for a traditional oscilloscope analyzer with arbitrary waveform function, the host computer sends digital waveform source data with specific amplitude and frequency according to the arbitrary waveform parameters set by the user. These data are stored in the internal RAM of the FPGA, and then specific data are parsed according to the set frequency using the direct digital frequency synthesis principle to obtain digital waveform data with amplitude and frequency information. The arbitrary waveform data are transmitted to the data sending module and then transmitted to the DAC through the data sending module for digital-to-analog conversion, and then the obtained arbitrary waveform signal (AWG signal) is output for use by the device under test or used as an external trigger signal source to achieve the external trigger function. A traditional oscilloscope analyzer with arbitrary waveform function cannot simultaneously implement the function of using the arbitrary waveform generator as a source to output to other devices under test and the function of achieving external trigger without relying on an external source for its own device. Traditional devices can only implement one of these functions at the same time, which is not suitable for the analysis of electronic systems with small space, multiple parameters, and high flexibility. When choosing to implement the external trigger function, the arbitrary waveform signal is input to the external trigger channel through an external connection line ( Figure 1 the connection method ① in), and the external trigger comparison signal is generated through the trigger comparator and received by the data receiving module in the FPGA and then sent to the trigger source selection module in the trigger module; when the arbitrary waveform signal is output for use by other devices under test ( Figure 1② In the connection method, the device under test inputs the analog signal to be tested into the analog channel (signal conditioning channel) for conditioning, and then performs ADC conversion. After the ADC conversion, the sampled data is received by another data receiving module. One path passes through the decimation module and then enters the FIFO for storage under the control of the trigger signal Trig, and then is read out for three-dimensional mapping. The mapped waveform data is controlled by the communication interface and sent to the host computer for display. The other path is sent to the trigger coupling module for coupling selection, and then sent to the trigger comparator of the trigger module to generate an internal trigger comparison signal to the trigger source selection module. The trigger source selection module selects the internal trigger comparison signal or the external trigger comparison signal according to the instruction of the host computer and sends it to the trigger control module to generate the trigger signal Trig. In this way, the internal working clock frequency of the FPGA has limitations on the trigger accuracy, and the trigger accuracy is not high. At the same time, it is impossible to avoid the jitter of the analog device comparator and the systematic error introduced by the different paths of the trigger signal and the ADC sampled data. Summary of the Invention

[0008] The purpose of the present invention is to overcome the deficiencies of the prior art and provide a method for realizing arbitrary wave triggering in an oscilloscope analyzer to improve the trigger accuracy and realize the external trigger function of the device without relying on an external source, and avoid the systematic error introduced by the different paths of the trigger signal and the ADC sampled data.

[0009] To achieve the above-mentioned invention purpose, the method for realizing arbitrary wave triggering in an oscilloscope analyzer according to the present invention is characterized by including:

[0010] (1) The FPGA receives the ADC sampled and quantized data and performs serial-to-parallel conversion

[0011] The FPGA's data receiving module receives the MGSPS sampled data of ADC sampling and quantization from one channel. The working frequency of the FPGA is F MHz. The MGSPS sampled data is decelerated to N-channel parallel sampled data through the data receiving module, and N = M * 1000 / F;

[0012] The N-channel parallel sampled data is divided into two paths for data transmission. In one path, the parallel sampled data enters the decimation module for decimation processing according to the time base gear requirement, and the processed parallel sampled data is stored in the main FIFO. In the other path, the parallel sampled data is transmitted to the trigger coupling module. The trigger coupling module selects the parallel sampled data from this channel or the N-channel parallel waveform data from the arbitrary waveform data processing module as the N-channel trigger parallel data according to the instruction issued by the host computer. At the same time, the coupling method is selected, and finally the coupled N-channel trigger parallel data is transmitted to the main trigger module for trigger "coarse" searching;

[0013] Among them, the oscilloscope analyzer integrates an arbitrary waveform generator module. The arbitrary waveform data generated by it is sent to the DAC to be converted into an arbitrary waveform, and after being conditioned by the signal conditioning module, it is output to the device under test for use. Another path transmits the arbitrary waveform data to the arbitrary waveform data processing module for processing, and then obtains N-channel parallel waveform data and transmits it to the trigger coupling module;

[0014] (2) The main trigger module performs "coarse" trigger point finding

[0015] The N-channel parallel trigger data after coupling of one channel is sent into a trigger comparison module in the main trigger module. The trigger comparison module sequentially compares the N-channel parallel trigger data with the high and low threshold comparison levels set by the user to determine in which FPGA clock cycle the N-channel parallel trigger data meets the trigger condition, that is, the FPGA clock cycle where the trigger point is located:

[0016] First, the nth channel trigger data of the N-channel parallel trigger data enters the comparison circuit. When comparing with the high threshold comparison level, when it is greater than the high threshold comparison level, the comparison circuit outputs a high comparison signal TH n is high. When it is less than or equal to the low threshold comparison level, the comparison circuit outputs a high comparison signal TH n is low. Similarly, when comparing with the low threshold comparison level, when it is greater than the low threshold comparison level, the comparison circuit outputs a low comparison signal TL n is high. When it is less than or equal to the low threshold comparison level, the comparison circuit outputs a low comparison signal TL n is low;

[0017] Then, the high comparison signal TH n , the low comparison signal TL n are sent into the trigger result comparison circuit, and the comparison result signal LS n is output:

[0018] LS1 = TH1 | (TL1 & LS N )

[0019] LS2 = TH2 | (TL2 & TH1) | (TL2 & TL1 & LS N )

[0020] LS3 = TH3 | (TL3 & TH2) | (TL3 & TL2 & TH1) | (TL3 & TL2 & TL1 & LS N )

[0021] LS4 = TH4 | (TL4 & TH3) | (TL4 & TL3 & TH2) | (TL4 & TL3 & TL2 & TH1) | (TL4 & TL3 & TL2 & TL1 & LS N )

[0022] ……

[0023] LS N = TH N |(TL N & TH N-1 )|(TL N & TL N-1 & TH N-2 )|(TL N & TL N-1 & TL N-2 & TH N-3 )…|(TL N & TL N-1 & TL N-2 …& TL2& TH1)|(TL N & TL N-1 & TL N-2 …& TL1& LS N )

[0024] Among them, the comparison result signal LS on the right side of the equation N is the comparison result of the Nth trigger data in the previous FPGA clock cycle;

[0025] Then, the trigger result comparison circuit outputs the comparison result signal LS n , n = 1, 2, …, N to the trigger source module;

[0026] In the trigger source module, the comparison result signals output by the trigger source modules from multiple channels are received, and a comparison result signal LS of one channel is selected according to the instruction issued by the host computer n , n = 1, 2, …, N or an external trigger comparison signal is selected to generate a trigger signal Trig1 and transmitted to the trigger control module:

[0027] In the trigger source module, first, the trigger source selection module selects a comparison result signal LS of one channel according to the instruction issued by the host computer n , n = 1, 2, …, N or selects an external trigger comparison signal as the trigger source signal and sends it to the trigger condition judgment module. Then, the trigger condition judgment module makes a trigger judgment according to the user-set trigger condition, outputs a trigger signal at the output end of the trigger signal corresponding to the user-set trigger condition, and finally, the trigger pulse multiplexer selects the output end of the trigger signal corresponding to the user-set trigger condition of the trigger condition judgment module to obtain the trigger signal Trig1;

[0028] In the trigger control module, it receives the acquisition start enable signal sent from the host computer and the register values related to trigger control. According to the trigger signal Trig1 generated by the trigger source module, it generates the read / write enable for controlling the orderly storage of the main FIFO, namely the FIFO control enable, so as to achieve the correct read / write control of the main FIFO to store the parallel sampling data, that is, to capture the waveform of interest to the user, and effectively "coarsely" locate the trigger point within one FPGA clock cycle, namely N sampling points.

[0029] (3) The trigger module performs "fine" trigger point search.

[0030] After the end of a single acquisition and storage process, the data stored in the main FIFO is read out. The parallel sampling data is converted from parallel to serial, and at this time, there is only one sampling point's data in a single FPGA clock cycle. At this time, the digital trigger module also performs trigger comparison and judgment on the data before it enters the slave FIFO.

[0031] The slave trigger module includes a trigger comparison module, a trigger source module, and a trigger control module. The trigger comparison module compares the serial sampling data with the comparison level set by the user and outputs a comparison signal to the trigger source module. The trigger source module makes a trigger judgment on the comparison signal according to the trigger condition set by the user and outputs the trigger signal Trig2 according to the selection. Then, according to the trigger signal Trig2, the read / write enable for controlling the orderly storage of the slave FIFO, namely the FIFO control enable, is generated in the trigger control module, so as to achieve the correct read / write control of the slave FIFO to store the serial sampling data, that is, to capture the waveform of interest to the user, and improve the trigger accuracy to 1 sampling point.

[0032] (4) Stable waveform display

[0033] The serial sampling data stored in the slave FIFO is read and transmitted to the three-dimensional mapping module for waveform mapping. The waveform data obtained after waveform mapping is transmitted to the host computer for stable waveform display.

[0034] The invention object of the present invention is realized as follows:

[0035] The method for implementing arbitrary wave triggering in an oscilloscope analyzer according to the present invention adopts master-slave digital triggering based on "coarse" and "fine" two-stage triggering using the logic resources in the FPGA. The master trigger "coarsely" locates the trigger point within one FPGA clock cycle, and the slave trigger "finely" locates the trigger point to improve the trigger accuracy to 1 sampling point. Among them, hysteresis comparison technology and carry look-ahead algorithm are introduced in the "coarse" trigger to implement digital trigger judgment for parallel trigger data, thereby solving the problem of low trigger accuracy. At the same time, the present invention designs an arbitrary wave triggering function using the arbitrary waveform generator module integrated in the oscilloscope analyzer. Based on the master-slave digital trigger system, an arbitrary waveform generator with external trigger function is realized, which has the advantages of simple structure, small signal quantization error, fast trigger speed, and high trigger accuracy compared with traditional external triggers. In addition, the implementation of this function also solves the problem that traditional devices with arbitrary wave functions cannot simultaneously use the arbitrary waveform generator as a source to output to other devices under test and their own devices can achieve external trigger functions without relying on external sources. Description of the Drawings

[0036] Figure 1 is the trigger principle block diagram of a traditional oscilloscope analyzer with arbitrary wave function;

[0037] Figure 2 is the trigger principle block diagram of a specific embodiment of an oscilloscope analyzer with arbitrary wave function constructed according to the present invention;

[0038] Figure 3 is the flowchart of a specific embodiment of the method for implementing arbitrary wave triggering in the oscilloscope analyzer according to the present invention;

[0039] Figure 4 is Figure 2 the principle block diagram of the master trigger module and the slave trigger module shown;

[0040] Figure 5 is the schematic diagram of the implementation principle of the hysteresis comparison technology in the present invention;

[0041] Figure 6 is Figure 4 the principle block diagram of the specific implementation of the comparison result generation circuit in;

[0042] Figure 7 is the flowchart of a specific embodiment of arbitrary wave triggering. Detailed Embodiment

[0043] The following describes the specific embodiments of the present invention with reference to the drawings, so that those skilled in the art can better understand the present invention. It should be particularly noted that in the following description, when the detailed description of known functions and designs may dilute the main content of the present invention, these descriptions will be omitted here.

[0044] In this embodiment, as Figure 2 shown, the present invention designs a master-slave digital trigger with "coarse and fine" two-stage triggering to improve the trigger precision of the system, avoid the systematic errors introduced in the traditional trigger scheme due to comparator jitter and the different data paths of the trigger signal and ADC sampling data, solve the limitation of the internal clock frequency of the FPGA on the trigger precision, strengthen the independent working ability of the acquisition module, and make the system efficient. At the same time, based on the master-slave digital trigger system, an arbitrary waveform trigger scheme is designed, and the external trigger function is realized through the arbitrary waveform generator integrated in the device, reducing the data transmission path, reducing the data transmission error, and improving the trigger precision. In addition, it solves the problem that the traditional device with arbitrary waveform function cannot simultaneously use the arbitrary waveform generator as a source to output to other devices and its own device can realize the external trigger function without relying on an external source.

[0045] To achieve the object of the present invention, as Figure 2 shown, the specific implementation of the present invention includes three parts:

[0046] 1. A high-performance oscilloscope analyzer is designed with a signal conditioning channel, ADC, DAC, FPGA, USB, and PC as the core components of the system

[0047] The signal conditioning channel performs processing such as gain control and offset adjustment on the input analog signal, making the analog signal approach the ADC input range to the greatest extent, thereby improving the quantization precision and reducing the quantization error; the high-performance ADC converts the analog signal into a digital signal; the high-performance DAC converts the digital waveform data into an analog waveform data; the FPGA is responsible for receiving the high-speed data stream transmitted by the ADC and processing it, and at the same time inputting the digital waveform data to the DAC; the USB chip is the transmission bridge between the FPGA and the PC, and the PC is responsible for receiving the input digital signal and displaying it, and at the same time sending specific digital waveform data.

[0048] 2. Based on the digital trigger mode and featuring hysteresis comparison technology and carry look-ahead algorithm, a master-slave digital trigger system based on "coarse and fine" two-stage triggering is designed.

[0049] First, our analog signal is adjusted to an appropriate range for ADC acquisition through an analog channel. The high-performance ADC converts the analog signal into a digital signal. Then, the FPGA receives the quantization data obtained from the ADC sampling through a data receiving module. After the acquisition data is decelerated, it becomes multi-channel parallel sampling data and is respectively transmitted to a trigger coupling module and a decimation module. After the coupling method is set by the user on the host computer, our multi-channel sampling data is transmitted to the main trigger module. In the main trigger module, hysteresis comparison technology is introduced to improve our trigger accuracy, and a carry look-ahead algorithm is introduced to improve our operation speed. During the main trigger process, the trigger comparison module sequentially compares the multi-channel parallel quantization data obtained from the ADC sampling with the comparison level set by the user to obtain a comparison signal, and transmits the comparison signal to the trigger source module. The comparison signal enters the trigger source module, and respective trigger signals are generated through trigger condition judgment modules of different trigger types. Finally, the trigger source module determines the finally selected output corresponding trigger signal Trig1 according to the trigger type set by the user, and transmits the trigger signal Trig1 to the trigger control module. The trigger control module mainly realizes functions such as trigger mode selection, pre-trigger, trigger delay, and rearm. This module needs to receive the acquisition start enable signal sent from the host computer and some register values related to trigger control, and then generates the read / write enable for controlling the orderly storage of the main FIFO according to the trigger signal Trig1 generated by the trigger source module, so as to realize the correct read / write control of the main FIFO to capture the waveform of interest to the user. Through the design of the main digital trigger module, the trigger point is "coarsely" located within one clock cycle. After one acquisition and storage process ends, the data stored in the main FIFO is read out. After the parallel sampling data undergoes serial-to-parallel conversion, it is converted into serial data. At this time, there is only one sampling point data in a single clock working cycle. At this time, the slave digital trigger module also performs trigger comparison and judgment on the data before entering the slave FIFO. Similar to the main digital trigger, it also generates the correct read / write control enable for the slave FIFO, and performs another precise digital trigger on the serial quantization sampling data. After a process of "coarse" trigger point finding and a process of "fine" trigger point finding, the system trigger accuracy is finally improved to one sampling point. Finally, the waveform data is transmitted to the host computer for display through the data transmission module.

[0050] 3. Based on an arbitrary waveform generator and a master-slave digital trigger system, an arbitrary wave trigger function with an external trigger function is designed.

[0051] In this solution, the host computer sends digital waveform source data with specific amplitude and frequency according to the set parameters. These data are stored in the internal RAM of the FPGA, and then specific data are parsed according to the set frequency using the DDFS principle to obtain digital waveform data with amplitude and frequency information. One path of arbitrary waveform data is transmitted to the data sending module, and then transmitted to the DAC through the data sending module to complete the generation of the arbitrary waveform, and then output to the device under test for use; the other path of arbitrary waveform data is transmitted to the digital trigger module, and the arbitrary waveform trigger function is realized through the master-slave digital trigger module, and a trigger signal is generated to achieve the external trigger function. The host computer sends waveform and address data of P points (P is the depth of the arbitrary wave), and these data are stored in the waveform lookup table according to the address. The FPGA reads the address according to the set frequency to obtain digital waveform data with amplitude and frequency information. In the arbitrary waveform generator path, these data are transmitted to the DAC for digital-to-analog conversion and converted into analog data for waveform output. At the same time, in the arbitrary wave trigger path, the waveform data transmitted to the DAC are transmitted to the master-slave digital trigger system, and the arbitrary wave trigger function is finally realized by comparing the digital waveform level value with the high and low threshold levels set in the master-slave digital trigger system. Such an arbitrary wave trigger path will reduce the arbitrary wave signal transmission path, eliminate the problem of data transmission error, and improve the external trigger accuracy of the system; in addition, it solves the problem that traditional devices with arbitrary wave functions cannot simultaneously use the arbitrary waveform generator as a source to output to other devices and the problem that their own devices can achieve the external trigger function without relying on an external source.

[0052] Figure 3 It is a flowchart of a specific implementation manner of the method for realizing arbitrary wave trigger in the oscilloscope analyzer of the present invention.

[0053] In this embodiment, as Figure 3 shown, the method for realizing arbitrary wave trigger in the oscilloscope analyzer of the present invention includes the following steps:

[0054] Step S1: The FPGA receives the ADC sampling quantization data and performs serial-to-parallel conversion

[0055] In this embodiment, as Figure 2 shown, the data receiving module of the FPGA receives the M GSPS sampling data of ADC sampling quantization from one channel. The working frequency of the FPGA is F MHz. The M GSPS sampling data is decelerated to N-channel parallel sampling data through the data receiving module, and N = M * 1000 / F.

[0056] The N-channel parallel sampling data is divided into two paths for data transmission. In one path, the parallel sampling data enters the decimation module according to the time base gear requirement, undergoes decimation processing, and stores the processed parallel sampling data into the main FIFO. In the other path, the parallel sampling data is transmitted to the trigger coupling module. The trigger coupling module selects, according to the instruction issued by the host computer, whether the parallel sampling data from this channel or the N-channel parallel waveform data from any waveform data processing module is used as the N-channel trigger parallel data. At the same time, the coupling method is selected, and finally the coupled N-channel trigger parallel data is transmitted to the main trigger module for trigger "coarse" point finding.

[0057] Among them, the oscilloscope analyzer integrates an arbitrary waveform generator module. The arbitrary waveform data generated by it is sent to the DAC to be converted into an arbitrary waveform, and after being conditioned by the signal conditioning module, it is output to the device under test for use. Another path transmits the arbitrary waveform data to the arbitrary waveform data processing module for processing to obtain N-channel parallel waveform data and transmits it to the trigger coupling module. Since this arbitrary wave trigger function is completed inside the FPGA, it can reduce the transmission error and quantization error of external connection lines and data, and improve the trigger accuracy.

[0058] In this embodiment, taking the working frequency of the FPGA as 250 MHz and taking the example that the ADC sampled and quantized 1 GSPS sampling data is decelerated and received into 4-channel parallel sampling data by the data receiving module for illustration. Among them, the coupling methods are divided into: AC coupling, DC coupling, high-frequency suppression, and low-frequency suppression. The design of the trigger coupling function can eliminate the noise in the signal and avoid incorrect triggering of the subsequent trigger circuit. The coupling method belongs to the prior art and will not be elaborated here.

[0059] Step S2: The main trigger module performs trigger "coarse" point finding

[0060] As Figure 4 shown, the coupled N-channel parallel trigger data of one channel is sent into a trigger comparison module in the main trigger module. The trigger comparison module sequentially compares the N-channel parallel trigger data with the high and low threshold comparison levels set by the user to determine in which FPGA clock cycle the N-channel parallel trigger data meets the trigger condition, that is, the FPGA clock cycle where the trigger point is located.

[0061] First, the nth trigger data of the N-channel parallel trigger data enters the comparison circuit. When comparing with the high threshold comparison level, when it is greater than the high threshold comparison level, the comparison circuit outputs a high comparison signal TH n is high. When it is less than or equal to the low threshold comparison level, the comparison circuit outputs a high comparison signal TH n is low. Similarly, when comparing with the low threshold comparison level, when it is greater than the low threshold comparison level, the comparison circuit outputs a low comparison signal TL nis high, and when it is less than or equal to the low threshold comparison level, the comparison circuit outputs a low comparison signal TL n is low.

[0062] In the design of the trigger result comparison circuit of the present invention, a dual trigger level comparison method is introduced to implement the trigger hysteresis function, that is, a high threshold comparison level VH and a low threshold comparison level VL. The difference between the two comparison levels VH and VL is the hysteresis range, and the size of the hysteresis range can be adjusted according to user needs. By using the dual trigger level comparison method to suppress noise and avoid false triggering caused by a single trigger level. The implementation principle of the hysteresis comparison technology is as Figure 5 shown. Figure 5 In the figure, the LS signal represents the final comparison result of the logical state of the single-channel sampled data. When the value of the sampled data is greater than the high threshold comparison level VH, the comparison result LS is set high; when the value of the sampled data is less than the low threshold comparison level VL, the comparison result LS is set low; when the value of the sampled data is between the low threshold comparison level VL and the high threshold comparison level VH, the comparison result LS remains unchanged from the previous clock cycle.

[0063] To implement the trigger hysteresis function, when making a trigger judgment on the parallel trigger data, since the input multi-channel comparison signals are input in one trigger clock, it is impossible to detect the occurrence of a trigger event only based on the input results of two adjacent comparators. It is necessary to use the state of the previous parallel trigger data to judge the generation of the trigger signal. Taking the rising edge trigger as an example, if the signal rises from below the low threshold comparison level and crosses the high threshold comparison level, it is judged as a rising edge trigger. If the signal drops from the high threshold comparison level and crosses the high threshold comparison level again, no rising edge trigger signal is generated. Therefore, when making a trigger judgment on the parallel trigger data, the comparison result LS n is introduced to represent the state of the nth parallel trigger data bit. When the nth parallel trigger data enters the digital comparison circuit and is judged to be greater than the high threshold comparison level, the comparison result LS n is high level. When the digital signal is less than the low threshold comparison level, the comparison result is low level. When the trigger signal is between the trigger thresholds, the comparison result, that is, the trigger logic state, remains unchanged. LS N represents the comparison result of the last channel, that is, the Nth parallel trigger data in the previous beat. The logical state of the trigger comparison, that is, the comparison result of the first channel, can be expressed by the formula:

[0064] LS1 = TH1 | (TL1 & LS N ) (1)

[0065] For the parallel trigger data, the comparison result LS of each digital signal nAll are related to the logical states of digital signals at previous moments. There is a feedback mechanism among the logical states of the parallel trigger signals. The comparison result LS2 of the second path is jointly determined by the comparison result LS1 of the first path, the high comparison signal TH2 and the low comparison signal TL2 of the second path. The comparison result LS n of the nth path is determined by the comparison result LS n-1 of the (n - 1)th path, as well as the high comparison signal TH n and the low comparison signal TL n of the nth path jointly. In the design, to reduce the time consumed by carry transmission, a look-ahead carry algorithm is introduced in the comparison module. The design idea of this algorithm is based on the design idea of a look-ahead carry adder, which generates carry logic ahead of the input data to shorten the calculation time. This logical iterative algorithm can quickly calculate the logical state value and improve the operation speed by generating carry signals in advance. If the look-ahead carry is not used, the comparison signal of the nth path LS n needs to generate a carry by adding up from the comparison result LS1 signal of the first path, which will lead to too long combinational logic delay. In this implementation case, we use 4-way parallel input data for design explanation (in actual application, the number of parallel input data paths and the number of trigger comparators can be designed according to requirements, with strong scalability and practicability). The implementation principle of the digital trigger comparison module is as shown in Figure 4 .

[0066] Figure 4 The specific implementation of the comparison result generation circuit in Figure 6 is as shown. In this implementation case, 4-way parallel input data is used to explain the implementation of the comparison result generation circuit. The look-ahead carry algorithm is used in the comparison result generation circuit to improve the operation rate. By the look-ahead carry algorithm, carry logic is generated in advance, greatly reducing the calculation time. When calculating the logical state value, the trigger state of the previous digital signal and the input signal value can be used to represent the current trigger state. From Equation (1), the state expression of the comparison result LS2 of the second path is:

[0067] LS2 = TH2 | (TL2 & LS1) (2)

[0068] Substitute Equation (1) into Equation (2) and simplify it to Equation (3):

[0069] LS2 = TH2 | (TL2 & TH1) | (TL2 & TL1 & LS N ) (3)

[0070] Iterate like this all the time. The high comparison signal TH n , the low comparison signal TL n are sent into the trigger result comparison circuit, and the output comparison result signal LS n is:

[0071] LS1 = TH1 | (TL1 & LS N )

[0072] LS2 = TH2 | (TL2 & TH1) | (TL2 & TL1 & LS N )

[0073] LS3 = TH3 | (TL3 & TH2) | (TL3 & TL2 & TH1) | (TL3 & TL2 & TL1 & LS N )

[0074] LS4 = TH4 | (TL4 & TH3) | (TL4 & TL3 & TH2) | (TL4 & TL3 & TL2 & TH1) | (TL4 & TL3 & TL2 & TL1 & LS N )

[0075] ……

[0076] LS N = TH N | (TL N & TH N-1 ) | (TL N & TL N-1 & TH N-2 ) | (TL N & TL N-1 & TL N-2 & TH N-3 )… | (TL N & TL N-1 & TL N-2 … & TL2 & TH1) | (TL N & TL N-1 & TL N-2 … & TL1 & LS N )

[0077] Among them, the comparison result signal LS on the right side of the equation N is the comparison result of the Nth trigger data in the previous FPGA clock cycle.

[0078] Then, the trigger result comparison circuit outputs the comparison result signal LS n , n = 1, 2, …, N to the trigger source module;

[0079] In the trigger source module, the comparison result signals output by the trigger source modules from multiple channels are received, and a comparison result signal LS of one channel is selected according to the instruction issued by the host computer n , n = 1, 2, …, N or an external trigger comparison signal is selected to generate a trigger signal Trig1 and transmitted to the trigger control module.

[0080] In the trigger source module, first, the comparison signal source is determined according to the issued channel selection signal. In Figure 4 , the comparison signals of channel 1, channel 2, and external trigger comparison signal are used for explanation. Since our device has functions such as dual-channel signal acquisition, arbitrary wave trigger, and external trigger, multiple trigger comparison modules are designed in the actual design to meet the requirements of multi-channel signal acquisition. Therefore, we need to select the required trigger comparison signal source in the trigger source selection module according to the trigger channel information set by the user.

[0081] In the trigger source module, first, the trigger source selection module selects the comparison result signal LS of one channel according to the instruction issued by the host computer n , n = 1, 2, …, N or selects the external trigger comparison signal as the trigger source signal and sends it to the trigger condition judgment module. Then, the trigger condition judgment module makes a trigger judgment according to the trigger condition set by the user, and outputs a trigger signal at the trigger signal output end set by the corresponding user-defined trigger condition. Finally, the trigger pulse multiplexer selects the trigger signal output end set by the user-defined trigger condition of the trigger condition judgment module to obtain the trigger signal Trig1.

[0082] Common trigger conditions in the trigger condition judgment module include edge trigger, pulse width trigger, slope trigger, under-amplitude trigger, etc. For example, when the trigger type is selected as edge trigger and the trigger polarity is selected as negative polarity, the edge trigger judgment module in the trigger source module needs to invert the comparison signal to obtain the correct trigger signal, and finally select the trigger signal Trig1 generated by the edge trigger in the trigger pulse multiplexer. When the trigger type is selected as pulse width trigger and the trigger polarity is selected as positive polarity, the pulse width module of the trigger condition judgment module needs to count the number of consecutive 1s in the comparison signal, that is, the positive pulse width of the comparison signal, and compare the pulse width with the user-defined value to obtain the trigger signal. Similarly, select the trigger pulse generated by the pulse width trigger in the trigger pulse multiplexer as the final trigger signal Trig1.

[0083] In the trigger control module, the trigger control module mainly realizes functions such as trigger mode selection, pre-trigger, trigger delay, and suppression. It receives the acquisition start enable signal issued by the host computer and the register values related to trigger control, and generates the read / write enable for controlling the orderly storage of the main FIFO, that is, the FIFO control enable, according to the trigger signal Trig1 generated by the trigger source module, so as to realize the correct read / write control of the main FIFO to store parallel sampling data, that is, capture the waveform of interest to the user, and effectively "coarsely" locate the trigger point within one FPGA clock cycle, that is, within N sampling points (within 4 sampling points in this embodiment).

[0084] Step S3: Perform "fine" trigger point finding in the trigger module

[0085] The main digital trigger module will locate the trigger point within one clock cycle (i.e., within 4 sampling points). After one acquisition and storage process ends, the data stored in the main FIFO will be read out. The parallel sampling data is converted from parallel to serial sampling data through a parallel-to-serial converter. At this time, there is only the data of one sampling point in a single FPGA clock cycle. At this time, the slave digital trigger module also makes a trigger comparison and judgment on the data before entering the slave FIFO.

[0086] The slave trigger module includes a trigger comparison module, a trigger source module, and a trigger control module. The trigger comparison module compares the serial sampling data with the comparison level set by the user and outputs a comparison signal to the trigger source module. The trigger source module makes a trigger judgment on the comparison signal according to the trigger condition set by the user and outputs the trigger signal Trig2 according to the selection. Then, according to the trigger signal Trig2, a read-write enable for controlling the orderly storage of the slave FIFO, that is, the FIFO control enable, is generated in the trigger control module, so as to realize the correct read-write control of the slave FIFO to store the serial sampling data, that is, to capture the waveform of interest to the user, and improve the trigger accuracy to 1 sampling point.

[0087] The slave trigger is the same as the current trigger and is an existing technology, so it will not be elaborated here.

[0088] Step S4: Stable waveform display

[0089] Read the stored serial sampling data from the slave FIFO and transmit it to the three-dimensional mapping module for waveform mapping. The waveform data obtained after waveform mapping is transmitted to the host computer for stable display of the waveform.

[0090] In this embodiment, while realizing the external trigger function by using the arbitrary wave trigger function, the arbitrary waveform generator is used as a source and output to other devices under test for use.

[0091] In this embodiment, the process of realizing the arbitrary wave trigger function based on the master-slave digital trigger is as Figure 7 shown, including the following steps:

[0092] Step S21: The user sets waveform parameters through the host computer

[0093] First, open the arbitrary waveform generator setting interface on the host computer, set parameters such as the amplitude, frequency, bias, etc. of the required waveform, and then turn on the arbitrary wave output.

[0094] Step S22: The host computer transmits the waveform and address data to the FPGA through USB3.0 communication and stores them in the internal RAM of the FPGA

[0095] After the host computer turns on the arbitrary wave output, it transmits the waveform data set by the host computer through the USB3.0 communication module, and then stores it in the internal RAM of the FPGA.

[0096] Step S23: The FPGA addresses and reads data in the waveform lookup table according to requirements to obtain digital waveform data

[0097] Read data information from the RAM in the FPGA, and use the DDFS principle to parse specific data based on the set frequency for the data, obtaining digital waveform data with waveform information such as amplitude, frequency, and offset. The number of parallel paths of the waveform data output by waveform lookup can be designed according to the size of the RAM storing the arbitrary waveform data to output the number of paths of arbitrary waveform data. In this practical case, we design to output 4 paths of 16-bit wide parallel arbitrary waveform data from the waveform lookup table for explanation.

[0098] Step S24: Is the arbitrary wave trigger function enabled?

[0099] At this time, select whether to enable the arbitrary wave trigger function on the host computer. If it is necessary to start the arbitrary wave trigger function, just select the option to enable the arbitrary wave trigger and the master-slave data trigger option on the host computer, and then the host computer sends relevant instructions to the FPGA through the USB3.0 communication module. At this time, the waveform data obtained in step S23 will be transmitted to the arbitrary waveform generation path and the arbitrary wave trigger path respectively; if the arbitrary wave trigger function is not enabled, just do not enable the arbitrary wave trigger on the host computer, and then the host computer sends the relevant instructions to the FPGA through the USB3.0 communication module. At this time, the waveform data obtained in step S23 will be transmitted to the arbitrary waveform generation path.

[0100] Step S25: The waveform data is sent to the DAC through the FPGA data sending module

[0101] In the arbitrary waveform generation path, the digital waveform data is sent to the DAC through the data sending module in the FPGA, converting the digital waveform data into an analog waveform signal, and then outputting the analog waveform data to the analog channel for signal conditioning.

[0102] Step S26: Output the set arbitrary waveform through the analog channel

[0103] The waveform data output by the DAC is adjusted by the arbitrary wave analog channel and finally outputs an analog waveform signal with the waveform parameters set on the host computer.

[0104] Step S27: The host computer sets the arbitrary wave trigger level

[0105] This step is implemented when starting the arbitrary wave trigger function. At this time, we enable the arbitrary wave trigger function on the host computer. In the arbitrary wave trigger path, the arbitrary wave waveform data first passes through the arbitrary waveform data processing module for data processing, and then is transmitted to the master-slave digital trigger system to complete our arbitrary wave trigger function. At the same time, the corresponding trigger level parameters are set on the host computer. The specific arbitrary waveform data processing module and trigger level parameter setting conversion are shown in the following specific derivation. In this step, the DAC resolution is selected as 16 bits, and the trigger level is 12 bits.

[0106] In this design, the digital waveform level value is calculated from the arbitrary wave output amplitude value for participating in the trigger comparison design. The arbitrary wave output amplitude value V OUT is related to the signal conditioning channel and DAC settings, and can be specifically expressed by the following formula:

[0107]

[0108] where K AWG is the gain multiple of the signal conditioning channel, V AWG_ref represents the DAC reference voltage, b is the DAC output resolution, N AWG is the waveform level value represented by the arbitrary waveform data, and V AWG_offset is the offset voltage of the signal conditioning channel.

[0109] The gain multiple of the signal conditioning channel of the present invention consists of three parts: a fixed gain amplifier, a variable gain amplifier, and a digitally controlled attenuator. The gain multiple of the fixed gain amplifier is the product of all amplifier multiples. The gain multiple of the variable gain amplifier is controlled by the input voltage value V GAIN of the GAIN pin, and can be specifically expressed by the formula:

[0110]

[0111] where M is the gain coefficient of the variable gain amplifier, and ICPT is the compensation decibel number. The input of the GAIN pin comes from the DAC chip on the conditioning channel. By configuring different input values for the DAC chip, the input voltage value of this pin is changed, and then the gain multiple of the variable gain amplifier is changed, so as to realize the control and adjustment of the gain multiple by the host computer.

[0112] The digitally controlled attenuator selects attenuation through a relay. The host computer sets the corresponding parameter configuration of the relay switch according to the amplitude size to select whether the signal path is an attenuation path. In this case, we select the DAC resolution as 16 bits, so the waveform data level value N AWG is obtained from formula (4):

[0113]

[0114] In the design, the trigger level is 12 bits. Therefore, when calculating the 12-bit trigger level value N TRIG when, from V OUT = V trig we have:

[0115]

[0116] However, since the waveform data sent to the DAC is 16 bits and our trigger level is 12 bits, the waveform data needs to be converted to 12-bit waveform data according to formula (11) before digital comparison:

[0117]

[0118] In actual operation, the waveform data level value needs to be converted to 12 bits. The method of operation in the FPGA is to shift N AWG right by 4 bits or directly intercept its high 12 bits.

[0119] Step S28: The master-slave digital trigger system realizes the arbitrary wave trigger function

[0120] Set our arbitrary wave trigger level parameters in the manner of step S27. At this time, after starting the arbitrary wave trigger function, our 4-channel 16-bit arbitrary wave waveform data is output from the waveform lookup table (the number of waveform data channels output from the waveform lookup table can be designed according to the size of the RAM storing the arbitrary waveform data. In this practical case, we design to output 4-channel 16-bit wide parallel arbitrary waveform data from the waveform lookup table for explanation), and then the arbitrary wave waveform data is processed by the arbitrary wave data processing module and then transmitted to the trigger coupling module for the selection of the coupling method (in the arbitrary wave data processing module, the arbitrary wave waveform data N AWG of each channel is shifted right by 4 bits or directly intercepts its high 12-bit level value to convert the 16-bit wide waveform data to 12-bit wide arbitrary waveform data). The waveform data after trigger coupling is transmitted to the master-slave digital trigger system to complete the arbitrary wave trigger function. In the arbitrary wave trigger path, the arbitrary wave waveform data is transmitted to the aforementioned "coarse and fine" two-stage digital trigger module to realize our arbitrary wave trigger function, and the trigger accuracy is improved to one sampling point to realize the external trigger function.

[0121] According to the above formula calculation, this design realizes the arbitrary wave trigger function based on the master-slave digital trigger system. In specific use, as long as the high and low threshold voltages are set, the high and low threshold level values can be calculated through the formula. Whether using the sequential comparison method or the threshold comparison method, only need to set the trigger level value N TRIG , and then the waveform data N AWGConverted to N according to formula (11) trig After that, the arbitrary wave trigger function can be realized, so as to realize the external trigger function, thereby solving the problem that the traditional digital storage oscilloscope with arbitrary wave function cannot simultaneously output the arbitrary wave as a source for other devices under test and realize the external trigger function of its own device without relying on an external source, making the device more efficient, providing a more convenient test environment for users, and improving the accuracy of our external trigger.

[0122] Although the above description of the illustrative specific embodiments of the present invention is provided for the convenience of those skilled in the art to understand the present invention, it should be clear that the present invention is not limited to the scope of the specific embodiments. For those of ordinary skill in the art in this technical field, as long as various changes are within the spirit and scope of the present invention defined and determined by the appended claims, these changes are obvious, and all inventions and creations using the concept of the present invention are within the scope of protection.

Claims

1. A method for implementing arbitrary wave triggering in an oscilloscope analyzer, characterized in that, Including: (1) The FPGA receives the ADC sampled and quantized data and performs serial-to-parallel conversion The data receiving module of the FPGA receives the M GSPS sampled data sampled and quantized by the ADC from one channel. The working frequency of the FPGA is F MHz. The M GSPS sampled data is decelerated into N-channel parallel sampled data by the data receiving module, where N = M * 1000 / F; The N-channel parallel sampled data is divided into two paths for data transmission. In one path, the parallel sampled data enters the decimation module for decimation processing according to the time base gear requirement, and the processed parallel sampled data is stored in the main FIFO. In the other path, the parallel sampled data is transmitted to the trigger coupling module. The trigger coupling module selects whether to use the parallel sampled data from this channel or the N-channel parallel waveform data from the arbitrary waveform data processing module as the N-channel trigger parallel data according to the instruction issued by the host computer. At the same time, the coupling method is selected, and finally the coupled N-channel trigger parallel data is transmitted to the main trigger module for trigger "coarse" point finding; Among them, the oscilloscope analyzer integrates an arbitrary waveform generator module. The arbitrary waveform data generated by it is sent to the DAC to be converted into an arbitrary waveform, and after being conditioned by the signal conditioning module, it is output to the device under test for use. Another path transmits the arbitrary waveform data to the arbitrary waveform data processing module for processing to obtain N-channel parallel waveform data and transmits it to the trigger coupling module; (2) The main trigger module performs trigger "coarse" point finding The coupled N-channel parallel trigger data of one channel is sent into a trigger comparison module in the main trigger module. The trigger comparison module sequentially compares the N-channel parallel trigger data with the high and low threshold comparison levels set by the user to determine in which FPGA clock cycle the N-channel parallel trigger data satisfies the trigger condition, that is, the FPGA clock cycle where the trigger point is located: First, the nth trigger data of the N-channel parallel trigger data enters the comparison circuit. When comparing with the high threshold comparison level, if it is greater than the high threshold comparison level, the comparison circuit outputs a high comparison signal TH n is high. If it is less than or equal to the low threshold comparison level, the comparison circuit outputs a high comparison signal TH n is low. Similarly, when comparing with the low threshold comparison level, if it is greater than the low threshold comparison level, the comparison circuit outputs a low comparison signal TL n is high. If it is less than or equal to the low threshold comparison level, the comparison circuit outputs a low comparison signal TL n is low; Then, the high comparison signal TH n , the low comparison signal TL n are fed into the trigger result comparison circuit, and the comparison result signal LS n is output: LS1 = TH1 | (TL1 & LS N ) LS2 = TH2 | (TL2 & TH1) | (TL2 & TL1 & LS N ) LS3 = TH3 | (TL3 & TH2) | (TL3 & TL2 & TH1) | (TL3 & TL2 & TL1 & LS N ) LS4 = TH4 | (TL4 & TH3) | (TL4 & TL3 & TH2) | (TL4 & TL3 & TL2 & TH1) | (TL4 & TL3 & TL2 & TL1 & LS N ) …… LS N = TH N |(TL N & TH N-1 )|(TL N & TL N-1 & TH N-2 )|(TL N & TL N-1 & TL N-2 & TH N-3 )…|(TL N & TL N-1 & TL N-2 …& TL2& TH1)|(TL N & TL N-1 & TL N-2 …& TL1& LS N ) Among them, the comparison result signal LS on the right side of the equation N is the comparison result of the Nth trigger data in the previous FPGA clock cycle; Then, trigger the result comparison circuit to output a comparison result signal LS n , n = 1, 2, …, N to the trigger source module; In the trigger source module, the comparison result signals output by the trigger source module from multiple channels are received, and the comparison result signal LS of one channel is selected according to the instruction issued by the host computer n , n = 1, 2, …, N, or an external trigger comparison signal is selected to generate a trigger signal Trig1 and transmitted to the trigger control module: In the trigger source module, first, the trigger source selection module selects the comparison result signal LS of one channel according to the instruction issued by the host computer n , n = 1, 2, …, N or selects the external trigger comparison signal as the trigger source signal and sends it to the trigger condition judgment module. Then, the trigger condition judgment module makes a trigger judgment according to the trigger conditions set by the user, and outputs a trigger signal at the trigger signal output end corresponding to the trigger conditions set by the user. Finally, the trigger pulse multiplexer selects the trigger signal output end of the trigger conditions set by the user of the trigger condition judgment module to obtain the trigger signal Trig1; In the trigger control module, it receives the acquisition start enable signal and the register values related to trigger control issued by the host computer, and generates the read / write enable for controlling the orderly storage of the main FIFO, that is, the FIFO control enable, according to the trigger signal Trig1 generated by the trigger source module, so as to realize the correct read / write control of the main FIFO to store the parallel sampled data, that is, to capture the waveform of interest to the user, and effectively "coarsely" locate the trigger point within one FPGA clock cycle, that is, within N sampling points; (3) The slave trigger module performs trigger "fine" point finding After one acquisition and storage process ends, the data stored in the main FIFO will be read out. The parallel sampled data is converted from parallel to serial into serial sampled data. At this time, there is only one sampling point's data in a single FPGA clock cycle. At this time, the digital trigger module also performs trigger comparison and judgment on the data before entering the slave FIFO; The trigger module includes a trigger comparison module, a trigger source module, and a trigger control module. The trigger comparison module compares the serial sampled data with the comparison level set by the user and outputs a comparison signal to the trigger source module. The trigger source module makes a trigger judgment on the comparison signal according to the trigger condition set by the user and outputs a trigger signal Trig2 according to the selection. Then, according to the trigger signal Trig2, read and write enables for orderly storage in the slave FIFO, namely FIFO control enables, are generated in the trigger control module, so as to realize the correct read and write control of the slave FIFO to store the serial sampled data, that is, to capture the waveform of interest to the user, and improve the trigger accuracy to 1 sampling point; (4), Stable waveform display The stored serial sampled data is read from the slave FIFO and transmitted to the three-dimensional mapping module for waveform mapping. The waveform data obtained after waveform mapping is transmitted to the host computer for stable display of the waveform.

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