Array substrate and display device

Abstract

The present application provides an array substrate and a display device, the array substrate comprising a plurality of gate line groups, a plurality of common lines and a plurality of data lines; wherein the common lines and the data lines are alternately arranged, the gate line groups are insulated and overlapped with the common lines and the data lines to define a plurality of pixel regions; a pixel electrode arranged on the substrate and located in the pixel region; an insulating layer covering the gate line groups, the common lines, the data lines and the pixel electrodes; a common electrode arranged above the insulating layer; the common electrode is connected to the common line through at least one contact hole penetrating the insulating layer. In the present application, the common electrode is connected to the common line through at least one contact hole penetrating the insulating layer, which greatly reduces the resistance load of the common line, improves the pixel charging rate, and improves the display effect of the display panel.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a display device. Background Art

[0002] The array substrate of the liquid crystal display device has a plurality of intersecting gate lines and data lines, and a plurality of pixel units arranged in a matrix are defined by the intersection of the gate lines and the data lines. In the display process of a frame of the picture, a driving signal of a certain frequency is used to scan the gate lines from top to bottom line by line, and the thin film transistors of the pixel units are controlled to turn on, so that the pixel units are turned on line by line. At the same time, the data lines charge the turned-on pixel units (the thin film transistors inside), thereby controlling the deflection of the liquid crystal molecules at different angles to realize the picture display. In the pixel design of the display panel, the main factors affecting its charging rate are: resistance and capacitance load (RC loading), storage capacitance (Cst), maximum liquid crystal capacitance (Clc_max), channel width-to-length ratio, etc. Among them, the resistance and capacitance load (RC loading) is the load on the gate line (Gate line) / data line (Data line).

[0003] The development trend of liquid crystal display devices is large size, high resolution, and high response speed. However, while pursuing large size, high resolution, and high response speed, the length of the gate line and the data line will also increase. The gate signal or the source signal will be attenuated due to the increase in line impedance when transmitted over long distances. For example, the larger the Gate line load, the longer it takes for the Gate voltage at the pixel position to rise to a high level (VGH), and the actual charging time of the pixel is reduced, which will affect the charging of the pixel; the larger the Data line load, the longer it takes for the Data voltage to rise to the operating voltage (Vop) of the liquid crystal layer, which will also affect the charging of the pixel. Ultimately, the signals received by the near-end pixel and the far-end pixel are inconsistent, and the far-end pixel is more likely to have insufficient charging time and charging voltage, resulting in poor display. Summary of the invention

[0004] In view of the above problems, the present application provides an array substrate and a display device, which solve the technical problem in the prior art that the resistance and capacitance load (RC loading) greatly affects the pixel charging rate.

[0005] In a first aspect, the present application provides an array substrate, comprising:

[0006] substrate substrate;

[0007] A plurality of gate line groups are arranged on the base substrate at intervals and extend along the row direction;

[0008] A plurality of common lines and a plurality of data lines are arranged on the base substrate at intervals and extend along the column direction; wherein the common lines and the data lines are arranged alternately, and the gate line group is insulated and overlapped with the common lines and the data lines to define a plurality of pixel areas;

[0009] A pixel electrode disposed on the base substrate and located in the pixel area;

[0010] an insulating layer covering the gate line group, the common line, the data line and the pixel electrode;

[0011] A common electrode is arranged above the insulating layer; wherein the orthographic projection of the common electrode on the base substrate at least covers a portion of the gate line group, a portion of the common line, a portion of the data line and a portion of the pixel electrode on the base substrate; the common electrode is connected to the common line via at least one contact hole penetrating the insulating layer.

[0012] In some embodiments, in the above array substrate, each of the gate line groups includes two gate lines arranged at intervals;

[0013] The two gate lines of each gate line group, the common line and the data line are arranged to form a plurality of gap areas.

[0014] In some embodiments, in the above array substrate, the orthographic projection of the contact hole on the base substrate falls between the orthographic projections of two gate lines of the gate line group on the base substrate.

[0015] In some embodiments, in the above array substrate, the distance between the orthographic projection of the contact hole on the base substrate and the orthographic projection of the gate lines on both sides thereof on the base substrate is the same.

[0016] In some embodiments, in the above array substrate, the common line is provided with a contact pad for connecting with the contact hole;

[0017] Wherein, the size of the contact pad is larger than the line width of the common line portion between two adjacent pixel regions.

[0018] In some embodiments, in the above array substrate, the contact pad is in a square or circular shape.

[0019] In some embodiments, in the above array substrate, the common electrode includes a plurality of first sub-electrodes that are spaced apart and extend along a row direction, and a plurality of second sub-electrodes connected between any two adjacent rows of the first sub-electrodes.

[0020] In some embodiments, in the above array substrate, the orthographic projection of the second sub-electrode on the base substrate at least covers the orthographic projection of the contact pad on the base substrate.

[0021] In some embodiments, in the above array substrate, the orthographic projection of the second sub-electrode on the base substrate coincides with the center of the orthographic projection of the contact pad on the base substrate.

[0022] In some embodiments, the array substrate further comprises: a thin film transistor disposed in the gap region, the thin film transistor comprising a source electrode, a drain electrode and a gate electrode;

[0023] The source of the thin film transistor is connected to the adjacent data line, the drain of the thin film transistor is connected to the corresponding pixel electrode, and the gate of the thin film transistor is connected to the corresponding gate line.

[0024] In some embodiments, in the above array substrate, the orthographic projection of the second sub-electrode on the base substrate does not cover the orthographic projection of the data line and the thin film transistor on the base substrate.

[0025] In some embodiments, in the above array substrate, a distance between an orthographic projection of the second sub-electrode on the base substrate and an orthographic projection of the gates of the thin film transistors on both sides thereof on the base substrate is greater than a first preset distance.

[0026] In some embodiments, in the above-mentioned array substrate, the orthographic projection of the first sub-electrode on the base substrate at least covers part of the orthographic projection of the pixel electrode on the base substrate, and the orthographic projection of the first sub-electrode on the base substrate does not cover the orthographic projection of the gate line group on the base substrate.

[0027] In some embodiments, in the above array substrate, a distance between an orthographic projection of the first sub-electrode on the base substrate and an orthographic projection of the gate line groups on both sides thereof on the base substrate is greater than a second preset distance.

[0028] In some embodiments, in the above array substrate, the overlapping portion of the orthographic projection of the first sub-electrode on the base substrate and the orthographic projection of the pixel electrode on the base substrate is in a stripe shape.

[0029] In some embodiments, in the above array substrate, the first sub-electrode further covers the common line portion and the data line portion between any two adjacent pixel regions in the same row.

[0030] In some embodiments, in the above array substrate, the orthographic projection of the pixel electrode on the base substrate does not cover the orthographic projections of the gate line group, the common line and the data line on the base substrate.

[0031] In some embodiments, in the above array substrate, the data line and the common line include a first conductive layer and a second conductive layer sequentially stacked on the base substrate;

[0032] The orthographic projection of the first conductive layer on the base substrate covers a portion of the orthographic projection of the second conductive layer on the base substrate.

[0033] In some embodiments, in the above array substrate, the first conductive layer and the pixel electrode are located on the same layer, and the second conductive layer is a metal layer.

[0034] In a second aspect, the present application provides a display device, comprising an array substrate as described in any one of the first aspects.

[0035] By adopting the above technical solution, at least the following technical effects can be achieved:

[0036] The present application provides an array substrate and a display device, the array substrate comprising a plurality of gate line groups, a plurality of common lines and a plurality of data lines; wherein the common lines and the data lines are alternately arranged, the gate line groups are insulated and overlapped with the common lines and the data lines to define a plurality of pixel regions; a pixel electrode arranged on the base substrate and located in the pixel region; an insulating layer covering the gate line groups, the common lines, the data lines and the pixel electrodes; a common electrode arranged above the insulating layer; wherein the orthographic projection of the common electrode on the base substrate at least covers the orthographic projection of part of the gate line groups, part of the common lines, part of the data lines and part of the pixel electrodes on the base substrate; the common electrode is connected to the common line through at least one contact hole penetrating the insulating layer. In the present application, the common electrode is connected to the common line through at least one contact hole penetrating the insulating layer, which greatly reduces the resistance load of the common line, improves the pixel charging rate, and improves the display effect of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The accompanying drawings are used to provide a further understanding of the present application and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present application but do not constitute a limitation to the present application. In the accompanying drawings:

[0038] Figure 1 is a schematic diagram of a front top view of an array substrate;

[0039] Figure 2 yes Figure 1Schematic diagram of the cross-sectional structure along the tangent line A-A';

[0040] Figure 3 yes Figure 1 Schematic diagram of the cross-sectional structure along the tangent line B-B';

[0041] Figure 4 is a schematic diagram of a front plan view of an array substrate shown in an exemplary embodiment of the present application;

[0042] Figure 5 yes Figure 4 Schematic diagram of the cross-sectional structure along the tangent line C-C';

[0043] Figure 6 yes Figure 4 Schematic diagram of the cross-sectional structure along the tangent line D-D';

[0044] Figure 7 yes Figure 4 Schematic diagram of the cross-sectional structure along the tangent line E-E';

[0045] In the drawings, the same reference numerals are used for the same components, and the drawings are not drawn to scale;

[0046] The accompanying drawings are marked as follows:

[0047] 11-base substrate; 12-gate line group; 121 / 122-gate line; 13-data line; 14-common line; 15-pixel electrode; 16-common electrode; 17-thin film transistor; 171-gate; 172-active layer; 173-drain; 18-insulating layer; 19-protective layer; BM-black matrix layer; 30-opposite substrate;

[0048] 21-base substrate; 22-gate line group; 221 / 222-gate line; 23-data line; 231-first conductive layer; 232-second conductive layer; 24-common line; 241-contact pad; 242-contact hole; 25-pixel electrode; 26-common electrode; 261-first sub-electrode; 262-second sub-electrode; 27-thin film transistor; 271-gate; 272-active layer; 273-drain; 274-source; 28-insulating layer; 29-protective layer; BM-black matrix layer; 40-opposite substrate. DETAILED DESCRIPTION

[0049] The following will describe the implementation methods of the present application in detail in conjunction with the accompanying drawings and embodiments, so that the implementation process of how the present application applies technical means to solve technical problems and achieve corresponding technical effects can be fully understood and implemented accordingly. The embodiments of the present application and the various features in the embodiments can be combined with each other without conflict, and the technical solutions formed are all within the scope of protection of the present application. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. The same reference numerals throughout represent the same elements.

[0050] It should be understood that although the terms "first", "second", "third", etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer or part discussed below can be represented as a second element, component, region, layer or part.

[0051] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present application. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0052] In order to thoroughly understand the present application, detailed structures and steps will be presented in the following description to illustrate the technical solution proposed by the present application. The preferred embodiments of the present application are described in detail below, but in addition to these detailed descriptions, the present application may also have other implementation methods.

[0053] A schematic diagram of the structure of an array substrate, such as Figure 1 , Figure 2 and Figure 3 As shown, it includes a base substrate 11 , a plurality of gate line groups 12 , a plurality of data lines 13 , a plurality of common lines 14 , a pixel electrode 15 , an insulating layer 18 , a common electrode 16 and a thin film transistor 17 .

[0054] A plurality of gate line groups 12 are disposed on the base substrate 11 at intervals and extend along a row direction. Each gate line group 12 includes two gate lines 121 and 122 .

[0055] A plurality of common lines 14 are disposed on the base substrate 11 at intervals and extend along the column direction, and the plurality of common lines 14 are arranged along the row direction.

[0056] The data lines 13 are disposed on the base substrate 11 at intervals and extend along the column direction, and the data lines 13 are arranged along the row direction.

[0057] The common lines 14 and the data lines 13 are alternately arranged along the row direction, and the gate line group 12 is insulated and overlapped with the common lines 14 and the data lines 13 to define a plurality of pixel regions (not marked in the figure).

[0058] The pixel electrode 15 is disposed on the base substrate 11 and is located in the pixel region. The orthographic projection of the pixel electrode 15 on the base substrate 11 does not cover the orthographic projections of the gate line group 12 , the common line 14 and the data line 13 on the base substrate 11 .

[0059] The insulating layer 18 covers the gate line group 12 , the common line 14 , the data line 13 and the pixel electrode 15 . The insulating layer 18 is used to isolate the gate line group 12 , the common line 14 , the data line 13 and the pixel electrode 15 from other film layers thereon.

[0060] The common electrode 16 is disposed above the insulating layer 18 , and its orthographic projection on the base substrate 11 completely covers the orthographic projections of the gate line group 12 , the common line 14 and the data line 13 on the base substrate 11 , and covers part of the orthographic projection of the pixel electrode 15 on the base substrate 11 .

[0061] Among them, the overlapping part of the orthographic projection of the common electrode 16 on the base substrate 11 and the orthographic projection of the pixel electrode 15 on the base substrate 11 is in the shape of stripes, that is, the common electrode 16 is in the shape of stripes at the position of the pixel electrode 15 (a slit is formed between the two stripes), and different voltage differences are provided between the striped common electrode 16 and the pixel electrode 15 thereunder to form an electric field. There will be a strongest edge vertical electric field at the edge of the striped electrode, so the liquid crystal will tend to be arranged parallel to the vertical electric field here, thereby enhancing the penetration effect of light and improving the display effect of the liquid crystal layer.

[0062] The thin film transistor 17 includes a gate 171 , an active layer 172 , a source (not marked in the figure) and a drain 173 . The gate is connected to the corresponding gate line 121 or 122 , the source is connected to the adjacent data line 13 , and the drain 173 is connected to the corresponding pixel electrode 15 .

[0063] One pixel unit includes a pixel region and a gap region formed by two gate lines 121 and 122 in the gate line group 12 and the common line 14 and the data line 13. The length of the gate line 121 or 122 in one pixel unit is the gate line length between two adjacent data lines 13 and the common line 14. The thin film transistor 17 is located in the gap region.

[0064] A protection layer 19 is also disposed above the common electrode 16 .

[0065] In the liquid crystal display panel corresponding to the above array substrate, the data line 13 , the common line 14 and the gate line 121 or 122 are shielded by the black matrix layer BM disposed on the opposite substrate 30 .

[0066] In this array substrate, although the common electrode 16 and the common line 14 are connected to the same signal Vcom, the signals of the common electrode 16 and the common line 14 are obtained from an external driving unit, and there is no connection relationship between the common electrode 16 and the common line 14.

[0067] The calculation method of the resistance R of the common line 14 is: R=L÷W×Rs, where L is the length of the conductive film along the current direction, W is the width of the conductive cross-section, Rs is the square resistance of the metal, Rs=ρ / d, ρ is the film resistivity, d is the film thickness, so the resistance load of the common electrode 16 and the common line 14 is large.

[0068] In addition, the capacitance calculation formula is: C = (ε0·ε r ·S) / d, where ε0 is the dielectric constant of vacuum (8.85418*10 -12 F / m), ε r is the relative dielectric constant, S is the effective area of ​​the capacitor, and d is the thickness of the dielectric layer. Therefore, since the common electrode 16 covers all areas except the slit, the parasitic capacitance between the common electrode 16 and the data line 13, the gate 121 or 122, and the thin film transistor 17 is relatively large.

[0069] Therefore, the resistance and capacitance load (RC loading) of the array substrate will cause a large delay in signal transmission, which greatly affects the charging rate of the pixel (the thin film transistor 17 therein).

[0070] The present application embodiment provides an array substrate. Figure 4 , Figure 5 , Figure 6 and Figure 7 The array substrate includes a base substrate 21 , a plurality of gate line groups 22 , a plurality of data lines 23 , a plurality of common lines 24 , a pixel electrode 25 , an insulating layer 28 and a common electrode 26 .

[0071] A plurality of gate line groups 22 are disposed on the base substrate 21 at intervals and extend along the row direction.

[0072] A plurality of common lines 24 are disposed on the base substrate 21 at intervals and extend along the column direction, and the plurality of common lines 24 are arranged along the row direction.

[0073] The data lines 23 are disposed on the base substrate 21 at intervals and extend along the column direction, and the data lines 23 are arranged along the row direction.

[0074] The common lines 24 and the data lines 23 are alternately arranged along the row direction, and the gate line group 22 is insulated and overlapped with the common lines 24 and the data lines 23 to define a plurality of pixel regions (not marked in the figure).

[0075] The pixel electrode 25 is disposed on the base substrate 21 and is located in the pixel region. The orthographic projection of the pixel electrode 25 on the base substrate 21 does not cover the orthographic projections of the gate line group 22 , the common line 24 and the data line 23 on the base substrate 21 .

[0076] The insulating layer 28 covers the gate line group 22 , the common line 24 , the data line 23 and the pixel electrode 25 . The insulating layer 28 is used to isolate the gate line group 22 , the common line 24 , the data line 23 and the pixel electrode 25 from other film layers thereon.

[0077] The common electrode 26 is disposed above the insulating layer 28 , and its orthographic projection on the base substrate 21 at least covers a portion of the gate line group 22 , a portion of the common line 24 , a portion of the data line 23 , and a portion of the pixel electrode 25 on the base substrate 21 .

[0078] The common electrode 26 is connected to the common line 24 via at least one contact hole 242 penetrating the insulating layer 28 , and the two are connected in parallel, which greatly reduces the resistance load of the common line 24 , improves the pixel charging rate, and improves the display effect of the display panel.

[0079] In some embodiments, the orthographic projections of the contact holes 242 on the base substrate 21 are arranged in an array. The more contact holes 242 there are, the better the connection between the common electrode 26 and the common line 24 is. If a certain contact hole 242 is defective, the connection between the common electrode 26 and the common line 24 is not affected by the other contact holes 242.

[0080] In some embodiments, the material of the pixel electrode 25 includes indium tin oxide (ITO).

[0081] In some embodiments, each gate line group 22 includes two gate lines 221 and 222 that are spaced apart from each other; the two gate lines 221 and 222 of each gate line group 22 and the common line 24 and the data line 23 are arranged to form a plurality of gap regions.

[0082] In some embodiments, the material of the gate lines 221 and 222 includes molybdenum.

[0083] In some embodiments, Figure 4 and 6As shown, the orthographic projection of the contact hole 242 for connecting the common electrode 26 and the common line 24 on the base substrate 21 falls between the orthographic projections of the two gate lines 221 and 222 of the gate line group 22 on the base substrate 21 .

[0084] Furthermore, in some embodiments, the distance between the orthographic projection of the contact hole 242 on the base substrate 21 and the orthographic projection of the gate lines on both sides thereof on the base substrate 21 is the same, that is, the orthographic projection of the contact hole 242 on the base substrate 21 is located in the middle position between the two gate lines 221 and 222 of the gate line group 22.

[0085] In some embodiments, the contact hole 242 has a size of 11 um×11 um.

[0086] In some embodiments, the common line 24 is provided with a contact pad 241 for connecting with the contact hole 242 ; wherein the size of the contact pad 241 is larger than the line width of the common line 24 portion between two adjacent pixel regions.

[0087] The contact pad 241 corresponds to a portion of the common line 24 with a larger line width.

[0088] In some embodiments, the contact pad 241 is square or circular in shape.

[0089] In some embodiments, the common electrode 26 includes a plurality of first sub-electrodes 261 that are spaced apart and extend along the row direction, and a plurality of second sub-electrodes 262 that are connected between any two adjacent rows of the first sub-electrodes 261 .

[0090] In some embodiments, the orthographic projection of the second sub-electrode 262 on the base substrate 21 at least covers the orthographic projection of the contact pad 241 on the base substrate 21 .

[0091] In some embodiments, the orthographic projection of the second sub-electrode 262 on the base substrate 21 coincides with the center of the orthographic projection of the contact pad 241 on the base substrate 21 .

[0092] In some embodiments, the array substrate further includes a thin film transistor 27 disposed in the gap region, and the thin film transistor 27 includes a gate 271 , an active layer 272 , a source 274 and a drain 273 .

[0093] Among them, the source 274 of the thin film transistor 27 is connected to its adjacent data line 23, the drain 273 of the thin film transistor 27 is connected to its corresponding pixel electrode 25, the gate 271 of the thin film transistor 27 is connected to its corresponding gate line 221 or 222, and the gate 271 of the thin film transistor 27 and the gate lines 221 and 222 are located in the same layer.

[0094] In some embodiments, the thin film transistor 27 may be a bottom-gate thin film transistor.

[0095] In some embodiments, the gate 271 of the thin film transistor 27 is made of the same material as the gate lines 221 and 222 .

[0096] One pixel unit includes a pixel region and a gap region formed by two gate lines 221 and 222 in the gate line group 22 and the common line 24 and the data line 23. The length of the gate lines 221 and 222 in one pixel unit is the gate line length between two adjacent data lines 23 and the common line 24. The thin film transistor 27 is located in the gap region.

[0097] In some embodiments, the orthographic projection of the second sub-electrode 262 on the base substrate 21 does not cover the orthographic projection of the data line 23 and the thin film transistor 27 on the base substrate 21. That is, the common electrode 26 is provided with openings at the positions of the thin film transistor 27, the gate lines 221 and 222 on both sides of the thin film transistor 27, and the data line 23 between two adjacent thin film transistors 27.

[0098] Since the common electrode 26 is stripe-shaped at the position of the pixel electrode 25 and has a small coverage area, in the above-mentioned array substrate, the openings set at the positions of the thin film transistor 27, the gate lines on both sides of the thin film transistor 27, and the data line 23 between two adjacent thin film transistors 27 can reduce the capacitance between the common electrode 26 and the gate line, as well as the capacitance between the common electrode 26 and the data line 23.

[0099] In some embodiments, without affecting the coverage of the common electrode 26 above the pixel electrode 25, the above structure can even reduce the overall coverage of the common electrode 26 by at least 60%, greatly reducing the capacitance between the common electrode 26 and the gate line, and the capacitance between the common electrode 26 and the data line 23.

[0100] In some embodiments, the distances ( S1 and S2 ) between the orthographic projection of the second sub-electrode 262 on the base substrate 21 and the orthographic projections of the gates 271 of the thin film transistors 27 on both sides thereof on the base substrate 21 are greater than the first preset distance.

[0101] In some embodiments, the first preset distance is greater than or equal to 3 um and less than or equal to 10 um, that is, 3 um ≤ S1 = S2 ≤ 10 um.

[0102] In some embodiments, the orthographic projection of the first sub-electrode 261 on the base substrate 21 at least covers a portion of the orthographic projection of the pixel electrode 25 on the base substrate 21 , and the orthographic projection of the first sub-electrode 261 on the base substrate 21 does not cover the orthographic projection of the gate line group 22 on the base substrate 21 .

[0103] In some embodiments, the distances ( S3 and S4 ) between the orthographic projection of the first sub-electrode 261 on the base substrate 21 and the orthographic projections of the gate line groups 22 on both sides thereof on the base substrate 21 are greater than the second preset distance.

[0104] In some embodiments, the second preset distance may be 1.25 um.

[0105] In some embodiments, Figure 4 As shown, the overlapped part of the orthographic projection of the first sub-electrode 261 on the base substrate 21 and the orthographic projection of the pixel electrode 25 on the base substrate 21 is in the shape of stripes. That is, the common electrode 26 is in the shape of stripes at the position of the pixel electrode 25 (a slit is formed between the two stripes), and different voltage differences are provided between the striped common electrode 26 and the pixel electrode 25 thereunder to form an electric field. The strongest edge vertical electric field exists at the edge of the striped electrode, so the liquid crystal tends to be arranged parallel to the vertical electric field, thereby enhancing the penetration effect of light and improving the display effect of the liquid crystal layer.

[0106] In some embodiments, the first sub-electrode 261 also covers a portion of the common line 24 and a portion of the data line 23 between any two adjacent pixel regions in the same row.

[0107] In some embodiments, Figure 5 As shown, the data line 23 includes a first conductive layer 231 and a second conductive layer 232 stacked in sequence above the base substrate 21 ; wherein the orthographic projection of the first conductive layer 231 on the base substrate 21 partially covers the orthographic projection of the second conductive layer 232 on the base substrate 21 .

[0108] In some embodiments, the common line 24 also includes a first conductive layer and a second conductive layer stacked in sequence on the base substrate 21, and the film layer structure is similar to that of the data line 23, and both can achieve the effect of reducing the resistance load of the wire.

[0109] In some embodiments, the first conductive layer 231 and the pixel electrode 25 are located on the same layer.

[0110] In some embodiments, the first conductive layer 231 and the pixel electrode 25 are made of the same material, both including indium tin oxide (ITO).

[0111] In some embodiments, the orthographic projection of the second sub-electrode 262 on the base substrate 21 does not cover the orthographic projection of the first conductive layer 231 on the base substrate 21. It can be understood that the first conductive layer 231 is located between adjacent pixel regions, the common line 24 and the data line 23 between the adjacent pixel regions are double-layer structures, and the common line 24 and the data line 23 between the gate lines 221 and 222 in the gate line group 22 are both single-layer structures, such as Figure 6 shown.

[0112] In some embodiments, the second conductive layer 232 is located on the same layer as the source 274 and the drain 273 of the thin film transistor 27 .

[0113] In some embodiments, the second conductive layer 232 is a metal layer, and the material of the second conductive layer 232 is the same as the material of the source 274 and the drain 273 of the thin film transistor 27 .

[0114] A protection layer 29 is also disposed above the common electrode 26 .

[0115] In the liquid crystal display panel corresponding to the above array substrate, the data line 23 , the common line 24 and the gate lines 221 and 222 are shielded by the black matrix layer BM disposed on the opposite substrate 40 .

[0116] In the present application, the common electrode is connected to the common line through at least one contact hole penetrating the insulating layer, which greatly reduces the resistance load of the common line, improves the pixel charging rate, and improves the display effect of the display panel.

[0117] An embodiment of the present application further provides a display device, which includes the above-mentioned array substrate.

[0118] In some embodiments, the display device is a display panel, and the display panel includes the above-mentioned display substrate and a glass cover.

[0119] In some embodiments, the display device may include a display panel and a housing, wherein the display panel is connected to the housing, for example, the display panel is embedded in the housing. The display device may be, for example, a mobile phone, a tablet computer, a television, a laptop computer, a digital photo frame, a navigator, or any other device having a display function.

[0120] The above are only preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various modifications and changes. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application. Although the implementation methods disclosed in the present application are as above, the content is only an implementation method adopted to facilitate the understanding of the present application and is not intended to limit the present application. Any technician in the technical field to which the present application belongs can make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in the present application, but the protection scope of the present application shall still be subject to the scope defined by the attached claims.

Claims

1. An array substrate, characterized in that: include: substrate substrate; A plurality of gate line groups are arranged on the base substrate at intervals and extend along the row direction; A plurality of common lines and a plurality of data lines are arranged on the base substrate at intervals and extend along the column direction; wherein the common lines and the data lines are arranged alternately, and the gate line group is insulated and overlapped with the common lines and the data lines to define a plurality of pixel areas; A pixel electrode disposed on the base substrate and located in the pixel area; an insulating layer covering the gate line group, the common line, the data line and the pixel electrode; A common electrode is disposed above the insulating layer; wherein the orthographic projection of the common electrode on the base substrate at least covers a portion of the gate line group, a portion of the common line, a portion of the data line and a portion of the pixel electrode on the base substrate; the common electrode is connected to the common line via at least one contact hole penetrating the insulating layer; Each of the gate line groups comprises two gate lines arranged at intervals; the two gate lines of each gate line group and the common line and the data line are arranged to form a plurality of gap areas; The orthographic projection of the contact hole on the substrate falls between the orthographic projections of two gate lines of the gate line group on the substrate; The common line is provided with a contact pad for connecting with the contact hole; Wherein, the size of the contact pad is larger than the line width of the common line portion between two adjacent pixel regions; The contact pad is in the shape of a square or a circle; The common electrode comprises a plurality of first sub-electrodes arranged at intervals and extending along the row direction, and a plurality of second sub-electrodes connected between any two adjacent rows of the first sub-electrodes; It also includes: a thin film transistor disposed in the gap region, the thin film transistor including a source electrode, a drain electrode and a gate electrode; Wherein, the source electrode of the thin film transistor is connected to the adjacent data line, the drain electrode of the thin film transistor is connected to the corresponding pixel electrode, and the gate electrode of the thin film transistor is connected to the corresponding gate line; The orthographic projection of the second sub-electrode on the base substrate does not cover the orthographic projections of the data line and the thin film transistor on the base substrate.

2. The array substrate according to claim 1, characterized in that: The orthographic projection of the contact hole on the base substrate is the same as the distance between the orthographic projections of the gate lines on both sides of the contact hole on the base substrate.

3. The array substrate according to claim 1, characterized in that: The orthographic projection of the second sub-electrode on the base substrate at least covers the orthographic projection of the contact pad on the base substrate.

4. The array substrate according to claim 3, characterized in that: The orthographic projection of the second sub-electrode on the base substrate coincides with the center of the orthographic projection of the contact pad on the base substrate.

5. The array substrate according to claim 1, characterized in that: The distance between the orthographic projection of the second sub-electrode on the base substrate and the orthographic projections of the gate electrodes of the thin film transistors on both sides thereof on the base substrate is greater than a first preset distance.

6. The array substrate according to claim 1, characterized in that: The orthographic projection of the first sub-electrode on the base substrate at least covers a portion of the orthographic projection of the pixel electrode on the base substrate, and the orthographic projection of the first sub-electrode on the base substrate does not cover the orthographic projection of the gate line group on the base substrate.

7. The array substrate according to claim 6, characterized in that: The distance between the orthographic projection of the first sub-electrode on the base substrate and the orthographic projections of the gate line groups on both sides thereof on the base substrate is greater than a second preset distance.

8. The array substrate according to claim 1, characterized in that: The overlapping portion of the orthographic projection of the first sub-electrode on the base substrate and the orthographic projection of the pixel electrode on the base substrate is in a stripe shape.

9. The array substrate according to claim 1, characterized in that: The first sub-electrode also covers the common line portion and the data line portion between any two adjacent pixel regions in the same row.

10. The array substrate according to claim 1, characterized in that: The orthographic projection of the pixel electrode on the base substrate does not cover the orthographic projections of the gate line group, the common line and the data line on the base substrate.

11. The array substrate according to claim 1, characterized in that: The data line and the common line include a first conductive layer and a second conductive layer stacked sequentially above the base substrate; The orthographic projection of the first conductive layer on the base substrate covers a portion of the orthographic projection of the second conductive layer on the base substrate.

12. The array substrate according to claim 11, characterized in that: The first conductive layer and the pixel electrode are located in the same layer, and the second conductive layer is a metal layer.

13. A display device, characterized in that: It comprises the array substrate as claimed in any one of claims 1 to 12.

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