In-memory computing readout circuit

Abstract

The application provides an in-memory computing readout circuit, comprising: a control circuit, configured to pull up a bit line voltage when an analog voltage quantity is input to a global bit line, and send a counting enable signal when the pulling up starts and send a counting end signal when the pulling up ends; a comparator, configured to flip when the bit line voltage reaches a reference voltage, wherein the reference voltage is a pre-stored voltage of the global bit line, so that the control circuit determines whether the pulling up process ends according to the flipping of the comparator; and a counter, configured to count according to the counting enable signal and the counting end signal output by the control circuit, and output a counting result after counting ends. By controlling the counting state of the counter according to the voltage pulling up state through the control circuit and taking the pre-stored voltage of the global bit line as the reference voltage, the area of the in-memory computing readout circuit can be reduced, and the manufacturing cost and use cost of the in-memory computing readout circuit can be reduced.

Description

Technical Field

[0001] This invention relates to the field of in-memory computing technology, and in particular to an in-memory computing readout circuit. Background Technology

[0002] In-memory computing, by embedding computing units into memory, can reduce computational latency and power consumption caused by data transfer, and greatly improve the processor's processing speed and performance.

[0003] Current in-memory computing system readout circuits input analog voltage into a multi-bit parallel analog-to-digital converter (flash ADC), compare it with different reference voltages to obtain a digital result represented as a thermometer code, and then convert it into a binary code output through a digital-to-digital converter. Because the multi-bit parallel ADC requires an additional reference voltage generation circuit, and the counting circuit remains constantly open, it increases manufacturing costs and consumes a significant amount of power. Furthermore, the number of comparators in a multi-bit parallel ADC is an exponential power of the output bit width; therefore, the number of comparators increases with output accuracy, leading to increased manufacturing costs and a larger circuit footprint, ultimately affecting the practicality and cost-effectiveness of the in-memory computing readout circuit. Summary of the Invention

[0004] This invention provides an in-memory computing readout circuit to solve the problems of current in-memory computing readout circuits which require a separate reference voltage generation circuit, a normally open counting circuit, and multiple comparators based on output accuracy requirements. This leads to increased power consumption, higher usage and manufacturing costs, and a larger circuit area, thus affecting the practicality and economy of the in-memory computing readout circuit.

[0005] This invention provides an in-memory computation readout circuit, comprising:

[0006] The control circuit is used to pull up the bit line voltage when an analog voltage is input to the global bit line, and to issue a counting enable signal when the pull-up starts and a counting end signal when the pull-up ends.

[0007] A comparator, the input of which is connected to the bit line voltage and a reference voltage, and the output of which is connected to the input of the control circuit, is used to flip when the bit line voltage reaches the reference voltage, wherein the reference voltage is a pre-stored voltage of the global bit line, so that the control circuit can determine whether the pull-up process has ended based on the flip of the comparator;

[0008] A counter, the input of which is connected to the output of the control circuit, is used to count according to the count enable signal and the count end signal output by the control circuit, and outputs the count result after the count is completed.

[0009] In one feasible implementation, the in-memory computation readout circuit further includes:

[0010] A pull-up selection circuit is provided, wherein the input terminal of the pull-up selection circuit is connected to the global bit line, and the output terminal is connected to the input terminal of the comparator. The pull-up selection circuit includes a multiplexer and at least two PMOS transistors. The multiplexer is used to determine the number of PMOS transistors that are turned on based on the pull-up speed.

[0011] In one feasible implementation, the control circuit is used to pull up the bit line voltage to a preset voltage.

[0012] The preset voltage is greater than the reference voltage, and the difference between the preset voltage and the reference voltage is greater than the threshold voltage of the PMOS transistor.

[0013] In one feasible implementation, the in-memory computation readout circuit further includes:

[0014] An analog voltage input circuit is provided, wherein the input terminal of the analog voltage input circuit is connected to the output terminal of the excitation signal, and the output terminal is connected to the global bit line. The analog voltage input circuit is used to determine the analog voltage based on the excitation signal and output the analog voltage.

[0015] In one feasible implementation, the analog voltage input circuit includes a static random access memory (SRAM) array.

[0016] In this array, each storage cell stores analog voltage weight data. The excitation signal is input to the storage cell through the word line of each storage cell, and the storage cell inputs the corresponding single-bit digital voltage to the global bit line.

[0017] In one feasible implementation, the control circuit includes:

[0018] The first switching unit is used to control the conduction state of the first switching unit according to the input level signal. When the first switching unit is on, it controls the reference voltage input to the comparator and transmits the level signal.

[0019] In one feasible implementation, the control circuit includes:

[0020] The second switching unit is used to control the conduction state of the second switching unit according to the input level signal. When the second switching unit is on, it controls the bit line voltage input to the comparator and outputs a conduction signal.

[0021] In one feasible implementation, the control circuit includes:

[0022] The delay unit has its input terminal connected to the level signal output terminal of the first switching unit and the level signal input to the control circuit, and its output terminal connected to the level signal input terminal of the second switching unit. The delay unit is used to input the level signal to the second switching unit after a delay time when it receives the level signal transmitted by the first switching unit.

[0023] In one feasible implementation, the control circuit includes:

[0024] An AND gate logic unit is provided, wherein the input terminal of the AND gate logic unit is connected to the output terminal of the comparator, the on signal output terminal of the second switch unit, and the pull-up enable signal output terminal, and the output terminal is connected to the input terminal of the counter. The AND gate logic unit is used to output a counting enable signal to the counter when all three input terminals are at a high level.

[0025] In one feasible implementation, the comparator is a single-bit comparator.

[0026] As can be seen from the above technical solutions, the present invention provides an in-memory calculation readout circuit, comprising: a control circuit, wherein the control circuit is used to pull up the bit line voltage when an analog voltage is input to the global bit line, and to issue a counting enable signal when the pull-up begins and a counting end signal when the pull-up ends; a comparator, wherein the input terminal of the comparator is connected to the bit line voltage and a reference voltage, and the output terminal is connected to the input terminal of the control circuit, the comparator is used to flip when the bit line voltage reaches the reference voltage, wherein the reference voltage is a pre-stored voltage of the global bit line, so that the control circuit determines whether the pull-up process has ended based on the flipping state of the comparator; and a counter, wherein the input terminal of the counter is connected to the output terminal of the control circuit, the counter is used to count according to the counting enable signal and the counting end signal output by the control circuit, and to output the counting result after the counting ends. In this embodiment, the control circuit controls the counting state of the counter according to the voltage pull-up state, which can reduce the power consumption of the counter. The comparator uses the voltage pre-stored on the global bit line as the reference voltage, which can realize the adjustment of the reference voltage by adjusting the pre-stored voltage on the global bit line without setting a reference voltage input circuit. This can reduce the area of ​​the in-memory computing readout circuit and reduce the power consumption of the reference voltage adjustment. The counting of the counter can directly output the target form of digital result without the need for additional conversion circuits, which can simplify the structure of the in-memory computing readout circuit, reduce the manufacturing cost and usage cost of the in-memory computing readout circuit, and thus improve the practicality and economy of the in-memory computing readout circuit. Attached Figure Description

[0027] To more clearly illustrate the technical solution of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 A schematic structural diagram of an in-memory computing readout circuit provided for an embodiment of this application;

[0029] Figure 2 A schematic diagram of an in-memory computing readout circuit provided for an embodiment of this application;

[0030] Figure 3 This is a schematic pin connection circuit diagram of a control circuit for an in-memory computing readout circuit provided in an embodiment of this application. Detailed Implementation

[0031] The embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described below do not represent all embodiments consistent with this application. They are merely examples of systems and methods consistent with some aspects of this application as detailed in the claims. In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can also be implemented in other ways, and the apparatus embodiments described below are merely exemplary.

[0032] like Figure 1 As shown, this application embodiment provides an in-memory computing readout circuit 100, including:

[0033] Control circuit 101 is used to pull up the bit line voltage when an analog voltage is input to the global bit line, and to issue a counting enable signal when the pull-up starts and a counting end signal when the pull-up ends.

[0034] Comparator 102, the input terminal of the comparator is connected to the bit line voltage and the reference voltage, and the output terminal is connected to the input terminal of the control circuit. The comparator is used to flip when the bit line voltage reaches the reference voltage, wherein the reference voltage is the pre-stored voltage of the global bit line, so that the control circuit determines whether the pull-up process has ended based on the flip of the comparator.

[0035] Counter 103, the input terminal of the counter is connected to the output terminal of the control circuit, the counter is used to count according to the counting enable signal and the counting end signal output by the control circuit, and output the counting result after the counting ends.

[0036] For example, the control circuit described above can pull up the bit line voltage on the global bit line according to the pull-up enable signal, and can stop pulling up the bit line voltage on the global bit line according to the pull-up stop signal. The pull-up enable signal can be determined based on the calculation progress of the analog voltage, and the pull-up stop signal can be the toggle signal of the comparator, or it can be a signal sent to the control circuit by an external control to stop the voltage pull-up.

[0037] For example, the comparator described above can be a voltage comparator. The reference voltage can be adjusted by regulating the pre-stored voltage on the global bit line.

[0038] For example, the type of the counter can be determined according to the type of the output result to directly obtain the digital output result of the target output method. For example, the counter can be a counter that outputs binary code.

[0039] By controlling the counter's counting state according to the voltage pull-up state through the control circuit, the counter's power consumption can be reduced. The comparator uses the voltage pre-stored on the global bit line as the reference voltage, eliminating the need for a separate reference voltage input circuit. The reference voltage can be adjusted simply by regulating the pre-stored voltage on the global bit line, reducing the area of ​​the in-memory computing readout circuit and lowering the power consumption for adjusting the reference voltage. The counter can directly output the target digital result without additional conversion circuitry, simplifying the structure of the in-memory computing readout circuit and reducing its manufacturing and operating costs. This, in turn, improves the practicality and economy of the in-memory computing readout circuit.

[0040] According to some embodiments, the above-described in-memory calculation readout circuit further includes:

[0041] The pull-up selection circuit has its input terminal connected to the global bit line and its output terminal connected to the input terminal of the comparator. The pull-up selection circuit includes a multiplexer and at least two PMOS transistors. The multiplexer is used to determine the number of PMOS transistors that are turned on based on the pull-up speed.

[0042] For example, the PMOS transistors can be driven individually using the multiplexer described above, or the PMOS transistors can be connected in series, and the multiplexer can select the first PMOS transistor to be turned on based on the current flow, thereby controlling the number of PMOS transistors turned on.

[0043] Since the pull-up speed of the bit line voltage is negatively correlated with the accuracy of the output result, the slower the pull-up speed, the higher the accuracy of the output result. In practical applications, due to the limitation of readout time, the pull-up speed needs to be adjusted. By controlling the number of PMOS transistors turned on through the pull-up selection circuit mentioned above to control the pull-up speed of the bit line voltage, the speed adjustment steps can be simplified, the adjustment efficiency can be improved, and the adjustment difficulty can be reduced. In this way, the flexibility and practicality of the in-memory calculation readout circuit can be improved.

[0044] According to some embodiments, the control circuit described above is used to pull up the bit line voltage to a preset voltage.

[0045] The preset voltage is a voltage value that is greater than the reference voltage and the difference between the preset voltage and the reference voltage is greater than the threshold voltage of the PMOS transistor.

[0046] Since the pull-up speed of a PMOS transistor to the bit line voltage varies non-linearly with the operating voltage, setting the difference between the preset voltage and the reference voltage as the threshold voltage of the PMOS transistor can keep the pull-up speed of a single PMOS transistor constant, making it easier to linearly adjust the pull-up speed and thus improve the accuracy of the output results.

[0047] According to some embodiments, the above-described in-memory calculation readout circuit further includes:

[0048] An analog voltage input circuit is provided, wherein the input terminal of the analog voltage input circuit is connected to the output terminal of the excitation signal, and the output terminal is connected to the global bit line. The analog voltage input circuit is used to determine the analog voltage based on the excitation signal and output the analog voltage.

[0049] The analog voltage input circuit described above can determine the analog voltage based on the input excitation signal and output the analog voltage to the multiplexer and comparator. This simplifies the process of determining the analog voltage, improves the integration of the in-memory calculation output circuit, and thus enhances the practicality and convenience of the in-memory calculation output circuit.

[0050] According to some embodiments, the analog voltage input circuit described above includes a static random access memory (SRAM) array.

[0051] In this array, each storage cell stores analog voltage weight data. The excitation signal is input to the storage cell through the word line of each storage cell, and the storage cell inputs the corresponding single-bit digital voltage to the global bit line.

[0052] By using a storage array in the analog voltage input circuit, the excitation signal input to each storage cell can be easily adjusted according to the weight data in each storage cell, thereby improving the accuracy and flexibility of the analog voltage output and enhancing the practicality of the in-memory calculation output circuit.

[0053] like Figure 2As shown, the circuit includes an analog voltage input circuit 210, which comprises n memory cells 211 and n word lines 212. The excitation signal on each word line 212 can be used to obtain a single-bit digital voltage on each memory cell through the weighted data in the memory cell 211. By inputting all the single-bit digital voltages together to the global bit line, an analog voltage can be generated on the global bit line. The global bit line inputs the analog voltage to a multiplexer 221. The multiplexer can determine the turn-on start of the PMOS transistor 222 based on the selection signal. The gate of each PMOS transistor 222 is connected to a pull-up current control unit 223. The pull-up current control unit 223 can control the pull-up speed of each PMOS transistor 222. The output terminal of the series-connected PMOS transistors 222 can output the voltage after the analog voltage has been pulled up, and the pulled-up voltage is input to a comparator 230. The input of comparator 230 is also connected to a reference voltage. Comparator 230 obtains the comparison result between the pulled-up voltage and the reference voltage, and inputs this comparison result to control circuit 240. Control circuit 240 generates a stop counting signal when comparator 230 flips, and generates a counting enable signal when the pull-up begins. The stop counting signal and the counting enable signal are input to counter 250 to control the timing of counter 250's operation. Counter 250 outputs the counting result when it stops counting.

[0054] According to some embodiments, the control circuit described above includes:

[0055] The first switching unit is used to control the conduction state of the first switching unit according to the input level signal. When the first switching unit is on, it controls the reference voltage input to the comparator and transmits the level signal.

[0056] For example, the first switching unit can be a high-level conduction unit or a low-level conduction unit, including four ports, wherein the first port is used to connect to the input level signal, the second port is used to connect to the reference voltage, the third port is used to connect to the input terminal of the comparator, and the fourth port is used to output the input level signal.

[0057] The first switching unit described above can independently form two non-interfering transmission paths. It can transmit input level signals and also control the on / off state of the other transmission path based on the level signal, thereby controlling the input terminal of the comparator and inputting a reference voltage to the comparator. This first switching unit improves the integration of the control circuit, simplifies the control process, increases control efficiency, and saves control costs.

[0058] According to some embodiments, the control circuit described above includes:

[0059] The second switching unit is used to control the conduction state of the second switching unit according to the input level signal. When the second switching unit is on, it controls the bit line voltage input to the comparator and outputs a conduction signal.

[0060] For example, the second switching unit can be a level-conducting unit with the opposite conduction characteristics to the first switching unit, including four ports. The first port is used to connect to the input level signal. The first port of the second switching unit is connected to the level signal of the input control circuit and the output terminal of the first switching unit to conduct when the first switching unit is off. The second port is used to connect to the bit line voltage. The third port is used to connect to the input terminal of the comparator. The fourth port is used to output the input level signal.

[0061] The second switching unit described above can form two non-interfering transmission paths. It can transmit input level signals and control the on / off state of the other transmission path based on the level signals. The second switching unit can input bit line voltage to the comparator when the first switching unit stops inputting reference voltage to the input terminal of the comparator, so as to control the input terminal of the comparator. This can improve the integration level of the control circuit, simplify the control process, improve control efficiency, and save control costs.

[0062] According to some embodiments, the control circuit described above includes:

[0063] The delay unit has its input terminal connected to the level signal output terminal of the first switch unit and the level signal input to the control circuit, and its output terminal connected to the level signal input terminal of the second switch unit. The delay unit is used to input the level signal to the second switch unit after a delay time when it receives the level signal transmitted by the first switch unit.

[0064] The aforementioned delay unit can delay the conduction of the first and second switching units when the level signal of the control circuit changes. This avoids the comparator misjudging the input reference voltage caused by rapid switching of the comparator's input port, which would affect the accuracy of the in-memory calculation and readout circuit. In this way, the practicality and accuracy of the in-memory calculation and readout circuit can be improved.

[0065] According to some embodiments, the control circuit described above includes:

[0066] The AND gate logic unit has its input terminal connected to the output terminal of the comparator, the on signal output terminal of the second switch unit, and the pull-up enable signal output terminal. Its output terminal is connected to the input terminal of the counter. The AND gate logic unit is used to output a counting enable signal to the counter when all three input terminals are at a high level.

[0067] Since the control circuit determines the counter's stop counting time based on the comparator's flip-flop and the external pull-up control signal, the timing of issuing the stop counting signal needs to be determined by the comparator's output level signal and the external pull-up enable signal. Furthermore, the level signal output by the second switch unit can determine whether there is a bit line voltage input to the comparator. If there is no bit line voltage input, the counter is considered not to have started, and therefore no stop counting signal needs to be issued. In summary, the above AND gate logic unit can issue a stop counting signal to the counter when the comparator flips, the second switch unit is turned on, and a pull-up enable signal is present, causing the counter to stop counting and output the counting result. This avoids incomplete criteria leading to misjudgment of the counter's stop time, affecting the accuracy of the in-memory calculation readout circuit, and thus improving the practicality and accuracy of the in-memory calculation readout circuit.

[0068] like Figure 3As shown, in the idle state, the EN_n enable signal is pulled high, and the pull-up enable signal PU_EN is pulled low. The first switching unit T1 is in the on state, which can transmit the reference voltage VDD level signal to the left port D of capacitor C. Transistor N2 is in the on state, shorting the two ends of the inverter composed of NMOS transistor N1 and PMOS transistor P1, so that the voltage at points E and F is kept at half of the comparator voltage V_COMP. When the analog voltage input circuit receives the excitation signal, the analog voltage input circuit starts to calculate the analog voltage. The EN_n enable signal is pulled low, and the pull-up enable signal PU_EN is still low. The first switching unit T1 and transistor N2 are in the off state. The EN_n enable signal, after being delayed by the delay unit BUF, is input to the second switching unit T2. The second switching unit T2 is in the on state, and the bit line voltage V_GBL starts to decrease from the reference voltage VDD and is input to the left port D of capacitor C. Based on the characteristics of a capacitor, when at least one end of the capacitor is floating, the voltage difference across the capacitor remains constant. Therefore, the voltage at point E starts to decrease from half of the comparator voltage V_COMP as the voltage at point D decreases, and the decrease is equal to the difference between the bit line voltage V_GBL and the reference voltage VDD. At this time, the output of the inverter composed of NMOS transistor N1 and PMOS transistor P1 is at a high level. After the analog voltage input circuit completes the calculation, PU_EN is pulled high. During the pull-up process, the bit line voltage V_GBL gradually rises, causing the voltages at points D and E to rise. When the voltage rises above the reference voltage VDD, the voltage at point E is above half of the comparator voltage V_COMP, causing the inverter to flip. The output signal is shaped by two stages of inverters, INV3 and INV4. The flip result of the comparator is transmitted to the AND gate, and ANDed with the pull-up enable signal PU_EN and the conduction signal of the second switch unit T2 to obtain the final counting enable signal COMP_OUT transmitted to the counter.

[0069] According to some embodiments, the comparator described above is a single-bit comparator.

[0070] Because single-bit comparators have a relatively simple structure and can perform continuous comparisons, they can save on comparator production costs and increase comparison speed. This, in turn, can save on the production costs of in-memory computing readout circuits, increase the readout speed of in-memory computing readout circuits, and improve the practicality of in-memory computing readout circuits.

[0071] In summary, the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit it. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A memory-based calculation and readout circuit, characterized in that, include: The control circuit is used to pull up the bit line voltage when an analog voltage is input to the global bit line, and to issue a counting enable signal when the pull-up starts and a counting end signal when the pull-up ends. A comparator, the input of which is connected to the bit line voltage and a reference voltage, and the output of which is connected to the input of the control circuit, is used to flip when the bit line voltage reaches the reference voltage, wherein the reference voltage is a pre-stored voltage of the global bit line, so that the control circuit can determine whether the pull-up process has ended based on the flip of the comparator; A counter, the input of which is connected to the output of the control circuit, is used to count according to the count enable signal and the count end signal output by the control circuit, and outputs the count result after the count is completed.

2. The in-memory calculation and readout circuit as described in claim 1, characterized in that, Also includes: A pull-up selection circuit is provided, wherein the input terminal of the pull-up selection circuit is connected to the global bit line, and the output terminal is connected to the input terminal of the comparator. The pull-up selection circuit includes a multiplexer and at least two PMOS transistors. The multiplexer is used to determine the number of PMOS transistors that are turned on based on the pull-up speed.

3. The in-memory calculation and readout circuit as described in claim 2, characterized in that, The control circuit is used to pull up the bit line voltage to a preset voltage. The preset voltage is greater than the reference voltage, and the difference between the preset voltage and the reference voltage is greater than the threshold voltage of the PMOS transistor.

4. The in-memory calculation and readout circuit as described in claim 1, characterized in that, Also includes: An analog voltage input circuit is provided, wherein the input terminal of the analog voltage input circuit is connected to the output terminal of the excitation signal, and the output terminal is connected to the global bit line. The analog voltage input circuit is used to determine the analog voltage based on the excitation signal and output the analog voltage.

5. The in-memory calculation and readout circuit as described in claim 4, characterized in that, The analog voltage input circuit includes a static random access memory array, wherein each storage cell in the storage array stores analog voltage weight data, the excitation signal is input to the storage cell through the word line of each storage cell, and the storage cell inputs the corresponding single-bit digital voltage to the global bit line.

6. The in-memory calculation and readout circuit as described in claim 1, characterized in that, The control circuit includes: The first switching unit is used to control the conduction state of the first switching unit according to the input level signal. When the first switching unit is on, it controls the reference voltage input to the comparator and transmits the level signal.

7. The in-memory calculation and readout circuit as described in claim 4, characterized in that, The control circuit includes: The second switching unit is used to control the conduction state of the second switching unit according to the input level signal. When the second switching unit is on, it controls the bit line voltage input to the comparator and outputs a conduction signal.

8. The in-memory calculation and readout circuit as described in claim 7, characterized in that, The control circuit includes: The delay unit has its input terminal connected to the level signal output terminal of the first switching unit and its output terminal connected to the level signal input terminal of the second switching unit. The delay unit is used to input the level signal to the second switching unit after a delay time when it receives the level signal transmitted by the first switching unit.

9. The in-memory calculation and readout circuit as described in claim 8, characterized in that, The control circuit includes: An AND gate logic unit is provided, wherein the input terminal of the AND gate logic unit is connected to the output terminal of the comparator, the on signal input terminal of the second switch unit, and the output terminal of the pull-up enable signal, and the output terminal of the AND gate logic unit is connected to the input terminal of the counter. The AND gate logic unit is used to output a counting enable signal to the counter when all three input terminals are at a high level.

10. The in-memory calculation and readout circuit as described in claim 1, characterized in that, The comparator is a single-bit comparator.

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