Method of manufacturing a semiconductor structure, semiconductor structure and memory

Abstract

The present disclosure provides a semiconductor structure manufacturing method, a semiconductor structure and a memory, and relates to the technical field of semiconductors. The semiconductor structure manufacturing method comprises the following steps: providing a semiconductor substrate; forming a metal layer on one side of the semiconductor substrate, and performing annealing treatment on the metal layer; forming a dielectric layer on the side of the metal layer away from the semiconductor substrate; and forming an insulating layer covering the dielectric layer and the metal layer. The resistance of the metal layer during the manufacturing process of the semiconductor structure can be avoided from becoming large.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a method for manufacturing a semiconductor structure, a semiconductor structure, and a memory. Background Technology

[0002] With the development of semiconductor technology, memory devices are increasingly pursuing high speed, high integration density, and low power consumption. Typically, integrated circuit memories consist of several memory cells, and bit lines are usually formed in the memory cells, which are connected to the source / drain regions of the transistors in the memory cells.

[0003] However, in current semiconductor devices, bit lines still have relatively large resistance, resulting in a small current flowing through the bit lines, which slows down the charging and discharging speed of the storage capacitor and thus affects the performance of the semiconductor device.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of this disclosure is to provide a method for manufacturing a semiconductor structure, a semiconductor structure, and a memory, which can avoid the increase in resistance of the metal layer during the semiconductor structure manufacturing process.

[0006] According to one aspect of the present disclosure, a method for manufacturing a semiconductor structure is provided, the method comprising:

[0007] Provide semiconductor substrates;

[0008] A metal layer is formed on one side of the semiconductor substrate, and the metal layer is annealed.

[0009] A dielectric layer is formed on the side of the metal layer opposite to the semiconductor substrate;

[0010] An insulating layer is formed covering the dielectric layer and the metal layer.

[0011] In one exemplary embodiment of this disclosure, before forming a metal layer on one side of the semiconductor substrate, the manufacturing method further includes:

[0012] A semiconductor layer is formed on one side of the semiconductor substrate, and a metal layer is located on the side of the semiconductor layer opposite to the semiconductor substrate.

[0013] In one exemplary embodiment of this disclosure, an insulating layer covering the dielectric layer and the metal layer is formed, comprising:

[0014] A first sub-insulating layer is formed by using thermal atomic layer deposition to cover the dielectric layer and the metal layer.

[0015] In one exemplary embodiment of this disclosure, forming an insulating layer covering the dielectric layer and the metal layer further includes:

[0016] A second sub-insulating layer is formed by plasma-enhanced atomic layer deposition (PEALD) to cover the first sub-insulating layer; the second sub-insulating layer and the first sub-insulating layer together form the insulating layer.

[0017] In one exemplary embodiment of this disclosure, when the first sub-insulating layer is formed using the thermal atomic layer deposition method, the pressure of the reaction chamber is reduced by 5%-10%.

[0018] In one exemplary embodiment of this disclosure, when the first sub-insulating layer is formed using the thermal atomic layer deposition method, the temperature of the reaction chamber is set at 500°C-650°C.

[0019] In one exemplary embodiment of this disclosure, the first sub-insulating layer is formed by using the precursor gas dichlorosilane and the reactant gas ammonia.

[0020] In one exemplary embodiment of this disclosure, the thickness of the first sub-insulating layer is 1nm-3nm.

[0021] In one exemplary embodiment of this disclosure, the second sub-insulating layer is formed by reacting the precursor gas dichlorosilane with the reactive gas ammonia.

[0022] In one exemplary embodiment of this disclosure, the thickness of the second sub-insulating layer is 10nm-30nm.

[0023] In one exemplary embodiment of this disclosure, the conditions for annealing the metal layer include:

[0024] First, raise the temperature to 700℃-800℃, hold the temperature for 30min-60min, and then lower the temperature to 500℃-650℃.

[0025] In one exemplary embodiment of this disclosure, when the metal layer is annealed, an inert gas of 7 slm-9 slm is introduced into the reaction chamber.

[0026] In one exemplary embodiment of this disclosure, the material of the metal layer includes tungsten.

[0027] In one exemplary embodiment of this disclosure, the insulating layer is made of silicon nitride.

[0028] According to another aspect of the present disclosure, a semiconductor structure is provided, which is formed by the manufacturing method described above.

[0029] In one exemplary embodiment of this disclosure, the semiconductor structure includes bit lines.

[0030] According to another aspect of the present disclosure, a memory is provided that includes the semiconductor structure described above.

[0031] The semiconductor structure manufacturing method provided in the embodiments of this disclosure includes a metal layer formed in the semiconductor structure, and the metal layer is annealed. By annealing the metal layer, the number of grain boundaries in the metal layer can be reduced. By reducing the number of grain boundaries in the metal layer, the cross-sectional area of ​​the metal layer increases. When the material and length of the metal layer remain unchanged, the larger the cross-sectional area, the smaller the resistance, thereby achieving the purpose of reducing the resistance of the metal layer. When an insulating layer covering the metal layer is subsequently formed, and the metal layer forms a metal composite that increases the resistance of the metal layer, the portion of the increased resistance caused by the formation of the metal composite can be offset by the portion of the metal layer whose resistance is reduced by the annealing process, thereby avoiding an increase in the resistance of the metal layer and meeting the design requirements.

[0032] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0033] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort. In the drawings:

[0034] Figure 1 A flowchart illustrating a method for manufacturing a semiconductor structure according to an embodiment of this disclosure;

[0035] Figures 2-4 This is a process diagram of the manufacturing process of a semiconductor structure provided in one embodiment of the present disclosure. Detailed Implementation

[0036] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be more thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art.

[0037] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced without one or more of the specific details, or other methods, steps, etc., can be employed. In other instances, well-known method implementations or operations are not shown or described in detail to avoid obscuring various aspects of this disclosure.

[0038] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0039] The terms “a,” “one,” “the,” and “at least one” are used to indicate the existence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” etc. are used only as markers and are not a limitation on the number of objects.

[0040] Embodiments of this disclosure provide a method for manufacturing a semiconductor structure, such as... Figure 1 As shown, the manufacturing method includes:

[0041] Step S100: Provide a semiconductor substrate;

[0042] Step S200: Form a metal layer on one side of the semiconductor substrate and anneal the metal layer.

[0043] Step S300: Form a dielectric layer on the side of the metal layer away from the semiconductor substrate;

[0044] Step S400: Form an insulating layer covering the dielectric layer and the metal layer.

[0045] The semiconductor structure manufacturing method provided in the embodiments of this disclosure includes a metal layer formed in the semiconductor structure, and the metal layer is annealed. By annealing the metal layer, the number of grain boundaries in the metal layer can be reduced. By reducing the number of grain boundaries in the metal layer, the cross-sectional area of ​​the metal layer increases. With the material and length of the metal layer remaining unchanged, the larger the cross-sectional area, the smaller the resistance, thereby achieving the purpose of reducing the resistance of the metal layer. When an insulating layer covering the metal layer is subsequently formed, and the formation of a metal composite between the insulating layer and the metal layer causes the resistance of the metal layer to increase, the portion of the increased resistance caused by the formation of the metal composite can be offset by the portion of the metal layer whose resistance is reduced by the annealing process, thereby avoiding an increase in the resistance of the metal layer and meeting the design requirements.

[0046] The steps in the method for manufacturing the semiconductor structure provided in this disclosure will now be described in detail.

[0047] In step S100, a semiconductor substrate is provided.

[0048] Specifically, such as Figure 2 As shown, a semiconductor substrate 100 is provided, which may be formed in a substrate 200. The semiconductor substrate 100 may be made of a single-element semiconductor material, such as silicon (Si); or a compound semiconductor material, such as gallium arsenide (GaAs), indium phosphide (InP), silicon carbide (SiC), or gallium nitride (GaN), or a combination thereof. The substrate 200 is an insulating material, such as silicon oxide (SiO), silicon oxynitride (SiOxNy), silicon nitride (Si3N4), or other suitable insulating materials (e.g., organic polymer compounds), or a combination thereof.

[0049] In step S200, a metal layer is formed on one side of the semiconductor substrate, and the metal layer is annealed.

[0050] Specifically, such as Figure 2 As shown, a metal layer 400 can be formed on one side of a semiconductor substrate 100 using physical vapor deposition (PVD), chemical vapor deposition (CVD), spin coating, or a combination thereof, and then annealed. Annealing the metal layer 400 reduces the number of grain boundaries; reducing the number of grain boundaries increases the cross-sectional area of ​​the metal layer 400. With the material and length of the metal layer 400 remaining constant, a larger cross-sectional area results in lower electrical resistance.

[0051] When annealing the metal layer 400, the reaction chamber is first heated to 700℃-800℃, such as 700℃, 720℃, 750℃, 770℃, 790℃, 800℃, etc., which are not listed here. Of course, the reaction chamber containing the metal layer 400 can also be heated to a temperature lower than 700℃ or higher than 800℃, which is not limited here. After the heating is completed, the temperature is then held for 30min-60min, such as 30min, 40min, 50min, 60min, etc., which are not listed here. Of course, the temperature holding time can also be less than 30min or greater than 60min, which is not limited here. After the heat preservation time is up, the temperature is then lowered to 500℃-650℃, such as 500℃, 520℃, 550℃, 580℃, 600℃, 620℃, 650℃, etc., which will not be listed here; of course, the temperature can also be lowered to less than 500℃ or greater than 650℃, which is not limited here.

[0052] Furthermore, during the annealing process of the metal layer 400, an inert gas of 7 slm-9 slm is introduced into the reaction chamber containing the metal layer 400. The inert gas disclosed herein refers to a chemically inert gas that will not react with the materials used in the semiconductor structure manufacturing process; an example of an inert gas is nitrogen (N2). By introducing the inert gas, other gases can be excluded, thereby preventing the metal layer 400 from reacting with other gases at high temperatures during the annealing process to form an oxide layer or compound layer.

[0053] The metal layer 400 is made of materials such as tungsten (W), titanium (Ti), platinum (Pt), ruthenium (Ru), gold (Au), silver (Ag), molybdenum (Mo), aluminum (Al), copper (Cu), neodymium (Nd), chromium (Cr), tantalum (Ta), or a combination of the above materials.

[0054] In one embodiment of this disclosure, such as Figure 2 As shown, before forming a metal layer 400 on one side of the semiconductor substrate 100, the manufacturing method further includes forming a semiconductor layer 300 on one side of the semiconductor substrate 100, wherein the metal layer 400 is located on the side of the semiconductor layer 300 opposite to the semiconductor substrate 100.

[0055] The semiconductor layer 300 can be made of amorphous silicon, polycrystalline silicon, microcrystalline silicon, monocrystalline silicon, oxide semiconductor materials, organosilicon materials, organooxide semiconductor materials, or combinations thereof. The semiconductor layer 300 can be formed by, for example, physical vapor deposition, chemical vapor deposition, or combinations thereof.

[0056] In step S300, a dielectric layer is formed on the side of the metal layer that faces away from the semiconductor substrate.

[0057] Specifically, a dielectric layer 500 can be formed on the side of the metal layer 400 facing away from the semiconductor substrate 100 by physical vapor deposition, chemical vapor deposition, spin coating, or a combination thereof. The material of the dielectric layer 500 can be, for example, silicon oxide (SiO), silicon oxynitride (SiOxNy), silicon nitride (Si3N4), or other suitable insulating materials (e.g., organic polymer compounds) or combinations thereof.

[0058] In step S400, an insulating layer covering the dielectric layer and the metal layer is formed.

[0059] Specifically, silicon nitride plays a crucial role in the bit lines (BLs) of Dynamic Random Access Memory (DRAM), primarily by preventing metal corrosion and reducing leakage current. Currently, the main method for forming silicon nitride in bit lines is through Plasma ALD (Plasma Enhanced Atomic Layer Deposition). Plasma ALD offers good step coverage, a fast reaction rate, and a relatively low reaction temperature. The reacting gases introduced are nitrogen (NH3) and dichlorosilane (SiH2Cl2), and the reaction equation is: 3SiH2Cl2 + 10NH3 → Si3N4 + 6NH4Cl2 + 6H2.

[0060] However, during silicon nitride deposition using Plasma ALD, NH3 ions exhibit high reactivity and readily form metal complexes with the metal substrate. For example, if the metal layer includes tungsten (W), ammonia reacts with tungsten to form a tungsten nitride complex, as shown in the reaction equation: W + N. . →WN, the resistance of the tungsten nitride composite is greater than that of metallic tungsten, resulting in a larger bit line resistance, which in turn leads to a worse bit line refresh performance.

[0061] like Figure 3 As shown, this disclosure first employs thermal atomic layer deposition (thermal ALD) at a temperature of 500℃-650℃, introducing the precursor DCS (SiH2Cl2) and the reactive gas NH3 to form a first sub-insulating layer (Si3N4) 610 covering the dielectric layer 500 and the metal layer 400. In thermal ALD, the reactivity of NH3 is weaker than that in plasma-enhanced atomic layer deposition, thus making it less likely to form metal complexes such as tungsten nitride (WN), thereby preventing the metal layer 400 from forming compounds that increase its resistance.

[0062] Furthermore, during thermal atomic layer deposition, the pressure in the reaction chamber can be reduced by 5%-10% to increase the N2 concentration in the chamber and reduce the O2 concentration, thereby reducing the oxidation of the metal layer 400 (e.g., W).

[0063] The thickness of the first sub-insulating layer 610 can be 1nm-3nm, such as 1nm, 2nm, 3nm, etc., which will not be listed here; of course, the thickness of the first sub-insulating layer 610 can also be less than 1nm or greater than 3nm, which will not be limited here.

[0064] like Figure 4 As shown, after the first sub-insulating layer 610 is formed, plasma-enhanced atomic layer deposition (Plasma ALD) is then used to introduce the precursor DCS (SiH2Cl2) and the reactive gas NH3 at a temperature of 500℃-650℃ to form a second sub-insulating layer (Si3N4) 620 covering the first sub-insulating layer 610. The second sub-insulating layer 620 and the first sub-insulating layer 610 are combined to form an insulating layer 600.

[0065] The thickness of the second sub-insulating layer 620 can be 10nm-30nm, such as 10nm, 15nm, 20nm, 25nm, 30nm, etc., which will not be listed here; of course, the thickness of the second sub-insulating layer 620 can also be less than 10nm or greater than 30nm, which will not be limited here.

[0066] The method for forming an insulating layer disclosed herein first forms a first sub-insulating layer 610 using thermal atomic layer deposition (TID). During the formation of the first sub-insulating layer 610 using TID, the activity of NH3 is relatively weak, making it less likely to form metal complexes such as tungsten nitride (WN), thus avoiding the formation of compounds in the metal layer 400 and resulting in increased resistance. Next, a second sub-insulating layer 620 is formed using plasma-enhanced atomic layer deposition (PEAD). During the formation of the second sub-insulating layer 620, the uniformity and step coverage of the second sub-insulating layer 620 are good, and the thickness of the second sub-insulating layer 620 is greater than that of the first sub-insulating layer 610. This method avoids the formation of compounds between the insulating layer 600 and the metal layer 400, which would lead to increased resistance in the metal layer 400, while also ensuring good uniformity and step coverage of the formed insulating layer 600.

[0067] It should be noted that although the steps of the method in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or a step may be broken down into multiple steps.

[0068] This disclosure also provides a semiconductor structure formed by the above-described manufacturing method.

[0069] In one embodiment of this disclosure, the semiconductor structure includes bit lines. For example... Figure 4 As shown, the semiconductor structure includes: a semiconductor substrate 100, a semiconductor layer 300, a metal layer 400, and a dielectric layer 500 stacked sequentially, with an insulating layer 600 covering the semiconductor layer 300, the metal layer 400, and the dielectric layer 500. The semiconductor layer 300, the metal layer 400, and the dielectric layer 500 together constitute a bit line structure.

[0070] The semiconductor substrate 100 can be made of a single-element semiconductor material, such as silicon (Si); or it can be made of a compound semiconductor material, such as gallium arsenide (GaAs), indium phosphide (InP), silicon carbide (SiC), or gallium nitride (GaN), or a combination thereof. The semiconductor layer 300 can be made of amorphous silicon, polycrystalline silicon, microcrystalline silicon, single-crystal silicon, oxide semiconductor material, organosilicon material, organooxide semiconductor material, or a combination thereof.

[0071] After forming a metal layer 400 on one side of the semiconductor substrate 100, the metal layer 400 is annealed. Annealing the metal layer 400 reduces the number of grain boundaries. Reducing the number of grain boundaries increases the cross-sectional area of ​​the metal layer 400. With the material and length of the metal layer 400 remaining constant, a larger cross-sectional area results in lower electrical resistance. The material of the metal layer 400 may be, for example, tungsten (W), titanium (Ti), platinum (Pt), ruthenium (Ru), gold (Au), silver (Ag), molybdenum (Mo), aluminum (Al), copper (Cu), neodymium (Nd), chromium (Cr), tantalum (Ta), or a combination of these materials.

[0072] The dielectric layer 500 may be made of materials such as silicon oxide (SiO), silicon oxynitride (SiOxNy), silicon nitride (Si3N4), or other suitable insulating materials (e.g., organic polymer compounds) or combinations thereof.

[0073] The insulating layer 600 includes a first sub-insulating layer 610 and a second sub-insulating layer 620. This disclosure first employs thermal atomic layer deposition (TID) at a temperature of 500℃-650℃, introducing a precursor DCS (SiH2Cl2) and a reactive gas NH3 to form a first sub-insulating layer (Si3N4) 610 covering the dielectric layer 500 and the metal layer 400. In TID, the reactivity of NH3 is weaker than in plasma-enhanced atomic layer deposition (PEA), thus making it less likely to form metal complexes such as tungsten nitride (WN), thereby preventing the formation of compounds in the metal layer 400 and preventing increased resistance. The thickness of the first sub-insulating layer 610 can be 1nm-3nm, for example, 1nm, 2nm, 3nm, etc., which are not listed here; of course, the thickness of the first sub-insulating layer 610 can also be less than 1nm or greater than 3nm, which is not limited here.

[0074] After forming the first sub-insulating layer 610, plasma-enhanced atomic layer deposition (PEALD) is then used at a temperature of 500℃-650℃ to introduce the precursor DCS (SiH2Cl2) and the reactive gas NH3 to form a second sub-insulating layer (Si3N4) 620 covering the first sub-insulating layer 610. The second sub-insulating layer 620 and the first sub-insulating layer 610 combine to form the insulating layer 600. The thickness of the second sub-insulating layer 620 can be 10nm-30nm, such as 10nm, 15nm, 20nm, 25nm, 30nm, etc., which are not listed here; of course, the thickness of the second sub-insulating layer 620 can also be less than 10nm or greater than 30nm, which is not limited here.

[0075] The insulating layer 600 provided in this disclosure includes a first sub-insulating layer 610 and a second sub-insulating layer 620. The first sub-insulating layer 610 is formed by thermal atomic layer deposition. When the first sub-insulating layer 610 is formed by thermal atomic layer deposition, the activity of NH3 is relatively weak, so it is not easy to form metal compounds such as tungsten nitride (WN), thereby avoiding the formation of compounds in the metal layer 400 and preventing the resistance from increasing. The second sub-insulating layer 620 is formed by plasma-enhanced atomic layer deposition. When the second sub-insulating layer 620 is formed by plasma-enhanced atomic layer deposition, the uniformity and step coverage of the second sub-insulating layer 620 are better, and the thickness of the second sub-insulating layer 620 is greater than the thickness of the first sub-insulating layer 610. While avoiding the formation of compounds between the insulating layer 600 and the metal layer 400, which would lead to an increase in the resistance of the metal layer 400, the uniformity and step coverage of the formed insulating layer 600 are also better.

[0076] This disclosure also provides a memory, including the semiconductor structure described above. The memory can be Dynamic Random Access Memory (DRAM), or Read-Only Memory (ROM), and its type is not specifically limited herein. This memory can be used in mobile phones, tablets, or other terminal devices, and its beneficial effects are similar to those described in the manufacturing method, which will not be elaborated further here.

[0077] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the following claims.

[0078] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A method of manufacturing a semiconductor structure, characterized by, The application relates to a semiconductor structure and a manufacturing method thereof. The application provides a semiconductor substrate; forming a semiconductor layer and a metal layer on one side of the semiconductor substrate, and annealing the metal layer on the side of the semiconductor layer away from the semiconductor substrate; forming a dielectric layer on the side of the metal layer away from the semiconductor substrate; forming an insulating layer covering the dielectric layer and the metal layer, comprising: forming a first sub-insulating layer covering the dielectric layer and the metal layer by using a thermal atomic layer deposition method; forming a second sub-insulating layer covering the first sub-insulating layer by using a plasma enhanced atomic layer deposition method; the second sub-insulating layer and the first sub-insulating layer form the insulating layer; the thickness of the second sub-insulating layer is greater than the thickness of the first sub-insulating layer.

2. The production method according to claim 1, characterized by When the first sub-insulating layer is formed by using the thermal atomic layer deposition method, the pressure of a reaction cavity is reduced by 5%-10%.

3. The production method according to claim 1, characterized by When the first sub-insulating layer is formed by using the thermal atomic layer deposition method, the temperature of the reaction cavity is set to 500-650 DEG C.

4. The production method according to claim 1, characterized by The first sub-insulating layer is formed by using a precursor gas dichlorosilane and a reaction gas ammonia.

5. The production method according to claim 1, characterized by The thickness of the first sub-insulating layer is 1-3 nm.

6. The production method according to claim 1, characterized by The second sub-insulating layer is formed by using a precursor gas dichlorosilane and a reaction gas ammonia.

7. The production method according to claim 1, wherein The thickness of the second sub-insulating layer is 10-30 nm.

8. The production method according to claim 1, characterized by The annealing conditions of the metal layer include: firstly, the temperature is raised to 700-800 DEG C and kept for 30-60 min, and then the temperature is reduced to 500-650 DEG C.

9. The production method according to claim 1 or 8, characterized by, When the metal layer is annealed, 7-9 slm inert gas is introduced into the reaction cavity.

10. The production method according to claim 1, characterized by The material of the metal layer comprises tungsten.

11. The production method according to claim 1, characterized by The material of the insulating layer comprises silicon nitride.

12. A semiconductor structure, characterized by The manufacturing method is formed by the manufacturing method in any one of claims 1-11.

13. The semiconductor structure of claim 12, wherein, The semiconductor structure comprises a bit line.

14. A memory, comprising: The application relates to a semiconductor structure and a manufacturing method thereof. The application relates to a semiconductor structure and a manufacturing method thereof.

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