Semiconductor structure and its formation method

Abstract

A semiconductor structure and a method for forming the same, the method comprising: etching the sidewalls of an initial channel layer to form a channel layer; forming a trench between two adjacent sacrificial layers, wherein the trench exposes a channel layer sidewall recessed relative to the sacrificial layer sidewall; forming a dielectric wall within the opening and the trench; after forming the dielectric wall, forming an interlayer dielectric layer and a gate opening within the interlayer dielectric layer on a substrate, the gate opening being located on a portion of the sidewalls and top surface of an initial composite layer and exposing a portion of the sacrificial layer; removing the exposed sacrificial layer from the gate opening; forming a gate trench between adjacent channel layers and between the channel layer and the dielectric wall, wherein the gate trench and the channel layer form a composite layer; and forming a gate within the gate opening and the gate trench, the gate surrounding the channel layer, which facilitates improved gate control over the channel, thereby improving device performance.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] In the current semiconductor field, the FinFET (Fin Field-Effect Transistor) is an emerging multi-gate device. Compared with planar metal-oxide-semiconductor field-effect transistors (MOSFETs), FinFETs have stronger short-channel rejection and higher operating current, and are now widely used in various semiconductor devices. However, with the further development of semiconductor technology, the transistor size has shrunk to below a few nanometers. The size of FinFETs themselves has already reached its limit. Limitations in fin spacing, short-channel effect, leakage current, and materials have made transistor manufacturing precarious, and even the physical structure cannot be completed.

[0003] Gate-all-around (GAA) devices have become a new direction for research and development in the industry. This technology is characterized by the gate completely surrounding the channel on all four sides. The source and drain no longer contact the substrate; instead, multiple source and drain electrodes, arranged laterally and perpendicularly to the gate in linear (rod-like), planar, or sheet-like shapes, are used to achieve the basic structure and function of a MOSFET. This design largely solves various problems caused by reducing the gate spacing, including capacitance effects. Furthermore, since the channel is surrounded by the gate on all four sides, the channel current flows more smoothly than with the three-sided enclosure of a FinFET.

[0004] As semiconductor technology advances further, there is a growing demand for smaller spacing between NFET and PFET devices within standard cells. However, for fin field-effect transistors and gate-all-around transistors (GAMTs), process limitations restrict the spacing between N-type and P-type devices. To enhance device miniaturization, forksheet devices are considered a natural extension of gate-all-around transistors. Compared to gate-all-around devices, the channel of a forksheet device is controlled by a fork-shaped gate structure, achieved by introducing a "dielectric wall" between the PMOS and NMOS devices before gate patterning. This dielectric wall physically isolates the P-gate trench from the N-gate trench, allowing for a tighter N-to-P spacing and better miniaturization in terms of area and performance.

[0005] However, the technology of Forksheet devices is not yet perfect and needs further improvement. Summary of the Invention

[0006] The technical problem solved by this invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of semiconductor structures.

[0007] To address the aforementioned technical problems, the present invention provides a semiconductor structure comprising: a substrate; two mutually discrete composite layers on the substrate and an opening between the two composite layers, the composite layer comprising a plurality of overlapping gate trenches on the substrate and a channel layer and a groove on the sidewall of the channel layer located between adjacent gate trenches, the exposed sidewall of the channel layer being recessed relative to the sidewall of the gate trench; a dielectric wall located within the opening and the groove adjacent to the opening; an interlayer dielectric layer on the substrate and a gate opening within the interlayer dielectric layer, the gate opening being located on a portion of the sidewall and top surface of the composite layer; and a gate located within the gate opening and the gate trench, the gate surrounding the channel layer.

[0008] Optionally, the composite layer further includes a bottom structure located at the bottom of the composite layer.

[0009] Optionally, the dielectric wall has a gap with the sidewall of the channel layer; the gate is also located in the gap.

[0010] Optionally, the size of the void in the direction perpendicular to the sidewall of the opening ranges from 1 nanometer to 3 nanometers.

[0011] Optionally, the groove has a size ranging from 1 nanometer to 3 nanometers along the direction perpendicular to the sidewall of the opening.

[0012] Optionally, it may also include an isolation layer located on the substrate and within the opening, the isolation layer being located on the sidewall of the bottom structure and below the dielectric wall, and the top surface of the isolation layer being flush with the top surface of the bottom structure.

[0013] Accordingly, the present invention also provides a method for forming a semiconductor structure, comprising: forming a substrate and two initial composite layers discretely separated on the substrate, wherein the two initial composite layers have an opening between them, the initial composite layer comprising a plurality of overlapping sacrificial layers on the substrate and an initial channel layer between two adjacent sacrificial layers; etching the sidewalls of the initial channel layer to form a channel layer, forming a groove between two adjacent sacrificial layers, wherein the sidewalls of the channel layer exposed by the groove are recessed relative to the sidewalls of the sacrificial layers; forming a dielectric wall in the opening and the groove; after forming the dielectric wall, forming an interlayer dielectric layer and a gate opening in the interlayer dielectric layer on the substrate, wherein the gate opening is located on a portion of the sidewalls and top surface of the initial composite layer and exposes a portion of the sacrificial layer; removing the exposed sacrificial layer from the gate opening, forming a gate trench between adjacent channel layers and between the channel layer and the dielectric wall, wherein the gate trench and the channel layer form a composite layer; and forming a gate in the gate opening and the gate trench, wherein the gate surrounds the channel layer.

[0014] Optionally, after forming the gate trench and before forming the gate, the method further includes: etching the dielectric wall to form a gap between the dielectric wall and the sidewall of the channel layer; the gate is also located in the gap.

[0015] Optionally, the etching process for the dielectric wall includes a wet etching process.

[0016] Optionally, the initial composite layer further includes a bottom structure located at the bottom of the initial composite layer.

[0017] Optionally, after forming the initial composite layer and before forming the dielectric wall, the method further includes: forming an isolation layer on the substrate and inside the opening, the isolation layer being located on the sidewall of the bottom structure, and the top surface of the isolation layer being flush with the top surface of the bottom structure.

[0018] Optionally, the method for forming the dielectric wall includes: forming a dielectric material layer on the surface of the substrate, the dielectric material layer also being located on the sidewalls and surface of the initial composite layer, and filling the opening and the groove adjacent to the opening; forming a patterned layer on the surface of the dielectric material layer, the patterned layer exposing the dielectric material layer on the surface of the substrate and the top surface of the initial composite layer; etching the dielectric material layer using the patterned layer as a mask until the top surface of the initial composite layer, the surface of the substrate, and the sidewalls of the channel layer and the sacrificial layer are exposed.

[0019] Optionally, the method for forming the gate opening includes: forming a dummy gate on the substrate, the dummy gate being located on a portion of the sidewall and surface of the initial composite layer and on top of the dielectric wall; forming an interlayer dielectric layer on the substrate, the interlayer dielectric layer being located on the sidewall of the dummy gate and exposing the top surface of the dummy gate; removing the dummy gate and forming the gate opening within the interlayer dielectric layer.

[0020] Optionally, the process for forming the groove includes one or a combination of dry etching or wet etching.

[0021] Optionally, the dielectric wall material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon carbonitride, and silicon carbonitride.

[0022] Optionally, the substrate includes a first region and a second region, the composite layer is located in the first region, and the method further includes: forming a second composite layer on the second region, the second composite layer including a plurality of overlapping second gate trenches located on the second region and a second channel layer located between adjacent second gate trenches; the gate opening is also located on a portion of the sidewall and top surface of the second composite layer; the gate is also located within the second gate trench and surrounds the second channel layer.

[0023] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0024] In the semiconductor structure formation method provided by the present invention, the initial channel layer is etched to form a groove between two adjacent sacrificial layers. The sidewall of the channel layer exposed by the groove is recessed relative to the sidewall of the sacrificial layer. After forming dielectric walls in the opening and the groove adjacent to the opening, a portion of the dielectric wall includes a protruding portion extending towards the sidewall of the channel layer. When a uniform gate material layer is formed on the surface of the channel layer, the protruding portion provides the gate material layer with redundant space to fill the space, thereby improving the bonding state between the gate material layer and the surface of the channel layer. This is beneficial to improving the gate's control capability over the channel, and thus improving the performance of the device.

[0025] Furthermore, after forming the gate trench, the dielectric wall is subjected to wet etching to create a gap between the dielectric wall and the sidewall of the channel layer; the gate is also located in the gap, so that the gate surrounds the channel layer on all four sides, which helps to improve the gate's control over the channel and thus improve the device's performance.

[0026] In the semiconductor device structure provided by the present invention, the improved bonding state between the gate material layer and the channel layer surface is beneficial to improving the gate's control over the channel, thereby improving the device's performance.

[0027] Furthermore, the dielectric wall and the sidewall of the channel layer have a gap; the gate is also located in the gap, so that the gate surrounds the channel layer on all four sides, which is beneficial to improve the gate's control over the channel, thereby improving the device's performance. Attached Figure Description

[0028] Figures 1 to 4 This is a schematic diagram of a semiconductor structure formation process;

[0029] Figures 5 to 13 This is a schematic diagram of the structure corresponding to each step in a semiconductor structure formation method according to an embodiment of the present invention;

[0030] Figures 14 to 15 This is a schematic diagram of the structure corresponding to each step in the semiconductor structure formation method of another embodiment of the present invention. Detailed Implementation

[0031] As described in the background section, the performance of semiconductor devices formed in the prior art needs improvement. The following analysis will illustrate this with reference to the structure of a semiconductor.

[0032] Figures 1 to 4 This is a cross-sectional schematic diagram of the semiconductor structure formation process.

[0033] Please refer to Figure 1 and Figure 2 , Figure 2 This is a top view. Figure 1 for Figure 2 A cross-sectional structural diagram along the XY direction shows an initial substrate (not shown); a composite layer (not shown) is formed on the initial substrate, the composite layer comprising several overlapping initial sacrificial layers (not shown) and an initial channel layer (not shown) located between adjacent initial sacrificial layers; a sidewall structure is formed on the surface of the composite layer, the sidewall structure comprising two mutually independent sidewalls 100; using the sidewall structure as a mask, the composite layer and the initial substrate are etched to form substrate 101 and substrate 1. Two separate composite layers 102 are provided on the substrate 101, with an opening 103 between the two composite layers 102. Each composite layer 102 includes a bottom structure 104 on the substrate 101, several overlapping sacrificial layers 105 on the bottom structure 104, and a channel layer 106 between two adjacent sacrificial layers 105. A first isolation structure 107 is formed on the substrate 101 and in the opening 103, with the top surface of the first isolation structure 107 flush with the top surface of the bottom structure 104.

[0034] Please refer to Figure 3 After the first isolation structure 107 is formed, a medium wall 108 is formed in the opening 103.

[0035] Please refer to Figure 4 Remove the sidewall 100 and the sacrificial layer 105, and form a gate trench (not shown in the figure) between adjacent channel layers 106; form a gate 109 on the substrate, the gate 109 being located in the trench and surrounding the channel layer 104.

[0036] The above method is used to form a forksheet device. The composite layers 102 on both sides of the dielectric wall 108 are used to form PMOS and NMOS devices, respectively. The dielectric wall 108 is used to isolate the NMOS and PMOS devices. Compared with the all-around gate device, the distance between the N-type and P-type devices can be greatly shortened, which is beneficial to increasing the device density. However, compared with the all-around gate device where the gate surrounds the channel on all four sides, the gate of the forksheet device only surrounds the channel from three sides, and the surface of the channel layer 104 and the dielectric wall 108 form a corner A (e.g., Figure 4 As shown, when the gate trench is filled with material, the corner A will hinder the filling of the gate material in the gate trench, making it difficult for the gate to properly wrap the channel, which in turn hinders the improvement of the gate's control over the channel.

[0037] To address the aforementioned issues, this invention provides a semiconductor structure formation method in which the initial channel layer is etched to form a groove between two adjacent sacrificial layers. The sidewalls of the channel layer exposed by the groove are recessed relative to the sidewalls of the sacrificial layers. After forming dielectric walls in the opening and the groove adjacent to the opening, a portion of the dielectric wall includes a protrusion extending towards the sidewall of the channel layer. When a uniform gate material layer is formed on the surface of the channel layer, the protrusion provides the gate material layer with space to fill redundant areas, thereby improving the bonding state between the gate material layer and the surface of the channel layer. This enhances the gate's control over the channel and ultimately improves the device's performance.

[0038] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0039] Figures 5 to 13 This is a schematic diagram of the structure corresponding to each step in a semiconductor structure formation method according to an embodiment of the present invention.

[0040] Please refer to Figure 5 and Figure 6 , Figure 6 for Figure 5 A top-view structural diagram. Figure 5 for Figure 6 A cross-sectional structural diagram along the DD1 direction shows a substrate 200 and two independent initial composite layers 201 on the substrate 200. An opening 202 is provided between the two initial composite layers 201. The initial composite layer 201 includes several overlapping sacrificial layers 203 on the substrate 200 and an initial channel layer 204 between two adjacent sacrificial layers 203.

[0041] In this embodiment, the initial composite layer 201 further includes a bottom structure 205, which is located at the bottom of the initial composite layer 201.

[0042] In this embodiment, the substrate 200 includes a first region I and a second region II, and the initial composite layer 201 is located on the first region I. The initial composite layer 201 is used to form a composite layer.

[0043] The method for forming the initial composite layer 201 includes: providing an initial substrate (not shown in the figure), the initial substrate including an initial first region (not shown in the figure); forming a composite layer (not shown in the figure) on the initial substrate, the composite layer including a plurality of overlapping sacrificial material layers (not shown in the figure) and a channel material layer (not shown in the figure) located between two adjacent sacrificial material layers; forming a patterned hard mask layer 206 on the composite layer; etching the composite layer and the initial substrate using the hard mask layer 206 as a mask to form the substrate and the initial composite layer 201 and the opening 202 on the substrate; forming a substrate 200 and a bottom structure 205 on the substrate 200 using the initial substrate; forming a first region I using the initial first region; forming the sacrificial layer 203 using the sacrificial material layer on the initial first region; and forming the initial channel layer 204 using the channel material layer on the initial first region.

[0044] The material of the sacrificial material layer 203 is different from the material of the initial channel layer 204. On the one hand, this facilitates the selection of an etching process with a large selectivity ratio between the sacrificial layer 203 and the initial channel layer 204 during subsequent etching of the sacrificial layer 203, thereby reducing etching damage to the initial channel layer 204. On the other hand, it facilitates the selection of an etching process with a large selectivity ratio between the initial channel layer 204 and the sacrificial layer 203 during subsequent etching of the initial channel layer 204, thereby reducing etching damage to the sacrificial layer 203.

[0045] In this embodiment, the sacrificial layer 203 is made of germanium-silicon, and the initial channel layer 204 is made of silicon. In other embodiments, the initial channel layer is made of Ge or GeSi, and the initial sacrificial layer can be made of ZnS, ZnSe, BeS, or GaP, etc. Subsequently, the initial channel layer 204 is used to form the channel of the device.

[0046] In this embodiment, a second initial composite layer 301 is also formed on the second region II. The second initial composite layer 301 on the second region II is used for the subsequent formation of the second composite layer.

[0047] The second initial composite layer 301 includes a bottom structure 302, several overlapping sacrificial layers 303 on the bottom structure 302, and a second initial channel layer 304 located between two second sacrificial layers 303. Subsequently, the initial second channel layer 304 is used to form the channel of the second region device.

[0048] The method for forming the initial second composite layer 301 includes: the initial substrate further includes an initial second region (not shown in the figure); while forming the initial composite layer 201, a second region II and a second initial composite layer 301 on the second region II are also formed, the initial second region forms the second region II, the sacrificial material layer on the initial second region forms the second sacrificial layer 303, and the channel material layer on the initial second region forms the second initial channel layer 304.

[0049] Subsequently, the sidewalls of the initial channel layer 204 are etched to form a channel layer, and a groove is formed between two adjacent sacrificial layers 203, wherein the exposed sidewalls of the channel layer in the groove are recessed relative to the sidewalls of the sacrificial layer 203; a dielectric wall is formed in the opening 202 and the groove.

[0050] In this embodiment, after forming the initial composite layer 201 and before forming the dielectric wall, the method further includes: forming an isolation layer 207 on the substrate 200 and inside the opening, wherein the isolation layer 207 is located on the sidewall of the bottom structure 205, and the top surface of the isolation layer 207 is flush with the top surface of the bottom structure 205.

[0051] Please refer to Figure 7 , Figure 7 The view direction is the same Figure 6 The initial channel layer 204 sidewalls are etched to form a channel layer 208, and a groove 209 is formed between two adjacent sacrificial layers 203, wherein the sidewalls of the channel layer 208 exposed by the groove 209 are recessed relative to the sidewalls of the sacrificial layer 203.

[0052] The formation process of the groove 209 includes one or a combination of dry etching and wet etching. In this embodiment, the formation process of the groove 209 is a dry etching process, which is beneficial for forming a better etching morphology.

[0053] In this embodiment, the sidewalls of the second initial channel layer 304 are also etched to form a second channel layer 305, and a second groove 306 is formed between two adjacent second sacrificial layers 303. The sidewalls of the second channel layer 305 exposed by the second groove 306 are recessed relative to the sidewalls of the second sacrificial layer 303.

[0054] The groove 209 has a size ranging from 1 nanometer to 3 nanometers along the direction perpendicular to the sidewall of the opening 202.

[0055] The formation process of the second groove 306 includes one or a combination of dry etching and wet etching processes. In this embodiment, the groove 209 and the second groove 306 are formed simultaneously in the same process to reduce the number of steps and lower production costs.

[0056] Subsequently, dielectric walls are formed within the opening 202 and the groove 209. The method for forming the dielectric walls is described in [reference needed]. Figures 8 to 9 .

[0057] Please refer to Figure 8 , Figure 8 The view direction is the same Figure 6 A dielectric material layer 210 is formed on the surface of the substrate 200. The dielectric material layer 210 is also located on the sidewalls and surface of the initial composite layer 201 and fills the opening 202 and the groove 209 adjacent to the opening 202. A patterned layer 211 is formed on the surface of the dielectric material layer 210, and the patterned layer 211 exposes the dielectric material layer 210 on the surface of the substrate 200 and the top surface of the initial composite layer 201.

[0058] The dielectric material layer 210 is made of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride. In this embodiment, the dielectric material layer 210 is made of silicon nitride. The dielectric material layer 210 is used to form a dielectric wall.

[0059] In this embodiment, the dielectric material layer 210 is also located on the sidewall of the hard mask layer 206 on the opening 202.

[0060] In this embodiment, the patterning layer 211 is located only on the surface of the dielectric material layer 210 on the opening 202, and is used as a mask to form the dielectric wall.

[0061] Please refer to Figure 9 , Figure 9 The view direction is the same Figure 6 The dielectric material layer 210 is etched using the patterned layer 211 as a mask until the top surface of the initial composite layer 201, the surface of the substrate 200, and the sidewalls of the channel layer 208 and the sacrificial layer 203 are exposed.

[0062] In this embodiment, the top surface of the second initial composite layer 301, the second channel layer 305, and the sidewalls of the second sacrificial layer 303 are also exposed.

[0063] The dielectric wall 212 is made of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbonitride. In this embodiment, the dielectric wall 212 is made of silicon nitride.

[0064] Subsequently, after the dielectric wall 212 is formed, an interlayer dielectric layer and a gate opening within the interlayer dielectric layer are formed on the substrate 200. The gate opening is located on a portion of the sidewall and top surface of the initial composite layer 201 and exposes a portion of the sacrificial layer 203.

[0065] Subsequently, a second composite layer is formed on the second region II. The second composite layer includes several overlapping second gate trenches located on the second region II and a second channel layer located between adjacent second gate trenches.

[0066] In this embodiment, the gate opening is also located on a portion of the sidewall and top surface of the second composite layer. For a method of forming the gate opening, please refer to [reference needed]. Figures 10 to 12 .

[0067] Please refer to Figure 10 and Figure 11 , Figure 10 for Figure 11 A top-view structural diagram. Figure 11 for Figure 10 A cross-sectional view along the DD1 direction shows that a dummy gate 213 is formed on the substrate 200. The dummy gate 213 is located on part of the sidewall and surface of the initial composite layer 201 and is located on top of the dielectric wall 212. An interlayer dielectric layer 214 is formed on the substrate 200. The interlayer dielectric layer 214 is located on the sidewall of the dummy gate 213 and exposes the top surface of the dummy gate 213.

[0068] In this embodiment, the dummy gate 213 is also located on the sidewall and surface of the second initial composite layer 301.

[0069] The dummy gate 213 is made of silicon. In this embodiment, the dummy gate 213 is made of polycrystalline silicon. The dummy gate 213 occupies space for the subsequent formation of the gate.

[0070] Please refer to Figure 12 , Figure 12 The view direction is the same Figure 11 Remove the dummy gate 213 and form the gate opening 215 in the interlayer dielectric layer 214; remove the exposed sacrificial layer 203 from the gate opening 215 and form a gate trench 216 between the adjacent channel layer 208 and the channel layer 208 and the dielectric wall 212, so that the gate trench 216 and the channel layer 208 form a composite layer.

[0071] In this embodiment, the second sacrificial layer 303 exposed by the gate opening 215 is also removed, and a second gate trench 307 is formed between adjacent second channel layers 305, so that the second gate trench 307 and the second channel layer 305 form a second composite layer.

[0072] Please refer to Figure 13 A gate 217 is formed within the gate opening 215 and the gate trench 216, and the gate 217 surrounds the channel layer 208.

[0073] The method of forming the gate 217 includes: forming a gate material layer in the gate opening 215, in the gate trench 216 and on the surface of the interlayer dielectric layer 214; and planarizing the gate material layer until the surface of the interlayer dielectric layer 214 is exposed.

[0074] In this embodiment, the gate 217 is also located within the second gate trench 307 and surrounds the second channel layer 305.

[0075] The material of the gate 217 includes metal.

[0076] Partial dielectric wall 212 includes a protrusion extending toward the sidewall of channel layer 208. When a uniform gate material layer is formed on the surface of channel layer 208, the protrusion provides the gate material layer with redundant space to fill the space, thereby improving the bonding state between the gate material layer and the surface of channel layer 208. This is beneficial to improving the control capability of gate 217 over the channel, and thus improving the performance of the device.

[0077] Accordingly, one embodiment of the present invention also provides a semiconductor structure formed using the above method. Please refer to [the original text]. Figure 13 It includes: a substrate 200; two mutually discrete composite layers located on the substrate 200 and an opening 202 between the two composite layers (e.g., ...). Figure 7 As shown), the composite layer includes a plurality of overlapping gate trenches 216 located on the substrate 200 (e.g., Figure 12 (as shown) and the channel layer 208 located between adjacent gate trenches 216 and the groove 209 on the sidewall of the channel layer 208 (as shown) Figure 9 As shown), the sidewalls of the channel layer 208 exposed by the groove 209 are recessed relative to the sidewalls of the gate trench 216; dielectric walls 212 are located in the opening 202 and the groove 209 adjacent to the opening 202; interlayer dielectric layer 214 is located on the substrate 200 (e.g., Figure 10 (as shown) and the gate opening 215 within the interlayer dielectric layer 214 (as shown) Figure 12 As shown, the gate opening 215 is located on the sidewall and top surface of a portion of the composite layer; the gate 217 is located within the gate opening 215 and the gate trench 216, and the gate 217 surrounds the channel layer 208.

[0078] In this embodiment, the substrate 200 includes a first region I and a second region II, and the composite layer is located in the first region I; the second region II has a second composite layer, which includes a plurality of overlapping second gate trenches 307 located in the second region II and a second channel layer 305 located between adjacent second gate trenches 307.

[0079] In this embodiment, the composite layer further includes a bottom structure 205, which is located at the bottom of the composite layer; the second composite layer further includes a second bottom structure 205, which is located at the bottom of the second composite layer.

[0080] The groove 209 has a size ranging from 1 nanometer to 3 nanometers along the direction perpendicular to the sidewall of the opening 202.

[0081] In this embodiment, the semiconductor structure further includes an isolation layer 207 located on the substrate 200 and within the opening 202. The isolation layer 207 is located on the sidewall of the bottom structure 205 and below the dielectric wall 212, and the top surface of the isolation layer 207 is flush with the top surface of the bottom structure 205.

[0082] In this embodiment, the gate 217 is also located within the second gate trench 307 and surrounds the second channel layer 305.

[0083] Figures 14 to 15 This is a schematic diagram of the structure corresponding to each step in the semiconductor structure formation method of another embodiment of the present invention.

[0084] Please Figure 12 Continue to refer to Figure 14 , Figure 14 The view direction is the same Figure 12 After the gate trench 216 is formed and before the gate is formed, the dielectric wall 212 is etched to form a gap 400 between the dielectric wall 212 and the sidewall of the channel layer 208.

[0085] The size of the void 400 in the direction perpendicular to the sidewall of the opening 202 ranges from 1 nanometer to 3 nanometers.

[0086] The etching process for the dielectric wall 212 includes a wet etching process.

[0087] In this embodiment, the gap 400 allows the subsequently formed gate to surround the channel layer 208 on all four sides. In other embodiments, the gap may not be formed.

[0088] Please refer to Figure 14 A gate 401 is formed in the gate opening 215 and the gate trench 216, and the gate 401 surrounds the channel layer 208.

[0089] The method for forming the gate 401 includes: forming a gate material layer in the gate opening 215, in the gate trench 216 and on the surface of the interlayer dielectric layer 214; and planarizing the gate material layer until the surface of the interlayer dielectric layer 214 is exposed.

[0090] In this embodiment, the gate 401 is also located within the second gate trench 307 and surrounds the second channel layer 305.

[0091] The material of the gate 401 includes metal.

[0092] Partial dielectric wall 212 includes a protrusion extending toward the sidewall of channel layer 208. When a uniform gate material layer is formed on the surface of channel layer 208, the protrusion provides the gate material layer with redundant space to fill the space, thereby improving the bonding state between the gate material layer and the surface of channel layer, which is beneficial to improving the gate's control over the channel and thus improving the performance of the device.

[0093] In this embodiment, the gate 401 is also located within the gap 400. The fact that the gate 401 is also located within the gap 400 allows the gate to surround the channel layer on all four sides, which helps improve the gate's control over the channel and thus improves the device's performance.

[0094] Accordingly, one embodiment of the present invention also provides a semiconductor structure formed using the above method. Please refer to [the original text]. Figure 15 It includes: a substrate 200; two mutually discrete composite layers located on the substrate 200 and an opening 202 between the two composite layers (e.g., ...). Figure 7 As shown), the composite layer includes a plurality of overlapping gate trenches 216 located on the substrate 200 (e.g., Figure 12 (as shown) and the channel layer 208 located between adjacent gate trenches 216 and the groove 209 on the sidewall of the channel layer 208 (as shown) Figure 9 As shown), the sidewalls of the channel layer 208 exposed by the groove 209 are recessed relative to the sidewalls of the gate trench 216; dielectric walls 212 are located in the opening 202 and the groove 209 adjacent to the opening 202; interlayer dielectric layer 214 is located on the substrate 200 (e.g., Figure 10 (as shown) and the gate opening 215 within the interlayer dielectric layer 214 (as shown) Figure 12 As shown), the gate opening 215 is located on the sidewall and top surface of a portion of the composite layer; the gate 401 is located within the gate opening 215 and the gate trench 216, and the gate 401 surrounds the channel layer 208.

[0095] Improving the bonding state between the gate material layer and the channel layer surface is beneficial to enhancing the gate's control over the channel, thereby improving device performance.

[0096] In this embodiment, the substrate 200 includes a first region I and a second region II, and the composite layer is located in the first region I; the second region II has a second composite layer, which includes a plurality of overlapping second gate trenches 307 located in the second region II and a second channel layer 305 located between adjacent second gate trenches 307.

[0097] In this embodiment, the composite layer further includes a bottom structure 205, which is located at the bottom of the composite layer; the second composite layer further includes a second bottom structure 205, which is located at the bottom of the second composite layer.

[0098] The dielectric wall 212 and the sidewall of the channel layer 208 have a gap 400 (e.g., Figure 14 (As shown); the gate 401 is also located in the gap 400. The gate is surrounded by the channel layer on all four sides, which helps to improve the control capability of the gate 401 over the channel layer 208, thereby improving the performance of the device.

[0099] The size of the void 400 in the direction perpendicular to the sidewall of the opening 202 ranges from 1 nanometer to 3 nanometers.

[0100] The groove 209 has a size ranging from 1 nanometer to 3 nanometers along the direction perpendicular to the sidewall of the opening 202.

[0101] In this embodiment, the semiconductor structure further includes an isolation layer 207 located on the substrate 200 and within the opening 202. The isolation layer 207 is located on the sidewall of the bottom structure 205 and below the dielectric wall 212, and the top surface of the isolation layer 207 is flush with the top surface of the bottom structure 205.

[0102] In this embodiment, the gate 401 is also located within the second gate trench 307 and surrounds the second channel layer 305.

[0103] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: Substrate; The composite layer comprises two independent composite layers on the substrate and an opening between the two composite layers. The composite layer includes a plurality of overlapping gate trenches on the substrate and a channel layer and a groove on the sidewall of the channel layer between adjacent gate trenches. The sidewall of the channel layer exposed by the groove is recessed relative to the sidewall of the gate trench. Dielectric walls located within the opening and the groove adjacent to the opening; An interlayer dielectric layer located on the substrate and a gate opening within the interlayer dielectric layer, the gate opening being located on a portion of the composite layer sidewall and top surface; A gate located within the gate opening and the gate trench, and the gate surrounding the channel layer.

2. The semiconductor structure as described in claim 1, characterized in that, The composite layer also includes a bottom structure located at the bottom of the composite layer.

3. The semiconductor structure as described in claim 1, characterized in that, The dielectric wall has a gap with the sidewall of the channel layer; the gate is also located in the gap.

4. The semiconductor structure as described in claim 3, characterized in that, The size of the void is in the range of 1 nanometer to 3 nanometers along the direction perpendicular to the sidewall of the opening.

5. The semiconductor structure as described in claim 1, characterized in that, The groove has a size ranging from 1 nanometer to 3 nanometers along the direction perpendicular to the sidewall of the opening.

6. The semiconductor structure as described in claim 2, characterized in that, It also includes an isolation layer located on the substrate and within the opening, the isolation layer being located on the sidewall of the bottom structure and below the dielectric wall, and the top surface of the isolation layer being flush with the top surface of the bottom structure.

7. A method for forming a semiconductor structure, characterized in that, include: A substrate and two initial composite layers discretely separated on the substrate are formed, the two initial composite layers having an opening between them, the initial composite layer including a plurality of overlapping sacrificial layers on the substrate and an initial channel layer between two adjacent sacrificial layers; The initial channel layer sidewalls are etched to form a channel layer, and a groove is formed between two adjacent sacrificial layers, wherein the channel layer sidewalls exposed by the grooves are recessed relative to the sacrificial layer sidewalls; Dielectric walls are formed within the opening and the groove; After the dielectric wall is formed, an interlayer dielectric layer and a gate opening within the interlayer dielectric layer are formed on the substrate. The gate opening is located on a portion of the initial composite layer sidewall and top surface, and exposes a portion of the sacrificial layer. Remove the exposed sacrificial layer from the gate opening, form a gate trench between the adjacent channel layer and the dielectric wall, and form a composite layer with the gate trench and the channel layer; A gate is formed within the gate opening and the gate trench, the gate surrounding the channel layer.

8. The method for forming a semiconductor structure as described in claim 7, characterized in that, After forming the gate trench and before forming the gate, the method further includes: etching the dielectric wall to form a gap between the dielectric wall and the sidewall of the channel layer; the gate is also located in the gap.

9. The method for forming a semiconductor structure as described in claim 8, characterized in that, The etching process for the dielectric wall includes a wet etching process.

10. The method for forming a semiconductor structure as described in claim 7, characterized in that, The initial composite layer also includes a bottom structure located at the bottom of the initial composite layer.

11. The method for forming a semiconductor structure as described in claim 10, characterized in that, After forming the initial composite layer and before forming the dielectric wall, the method further includes: forming an isolation layer on the substrate and inside the opening, the isolation layer being located on the sidewall of the bottom structure, and the top surface of the isolation layer being flush with the top surface of the bottom structure.

12. The method for forming a semiconductor structure as described in claim 7, characterized in that, The method for forming the dielectric wall includes: forming a dielectric material layer on the surface of the substrate, the dielectric material layer also being located on the sidewalls and surface of the initial composite layer, and filling the opening and the groove adjacent to the opening; forming a patterned layer on the surface of the dielectric material layer, the patterned layer exposing the dielectric material layer on the surface of the substrate and the top surface of the initial composite layer; etching the dielectric material layer using the patterned layer as a mask until the top surface of the initial composite layer, the surface of the substrate, and the sidewalls of the channel layer and the sacrificial layer are exposed.

13. The method for forming a semiconductor structure as described in claim 7, characterized in that, The method for forming the gate opening includes: forming a dummy gate on the substrate, the dummy gate being located on a portion of the sidewall and surface of the initial composite layer and on top of the dielectric wall; forming an interlayer dielectric layer on the substrate, the interlayer dielectric layer being located on the sidewall of the dummy gate and exposing the top surface of the dummy gate; removing the dummy gate and forming the gate opening within the interlayer dielectric layer.

14. The method for forming a semiconductor structure as described in claim 7, characterized in that, The process for forming the groove includes one or a combination of dry etching or wet etching.

15. The method for forming a semiconductor structure as described in claim 7, characterized in that, The dielectric wall material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbonitride.

16. The method for forming a semiconductor structure as described in claim 7, characterized in that, The substrate includes a first region and a second region, the composite layer is located in the first region, and the method further includes: forming a second composite layer on the second region, the second composite layer including a plurality of overlapping second gate trenches located on the second region and a second channel layer located between adjacent second gate trenches; the gate opening is also located on a portion of the sidewall and top surface of the second composite layer; the gate is also located within the second gate trench and surrounds the second channel layer.

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